[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / benet / be.h

/*
 * Copyright (C) 2005 - 2010 ServerEngines
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@serverengines.com
 *
 * ServerEngines
 * 209 N. Fair Oaks Ave
 * Sunnyvale, CA 94085
 */

#ifndef BE_H
#define BE_H

#include <linux/pci.h>
#include <linux/etherdevice.h>
#include <linux/version.h>
#include <linux/delay.h>
#include <net/tcp.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <linux/if_vlan.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/slab.h>

#include "be_hw.h"

#define DRV_VER			"2.103.175u"
#define DRV_NAME		"be2net"
#define BE_NAME			"ServerEngines BladeEngine2 10Gbps NIC"
#define BE3_NAME		"ServerEngines BladeEngine3 10Gbps NIC"
#define OC_NAME			"Emulex OneConnect 10Gbps NIC"
#define OC_NAME1		"Emulex OneConnect 10Gbps NIC (be3)"
#define DRV_DESC		"ServerEngines BladeEngine 10Gbps NIC Driver"

#define BE_VENDOR_ID 		0x19a2
#define BE_DEVICE_ID1		0x211
#define BE_DEVICE_ID2		0x221
#define OC_DEVICE_ID1		0x700
#define OC_DEVICE_ID2		0x710

static inline char *nic_name(struct pci_dev *pdev)
{
	switch (pdev->device) {
	case OC_DEVICE_ID1:
		return OC_NAME;
	case OC_DEVICE_ID2:
		return OC_NAME1;
	case BE_DEVICE_ID2:
		return BE3_NAME;
	default:
		return BE_NAME;
	}
}

/* Number of bytes of an RX frame that are copied to skb->data */
#define BE_HDR_LEN 		64
#define BE_MAX_JUMBO_FRAME_SIZE	9018
#define BE_MIN_MTU		256

#define BE_NUM_VLANS_SUPPORTED	64
#define BE_MAX_EQD		96
#define	BE_MAX_TX_FRAG_COUNT	30

#define EVNT_Q_LEN		1024
#define TX_Q_LEN		2048
#define TX_CQ_LEN		1024
#define RX_Q_LEN		1024	/* Does not support any other value */
#define RX_CQ_LEN		1024
#define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
#define MCC_CQ_LEN		256

#define MAX_RSS_QS		4	/* BE limit is 4 queues/port */
#define BE_MAX_MSIX_VECTORS	(MAX_RSS_QS + 1 + 1)/* RSS qs + 1 def Rx + Tx */
#define BE_NAPI_WEIGHT		64
#define MAX_RX_POST 		BE_NAPI_WEIGHT /* Frags posted at a time */
#define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)

#define FW_VER_LEN		32

#define BE_MAX_VF		32

struct be_dma_mem {
	void *va;
	dma_addr_t dma;
	u32 size;
};

struct be_queue_info {
	struct be_dma_mem dma_mem;
	u16 len;
	u16 entry_size;	/* Size of an element in the queue */
	u16 id;
	u16 tail, head;
	bool created;
	atomic_t used;	/* Number of valid elements in the queue */
};

static inline u32 MODULO(u16 val, u16 limit)
{
	BUG_ON(limit & (limit - 1));
	return val & (limit - 1);
}

static inline void index_adv(u16 *index, u16 val, u16 limit)
{
	*index = MODULO((*index + val), limit);
}

static inline void index_inc(u16 *index, u16 limit)
{
	*index = MODULO((*index + 1), limit);
}

static inline void *queue_head_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->head * q->entry_size;
}

static inline void *queue_tail_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->tail * q->entry_size;
}

static inline void queue_head_inc(struct be_queue_info *q)
{
	index_inc(&q->head, q->len);
}

static inline void queue_tail_inc(struct be_queue_info *q)
{
	index_inc(&q->tail, q->len);
}

struct be_eq_obj {
	struct be_queue_info q;
	char desc[32];

	/* Adaptive interrupt coalescing (AIC) info */
	bool enable_aic;
	u16 min_eqd;		/* in usecs */
	u16 max_eqd;		/* in usecs */
	u16 cur_eqd;		/* in usecs */

	struct napi_struct napi;
};

struct be_mcc_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	bool rearm_cq;
};

struct be_tx_stats {
	u32 be_tx_reqs;		/* number of TX requests initiated */
	u32 be_tx_stops;	/* number of times TX Q was stopped */
	u32 be_tx_wrbs;		/* number of tx WRBs used */
	u32 be_tx_events;	/* number of tx completion events  */
	u32 be_tx_compl;	/* number of tx completion entries processed */
	ulong be_tx_jiffies;
	u64 be_tx_bytes;
	u64 be_tx_bytes_prev;
	u64 be_tx_pkts;
	u32 be_tx_rate;
};

struct be_tx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	/* Remember the skbs that were transmitted */
	struct sk_buff *sent_skb_list[TX_Q_LEN];
};

/* Struct to remember the pages posted for rx frags */
struct be_rx_page_info {
	struct page *page;
	DEFINE_DMA_UNMAP_ADDR(bus);
	u16 page_offset;
	bool last_page_user;
};

struct be_rx_stats {
	u32 rx_post_fail;/* number of ethrx buffer alloc failures */
	u32 rx_polls;	/* number of times NAPI called poll function */
	u32 rx_events;	/* number of ucast rx completion events  */
	u32 rx_compl;	/* number of rx completion entries processed */
	ulong rx_jiffies;
	u64 rx_bytes;
	u64 rx_bytes_prev;
	u64 rx_pkts;
	u32 rx_rate;
	u32 rx_mcast_pkts;
	u32 rxcp_err;	/* Num rx completion entries w/ err set. */
	ulong rx_fps_jiffies;	/* jiffies at last FPS calc */
	u32 rx_frags;
	u32 prev_rx_frags;
	u32 rx_fps;		/* Rx frags per second */
};

struct be_rx_obj {
	struct be_adapter *adapter;
	struct be_queue_info q;
	struct be_queue_info cq;
	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
	struct be_eq_obj rx_eq;
	struct be_rx_stats stats;
	u8 rss_id;
	bool rx_post_starved;	/* Zero rx frags have been posted to BE */
	u32 cache_line_barrier[16];
};

struct be_vf_cfg {
	unsigned char vf_mac_addr[ETH_ALEN];
	u32 vf_if_handle;
	u32 vf_pmac_id;
	u16 vf_vlan_tag;
	u32 vf_tx_rate;
};

#define BE_INVALID_PMAC_ID		0xffffffff
struct be_adapter {
	struct pci_dev *pdev;
	struct net_device *netdev;

	u8 __iomem *csr;
	u8 __iomem *db;		/* Door Bell */
	u8 __iomem *pcicfg;	/* PCI config space */

	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
	struct be_dma_mem mbox_mem;
	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	 * is stored for freeing purpose */
	struct be_dma_mem mbox_mem_alloced;

	struct be_mcc_obj mcc_obj;
	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
	spinlock_t mcc_cq_lock;

	struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS];
	bool msix_enabled;
	bool isr_registered;

	/* TX Rings */
	struct be_eq_obj tx_eq;
	struct be_tx_obj tx_obj;
	struct be_tx_stats tx_stats;

	u32 cache_line_break[8];

	/* Rx rings */
	struct be_rx_obj rx_obj[MAX_RSS_QS + 1]; /* one default non-rss Q */
	u32 num_rx_qs;
	u32 big_page_size;	/* Compounded page size shared by rx wrbs */

	struct vlan_group *vlan_grp;
	u16 vlans_added;
	u16 max_vlans;	/* Number of vlans supported */
	u8 vlan_tag[VLAN_N_VID];
	u8 vlan_prio_bmap;	/* Available Priority BitMap */
	u16 recommended_prio;	/* Recommended Priority */
	struct be_dma_mem mc_cmd_mem;

	struct be_dma_mem stats_cmd;
	/* Work queue used to perform periodic tasks like getting statistics */
	struct delayed_work work;

	/* Ethtool knobs and info */
	bool rx_csum; 		/* BE card must perform rx-checksumming */
	char fw_ver[FW_VER_LEN];
	u32 if_handle;		/* Used to configure filtering */
	u32 pmac_id;		/* MAC addr handle used by BE card */

	bool eeh_err;
	bool link_up;
	u32 port_num;
	bool promiscuous;
	bool wol;
	u32 function_mode;
	u32 function_caps;
	u32 rx_fc;		/* Rx flow control */
	u32 tx_fc;		/* Tx flow control */
	bool ue_detected;
	bool stats_ioctl_sent;
	int link_speed;
	u8 port_type;
	u8 transceiver;
	u8 autoneg;
	u8 generation;		/* BladeEngine ASIC generation */
	u32 flash_status;
	struct completion flash_compl;

	bool sriov_enabled;
	struct be_vf_cfg vf_cfg[BE_MAX_VF];
	u8 base_eq_id;
	u8 is_virtfn;
};

#define be_physfn(adapter) (!adapter->is_virtfn)

/* BladeEngine Generation numbers */
#define BE_GEN2 2
#define BE_GEN3 3

extern const struct ethtool_ops be_ethtool_ops;

#define tx_stats(adapter)		(&adapter->tx_stats)
#define rx_stats(rxo)			(&rxo->stats)

#define BE_SET_NETDEV_OPS(netdev, ops)	(netdev->netdev_ops = ops)

#define for_all_rx_queues(adapter, rxo, i)				\
	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;	\
		i++, rxo++)

/* Just skip the first default non-rss queue */
#define for_all_rss_queues(adapter, rxo, i)				\
	for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\
		i++, rxo++)

#define PAGE_SHIFT_4K		12
#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)

/* Returns number of pages spanned by the data starting at the given addr */
#define PAGES_4K_SPANNED(_address, size) 				\
		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))

/* Byte offset into the page corresponding to given address */
#define OFFSET_IN_PAGE(addr)						\
		 ((size_t)(addr) & (PAGE_SIZE_4K-1))

/* Returns bit offset within a DWORD of a bitfield */
#define AMAP_BIT_OFFSET(_struct, field)  				\
		(((size_t)&(((_struct *)0)->field))%32)

/* Returns the bit mask of the field that is NOT shifted into location. */
static inline u32 amap_mask(u32 bitsize)
{
	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
}

static inline void
amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
{
	u32 *dw = (u32 *) ptr + dw_offset;
	*dw &= ~(mask << offset);
	*dw |= (mask & value) << offset;
}

#define AMAP_SET_BITS(_struct, field, ptr, val)				\
		amap_set(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field),		\
			val)

static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
{
	u32 *dw = (u32 *) ptr;
	return mask & (*(dw + dw_offset) >> offset);
}

#define AMAP_GET_BITS(_struct, field, ptr)				\
		amap_get(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field))

#define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
#define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
static inline void swap_dws(void *wrb, int len)
{
#ifdef __BIG_ENDIAN
	u32 *dw = wrb;
	BUG_ON(len % 4);
	do {
		*dw = cpu_to_le32(*dw);
		dw++;
		len -= 4;
	} while (len);
#endif				/* __BIG_ENDIAN */
}

static inline u8 is_tcp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);

	return val;
}

static inline u8 is_udp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);

	return val;
}

static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
{
	u8 data;

	pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
	pci_read_config_byte(adapter->pdev, 0xFE, &data);
	adapter->is_virtfn = (data != 0xAA);
}

static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
{
	u32 addr;

	addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);

	mac[5] = (u8)(addr & 0xFF);
	mac[4] = (u8)((addr >> 8) & 0xFF);
	mac[3] = (u8)((addr >> 16) & 0xFF);
	mac[2] = 0xC9;
	mac[1] = 0x00;
	mac[0] = 0x00;
}

extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
		u16 num_popped);
extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
extern void netdev_stats_update(struct be_adapter *adapter);
extern int be_load_fw(struct be_adapter *adapter, u8 *func);
#endif				/* BE_H */
Commit	Line	Data
6b7c5b94	1	/*
294aedcf	2	* Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94 SP	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
	11	* linux-drivers@serverengines.com
	12	*
	13	* ServerEngines
	14	* 209 N. Fair Oaks Ave
	15	* Sunnyvale, CA 94085
	16	*/
	17
	18	#ifndef BE_H
	19	#define BE_H
	20
	21	#include <linux/pci.h>
	22	#include <linux/etherdevice.h>
	23	#include <linux/version.h>
	24	#include <linux/delay.h>
	25	#include <net/tcp.h>
	26	#include <net/ip.h>
	27	#include <net/ipv6.h>
	28	#include <linux/if_vlan.h>
	29	#include <linux/workqueue.h>
	30	#include <linux/interrupt.h>
84517482	31	#include <linux/firmware.h>
5a0e3ad6	32	#include <linux/slab.h>
6b7c5b94 SP	33
	34	#include "be_hw.h"
	35
e2619843	36	#define DRV_VER "2.103.175u"
6b7c5b94 SP	37	#define DRV_NAME "be2net"
6b7c5b94 SP	38	#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
12d7ea2c	39	#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
c4ca2374	40	#define OC_NAME "Emulex OneConnect 10Gbps NIC"
12d7ea2c	41	#define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
35ecf03c	42	#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
6b7c5b94	43
c4ca2374 AK	44	#define BE_VENDOR_ID 0x19a2
c4ca2374 AK	45	#define BE_DEVICE_ID1 0x211
12d7ea2c	46	#define BE_DEVICE_ID2 0x221
c4ca2374	47	#define OC_DEVICE_ID1 0x700
e254f6ec	48	#define OC_DEVICE_ID2 0x710
c4ca2374 AK	49
	50	static inline char nic_name(struct pci_dev pdev)
	51	{
12d7ea2c AK	52	switch (pdev->device) {
12d7ea2c AK	53	case OC_DEVICE_ID1:
c4ca2374	54	return OC_NAME;
e254f6ec	55	case OC_DEVICE_ID2:
12d7ea2c AK	56	return OC_NAME1;
	57	case BE_DEVICE_ID2:
	58	return BE3_NAME;
	59	default:
c4ca2374	60	return BE_NAME;
12d7ea2c	61	}
c4ca2374 AK	62	}
c4ca2374 AK	63
6b7c5b94 SP	64	/* Number of bytes of an RX frame that are copied to skb->data */
	65	#define BE_HDR_LEN 64
	66	#define BE_MAX_JUMBO_FRAME_SIZE 9018
	67	#define BE_MIN_MTU 256
	68
	69	#define BE_NUM_VLANS_SUPPORTED 64
	70	#define BE_MAX_EQD 96
	71	#define BE_MAX_TX_FRAG_COUNT 30
	72
	73	#define EVNT_Q_LEN 1024
	74	#define TX_Q_LEN 2048
	75	#define TX_CQ_LEN 1024
	76	#define RX_Q_LEN 1024 /* Does not support any other value */
	77	#define RX_CQ_LEN 1024
5fb379ee	78	#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
6b7c5b94 SP	79	#define MCC_CQ_LEN 256
6b7c5b94 SP	80
3abcdeda SP	81	#define MAX_RSS_QS 4 /* BE limit is 4 queues/port */
3abcdeda SP	82	#define BE_MAX_MSIX_VECTORS (MAX_RSS_QS + 1 + 1)/* RSS qs + 1 def Rx + Tx */
6b7c5b94 SP	83	#define BE_NAPI_WEIGHT 64
	84	#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
	85	#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
	86
8788fdc2 SP	87	#define FW_VER_LEN 32
8788fdc2 SP	88
ba343c77 SB	89	#define BE_MAX_VF 32
ba343c77 SB	90
6b7c5b94 SP	91	struct be_dma_mem {
	92	void *va;
	93	dma_addr_t dma;
	94	u32 size;
	95	};
	96
	97	struct be_queue_info {
	98	struct be_dma_mem dma_mem;
	99	u16 len;
	100	u16 entry_size; /* Size of an element in the queue */
	101	u16 id;
	102	u16 tail, head;
	103	bool created;
	104	atomic_t used; /* Number of valid elements in the queue */
	105	};
	106
5fb379ee SP	107	static inline u32 MODULO(u16 val, u16 limit)
	108	{
	109	BUG_ON(limit & (limit - 1));
	110	return val & (limit - 1);
	111	}
	112
	113	static inline void index_adv(u16 *index, u16 val, u16 limit)
	114	{
	115	index = MODULO((index + val), limit);
	116	}
	117
	118	static inline void index_inc(u16 *index, u16 limit)
	119	{
	120	index = MODULO((index + 1), limit);
	121	}
	122
	123	static inline void queue_head_node(struct be_queue_info q)
	124	{
	125	return q->dma_mem.va + q->head * q->entry_size;
	126	}
	127
	128	static inline void queue_tail_node(struct be_queue_info q)
	129	{
	130	return q->dma_mem.va + q->tail * q->entry_size;
	131	}
	132
	133	static inline void queue_head_inc(struct be_queue_info *q)
	134	{
	135	index_inc(&q->head, q->len);
	136	}
	137
	138	static inline void queue_tail_inc(struct be_queue_info *q)
	139	{
	140	index_inc(&q->tail, q->len);
	141	}
	142
5fb379ee SP	143	struct be_eq_obj {
	144	struct be_queue_info q;
	145	char desc[32];
	146
	147	/* Adaptive interrupt coalescing (AIC) info */
	148	bool enable_aic;
	149	u16 min_eqd; /* in usecs */
	150	u16 max_eqd; /* in usecs */
	151	u16 cur_eqd; /* in usecs */
	152
	153	struct napi_struct napi;
	154	};
	155
	156	struct be_mcc_obj {
	157	struct be_queue_info q;
	158	struct be_queue_info cq;
7a1e9b20	159	bool rearm_cq;
5fb379ee SP	160	};
5fb379ee SP	161
3abcdeda	162	struct be_tx_stats {
6b7c5b94 SP	163	u32 be_tx_reqs; /* number of TX requests initiated */
6b7c5b94 SP	164	u32 be_tx_stops; /* number of times TX Q was stopped */
6b7c5b94 SP	165	u32 be_tx_wrbs; /* number of tx WRBs used */
	166	u32 be_tx_events; /* number of tx completion events */
	167	u32 be_tx_compl; /* number of tx completion entries processed */
4097f663 SP	168	ulong be_tx_jiffies;
	169	u64 be_tx_bytes;
	170	u64 be_tx_bytes_prev;
91992e44	171	u64 be_tx_pkts;
6b7c5b94	172	u32 be_tx_rate;
6b7c5b94 SP	173	};
6b7c5b94 SP	174
6b7c5b94 SP	175	struct be_tx_obj {
	176	struct be_queue_info q;
	177	struct be_queue_info cq;
	178	/* Remember the skbs that were transmitted */
	179	struct sk_buff *sent_skb_list[TX_Q_LEN];
	180	};
	181
	182	/* Struct to remember the pages posted for rx frags */
	183	struct be_rx_page_info {
	184	struct page *page;
fac6da5b	185	DEFINE_DMA_UNMAP_ADDR(bus);
6b7c5b94 SP	186	u16 page_offset;
	187	bool last_page_user;
	188	};
	189
3abcdeda SP	190	struct be_rx_stats {
	191	u32 rx_post_fail;/* number of ethrx buffer alloc failures */
	192	u32 rx_polls; /* number of times NAPI called poll function */
	193	u32 rx_events; /* number of ucast rx completion events */
	194	u32 rx_compl; /* number of rx completion entries processed */
	195	ulong rx_jiffies;
	196	u64 rx_bytes;
	197	u64 rx_bytes_prev;
	198	u64 rx_pkts;
	199	u32 rx_rate;
	200	u32 rx_mcast_pkts;
	201	u32 rxcp_err; /* Num rx completion entries w/ err set. */
	202	ulong rx_fps_jiffies; /* jiffies at last FPS calc */
	203	u32 rx_frags;
	204	u32 prev_rx_frags;
	205	u32 rx_fps; /* Rx frags per second */
	206	};
	207
6b7c5b94	208	struct be_rx_obj {
3abcdeda	209	struct be_adapter *adapter;
6b7c5b94 SP	210	struct be_queue_info q;
	211	struct be_queue_info cq;
	212	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
3abcdeda SP	213	struct be_eq_obj rx_eq;
	214	struct be_rx_stats stats;
	215	u8 rss_id;
	216	bool rx_post_starved; /* Zero rx frags have been posted to BE */
	217	u32 cache_line_barrier[16];
6b7c5b94 SP	218	};
6b7c5b94 SP	219
64600ea5 AK	220	struct be_vf_cfg {
	221	unsigned char vf_mac_addr[ETH_ALEN];
	222	u32 vf_if_handle;
	223	u32 vf_pmac_id;
1da87b7f	224	u16 vf_vlan_tag;
e1d18735	225	u32 vf_tx_rate;
64600ea5 AK	226	};
64600ea5 AK	227
9cd9000b	228	#define BE_INVALID_PMAC_ID 0xffffffff
6b7c5b94 SP	229	struct be_adapter {
	230	struct pci_dev *pdev;
	231	struct net_device *netdev;
	232
8788fdc2 SP	233	u8 __iomem *csr;
	234	u8 __iomem db; / Door Bell */
	235	u8 __iomem pcicfg; / PCI config space */
8788fdc2	236
2984961c	237	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
8788fdc2 SP	238	struct be_dma_mem mbox_mem;
	239	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	240	* is stored for freeing purpose */
	241	struct be_dma_mem mbox_mem_alloced;
	242
	243	struct be_mcc_obj mcc_obj;
	244	spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
	245	spinlock_t mcc_cq_lock;
6b7c5b94	246
3abcdeda	247	struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS];
6b7c5b94 SP	248	bool msix_enabled;
	249	bool isr_registered;
	250
	251	/* TX Rings */
	252	struct be_eq_obj tx_eq;
	253	struct be_tx_obj tx_obj;
3abcdeda	254	struct be_tx_stats tx_stats;
6b7c5b94 SP	255
	256	u32 cache_line_break[8];
	257
	258	/* Rx rings */
3abcdeda SP	259	struct be_rx_obj rx_obj[MAX_RSS_QS + 1]; /* one default non-rss Q */
3abcdeda SP	260	u32 num_rx_qs;
6b7c5b94 SP	261	u32 big_page_size; /* Compounded page size shared by rx wrbs */
	262
	263	struct vlan_group *vlan_grp;
82903e4b AK	264	u16 vlans_added;
82903e4b AK	265	u16 max_vlans; /* Number of vlans supported */
b738127d	266	u8 vlan_tag[VLAN_N_VID];
cc4ce020 SK	267	u8 vlan_prio_bmap; /* Available Priority BitMap */
cc4ce020 SK	268	u16 recommended_prio; /* Recommended Priority */
e7b909a6	269	struct be_dma_mem mc_cmd_mem;
6b7c5b94	270
3abcdeda	271	struct be_dma_mem stats_cmd;
6b7c5b94 SP	272	/* Work queue used to perform periodic tasks like getting statistics */
	273	struct delayed_work work;
	274
	275	/* Ethtool knobs and info */
	276	bool rx_csum; /* BE card must perform rx-checksumming */
6b7c5b94 SP	277	char fw_ver[FW_VER_LEN];
	278	u32 if_handle; /* Used to configure filtering */
	279	u32 pmac_id; /* MAC addr handle used by BE card */
	280
cf588477	281	bool eeh_err;
a8f447bd	282	bool link_up;
6b7c5b94	283	u32 port_num;
24307eef	284	bool promiscuous;
71d8d1b5	285	bool wol;
3486be29	286	u32 function_mode;
3abcdeda	287	u32 function_caps;
9e90c961 AK	288	u32 rx_fc; /* Rx flow control */
9e90c961 AK	289	u32 tx_fc; /* Tx flow control */
7c185276	290	bool ue_detected;
0fc48c37	291	bool stats_ioctl_sent;
0dffc83e AK	292	int link_speed;
0dffc83e AK	293	u8 port_type;
16c02145	294	u8 transceiver;
ee3cb629	295	u8 autoneg;
7b139c83	296	u8 generation; /* BladeEngine ASIC generation */
dd131e76 SB	297	u32 flash_status;
dd131e76 SB	298	struct completion flash_compl;
ba343c77 SB	299
ba343c77 SB	300	bool sriov_enabled;
64600ea5	301	struct be_vf_cfg vf_cfg[BE_MAX_VF];
ba343c77	302	u8 base_eq_id;
344dbf10	303	u8 is_virtfn;
6b7c5b94 SP	304	};
6b7c5b94 SP	305
344dbf10	306	#define be_physfn(adapter) (!adapter->is_virtfn)
ba343c77	307
7b139c83 AK	308	/* BladeEngine Generation numbers */
	309	#define BE_GEN2 2
	310	#define BE_GEN3 3
	311
0fc0b732	312	extern const struct ethtool_ops be_ethtool_ops;
6b7c5b94	313
3abcdeda SP	314	#define tx_stats(adapter) (&adapter->tx_stats)
3abcdeda SP	315	#define rx_stats(rxo) (&rxo->stats)
6b7c5b94 SP	316
	317	#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
	318
3abcdeda SP	319	#define for_all_rx_queues(adapter, rxo, i) \
	320	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
	321	i++, rxo++)
	322
	323	/* Just skip the first default non-rss queue */
	324	#define for_all_rss_queues(adapter, rxo, i) \
	325	for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\
	326	i++, rxo++)
	327
6b7c5b94 SP	328	#define PAGE_SHIFT_4K 12
	329	#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
	330
	331	/* Returns number of pages spanned by the data starting at the given addr */
	332	#define PAGES_4K_SPANNED(_address, size) \
	333	((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
	334	(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
	335
	336	/* Byte offset into the page corresponding to given address */
	337	#define OFFSET_IN_PAGE(addr) \
	338	((size_t)(addr) & (PAGE_SIZE_4K-1))
	339
	340	/* Returns bit offset within a DWORD of a bitfield */
	341	#define AMAP_BIT_OFFSET(_struct, field) \
	342	(((size_t)&(((_struct *)0)->field))%32)
	343
	344	/* Returns the bit mask of the field that is NOT shifted into location. */
	345	static inline u32 amap_mask(u32 bitsize)
	346	{
	347	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
	348	}
	349
	350	static inline void
	351	amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
	352	{
	353	u32 dw = (u32 ) ptr + dw_offset;
	354	*dw &= ~(mask << offset);
	355	*dw \|= (mask & value) << offset;
	356	}
	357
	358	#define AMAP_SET_BITS(_struct, field, ptr, val) \
	359	amap_set(ptr, \
	360	offsetof(_struct, field)/32, \
	361	amap_mask(sizeof(((_struct *)0)->field)), \
	362	AMAP_BIT_OFFSET(_struct, field), \
	363	val)
	364
	365	static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
	366	{
	367	u32 dw = (u32 ) ptr;
	368	return mask & (*(dw + dw_offset) >> offset);
	369	}
	370
	371	#define AMAP_GET_BITS(_struct, field, ptr) \
	372	amap_get(ptr, \
	373	offsetof(_struct, field)/32, \
	374	amap_mask(sizeof(((_struct *)0)->field)), \
	375	AMAP_BIT_OFFSET(_struct, field))
	376
	377	#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
	378	#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
	379	static inline void swap_dws(void *wrb, int len)
	380	{
	381	#ifdef __BIG_ENDIAN
	382	u32 *dw = wrb;
	383	BUG_ON(len % 4);
	384	do {
	385	dw = cpu_to_le32(dw);
	386	dw++;
	387	len -= 4;
	388	} while (len);
	389	#endif /* __BIG_ENDIAN */
	390	}
	391
392	static inline u8 is_tcp_pkt(struct sk_buff *skb)
393	{
394	u8 val = 0;
395
396	if (ip_hdr(skb)->version == 4)
397	val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
398	else if (ip_hdr(skb)->version == 6)
399	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
400
401	return val;
402	}
403
404	static inline u8 is_udp_pkt(struct sk_buff *skb)
405	{
406	u8 val = 0;
407
408	if (ip_hdr(skb)->version == 4)
409	val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
410	else if (ip_hdr(skb)->version == 6)
411	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
412
413	return val;
414	}
415
344dbf10 SB	416	static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
	417	{
	418	u8 data;
	419
	420	pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
	421	pci_read_config_byte(adapter->pdev, 0xFE, &data);
	422	adapter->is_virtfn = (data != 0xAA);
	423	}
	424
6d87f5c3 AK	425	static inline void be_vf_eth_addr_generate(struct be_adapter adapter, u8 mac)
	426	{
	427	u32 addr;
	428
	429	addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
	430
	431	mac[5] = (u8)(addr & 0xFF);
	432	mac[4] = (u8)((addr >> 8) & 0xFF);
	433	mac[3] = (u8)((addr >> 16) & 0xFF);
	434	mac[2] = 0xC9;
	435	mac[1] = 0x00;
	436	mac[0] = 0x00;
	437	}
	438
8788fdc2	439	extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
5fb379ee	440	u16 num_popped);
8788fdc2	441	extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
b31c50a7	442	extern void netdev_stats_update(struct be_adapter *adapter);
84517482	443	extern int be_load_fw(struct be_adapter adapter, u8 func);
6b7c5b94	444	#endif /* BE_H */