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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / b44.c
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753f4920 1/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
1da177e4
LT		 2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
753f4920
MB		 4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
8056bfaf 7 * Copyright (C) 2006 Broadcom Corporation.
eb032b98 8 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
1da177e4
LT		 9 *
10 * Distribute under GPL.
11 */
12
2fc96fff
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
1da177e4
LT		 15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/netdevice.h>
20#include <linux/ethtool.h>
21#include <linux/mii.h>
22#include <linux/if_ether.h>
72f4861e 23#include <linux/if_vlan.h>
1da177e4
LT		 24#include <linux/etherdevice.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/init.h>
89358f90 28#include <linux/dma-mapping.h>
753f4920 29#include <linux/ssb/ssb.h>
5a0e3ad6 30#include <linux/slab.h>
1da177e4
LT		 31
32#include <asm/uaccess.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35
753f4920 36
1da177e4
LT		 37#include "b44.h"
38
39#define DRV_MODULE_NAME "b44"
753f4920 40#define DRV_MODULE_VERSION "2.0"
1da177e4
LT		 41
42#define B44_DEF_MSG_ENABLE \
43 (NETIF_MSG_DRV | \
44 NETIF_MSG_PROBE | \
45 NETIF_MSG_LINK | \
46 NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | \
48 NETIF_MSG_IFUP | \
49 NETIF_MSG_RX_ERR | \
50 NETIF_MSG_TX_ERR)
51
52/* length of time before we decide the hardware is borked,
53 * and dev->tx_timeout() should be called to fix the problem
54 */
55#define B44_TX_TIMEOUT (5 * HZ)
56
57/* hardware minimum and maximum for a single frame's data payload */
58#define B44_MIN_MTU 60
59#define B44_MAX_MTU 1500
60
61#define B44_RX_RING_SIZE 512
62#define B44_DEF_RX_RING_PENDING 200
63#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
64 B44_RX_RING_SIZE)
65#define B44_TX_RING_SIZE 512
66#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
67#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
68 B44_TX_RING_SIZE)
1da177e4
LT		 69
70#define TX_RING_GAP(BP) \
71 (B44_TX_RING_SIZE - (BP)->tx_pending)
72#define TX_BUFFS_AVAIL(BP) \
73 (((BP)->tx_cons <= (BP)->tx_prod) ? \
74 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
75 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
76#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
77
4ca85795
FF		 78#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
79#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
1da177e4
LT		 80
81/* minimum number of free TX descriptors required to wake up TX process */
82#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
83
725ad800
GZ		 84/* b44 internal pattern match filter info */
85#define B44_PATTERN_BASE 0x400
86#define B44_PATTERN_SIZE 0x80
87#define B44_PMASK_BASE 0x600
88#define B44_PMASK_SIZE 0x10
89#define B44_MAX_PATTERNS 16
90#define B44_ETHIPV6UDP_HLEN 62
91#define B44_ETHIPV4UDP_HLEN 42
92
1da177e4 93static char version[] __devinitdata =
753f4920 94 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
1da177e4 95
753f4920
MB		 96MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
97MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
1da177e4
LT		 98MODULE_LICENSE("GPL");
99MODULE_VERSION(DRV_MODULE_VERSION);
100
101static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
102module_param(b44_debug, int, 0);
103MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
104
1da177e4 105
753f4920 106#ifdef CONFIG_B44_PCI
a3aa1884 107static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
753f4920
MB		 108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
110 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
111 { 0 } /* terminate list with empty entry */
112};
1da177e4
LT		 113MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114
753f4920
MB		 115static struct pci_driver b44_pci_driver = {
116 .name = DRV_MODULE_NAME,
117 .id_table = b44_pci_tbl,
118};
119#endif /* CONFIG_B44_PCI */
120
121static const struct ssb_device_id b44_ssb_tbl[] = {
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
123 SSB_DEVTABLE_END
124};
125MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126
1da177e4
LT		 127static void b44_halt(struct b44 *);
128static void b44_init_rings(struct b44 *);
5fc7d61a
MC		 129
130#define B44_FULL_RESET 1
131#define B44_FULL_RESET_SKIP_PHY 2
132#define B44_PARTIAL_RESET 3
fedb0eef
MB		 133#define B44_CHIP_RESET_FULL 4
134#define B44_CHIP_RESET_PARTIAL 5
5fc7d61a 135
00e8b3aa 136static void b44_init_hw(struct b44 *, int);
1da177e4 137
9f38c636 138static int dma_desc_sync_size;
753f4920 139static int instance;
9f38c636 140
3353930d
FR		 141static const char b44_gstrings[][ETH_GSTRING_LEN] = {
142#define _B44(x...) # x,
143B44_STAT_REG_DECLARE
144#undef _B44
145};
146
753f4920
MB		 147static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 dma_addr_t dma_base,
149 unsigned long offset,
150 enum dma_data_direction dir)
9f38c636 151{
39a6f4bc
FT		 152 dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
153 dma_desc_sync_size, dir);
9f38c636
JL		 154}
155
753f4920
MB		 156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
9f38c636 160{
39a6f4bc
FT		 161 dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
162 dma_desc_sync_size, dir);
9f38c636
JL		 163}
164
1da177e4
LT		 165static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
166{
753f4920 167 return ssb_read32(bp->sdev, reg);
1da177e4
LT		 168}
169
10badc21 170static inline void bw32(const struct b44 *bp,
1da177e4
LT		 171 unsigned long reg, unsigned long val)
172{
753f4920 173 ssb_write32(bp->sdev, reg, val);
1da177e4
LT		 174}
175
176static int b44_wait_bit(struct b44 *bp, unsigned long reg,
177 u32 bit, unsigned long timeout, const int clear)
178{
179 unsigned long i;
180
181 for (i = 0; i < timeout; i++) {
182 u32 val = br32(bp, reg);
183
184 if (clear && !(val & bit))
185 break;
186 if (!clear && (val & bit))
187 break;
188 udelay(10);
189 }
190 if (i == timeout) {
f6ca057f 191 if (net_ratelimit())
2fc96fff
JP		 192 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
193 bit, reg, clear ? "clear" : "set");
194
1da177e4
LT		 195 return -ENODEV;
196 }
197 return 0;
198}
199
753f4920 200static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 201{
202 u32 val;
203
753f4920
MB		 204 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
205 (index << CAM_CTRL_INDEX_SHIFT)));
1da177e4 206
753f4920 207 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4 208
753f4920 209 val = br32(bp, B44_CAM_DATA_LO);
1da177e4 210
753f4920
MB		 211 data[2] = (val >> 24) & 0xFF;
212 data[3] = (val >> 16) & 0xFF;
213 data[4] = (val >> 8) & 0xFF;
214 data[5] = (val >> 0) & 0xFF;
1da177e4 215
753f4920 216 val = br32(bp, B44_CAM_DATA_HI);
1da177e4 217
753f4920
MB		 218 data[0] = (val >> 8) & 0xFF;
219 data[1] = (val >> 0) & 0xFF;
1da177e4
LT		 220}
221
753f4920 222static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 223{
224 u32 val;
225
226 val = ((u32) data[2]) << 24;
227 val |= ((u32) data[3]) << 16;
228 val |= ((u32) data[4]) << 8;
229 val |= ((u32) data[5]) << 0;
230 bw32(bp, B44_CAM_DATA_LO, val);
10badc21 231 val = (CAM_DATA_HI_VALID |
1da177e4
LT		 232 (((u32) data[0]) << 8) |
233 (((u32) data[1]) << 0));
234 bw32(bp, B44_CAM_DATA_HI, val);
235 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
236 (index << CAM_CTRL_INDEX_SHIFT)));
10badc21 237 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4
LT		 238}
239
240static inline void __b44_disable_ints(struct b44 *bp)
241{
242 bw32(bp, B44_IMASK, 0);
243}
244
245static void b44_disable_ints(struct b44 *bp)
246{
247 __b44_disable_ints(bp);
248
249 /* Flush posted writes. */
250 br32(bp, B44_IMASK);
251}
252
253static void b44_enable_ints(struct b44 *bp)
254{
255 bw32(bp, B44_IMASK, bp->imask);
256}
257
753f4920 258static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
1da177e4
LT		 259{
260 int err;
261
262 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
263 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
264 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
753f4920 265 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 266 (reg << MDIO_DATA_RA_SHIFT) |
267 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
268 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
269 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
270
271 return err;
272}
273
753f4920 274static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
1da177e4
LT		 275{
276 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
277 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
278 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
753f4920 279 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 280 (reg << MDIO_DATA_RA_SHIFT) |
281 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
282 (val & MDIO_DATA_DATA)));
283 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
284}
285
753f4920
MB		 286static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
287{
288 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
289 return 0;
290
291 return __b44_readphy(bp, bp->phy_addr, reg, val);
292}
293
294static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
295{
296 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
297 return 0;
298
299 return __b44_writephy(bp, bp->phy_addr, reg, val);
300}
301
1da177e4 302/* miilib interface */
1da177e4
LT		 303static int b44_mii_read(struct net_device *dev, int phy_id, int location)
304{
305 u32 val;
306 struct b44 *bp = netdev_priv(dev);
753f4920 307 int rc = __b44_readphy(bp, phy_id, location, &val);
1da177e4
LT		 308 if (rc)
309 return 0xffffffff;
310 return val;
311}
312
313static void b44_mii_write(struct net_device *dev, int phy_id, int location,
314 int val)
315{
316 struct b44 *bp = netdev_priv(dev);
753f4920 317 __b44_writephy(bp, phy_id, location, val);
1da177e4
LT		 318}
319
320static int b44_phy_reset(struct b44 *bp)
321{
322 u32 val;
323 int err;
324
753f4920
MB		 325 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
326 return 0;
1da177e4
LT		 327 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
328 if (err)
329 return err;
330 udelay(100);
331 err = b44_readphy(bp, MII_BMCR, &val);
332 if (!err) {
333 if (val & BMCR_RESET) {
2fc96fff 334 netdev_err(bp->dev, "PHY Reset would not complete\n");
1da177e4
LT		 335 err = -ENODEV;
336 }
337 }
338
8850dce1 339 return err;
1da177e4
LT		 340}
341
342static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
343{
344 u32 val;
345
346 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
347 bp->flags |= pause_flags;
348
349 val = br32(bp, B44_RXCONFIG);
350 if (pause_flags & B44_FLAG_RX_PAUSE)
351 val |= RXCONFIG_FLOW;
352 else
353 val &= ~RXCONFIG_FLOW;
354 bw32(bp, B44_RXCONFIG, val);
355
356 val = br32(bp, B44_MAC_FLOW);
357 if (pause_flags & B44_FLAG_TX_PAUSE)
358 val |= (MAC_FLOW_PAUSE_ENAB |
359 (0xc0 & MAC_FLOW_RX_HI_WATER));
360 else
361 val &= ~MAC_FLOW_PAUSE_ENAB;
362 bw32(bp, B44_MAC_FLOW, val);
363}
364
365static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
366{
10badc21 367 u32 pause_enab = 0;
2b474cf5
GZ		 368
369 /* The driver supports only rx pause by default because
10badc21
JG		 370 the b44 mac tx pause mechanism generates excessive
371 pause frames.
2b474cf5
GZ		 372 Use ethtool to turn on b44 tx pause if necessary.
373 */
374 if ((local & ADVERTISE_PAUSE_CAP) &&
10badc21 375 (local & ADVERTISE_PAUSE_ASYM)){
2b474cf5
GZ		 376 if ((remote & LPA_PAUSE_ASYM) &&
377 !(remote & LPA_PAUSE_CAP))
378 pause_enab |= B44_FLAG_RX_PAUSE;
1da177e4
LT		 379 }
380
381 __b44_set_flow_ctrl(bp, pause_enab);
382}
383
6c08af03
HM		 384#ifdef CONFIG_BCM47XX
385#include <asm/mach-bcm47xx/nvram.h>
753f4920
MB		 386static void b44_wap54g10_workaround(struct b44 *bp)
387{
6c08af03 388 char buf[20];
753f4920
MB		 389 u32 val;
390 int err;
391
392 /*
393 * workaround for bad hardware design in Linksys WAP54G v1.0
394 * see https://dev.openwrt.org/ticket/146
395 * check and reset bit "isolate"
396 */
6c08af03 397 if (nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
753f4920 398 return;
6c08af03 399 if (simple_strtoul(buf, NULL, 0) == 2) {
753f4920
MB		 400 err = __b44_readphy(bp, 0, MII_BMCR, &val);
401 if (err)
402 goto error;
403 if (!(val & BMCR_ISOLATE))
404 return;
405 val &= ~BMCR_ISOLATE;
406 err = __b44_writephy(bp, 0, MII_BMCR, val);
407 if (err)
408 goto error;
409 }
410 return;
411error:
2fc96fff 412 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
753f4920
MB		 413}
414#else
415static inline void b44_wap54g10_workaround(struct b44 *bp)
416{
417}
418#endif
419
1da177e4
LT		 420static int b44_setup_phy(struct b44 *bp)
421{
422 u32 val;
423 int err;
424
753f4920
MB		 425 b44_wap54g10_workaround(bp);
426
427 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
428 return 0;
1da177e4
LT		 429 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
430 goto out;
431 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
432 val & MII_ALEDCTRL_ALLMSK)) != 0)
433 goto out;
434 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
435 goto out;
436 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
437 val | MII_TLEDCTRL_ENABLE)) != 0)
438 goto out;
439
440 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
441 u32 adv = ADVERTISE_CSMA;
442
443 if (bp->flags & B44_FLAG_ADV_10HALF)
444 adv |= ADVERTISE_10HALF;
445 if (bp->flags & B44_FLAG_ADV_10FULL)
446 adv |= ADVERTISE_10FULL;
447 if (bp->flags & B44_FLAG_ADV_100HALF)
448 adv |= ADVERTISE_100HALF;
449 if (bp->flags & B44_FLAG_ADV_100FULL)
450 adv |= ADVERTISE_100FULL;
451
452 if (bp->flags & B44_FLAG_PAUSE_AUTO)
453 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
454
455 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
456 goto out;
457 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
458 BMCR_ANRESTART))) != 0)
459 goto out;
460 } else {
461 u32 bmcr;
462
463 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
464 goto out;
465 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
466 if (bp->flags & B44_FLAG_100_BASE_T)
467 bmcr |= BMCR_SPEED100;
468 if (bp->flags & B44_FLAG_FULL_DUPLEX)
469 bmcr |= BMCR_FULLDPLX;
470 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
471 goto out;
472
473 /* Since we will not be negotiating there is no safe way
474 * to determine if the link partner supports flow control
475 * or not. So just disable it completely in this case.
476 */
477 b44_set_flow_ctrl(bp, 0, 0);
478 }
479
480out:
481 return err;
482}
483
484static void b44_stats_update(struct b44 *bp)
485{
486 unsigned long reg;
487 u32 *val;
488
489 val = &bp->hw_stats.tx_good_octets;
490 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
491 *val++ += br32(bp, reg);
492 }
3353930d
FR		 493
494 /* Pad */
495 reg += 8*4UL;
496
1da177e4
LT		 497 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
498 *val++ += br32(bp, reg);
499 }
500}
501
502static void b44_link_report(struct b44 *bp)
503{
504 if (!netif_carrier_ok(bp->dev)) {
2fc96fff 505 netdev_info(bp->dev, "Link is down\n");
1da177e4 506 } else {
2fc96fff
JP		 507 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
508 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
509 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
510
511 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
512 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
513 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
1da177e4
LT		 514 }
515}
516
517static void b44_check_phy(struct b44 *bp)
518{
519 u32 bmsr, aux;
520
753f4920
MB		 521 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
522 bp->flags |= B44_FLAG_100_BASE_T;
523 bp->flags |= B44_FLAG_FULL_DUPLEX;
524 if (!netif_carrier_ok(bp->dev)) {
525 u32 val = br32(bp, B44_TX_CTRL);
526 val |= TX_CTRL_DUPLEX;
527 bw32(bp, B44_TX_CTRL, val);
528 netif_carrier_on(bp->dev);
529 b44_link_report(bp);
530 }
531 return;
532 }
533
1da177e4
LT		 534 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
535 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
536 (bmsr != 0xffff)) {
537 if (aux & MII_AUXCTRL_SPEED)
538 bp->flags |= B44_FLAG_100_BASE_T;
539 else
540 bp->flags &= ~B44_FLAG_100_BASE_T;
541 if (aux & MII_AUXCTRL_DUPLEX)
542 bp->flags |= B44_FLAG_FULL_DUPLEX;
543 else
544 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
545
546 if (!netif_carrier_ok(bp->dev) &&
547 (bmsr & BMSR_LSTATUS)) {
548 u32 val = br32(bp, B44_TX_CTRL);
549 u32 local_adv, remote_adv;
550
551 if (bp->flags & B44_FLAG_FULL_DUPLEX)
552 val |= TX_CTRL_DUPLEX;
553 else
554 val &= ~TX_CTRL_DUPLEX;
555 bw32(bp, B44_TX_CTRL, val);
556
557 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
558 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
559 !b44_readphy(bp, MII_LPA, &remote_adv))
560 b44_set_flow_ctrl(bp, local_adv, remote_adv);
561
562 /* Link now up */
563 netif_carrier_on(bp->dev);
564 b44_link_report(bp);
565 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
566 /* Link now down */
567 netif_carrier_off(bp->dev);
568 b44_link_report(bp);
569 }
570
571 if (bmsr & BMSR_RFAULT)
2fc96fff 572 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
1da177e4 573 if (bmsr & BMSR_JCD)
2fc96fff 574 netdev_warn(bp->dev, "Jabber detected in PHY\n");
1da177e4
LT		 575 }
576}
577
578static void b44_timer(unsigned long __opaque)
579{
580 struct b44 *bp = (struct b44 *) __opaque;
581
582 spin_lock_irq(&bp->lock);
583
584 b44_check_phy(bp);
585
586 b44_stats_update(bp);
587
588 spin_unlock_irq(&bp->lock);
589
a72a8179 590 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
1da177e4
LT		 591}
592
593static void b44_tx(struct b44 *bp)
594{
595 u32 cur, cons;
596
597 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
598 cur /= sizeof(struct dma_desc);
599
600 /* XXX needs updating when NETIF_F_SG is supported */
601 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
602 struct ring_info *rp = &bp->tx_buffers[cons];
603 struct sk_buff *skb = rp->skb;
604
5d9428de 605 BUG_ON(skb == NULL);
1da177e4 606
39a6f4bc
FT		 607 dma_unmap_single(bp->sdev->dma_dev,
608 rp->mapping,
609 skb->len,
610 DMA_TO_DEVICE);
1da177e4
LT		 611 rp->skb = NULL;
612 dev_kfree_skb_irq(skb);
613 }
614
615 bp->tx_cons = cons;
616 if (netif_queue_stopped(bp->dev) &&
617 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
618 netif_wake_queue(bp->dev);
619
620 bw32(bp, B44_GPTIMER, 0);
621}
622
623/* Works like this. This chip writes a 'struct rx_header" 30 bytes
624 * before the DMA address you give it. So we allocate 30 more bytes
625 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
626 * point the chip at 30 bytes past where the rx_header will go.
627 */
628static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
629{
630 struct dma_desc *dp;
631 struct ring_info *src_map, *map;
632 struct rx_header *rh;
633 struct sk_buff *skb;
634 dma_addr_t mapping;
635 int dest_idx;
636 u32 ctrl;
637
638 src_map = NULL;
639 if (src_idx >= 0)
640 src_map = &bp->rx_buffers[src_idx];
641 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
642 map = &bp->rx_buffers[dest_idx];
bf0dcbd9 643 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
1da177e4
LT		 644 if (skb == NULL)
645 return -ENOMEM;
646
39a6f4bc
FT		 647 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
648 RX_PKT_BUF_SZ,
649 DMA_FROM_DEVICE);
1da177e4
LT		 650
651 /* Hardware bug work-around, the chip is unable to do PCI DMA
652 to/from anything above 1GB :-( */
39a6f4bc 653 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
28b76796 654 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
1da177e4 655 /* Sigh... */
39a6f4bc
FT		 656 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
657 dma_unmap_single(bp->sdev->dma_dev, mapping,
f225763a 658 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
1da177e4 659 dev_kfree_skb_any(skb);
bf0dcbd9 660 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
1da177e4
LT		 661 if (skb == NULL)
662 return -ENOMEM;
39a6f4bc
FT		 663 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
664 RX_PKT_BUF_SZ,
665 DMA_FROM_DEVICE);
666 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
667 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
668 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
669 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
1da177e4
LT		 670 dev_kfree_skb_any(skb);
671 return -ENOMEM;
672 }
a58c891a 673 bp->force_copybreak = 1;
1da177e4
LT		 674 }
675
72f4861e 676 rh = (struct rx_header *) skb->data;
1da177e4 677
1da177e4
LT		 678 rh->len = 0;
679 rh->flags = 0;
680
681 map->skb = skb;
753f4920 682 map->mapping = mapping;
1da177e4
LT		 683
684 if (src_map != NULL)
685 src_map->skb = NULL;
686
4ca85795 687 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
1da177e4
LT		 688 if (dest_idx == (B44_RX_RING_SIZE - 1))
689 ctrl |= DESC_CTRL_EOT;
690
691 dp = &bp->rx_ring[dest_idx];
692 dp->ctrl = cpu_to_le32(ctrl);
4ca85795 693 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
1da177e4 694
9f38c636 695 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 696 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 697 dest_idx * sizeof(*dp),
753f4920 698 DMA_BIDIRECTIONAL);
9f38c636 699
1da177e4
LT		 700 return RX_PKT_BUF_SZ;
701}
702
703static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
704{
705 struct dma_desc *src_desc, *dest_desc;
706 struct ring_info *src_map, *dest_map;
707 struct rx_header *rh;
708 int dest_idx;
a7bed27d 709 __le32 ctrl;
1da177e4
LT		 710
711 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
712 dest_desc = &bp->rx_ring[dest_idx];
713 dest_map = &bp->rx_buffers[dest_idx];
714 src_desc = &bp->rx_ring[src_idx];
715 src_map = &bp->rx_buffers[src_idx];
716
717 dest_map->skb = src_map->skb;
718 rh = (struct rx_header *) src_map->skb->data;
719 rh->len = 0;
720 rh->flags = 0;
753f4920 721 dest_map->mapping = src_map->mapping;
1da177e4 722
9f38c636 723 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 724 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 725 src_idx * sizeof(*src_desc),
753f4920 726 DMA_BIDIRECTIONAL);
9f38c636 727
1da177e4
LT		 728 ctrl = src_desc->ctrl;
729 if (dest_idx == (B44_RX_RING_SIZE - 1))
730 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
731 else
732 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
733
734 dest_desc->ctrl = ctrl;
735 dest_desc->addr = src_desc->addr;
9f38c636 736
1da177e4
LT		 737 src_map->skb = NULL;
738
9f38c636 739 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920 740 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
5d4d9e8a 741 dest_idx * sizeof(*dest_desc),
753f4920 742 DMA_BIDIRECTIONAL);
9f38c636 743
39a6f4bc
FT		 744 dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
745 RX_PKT_BUF_SZ,
746 DMA_FROM_DEVICE);
1da177e4
LT		 747}
748
749static int b44_rx(struct b44 *bp, int budget)
750{
751 int received;
752 u32 cons, prod;
753
754 received = 0;
755 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
756 prod /= sizeof(struct dma_desc);
757 cons = bp->rx_cons;
758
759 while (cons != prod && budget > 0) {
760 struct ring_info *rp = &bp->rx_buffers[cons];
761 struct sk_buff *skb = rp->skb;
753f4920 762 dma_addr_t map = rp->mapping;
1da177e4
LT		 763 struct rx_header *rh;
764 u16 len;
765
39a6f4bc
FT		 766 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
767 RX_PKT_BUF_SZ,
768 DMA_FROM_DEVICE);
1da177e4 769 rh = (struct rx_header *) skb->data;
a7bed27d 770 len = le16_to_cpu(rh->len);
72f4861e 771 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
1da177e4
LT		 772 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
773 drop_it:
774 b44_recycle_rx(bp, cons, bp->rx_prod);
775 drop_it_no_recycle:
553e2335 776 bp->dev->stats.rx_dropped++;
1da177e4
LT		 777 goto next_pkt;
778 }
779
780 if (len == 0) {
781 int i = 0;
782
783 do {
784 udelay(2);
785 barrier();
a7bed27d 786 len = le16_to_cpu(rh->len);
1da177e4
LT		 787 } while (len == 0 && i++ < 5);
788 if (len == 0)
789 goto drop_it;
790 }
791
792 /* Omit CRC. */
793 len -= 4;
794
a58c891a 795 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
1da177e4
LT		 796 int skb_size;
797 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
798 if (skb_size < 0)
799 goto drop_it;
39a6f4bc
FT		 800 dma_unmap_single(bp->sdev->dma_dev, map,
801 skb_size, DMA_FROM_DEVICE);
1da177e4 802 /* Leave out rx_header */
4ca85795
FF		 803 skb_put(skb, len + RX_PKT_OFFSET);
804 skb_pull(skb, RX_PKT_OFFSET);
1da177e4
LT		 805 } else {
806 struct sk_buff *copy_skb;
807
808 b44_recycle_rx(bp, cons, bp->rx_prod);
53639207 809 copy_skb = netdev_alloc_skb(bp->dev, len + 2);
1da177e4
LT		 810 if (copy_skb == NULL)
811 goto drop_it_no_recycle;
812
1da177e4
LT		 813 skb_reserve(copy_skb, 2);
814 skb_put(copy_skb, len);
815 /* DMA sync done above, copy just the actual packet */
72f4861e 816 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
d626f62b 817 copy_skb->data, len);
1da177e4
LT		 818 skb = copy_skb;
819 }
bc8acf2c 820 skb_checksum_none_assert(skb);
1da177e4
LT		 821 skb->protocol = eth_type_trans(skb, bp->dev);
822 netif_receive_skb(skb);
1da177e4
LT		 823 received++;
824 budget--;
825 next_pkt:
826 bp->rx_prod = (bp->rx_prod + 1) &
827 (B44_RX_RING_SIZE - 1);
828 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
829 }
830
831 bp->rx_cons = cons;
832 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
833
834 return received;
835}
836
bea3348e 837static int b44_poll(struct napi_struct *napi, int budget)
1da177e4 838{
bea3348e 839 struct b44 *bp = container_of(napi, struct b44, napi);
bea3348e 840 int work_done;
e99b1f04 841 unsigned long flags;
1da177e4 842
e99b1f04 843 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 844
845 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
846 /* spin_lock(&bp->tx_lock); */
847 b44_tx(bp);
848 /* spin_unlock(&bp->tx_lock); */
849 }
32737e93
ML		 850 if (bp->istat & ISTAT_RFO) { /* fast recovery, in ~20msec */
851 bp->istat &= ~ISTAT_RFO;
852 b44_disable_ints(bp);
853 ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
854 b44_init_rings(bp);
855 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
856 netif_wake_queue(bp->dev);
857 }
858
e99b1f04 859 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 860
bea3348e
SH		 861 work_done = 0;
862 if (bp->istat & ISTAT_RX)
863 work_done += b44_rx(bp, budget);
1da177e4
LT		 864
865 if (bp->istat & ISTAT_ERRORS) {
d15e9c4d 866 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 867 b44_halt(bp);
868 b44_init_rings(bp);
5fc7d61a 869 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
1da177e4 870 netif_wake_queue(bp->dev);
d15e9c4d 871 spin_unlock_irqrestore(&bp->lock, flags);
bea3348e 872 work_done = 0;
1da177e4
LT		 873 }
874
bea3348e 875 if (work_done < budget) {
288379f0 876 napi_complete(napi);
1da177e4
LT		 877 b44_enable_ints(bp);
878 }
879
bea3348e 880 return work_done;
1da177e4
LT		 881}
882
7d12e780 883static irqreturn_t b44_interrupt(int irq, void *dev_id)
1da177e4
LT		 884{
885 struct net_device *dev = dev_id;
886 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 887 u32 istat, imask;
888 int handled = 0;
889
65b984f2 890 spin_lock(&bp->lock);
1da177e4
LT		 891
892 istat = br32(bp, B44_ISTAT);
893 imask = br32(bp, B44_IMASK);
894
e78181fe
JB		 895 /* The interrupt mask register controls which interrupt bits
896 * will actually raise an interrupt to the CPU when set by hw/firmware,
897 * but doesn't mask off the bits.
1da177e4
LT		 898 */
899 istat &= imask;
900 if (istat) {
901 handled = 1;
ba5eec9c
FR		 902
903 if (unlikely(!netif_running(dev))) {
2fc96fff 904 netdev_info(dev, "late interrupt\n");
ba5eec9c
FR		 905 goto irq_ack;
906 }
907
288379f0 908 if (napi_schedule_prep(&bp->napi)) {
1da177e4
LT		 909 /* NOTE: These writes are posted by the readback of
910 * the ISTAT register below.
911 */
912 bp->istat = istat;
913 __b44_disable_ints(bp);
288379f0 914 __napi_schedule(&bp->napi);
1da177e4
LT		 915 }
916
ba5eec9c 917irq_ack:
1da177e4
LT		 918 bw32(bp, B44_ISTAT, istat);
919 br32(bp, B44_ISTAT);
920 }
65b984f2 921 spin_unlock(&bp->lock);
1da177e4
LT		 922 return IRQ_RETVAL(handled);
923}
924
925static void b44_tx_timeout(struct net_device *dev)
926{
927 struct b44 *bp = netdev_priv(dev);
928
2fc96fff 929 netdev_err(dev, "transmit timed out, resetting\n");
1da177e4
LT		 930
931 spin_lock_irq(&bp->lock);
932
933 b44_halt(bp);
934 b44_init_rings(bp);
5fc7d61a 935 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 936
937 spin_unlock_irq(&bp->lock);
938
939 b44_enable_ints(bp);
940
941 netif_wake_queue(dev);
942}
943
61357325 944static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 945{
946 struct b44 *bp = netdev_priv(dev);
c7193693 947 int rc = NETDEV_TX_OK;
1da177e4
LT		 948 dma_addr_t mapping;
949 u32 len, entry, ctrl;
22580f89 950 unsigned long flags;
1da177e4
LT		 951
952 len = skb->len;
22580f89 953 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 954
955 /* This is a hard error, log it. */
956 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
957 netif_stop_queue(dev);
2fc96fff 958 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
c7193693 959 goto err_out;
1da177e4
LT		 960 }
961
39a6f4bc
FT		 962 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
963 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
f65a7177
SH		 964 struct sk_buff *bounce_skb;
965
1da177e4 966 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
39a6f4bc
FT		 967 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
968 dma_unmap_single(bp->sdev->dma_dev, mapping, len,
f225763a 969 DMA_TO_DEVICE);
1da177e4 970
9034f77b 971 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
1da177e4 972 if (!bounce_skb)
c7193693 973 goto err_out;
1da177e4 974
39a6f4bc
FT		 975 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
976 len, DMA_TO_DEVICE);
977 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
978 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
979 dma_unmap_single(bp->sdev->dma_dev, mapping,
f225763a 980 len, DMA_TO_DEVICE);
1da177e4 981 dev_kfree_skb_any(bounce_skb);
c7193693 982 goto err_out;
1da177e4
LT		 983 }
984
f65a7177 985 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1da177e4
LT		 986 dev_kfree_skb_any(skb);
987 skb = bounce_skb;
988 }
989
990 entry = bp->tx_prod;
991 bp->tx_buffers[entry].skb = skb;
753f4920 992 bp->tx_buffers[entry].mapping = mapping;
1da177e4
LT		 993
994 ctrl = (len & DESC_CTRL_LEN);
995 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
996 if (entry == (B44_TX_RING_SIZE - 1))
997 ctrl |= DESC_CTRL_EOT;
998
999 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1000 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1001
9f38c636 1002 if (bp->flags & B44_FLAG_TX_RING_HACK)
753f4920
MB		 1003 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1004 entry * sizeof(bp->tx_ring[0]),
1005 DMA_TO_DEVICE);
9f38c636 1006
1da177e4
LT		 1007 entry = NEXT_TX(entry);
1008
1009 bp->tx_prod = entry;
1010
1011 wmb();
1012
1013 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1014 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1015 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1016 if (bp->flags & B44_FLAG_REORDER_BUG)
1017 br32(bp, B44_DMATX_PTR);
1018
1019 if (TX_BUFFS_AVAIL(bp) < 1)
1020 netif_stop_queue(dev);
1021
c7193693 1022out_unlock:
22580f89 1023 spin_unlock_irqrestore(&bp->lock, flags);
1da177e4 1024
c7193693 1025 return rc;
1da177e4 1026
c7193693
FR		 1027err_out:
1028 rc = NETDEV_TX_BUSY;
1029 goto out_unlock;
1da177e4
LT		 1030}
1031
1032static int b44_change_mtu(struct net_device *dev, int new_mtu)
1033{
1034 struct b44 *bp = netdev_priv(dev);
1035
1036 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1037 return -EINVAL;
1038
1039 if (!netif_running(dev)) {
1040 /* We'll just catch it later when the
1041 * device is up'd.
1042 */
1043 dev->mtu = new_mtu;
1044 return 0;
1045 }
1046
1047 spin_lock_irq(&bp->lock);
1048 b44_halt(bp);
1049 dev->mtu = new_mtu;
1050 b44_init_rings(bp);
5fc7d61a 1051 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1052 spin_unlock_irq(&bp->lock);
1053
1054 b44_enable_ints(bp);
10badc21 1055
1da177e4
LT		 1056 return 0;
1057}
1058
1059/* Free up pending packets in all rx/tx rings.
1060 *
1061 * The chip has been shut down and the driver detached from
1062 * the networking, so no interrupts or new tx packets will
1063 * end up in the driver. bp->lock is not held and we are not
1064 * in an interrupt context and thus may sleep.
1065 */
1066static void b44_free_rings(struct b44 *bp)
1067{
1068 struct ring_info *rp;
1069 int i;
1070
1071 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1072 rp = &bp->rx_buffers[i];
1073
1074 if (rp->skb == NULL)
1075 continue;
39a6f4bc
FT		 1076 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1077 DMA_FROM_DEVICE);
1da177e4
LT		 1078 dev_kfree_skb_any(rp->skb);
1079 rp->skb = NULL;
1080 }
1081
1082 /* XXX needs changes once NETIF_F_SG is set... */
1083 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1084 rp = &bp->tx_buffers[i];
1085
1086 if (rp->skb == NULL)
1087 continue;
39a6f4bc
FT		 1088 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1089 DMA_TO_DEVICE);
1da177e4
LT		 1090 dev_kfree_skb_any(rp->skb);
1091 rp->skb = NULL;
1092 }
1093}
1094
1095/* Initialize tx/rx rings for packet processing.
1096 *
1097 * The chip has been shut down and the driver detached from
1098 * the networking, so no interrupts or new tx packets will
874a6214 1099 * end up in the driver.
1da177e4
LT		 1100 */
1101static void b44_init_rings(struct b44 *bp)
1102{
1103 int i;
1104
1105 b44_free_rings(bp);
1106
1107 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1108 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1109
9f38c636 1110 if (bp->flags & B44_FLAG_RX_RING_HACK)
39a6f4bc
FT		 1111 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1112 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
9f38c636
JL		 1113
1114 if (bp->flags & B44_FLAG_TX_RING_HACK)
39a6f4bc
FT		 1115 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1116 DMA_TABLE_BYTES, DMA_TO_DEVICE);
9f38c636 1117
1da177e4
LT		 1118 for (i = 0; i < bp->rx_pending; i++) {
1119 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1120 break;
1121 }
1122}
1123
1124/*
1125 * Must not be invoked with interrupt sources disabled and
1126 * the hardware shutdown down.
1127 */
1128static void b44_free_consistent(struct b44 *bp)
1129{
b4558ea9
JJ		 1130 kfree(bp->rx_buffers);
1131 bp->rx_buffers = NULL;
1132 kfree(bp->tx_buffers);
1133 bp->tx_buffers = NULL;
1da177e4 1134 if (bp->rx_ring) {
9f38c636 1135 if (bp->flags & B44_FLAG_RX_RING_HACK) {
39a6f4bc
FT		 1136 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1137 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
9f38c636
JL		 1138 kfree(bp->rx_ring);
1139 } else
39a6f4bc
FT		 1140 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1141 bp->rx_ring, bp->rx_ring_dma);
1da177e4 1142 bp->rx_ring = NULL;
9f38c636 1143 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1144 }
1145 if (bp->tx_ring) {
9f38c636 1146 if (bp->flags & B44_FLAG_TX_RING_HACK) {
39a6f4bc
FT		 1147 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1148 DMA_TABLE_BYTES, DMA_TO_DEVICE);
9f38c636
JL		 1149 kfree(bp->tx_ring);
1150 } else
39a6f4bc
FT		 1151 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1152 bp->tx_ring, bp->tx_ring_dma);
1da177e4 1153 bp->tx_ring = NULL;
9f38c636 1154 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1155 }
1156}
1157
1158/*
1159 * Must not be invoked with interrupt sources disabled and
1160 * the hardware shutdown down. Can sleep.
1161 */
753f4920 1162static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1da177e4
LT		 1163{
1164 int size;
1165
1166 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
753f4920 1167 bp->rx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1168 if (!bp->rx_buffers)
1169 goto out_err;
1da177e4
LT		 1170
1171 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
753f4920 1172 bp->tx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1173 if (!bp->tx_buffers)
1174 goto out_err;
1da177e4
LT		 1175
1176 size = DMA_TABLE_BYTES;
39a6f4bc
FT		 1177 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1178 &bp->rx_ring_dma, gfp);
9f38c636
JL		 1179 if (!bp->rx_ring) {
1180 /* Allocation may have failed due to pci_alloc_consistent
1181 insisting on use of GFP_DMA, which is more restrictive
1182 than necessary... */
1183 struct dma_desc *rx_ring;
1184 dma_addr_t rx_ring_dma;
1185
753f4920 1186 rx_ring = kzalloc(size, gfp);
874a6214 1187 if (!rx_ring)
9f38c636
JL		 1188 goto out_err;
1189
39a6f4bc
FT		 1190 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1191 DMA_TABLE_BYTES,
1192 DMA_BIDIRECTIONAL);
9f38c636 1193
39a6f4bc 1194 if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
28b76796 1195 rx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1196 kfree(rx_ring);
1197 goto out_err;
1198 }
1199
1200 bp->rx_ring = rx_ring;
1201 bp->rx_ring_dma = rx_ring_dma;
1202 bp->flags |= B44_FLAG_RX_RING_HACK;
1203 }
1da177e4 1204
39a6f4bc
FT		 1205 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1206 &bp->tx_ring_dma, gfp);
9f38c636 1207 if (!bp->tx_ring) {
f225763a 1208 /* Allocation may have failed due to ssb_dma_alloc_consistent
9f38c636
JL		 1209 insisting on use of GFP_DMA, which is more restrictive
1210 than necessary... */
1211 struct dma_desc *tx_ring;
1212 dma_addr_t tx_ring_dma;
1213
753f4920 1214 tx_ring = kzalloc(size, gfp);
874a6214 1215 if (!tx_ring)
9f38c636
JL		 1216 goto out_err;
1217
39a6f4bc
FT		 1218 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1219 DMA_TABLE_BYTES,
1220 DMA_TO_DEVICE);
9f38c636 1221
39a6f4bc 1222 if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
28b76796 1223 tx_ring_dma + size > DMA_BIT_MASK(30)) {
9f38c636
JL		 1224 kfree(tx_ring);
1225 goto out_err;
1226 }
1227
1228 bp->tx_ring = tx_ring;
1229 bp->tx_ring_dma = tx_ring_dma;
1230 bp->flags |= B44_FLAG_TX_RING_HACK;
1231 }
1da177e4
LT		 1232
1233 return 0;
1234
1235out_err:
1236 b44_free_consistent(bp);
1237 return -ENOMEM;
1238}
1239
1240/* bp->lock is held. */
1241static void b44_clear_stats(struct b44 *bp)
1242{
1243 unsigned long reg;
1244
1245 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1246 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1247 br32(bp, reg);
1248 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1249 br32(bp, reg);
1250}
1251
1252/* bp->lock is held. */
fedb0eef 1253static void b44_chip_reset(struct b44 *bp, int reset_kind)
1da177e4 1254{
753f4920 1255 struct ssb_device *sdev = bp->sdev;
f8af11af 1256 bool was_enabled;
753f4920 1257
f8af11af
MB		 1258 was_enabled = ssb_device_is_enabled(bp->sdev);
1259
1260 ssb_device_enable(bp->sdev, 0);
1261 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1262
1263 if (was_enabled) {
1da177e4
LT		 1264 bw32(bp, B44_RCV_LAZY, 0);
1265 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
40ee8c76 1266 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1da177e4
LT		 1267 bw32(bp, B44_DMATX_CTRL, 0);
1268 bp->tx_prod = bp->tx_cons = 0;
1269 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1270 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1271 100, 0);
1272 }
1273 bw32(bp, B44_DMARX_CTRL, 0);
1274 bp->rx_prod = bp->rx_cons = 0;
f8af11af 1275 }
1da177e4
LT		 1276
1277 b44_clear_stats(bp);
1278
fedb0eef
MB		 1279 /*
1280 * Don't enable PHY if we are doing a partial reset
1281 * we are probably going to power down
1282 */
1283 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1284 return;
1285
753f4920
MB		 1286 switch (sdev->bus->bustype) {
1287 case SSB_BUSTYPE_SSB:
1288 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
39506a55
JL		 1289 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1290 B44_MDC_RATIO)
753f4920
MB		 1291 & MDIO_CTRL_MAXF_MASK)));
1292 break;
1293 case SSB_BUSTYPE_PCI:
753f4920
MB		 1294 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1295 (0x0d & MDIO_CTRL_MAXF_MASK)));
1296 break;
98a1e2a9
MB		 1297 case SSB_BUSTYPE_PCMCIA:
1298 case SSB_BUSTYPE_SDIO:
1299 WARN_ON(1); /* A device with this bus does not exist. */
1300 break;
753f4920
MB		 1301 }
1302
1da177e4
LT		 1303 br32(bp, B44_MDIO_CTRL);
1304
1305 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1306 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1307 br32(bp, B44_ENET_CTRL);
1308 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1309 } else {
1310 u32 val = br32(bp, B44_DEVCTRL);
1311
1312 if (val & DEVCTRL_EPR) {
1313 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1314 br32(bp, B44_DEVCTRL);
1315 udelay(100);
1316 }
1317 bp->flags |= B44_FLAG_INTERNAL_PHY;
1318 }
1319}
1320
1321/* bp->lock is held. */
1322static void b44_halt(struct b44 *bp)
1323{
1324 b44_disable_ints(bp);
fedb0eef
MB		 1325 /* reset PHY */
1326 b44_phy_reset(bp);
1327 /* power down PHY */
2fc96fff 1328 netdev_info(bp->dev, "powering down PHY\n");
fedb0eef
MB		 1329 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1330 /* now reset the chip, but without enabling the MAC&PHY
1331 * part of it. This has to be done _after_ we shut down the PHY */
1332 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1da177e4
LT		 1333}
1334
1335/* bp->lock is held. */
1336static void __b44_set_mac_addr(struct b44 *bp)
1337{
1338 bw32(bp, B44_CAM_CTRL, 0);
1339 if (!(bp->dev->flags & IFF_PROMISC)) {
1340 u32 val;
1341
1342 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1343 val = br32(bp, B44_CAM_CTRL);
1344 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1345 }
1346}
1347
1348static int b44_set_mac_addr(struct net_device *dev, void *p)
1349{
1350 struct b44 *bp = netdev_priv(dev);
1351 struct sockaddr *addr = p;
753f4920 1352 u32 val;
1da177e4
LT		 1353
1354 if (netif_running(dev))
1355 return -EBUSY;
1356
391fc09a
GZ		 1357 if (!is_valid_ether_addr(addr->sa_data))
1358 return -EINVAL;
1359
1da177e4
LT		 1360 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1361
1362 spin_lock_irq(&bp->lock);
753f4920
MB		 1363
1364 val = br32(bp, B44_RXCONFIG);
1365 if (!(val & RXCONFIG_CAM_ABSENT))
1366 __b44_set_mac_addr(bp);
1367
1da177e4
LT		 1368 spin_unlock_irq(&bp->lock);
1369
1370 return 0;
1371}
1372
1373/* Called at device open time to get the chip ready for
1374 * packet processing. Invoked with bp->lock held.
1375 */
1376static void __b44_set_rx_mode(struct net_device *);
5fc7d61a 1377static void b44_init_hw(struct b44 *bp, int reset_kind)
1da177e4
LT		 1378{
1379 u32 val;
1380
fedb0eef 1381 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5fc7d61a 1382 if (reset_kind == B44_FULL_RESET) {
00e8b3aa
GZ		 1383 b44_phy_reset(bp);
1384 b44_setup_phy(bp);
1385 }
1da177e4
LT		 1386
1387 /* Enable CRC32, set proper LED modes and power on PHY */
1388 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1389 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1390
1391 /* This sets the MAC address too. */
1392 __b44_set_rx_mode(bp->dev);
1393
1394 /* MTU + eth header + possible VLAN tag + struct rx_header */
1395 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1396 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1397
1398 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
5fc7d61a
MC		 1399 if (reset_kind == B44_PARTIAL_RESET) {
1400 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1401 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
5fc7d61a 1402 } else {
00e8b3aa
GZ		 1403 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1404 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1405 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1406 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
00e8b3aa 1407 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1da177e4 1408
00e8b3aa
GZ		 1409 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1410 bp->rx_prod = bp->rx_pending;
1da177e4 1411
00e8b3aa 1412 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
00e8b3aa 1413 }
1da177e4
LT		 1414
1415 val = br32(bp, B44_ENET_CTRL);
1416 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1417}
1418
1419static int b44_open(struct net_device *dev)
1420{
1421 struct b44 *bp = netdev_priv(dev);
1422 int err;
1423
753f4920 1424 err = b44_alloc_consistent(bp, GFP_KERNEL);
1da177e4 1425 if (err)
6c2f4267 1426 goto out;
1da177e4 1427
bea3348e
SH		 1428 napi_enable(&bp->napi);
1429
1da177e4 1430 b44_init_rings(bp);
5fc7d61a 1431 b44_init_hw(bp, B44_FULL_RESET);
1da177e4 1432
e254e9bf
JL		 1433 b44_check_phy(bp);
1434
1fb9df5d 1435 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
6c2f4267 1436 if (unlikely(err < 0)) {
bea3348e 1437 napi_disable(&bp->napi);
fedb0eef 1438 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
6c2f4267
FR		 1439 b44_free_rings(bp);
1440 b44_free_consistent(bp);
1441 goto out;
1442 }
1da177e4
LT		 1443
1444 init_timer(&bp->timer);
1445 bp->timer.expires = jiffies + HZ;
1446 bp->timer.data = (unsigned long) bp;
1447 bp->timer.function = b44_timer;
1448 add_timer(&bp->timer);
1449
1450 b44_enable_ints(bp);
d9e2d185 1451 netif_start_queue(dev);
6c2f4267 1452out:
1da177e4
LT		 1453 return err;
1454}
1455
1da177e4
LT		 1456#ifdef CONFIG_NET_POLL_CONTROLLER
1457/*
1458 * Polling receive - used by netconsole and other diagnostic tools
1459 * to allow network i/o with interrupts disabled.
1460 */
1461static void b44_poll_controller(struct net_device *dev)
1462{
1463 disable_irq(dev->irq);
7d12e780 1464 b44_interrupt(dev->irq, dev);
1da177e4
LT		 1465 enable_irq(dev->irq);
1466}
1467#endif
1468
725ad800
GZ		 1469static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1470{
1471 u32 i;
1472 u32 *pattern = (u32 *) pp;
1473
1474 for (i = 0; i < bytes; i += sizeof(u32)) {
1475 bw32(bp, B44_FILT_ADDR, table_offset + i);
1476 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1477 }
1478}
1479
1480static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1481{
1482 int magicsync = 6;
1483 int k, j, len = offset;
1484 int ethaddr_bytes = ETH_ALEN;
1485
1486 memset(ppattern + offset, 0xff, magicsync);
1487 for (j = 0; j < magicsync; j++)
1488 set_bit(len++, (unsigned long *) pmask);
1489
1490 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1491 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1492 ethaddr_bytes = ETH_ALEN;
1493 else
1494 ethaddr_bytes = B44_PATTERN_SIZE - len;
1495 if (ethaddr_bytes <=0)
1496 break;
1497 for (k = 0; k< ethaddr_bytes; k++) {
1498 ppattern[offset + magicsync +
1499 (j * ETH_ALEN) + k] = macaddr[k];
e0188829 1500 set_bit(len++, (unsigned long *) pmask);
725ad800
GZ		 1501 }
1502 }
1503 return len - 1;
1504}
1505
1506/* Setup magic packet patterns in the b44 WOL
1507 * pattern matching filter.
1508 */
1509static void b44_setup_pseudo_magicp(struct b44 *bp)
1510{
1511
1512 u32 val;
1513 int plen0, plen1, plen2;
1514 u8 *pwol_pattern;
1515 u8 pwol_mask[B44_PMASK_SIZE];
1516
dd00cc48 1517 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
725ad800 1518 if (!pwol_pattern) {
2fc96fff 1519 pr_err("Memory not available for WOL\n");
725ad800
GZ		 1520 return;
1521 }
1522
1523 /* Ipv4 magic packet pattern - pattern 0.*/
725ad800
GZ		 1524 memset(pwol_mask, 0, B44_PMASK_SIZE);
1525 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1526 B44_ETHIPV4UDP_HLEN);
1527
1528 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1529 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1530
1531 /* Raw ethernet II magic packet pattern - pattern 1 */
1532 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1533 memset(pwol_mask, 0, B44_PMASK_SIZE);
1534 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1535 ETH_HLEN);
1536
1537 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1538 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1539 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1540 B44_PMASK_BASE + B44_PMASK_SIZE);
1541
1542 /* Ipv6 magic packet pattern - pattern 2 */
1543 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1544 memset(pwol_mask, 0, B44_PMASK_SIZE);
1545 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1546 B44_ETHIPV6UDP_HLEN);
1547
1548 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1549 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1550 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1551 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1552
1553 kfree(pwol_pattern);
1554
1555 /* set these pattern's lengths: one less than each real length */
1556 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1557 bw32(bp, B44_WKUP_LEN, val);
1558
1559 /* enable wakeup pattern matching */
1560 val = br32(bp, B44_DEVCTRL);
1561 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1562
1563}
52cafd96 1564
753f4920
MB		 1565#ifdef CONFIG_B44_PCI
1566static void b44_setup_wol_pci(struct b44 *bp)
1567{
1568 u16 val;
1569
1570 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1571 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1572 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1573 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1574 }
1575}
1576#else
1577static inline void b44_setup_wol_pci(struct b44 *bp) { }
1578#endif /* CONFIG_B44_PCI */
1579
52cafd96
GZ		 1580static void b44_setup_wol(struct b44 *bp)
1581{
1582 u32 val;
52cafd96
GZ		 1583
1584 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1585
1586 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1587
1588 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1589
1590 val = bp->dev->dev_addr[2] << 24 |
1591 bp->dev->dev_addr[3] << 16 |
1592 bp->dev->dev_addr[4] << 8 |
1593 bp->dev->dev_addr[5];
1594 bw32(bp, B44_ADDR_LO, val);
1595
1596 val = bp->dev->dev_addr[0] << 8 |
1597 bp->dev->dev_addr[1];
1598 bw32(bp, B44_ADDR_HI, val);
1599
1600 val = br32(bp, B44_DEVCTRL);
1601 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1602
725ad800
GZ		 1603 } else {
1604 b44_setup_pseudo_magicp(bp);
1605 }
753f4920 1606 b44_setup_wol_pci(bp);
52cafd96
GZ		 1607}
1608
1da177e4
LT		 1609static int b44_close(struct net_device *dev)
1610{
1611 struct b44 *bp = netdev_priv(dev);
1612
1613 netif_stop_queue(dev);
1614
bea3348e 1615 napi_disable(&bp->napi);
ba5eec9c 1616
1da177e4
LT		 1617 del_timer_sync(&bp->timer);
1618
1619 spin_lock_irq(&bp->lock);
1620
1da177e4
LT		 1621 b44_halt(bp);
1622 b44_free_rings(bp);
c35ca399 1623 netif_carrier_off(dev);
1da177e4
LT		 1624
1625 spin_unlock_irq(&bp->lock);
1626
1627 free_irq(dev->irq, dev);
1628
52cafd96 1629 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 1630 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 1631 b44_setup_wol(bp);
1632 }
1633
1da177e4
LT		 1634 b44_free_consistent(bp);
1635
1636 return 0;
1637}
1638
1639static struct net_device_stats *b44_get_stats(struct net_device *dev)
1640{
1641 struct b44 *bp = netdev_priv(dev);
553e2335 1642 struct net_device_stats *nstat = &dev->stats;
1da177e4
LT		 1643 struct b44_hw_stats *hwstat = &bp->hw_stats;
1644
1645 /* Convert HW stats into netdevice stats. */
1646 nstat->rx_packets = hwstat->rx_pkts;
1647 nstat->tx_packets = hwstat->tx_pkts;
1648 nstat->rx_bytes = hwstat->rx_octets;
1649 nstat->tx_bytes = hwstat->tx_octets;
1650 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1651 hwstat->tx_oversize_pkts +
1652 hwstat->tx_underruns +
1653 hwstat->tx_excessive_cols +
1654 hwstat->tx_late_cols);
1655 nstat->multicast = hwstat->tx_multicast_pkts;
1656 nstat->collisions = hwstat->tx_total_cols;
1657
1658 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1659 hwstat->rx_undersize);
1660 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1661 nstat->rx_frame_errors = hwstat->rx_align_errs;
1662 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1663 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1664 hwstat->rx_oversize_pkts +
1665 hwstat->rx_missed_pkts +
1666 hwstat->rx_crc_align_errs +
1667 hwstat->rx_undersize +
1668 hwstat->rx_crc_errs +
1669 hwstat->rx_align_errs +
1670 hwstat->rx_symbol_errs);
1671
1672 nstat->tx_aborted_errors = hwstat->tx_underruns;
1673#if 0
1674 /* Carrier lost counter seems to be broken for some devices */
1675 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1676#endif
1677
1678 return nstat;
1679}
1680
1681static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1682{
22bedad3 1683 struct netdev_hw_addr *ha;
1da177e4
LT		 1684 int i, num_ents;
1685
4cd24eaf 1686 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
0ddf477b 1687 i = 0;
22bedad3 1688 netdev_for_each_mc_addr(ha, dev) {
0ddf477b
JP		 1689 if (i == num_ents)
1690 break;
22bedad3 1691 __b44_cam_write(bp, ha->addr, i++ + 1);
1da177e4
LT		 1692 }
1693 return i+1;
1694}
1695
1696static void __b44_set_rx_mode(struct net_device *dev)
1697{
1698 struct b44 *bp = netdev_priv(dev);
1699 u32 val;
1da177e4
LT		 1700
1701 val = br32(bp, B44_RXCONFIG);
1702 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
753f4920 1703 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1da177e4
LT		 1704 val |= RXCONFIG_PROMISC;
1705 bw32(bp, B44_RXCONFIG, val);
1706 } else {
874a6214 1707 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
cda22aa9 1708 int i = 1;
874a6214 1709
1da177e4
LT		 1710 __b44_set_mac_addr(bp);
1711
2f614fe0 1712 if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 1713 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1da177e4
LT		 1714 val |= RXCONFIG_ALLMULTI;
1715 else
874a6214 1716 i = __b44_load_mcast(bp, dev);
10badc21 1717
2f614fe0 1718 for (; i < 64; i++)
10badc21 1719 __b44_cam_write(bp, zero, i);
2f614fe0 1720
1da177e4
LT		 1721 bw32(bp, B44_RXCONFIG, val);
1722 val = br32(bp, B44_CAM_CTRL);
1723 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1724 }
1725}
1726
1727static void b44_set_rx_mode(struct net_device *dev)
1728{
1729 struct b44 *bp = netdev_priv(dev);
1730
1731 spin_lock_irq(&bp->lock);
1732 __b44_set_rx_mode(dev);
1733 spin_unlock_irq(&bp->lock);
1734}
1735
1736static u32 b44_get_msglevel(struct net_device *dev)
1737{
1738 struct b44 *bp = netdev_priv(dev);
1739 return bp->msg_enable;
1740}
1741
1742static void b44_set_msglevel(struct net_device *dev, u32 value)
1743{
1744 struct b44 *bp = netdev_priv(dev);
1745 bp->msg_enable = value;
1746}
1747
1748static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1749{
1750 struct b44 *bp = netdev_priv(dev);
753f4920 1751 struct ssb_bus *bus = bp->sdev->bus;
1da177e4 1752
27e09551 1753 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1754 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
753f4920
MB		 1755 switch (bus->bustype) {
1756 case SSB_BUSTYPE_PCI:
27e09551 1757 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
753f4920 1758 break;
753f4920 1759 case SSB_BUSTYPE_SSB:
27e09551 1760 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
753f4920 1761 break;
98a1e2a9
MB		 1762 case SSB_BUSTYPE_PCMCIA:
1763 case SSB_BUSTYPE_SDIO:
1764 WARN_ON(1); /* A device with this bus does not exist. */
1765 break;
753f4920 1766 }
1da177e4
LT		 1767}
1768
1769static int b44_nway_reset(struct net_device *dev)
1770{
1771 struct b44 *bp = netdev_priv(dev);
1772 u32 bmcr;
1773 int r;
1774
1775 spin_lock_irq(&bp->lock);
1776 b44_readphy(bp, MII_BMCR, &bmcr);
1777 b44_readphy(bp, MII_BMCR, &bmcr);
1778 r = -EINVAL;
1779 if (bmcr & BMCR_ANENABLE) {
1780 b44_writephy(bp, MII_BMCR,
1781 bmcr | BMCR_ANRESTART);
1782 r = 0;
1783 }
1784 spin_unlock_irq(&bp->lock);
1785
1786 return r;
1787}
1788
1789static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1790{
1791 struct b44 *bp = netdev_priv(dev);
1792
1da177e4
LT		 1793 cmd->supported = (SUPPORTED_Autoneg);
1794 cmd->supported |= (SUPPORTED_100baseT_Half |
1795 SUPPORTED_100baseT_Full |
1796 SUPPORTED_10baseT_Half |
1797 SUPPORTED_10baseT_Full |
1798 SUPPORTED_MII);
1799
1800 cmd->advertising = 0;
1801 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1802 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1803 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1804 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1805 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1806 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1807 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1808 cmd->advertising |= ADVERTISED_100baseT_Full;
1809 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
70739497
DD		 1810 ethtool_cmd_speed_set(cmd, ((bp->flags & B44_FLAG_100_BASE_T) ?
1811 SPEED_100 : SPEED_10));
1da177e4
LT		 1812 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1813 DUPLEX_FULL : DUPLEX_HALF;
1814 cmd->port = 0;
1815 cmd->phy_address = bp->phy_addr;
1816 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1817 XCVR_INTERNAL : XCVR_EXTERNAL;
1818 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1819 AUTONEG_DISABLE : AUTONEG_ENABLE;
47b9c3b1
GZ		 1820 if (cmd->autoneg == AUTONEG_ENABLE)
1821 cmd->advertising |= ADVERTISED_Autoneg;
1822 if (!netif_running(dev)){
70739497 1823 ethtool_cmd_speed_set(cmd, 0);
47b9c3b1
GZ		 1824 cmd->duplex = 0xff;
1825 }
1da177e4
LT		 1826 cmd->maxtxpkt = 0;
1827 cmd->maxrxpkt = 0;
1828 return 0;
1829}
1830
1831static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1832{
1833 struct b44 *bp = netdev_priv(dev);
25db0338 1834 u32 speed = ethtool_cmd_speed(cmd);
1da177e4 1835
1da177e4
LT		 1836 /* We do not support gigabit. */
1837 if (cmd->autoneg == AUTONEG_ENABLE) {
1838 if (cmd->advertising &
1839 (ADVERTISED_1000baseT_Half |
1840 ADVERTISED_1000baseT_Full))
1841 return -EINVAL;
25db0338
DD		 1842 } else if ((speed != SPEED_100 &&
1843 speed != SPEED_10) ||
1da177e4
LT		 1844 (cmd->duplex != DUPLEX_HALF &&
1845 cmd->duplex != DUPLEX_FULL)) {
1846 return -EINVAL;
1847 }
1848
1849 spin_lock_irq(&bp->lock);
1850
1851 if (cmd->autoneg == AUTONEG_ENABLE) {
47b9c3b1
GZ		 1852 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1853 B44_FLAG_100_BASE_T |
1854 B44_FLAG_FULL_DUPLEX |
1855 B44_FLAG_ADV_10HALF |
1da177e4
LT		 1856 B44_FLAG_ADV_10FULL |
1857 B44_FLAG_ADV_100HALF |
1858 B44_FLAG_ADV_100FULL);
47b9c3b1
GZ		 1859 if (cmd->advertising == 0) {
1860 bp->flags |= (B44_FLAG_ADV_10HALF |
1861 B44_FLAG_ADV_10FULL |
1862 B44_FLAG_ADV_100HALF |
1863 B44_FLAG_ADV_100FULL);
1864 } else {
1865 if (cmd->advertising & ADVERTISED_10baseT_Half)
1866 bp->flags |= B44_FLAG_ADV_10HALF;
1867 if (cmd->advertising & ADVERTISED_10baseT_Full)
1868 bp->flags |= B44_FLAG_ADV_10FULL;
1869 if (cmd->advertising & ADVERTISED_100baseT_Half)
1870 bp->flags |= B44_FLAG_ADV_100HALF;
1871 if (cmd->advertising & ADVERTISED_100baseT_Full)
1872 bp->flags |= B44_FLAG_ADV_100FULL;
1873 }
1da177e4
LT		 1874 } else {
1875 bp->flags |= B44_FLAG_FORCE_LINK;
47b9c3b1 1876 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
25db0338 1877 if (speed == SPEED_100)
1da177e4
LT		 1878 bp->flags |= B44_FLAG_100_BASE_T;
1879 if (cmd->duplex == DUPLEX_FULL)
1880 bp->flags |= B44_FLAG_FULL_DUPLEX;
1881 }
1882
47b9c3b1
GZ		 1883 if (netif_running(dev))
1884 b44_setup_phy(bp);
1da177e4
LT		 1885
1886 spin_unlock_irq(&bp->lock);
1887
1888 return 0;
1889}
1890
1891static void b44_get_ringparam(struct net_device *dev,
1892 struct ethtool_ringparam *ering)
1893{
1894 struct b44 *bp = netdev_priv(dev);
1895
1896 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1897 ering->rx_pending = bp->rx_pending;
1898
1899 /* XXX ethtool lacks a tx_max_pending, oops... */
1900}
1901
1902static int b44_set_ringparam(struct net_device *dev,
1903 struct ethtool_ringparam *ering)
1904{
1905 struct b44 *bp = netdev_priv(dev);
1906
1907 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1908 (ering->rx_mini_pending != 0) ||
1909 (ering->rx_jumbo_pending != 0) ||
1910 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1911 return -EINVAL;
1912
1913 spin_lock_irq(&bp->lock);
1914
1915 bp->rx_pending = ering->rx_pending;
1916 bp->tx_pending = ering->tx_pending;
1917
1918 b44_halt(bp);
1919 b44_init_rings(bp);
5fc7d61a 1920 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1921 netif_wake_queue(bp->dev);
1922 spin_unlock_irq(&bp->lock);
1923
1924 b44_enable_ints(bp);
10badc21 1925
1da177e4
LT		 1926 return 0;
1927}
1928
1929static void b44_get_pauseparam(struct net_device *dev,
1930 struct ethtool_pauseparam *epause)
1931{
1932 struct b44 *bp = netdev_priv(dev);
1933
1934 epause->autoneg =
1935 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1936 epause->rx_pause =
1937 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1938 epause->tx_pause =
1939 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1940}
1941
1942static int b44_set_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *epause)
1944{
1945 struct b44 *bp = netdev_priv(dev);
1946
1947 spin_lock_irq(&bp->lock);
1948 if (epause->autoneg)
1949 bp->flags |= B44_FLAG_PAUSE_AUTO;
1950 else
1951 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1952 if (epause->rx_pause)
1953 bp->flags |= B44_FLAG_RX_PAUSE;
1954 else
1955 bp->flags &= ~B44_FLAG_RX_PAUSE;
1956 if (epause->tx_pause)
1957 bp->flags |= B44_FLAG_TX_PAUSE;
1958 else
1959 bp->flags &= ~B44_FLAG_TX_PAUSE;
1960 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1961 b44_halt(bp);
1962 b44_init_rings(bp);
5fc7d61a 1963 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1964 } else {
1965 __b44_set_flow_ctrl(bp, bp->flags);
1966 }
1967 spin_unlock_irq(&bp->lock);
1968
1969 b44_enable_ints(bp);
10badc21 1970
1da177e4
LT		 1971 return 0;
1972}
1973
3353930d
FR		 1974static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1975{
1976 switch(stringset) {
1977 case ETH_SS_STATS:
1978 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1979 break;
1980 }
1981}
1982
b9f2c044 1983static int b44_get_sset_count(struct net_device *dev, int sset)
3353930d 1984{
b9f2c044
JG		 1985 switch (sset) {
1986 case ETH_SS_STATS:
1987 return ARRAY_SIZE(b44_gstrings);
1988 default:
1989 return -EOPNOTSUPP;
1990 }
3353930d
FR		 1991}
1992
1993static void b44_get_ethtool_stats(struct net_device *dev,
1994 struct ethtool_stats *stats, u64 *data)
1995{
1996 struct b44 *bp = netdev_priv(dev);
1997 u32 *val = &bp->hw_stats.tx_good_octets;
1998 u32 i;
1999
2000 spin_lock_irq(&bp->lock);
2001
2002 b44_stats_update(bp);
2003
2004 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2005 *data++ = *val++;
2006
2007 spin_unlock_irq(&bp->lock);
2008}
2009
52cafd96
GZ		 2010static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2011{
2012 struct b44 *bp = netdev_priv(dev);
2013
2014 wol->supported = WAKE_MAGIC;
2015 if (bp->flags & B44_FLAG_WOL_ENABLE)
2016 wol->wolopts = WAKE_MAGIC;
2017 else
2018 wol->wolopts = 0;
2019 memset(&wol->sopass, 0, sizeof(wol->sopass));
2020}
2021
2022static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2023{
2024 struct b44 *bp = netdev_priv(dev);
2025
2026 spin_lock_irq(&bp->lock);
2027 if (wol->wolopts & WAKE_MAGIC)
2028 bp->flags |= B44_FLAG_WOL_ENABLE;
2029 else
2030 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2031 spin_unlock_irq(&bp->lock);
2032
2033 return 0;
2034}
2035
7282d491 2036static const struct ethtool_ops b44_ethtool_ops = {
1da177e4
LT		 2037 .get_drvinfo = b44_get_drvinfo,
2038 .get_settings = b44_get_settings,
2039 .set_settings = b44_set_settings,
2040 .nway_reset = b44_nway_reset,
2041 .get_link = ethtool_op_get_link,
52cafd96
GZ		 2042 .get_wol = b44_get_wol,
2043 .set_wol = b44_set_wol,
1da177e4
LT		 2044 .get_ringparam = b44_get_ringparam,
2045 .set_ringparam = b44_set_ringparam,
2046 .get_pauseparam = b44_get_pauseparam,
2047 .set_pauseparam = b44_set_pauseparam,
2048 .get_msglevel = b44_get_msglevel,
2049 .set_msglevel = b44_set_msglevel,
3353930d 2050 .get_strings = b44_get_strings,
b9f2c044 2051 .get_sset_count = b44_get_sset_count,
3353930d 2052 .get_ethtool_stats = b44_get_ethtool_stats,
1da177e4
LT		 2053};
2054
2055static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056{
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 2059 int err = -EINVAL;
2060
2061 if (!netif_running(dev))
2062 goto out;
1da177e4
LT		 2063
2064 spin_lock_irq(&bp->lock);
2065 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2066 spin_unlock_irq(&bp->lock);
3410572d 2067out:
1da177e4
LT		 2068 return err;
2069}
2070
1da177e4
LT		 2071static int __devinit b44_get_invariants(struct b44 *bp)
2072{
753f4920
MB		 2073 struct ssb_device *sdev = bp->sdev;
2074 int err = 0;
2075 u8 *addr;
1da177e4 2076
753f4920 2077 bp->dma_offset = ssb_dma_translation(sdev);
1da177e4 2078
753f4920
MB		 2079 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2080 instance > 1) {
458414b2
LF		 2081 addr = sdev->bus->sprom.et1mac;
2082 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
753f4920 2083 } else {
458414b2
LF		 2084 addr = sdev->bus->sprom.et0mac;
2085 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
753f4920 2086 }
5ea79631
MB		 2087 /* Some ROMs have buggy PHY addresses with the high
2088 * bits set (sign extension?). Truncate them to a
2089 * valid PHY address. */
2090 bp->phy_addr &= 0x1F;
2091
753f4920 2092 memcpy(bp->dev->dev_addr, addr, 6);
391fc09a
GZ		 2093
2094 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2fc96fff 2095 pr_err("Invalid MAC address found in EEPROM\n");
391fc09a
GZ		 2096 return -EINVAL;
2097 }
2098
2160de53 2099 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4 2100
1da177e4
LT		 2101 bp->imask = IMASK_DEF;
2102
10badc21 2103 /* XXX - really required?
1da177e4 2104 bp->flags |= B44_FLAG_BUGGY_TXPTR;
753f4920 2105 */
52cafd96 2106
753f4920
MB		 2107 if (bp->sdev->id.revision >= 7)
2108 bp->flags |= B44_FLAG_B0_ANDLATER;
52cafd96 2109
1da177e4
LT		 2110 return err;
2111}
2112
403413e5
SH		 2113static const struct net_device_ops b44_netdev_ops = {
2114 .ndo_open = b44_open,
2115 .ndo_stop = b44_close,
2116 .ndo_start_xmit = b44_start_xmit,
2117 .ndo_get_stats = b44_get_stats,
2118 .ndo_set_multicast_list = b44_set_rx_mode,
2119 .ndo_set_mac_address = b44_set_mac_addr,
2120 .ndo_validate_addr = eth_validate_addr,
2121 .ndo_do_ioctl = b44_ioctl,
2122 .ndo_tx_timeout = b44_tx_timeout,
2123 .ndo_change_mtu = b44_change_mtu,
2124#ifdef CONFIG_NET_POLL_CONTROLLER
2125 .ndo_poll_controller = b44_poll_controller,
2126#endif
2127};
2128
753f4920
MB		 2129static int __devinit b44_init_one(struct ssb_device *sdev,
2130 const struct ssb_device_id *ent)
1da177e4
LT		 2131{
2132 static int b44_version_printed = 0;
1da177e4
LT		 2133 struct net_device *dev;
2134 struct b44 *bp;
0795af57 2135 int err;
1da177e4 2136
753f4920
MB		 2137 instance++;
2138
1da177e4 2139 if (b44_version_printed++ == 0)
2fc96fff 2140 pr_info("%s", version);
1da177e4 2141
1da177e4
LT		 2142
2143 dev = alloc_etherdev(sizeof(*bp));
2144 if (!dev) {
2fc96fff 2145 dev_err(sdev->dev, "Etherdev alloc failed, aborting\n");
1da177e4 2146 err = -ENOMEM;
753f4920 2147 goto out;
1da177e4
LT		 2148 }
2149
753f4920 2150 SET_NETDEV_DEV(dev, sdev->dev);
1da177e4
LT		 2151
2152 /* No interesting netdevice features in this card... */
2153 dev->features |= 0;
2154
2155 bp = netdev_priv(dev);
753f4920 2156 bp->sdev = sdev;
1da177e4 2157 bp->dev = dev;
a58c891a 2158 bp->force_copybreak = 0;
874a6214
FR		 2159
2160 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 2161
2162 spin_lock_init(&bp->lock);
2163
1da177e4
LT		 2164 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2165 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2166
403413e5 2167 dev->netdev_ops = &b44_netdev_ops;
bea3348e 2168 netif_napi_add(dev, &bp->napi, b44_poll, 64);
1da177e4 2169 dev->watchdog_timeo = B44_TX_TIMEOUT;
753f4920 2170 dev->irq = sdev->irq;
1da177e4
LT		 2171 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2172
753f4920
MB		 2173 err = ssb_bus_powerup(sdev->bus, 0);
2174 if (err) {
2175 dev_err(sdev->dev,
2176 "Failed to powerup the bus\n");
2177 goto err_out_free_dev;
2178 }
39a6f4bc
FT		 2179
2180 if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
2181 dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
753f4920 2182 dev_err(sdev->dev,
2fc96fff 2183 "Required 30BIT DMA mask unsupported by the system\n");
753f4920
MB		 2184 goto err_out_powerdown;
2185 }
39a6f4bc 2186
1da177e4
LT		 2187 err = b44_get_invariants(bp);
2188 if (err) {
753f4920 2189 dev_err(sdev->dev,
2fc96fff 2190 "Problem fetching invariants of chip, aborting\n");
753f4920 2191 goto err_out_powerdown;
1da177e4
LT		 2192 }
2193
2194 bp->mii_if.dev = dev;
2195 bp->mii_if.mdio_read = b44_mii_read;
2196 bp->mii_if.mdio_write = b44_mii_write;
2197 bp->mii_if.phy_id = bp->phy_addr;
2198 bp->mii_if.phy_id_mask = 0x1f;
2199 bp->mii_if.reg_num_mask = 0x1f;
2200
2201 /* By default, advertise all speed/duplex settings. */
2202 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2203 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2204
2205 /* By default, auto-negotiate PAUSE. */
2206 bp->flags |= B44_FLAG_PAUSE_AUTO;
2207
2208 err = register_netdev(dev);
2209 if (err) {
2fc96fff 2210 dev_err(sdev->dev, "Cannot register net device, aborting\n");
753f4920 2211 goto err_out_powerdown;
1da177e4
LT		 2212 }
2213
bcf64aa3
PF		 2214 netif_carrier_off(dev);
2215
753f4920 2216 ssb_set_drvdata(sdev, dev);
1da177e4 2217
10badc21 2218 /* Chip reset provides power to the b44 MAC & PCI cores, which
5c513129 2219 * is necessary for MAC register access.
10badc21 2220 */
fedb0eef 2221 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5c513129 2222
8850dce1
HM		 2223 /* do a phy reset to test if there is an active phy */
2224 if (b44_phy_reset(bp) < 0)
2225 bp->phy_addr = B44_PHY_ADDR_NO_PHY;
2226
2fc96fff
JP		 2227 netdev_info(dev, "Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2228 dev->dev_addr);
1da177e4
LT		 2229
2230 return 0;
2231
753f4920
MB		 2232err_out_powerdown:
2233 ssb_bus_may_powerdown(sdev->bus);
1da177e4
LT		 2234
2235err_out_free_dev:
2236 free_netdev(dev);
2237
753f4920 2238out:
1da177e4
LT		 2239 return err;
2240}
2241
753f4920 2242static void __devexit b44_remove_one(struct ssb_device *sdev)
1da177e4 2243{
753f4920 2244 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2245
874a6214 2246 unregister_netdev(dev);
e92aa634 2247 ssb_device_disable(sdev, 0);
753f4920 2248 ssb_bus_may_powerdown(sdev->bus);
874a6214 2249 free_netdev(dev);
fedb0eef 2250 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
753f4920 2251 ssb_set_drvdata(sdev, NULL);
1da177e4
LT		 2252}
2253
753f4920 2254static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
1da177e4 2255{
753f4920 2256 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4
LT		 2257 struct b44 *bp = netdev_priv(dev);
2258
753f4920
MB		 2259 if (!netif_running(dev))
2260 return 0;
1da177e4
LT		 2261
2262 del_timer_sync(&bp->timer);
2263
10badc21 2264 spin_lock_irq(&bp->lock);
1da177e4
LT		 2265
2266 b44_halt(bp);
10badc21 2267 netif_carrier_off(bp->dev);
1da177e4
LT		 2268 netif_device_detach(bp->dev);
2269 b44_free_rings(bp);
2270
2271 spin_unlock_irq(&bp->lock);
46e17853
PM		 2272
2273 free_irq(dev->irq, dev);
52cafd96 2274 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 2275 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 2276 b44_setup_wol(bp);
2277 }
753f4920 2278
fedb0eef 2279 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
1da177e4
LT		 2280 return 0;
2281}
2282
753f4920 2283static int b44_resume(struct ssb_device *sdev)
1da177e4 2284{
753f4920 2285 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2286 struct b44 *bp = netdev_priv(dev);
90afd0e5 2287 int rc = 0;
1da177e4 2288
753f4920 2289 rc = ssb_bus_powerup(sdev->bus, 0);
90afd0e5 2290 if (rc) {
753f4920
MB		 2291 dev_err(sdev->dev,
2292 "Failed to powerup the bus\n");
90afd0e5
DM		 2293 return rc;
2294 }
2295
1da177e4
LT		 2296 if (!netif_running(dev))
2297 return 0;
2298
afed4ccb
JH		 2299 spin_lock_irq(&bp->lock);
2300 b44_init_rings(bp);
2301 b44_init_hw(bp, B44_FULL_RESET);
2302 spin_unlock_irq(&bp->lock);
2303
2304 /*
2305 * As a shared interrupt, the handler can be called immediately. To be
2306 * able to check the interrupt status the hardware must already be
2307 * powered back on (b44_init_hw).
2308 */
90afd0e5
DM		 2309 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2310 if (rc) {
2fc96fff 2311 netdev_err(dev, "request_irq failed\n");
afed4ccb
JH		 2312 spin_lock_irq(&bp->lock);
2313 b44_halt(bp);
2314 b44_free_rings(bp);
2315 spin_unlock_irq(&bp->lock);
90afd0e5
DM		 2316 return rc;
2317 }
46e17853 2318
1da177e4 2319 netif_device_attach(bp->dev);
1da177e4 2320
1da177e4 2321 b44_enable_ints(bp);
d9e2d185 2322 netif_wake_queue(dev);
a72a8179
SH		 2323
2324 mod_timer(&bp->timer, jiffies + 1);
2325
1da177e4
LT		 2326 return 0;
2327}
2328
753f4920 2329static struct ssb_driver b44_ssb_driver = {
1da177e4 2330 .name = DRV_MODULE_NAME,
753f4920 2331 .id_table = b44_ssb_tbl,
1da177e4
LT		 2332 .probe = b44_init_one,
2333 .remove = __devexit_p(b44_remove_one),
753f4920
MB		 2334 .suspend = b44_suspend,
2335 .resume = b44_resume,
1da177e4
LT		 2336};
2337
753f4920
MB		 2338static inline int b44_pci_init(void)
2339{
2340 int err = 0;
2341#ifdef CONFIG_B44_PCI
2342 err = ssb_pcihost_register(&b44_pci_driver);
2343#endif
2344 return err;
2345}
2346
2347static inline void b44_pci_exit(void)
2348{
2349#ifdef CONFIG_B44_PCI
2350 ssb_pcihost_unregister(&b44_pci_driver);
2351#endif
2352}
2353
1da177e4
LT		 2354static int __init b44_init(void)
2355{
9f38c636 2356 unsigned int dma_desc_align_size = dma_get_cache_alignment();
753f4920 2357 int err;
9f38c636
JL		 2358
2359 /* Setup paramaters for syncing RX/TX DMA descriptors */
22d4d771 2360 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
9f38c636 2361
753f4920
MB		 2362 err = b44_pci_init();
2363 if (err)
2364 return err;
2365 err = ssb_driver_register(&b44_ssb_driver);
2366 if (err)
2367 b44_pci_exit();
2368 return err;
1da177e4
LT		 2369}
2370
2371static void __exit b44_cleanup(void)
2372{
753f4920
MB		 2373 ssb_driver_unregister(&b44_ssb_driver);
2374 b44_pci_exit();
1da177e4
LT		 2375}
2376
2377module_init(b44_init);
2378module_exit(b44_cleanup);
2379
kernel source for telekom puls (alcatel/mediatek)