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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / arm / at91_ether.c
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d4b7780e
AV		 1/*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
d4b7780e
AV		 22#include <linux/mii.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/dma-mapping.h>
27#include <linux/ethtool.h>
28#include <linux/platform_device.h>
29#include <linux/clk.h>
5a0e3ad6 30#include <linux/gfp.h>
d4b7780e
AV		 31
32#include <asm/io.h>
33#include <asm/uaccess.h>
34#include <asm/mach-types.h>
35
a09e64fb
RK		 36#include <mach/at91rm9200_emac.h>
37#include <mach/gpio.h>
38#include <mach/board.h>
d4b7780e
AV		 39
40#include "at91_ether.h"
41
42#define DRV_NAME "at91_ether"
43#define DRV_VERSION "1.0"
44
775637df
AV		 45#define LINK_POLL_INTERVAL (HZ)
46
d4b7780e
AV		 47/* ..................................................................... */
48
49/*
50 * Read from a EMAC register.
51 */
52static inline unsigned long at91_emac_read(unsigned int reg)
53{
54 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
55
56 return __raw_readl(emac_base + reg);
57}
58
59/*
60 * Write to a EMAC register.
61 */
62static inline void at91_emac_write(unsigned int reg, unsigned long value)
63{
64 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
65
66 __raw_writel(value, emac_base + reg);
67}
68
69/* ........................... PHY INTERFACE ........................... */
70
71/*
72 * Enable the MDIO bit in MAC control register
73 * When not called from an interrupt-handler, access to the PHY must be
74 * protected by a spinlock.
75 */
76static void enable_mdi(void)
77{
78 unsigned long ctl;
79
80 ctl = at91_emac_read(AT91_EMAC_CTL);
81 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
82}
83
84/*
85 * Disable the MDIO bit in the MAC control register
86 */
87static void disable_mdi(void)
88{
89 unsigned long ctl;
90
91 ctl = at91_emac_read(AT91_EMAC_CTL);
92 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
93}
94
95/*
96 * Wait until the PHY operation is complete.
97 */
98static inline void at91_phy_wait(void) {
99 unsigned long timeout = jiffies + 2;
100
101 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
102 if (time_after(jiffies, timeout)) {
103 printk("at91_ether: MIO timeout\n");
104 break;
105 }
106 cpu_relax();
107 }
108}
109
110/*
111 * Write value to the a PHY register
112 * Note: MDI interface is assumed to already have been enabled.
113 */
114static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
115{
116 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
117 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
118
119 /* Wait until IDLE bit in Network Status register is cleared */
120 at91_phy_wait();
121}
122
123/*
124 * Read value stored in a PHY register.
125 * Note: MDI interface is assumed to already have been enabled.
126 */
127static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
128{
129 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
130 | ((phy_addr & 0x1f) << 23) | (address << 18));
131
132 /* Wait until IDLE bit in Network Status register is cleared */
133 at91_phy_wait();
134
135 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
136}
137
138/* ........................... PHY MANAGEMENT .......................... */
139
140/*
141 * Access the PHY to determine the current link speed and mode, and update the
142 * MAC accordingly.
143 * If no link or auto-negotiation is busy, then no changes are made.
144 */
775637df 145static void update_linkspeed(struct net_device *dev, int silent)
d4b7780e 146{
c57ee096 147 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 148 unsigned int bmsr, bmcr, lpa, mac_cfg;
149 unsigned int speed, duplex;
150
151 if (!mii_link_ok(&lp->mii)) { /* no link */
152 netif_carrier_off(dev);
775637df
AV		 153 if (!silent)
154 printk(KERN_INFO "%s: Link down.\n", dev->name);
d4b7780e
AV		 155 return;
156 }
157
158 /* Link up, or auto-negotiation still in progress */
159 read_phy(lp->phy_address, MII_BMSR, &bmsr);
160 read_phy(lp->phy_address, MII_BMCR, &bmcr);
161 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
162 if (!(bmsr & BMSR_ANEGCOMPLETE))
163 return; /* Do nothing - another interrupt generated when negotiation complete */
164
165 read_phy(lp->phy_address, MII_LPA, &lpa);
166 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
167 else speed = SPEED_10;
168 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
169 else duplex = DUPLEX_HALF;
170 } else {
171 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
172 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
173 }
174
175 /* Update the MAC */
176 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
177 if (speed == SPEED_100) {
178 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
179 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
180 else /* 100 Half Duplex */
181 mac_cfg |= AT91_EMAC_SPD;
182 } else {
183 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
184 mac_cfg |= AT91_EMAC_FD;
185 else {} /* 10 Half Duplex */
186 }
187 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
188
775637df
AV		 189 if (!silent)
190 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
d4b7780e
AV		 191 netif_carrier_on(dev);
192}
193
194/*
195 * Handle interrupts from the PHY
196 */
7d12e780 197static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
d4b7780e
AV		 198{
199 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 200 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 201 unsigned int phy;
202
203 /*
204 * This hander is triggered on both edges, but the PHY chips expect
205 * level-triggering. We therefore have to check if the PHY actually has
206 * an IRQ pending.
207 */
208 enable_mdi();
209 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
210 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
211 if (!(phy & (1 << 0)))
212 goto done;
213 }
214 else if (lp->phy_type == MII_LXT971A_ID) {
215 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
216 if (!(phy & (1 << 2)))
217 goto done;
218 }
219 else if (lp->phy_type == MII_BCM5221_ID) {
220 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
221 if (!(phy & (1 << 0)))
222 goto done;
223 }
224 else if (lp->phy_type == MII_KS8721_ID) {
225 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
226 if (!(phy & ((1 << 2) | 1)))
227 goto done;
228 }
6b4aea73
AV		 229 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
230 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
231 if (!(phy & ((1 << 2) | 1)))
232 goto done;
233 }
234 else if (lp->phy_type == MII_DP83848_ID) {
235 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
236 if (!(phy & (1 << 7)))
237 goto done;
238 }
d4b7780e 239
775637df 240 update_linkspeed(dev, 0);
d4b7780e
AV		 241
242done:
243 disable_mdi();
244
245 return IRQ_HANDLED;
246}
247
248/*
249 * Initialize and enable the PHY interrupt for link-state changes
250 */
251static void enable_phyirq(struct net_device *dev)
252{
c57ee096 253 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 254 unsigned int dsintr, irq_number;
255 int status;
256
775637df
AV		 257 irq_number = lp->board_data.phy_irq_pin;
258 if (!irq_number) {
259 /*
260 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
261 * or board does not have it connected.
262 */
cf42553a 263 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
d4b7780e 264 return;
775637df 265 }
d4b7780e 266
d4b7780e
AV		 267 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
268 if (status) {
269 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
270 return;
271 }
272
273 spin_lock_irq(&lp->lock);
274 enable_mdi();
275
276 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
277 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
278 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
279 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
280 }
281 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
282 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
283 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
284 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
285 }
286 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
287 dsintr = (1 << 15) | ( 1 << 14);
288 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
289 }
290 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
291 dsintr = (1 << 10) | ( 1 << 8);
292 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
293 }
6b4aea73
AV		 294 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
295 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
296 dsintr = dsintr | 0x500; /* set bits 8, 10 */
297 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
298 }
299 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
300 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
301 dsintr = dsintr | 0x3c; /* set bits 2..5 */
302 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
303 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
304 dsintr = dsintr | 0x3; /* set bits 0,1 */
305 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
306 }
d4b7780e
AV		 307
308 disable_mdi();
309 spin_unlock_irq(&lp->lock);
310}
311
312/*
313 * Disable the PHY interrupt
314 */
315static void disable_phyirq(struct net_device *dev)
316{
c57ee096 317 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 318 unsigned int dsintr;
319 unsigned int irq_number;
320
775637df
AV		 321 irq_number = lp->board_data.phy_irq_pin;
322 if (!irq_number) {
cf42553a 323 del_timer_sync(&lp->check_timer);
d4b7780e 324 return;
775637df 325 }
d4b7780e
AV		 326
327 spin_lock_irq(&lp->lock);
328 enable_mdi();
329
330 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
331 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
332 dsintr = dsintr | 0xf00; /* set bits 8..11 */
333 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
334 }
335 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
336 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
337 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
338 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
339 }
340 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
341 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
342 dsintr = ~(1 << 14);
343 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
344 }
345 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
346 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
347 dsintr = ~((1 << 10) | (1 << 8));
348 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
349 }
6b4aea73
AV		 350 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
351 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
352 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
353 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
354 }
355 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
356 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
357 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
358 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
359 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
360 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
361 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
362 }
d4b7780e
AV		 363
364 disable_mdi();
365 spin_unlock_irq(&lp->lock);
366
d4b7780e
AV		 367 free_irq(irq_number, dev); /* Free interrupt handler */
368}
369
370/*
371 * Perform a software reset of the PHY.
372 */
373#if 0
374static void reset_phy(struct net_device *dev)
375{
c57ee096 376 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 377 unsigned int bmcr;
378
379 spin_lock_irq(&lp->lock);
380 enable_mdi();
381
382 /* Perform PHY reset */
383 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
384
385 /* Wait until PHY reset is complete */
386 do {
387 read_phy(lp->phy_address, MII_BMCR, &bmcr);
10a5a80b 388 } while (!(bmcr & BMCR_RESET));
d4b7780e
AV		 389
390 disable_mdi();
391 spin_unlock_irq(&lp->lock);
392}
393#endif
394
775637df
AV		 395static void at91ether_check_link(unsigned long dev_id)
396{
397 struct net_device *dev = (struct net_device *) dev_id;
cf42553a 398 struct at91_private *lp = netdev_priv(dev);
775637df
AV		 399
400 enable_mdi();
401 update_linkspeed(dev, 1);
402 disable_mdi();
403
cf42553a 404 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
775637df
AV		 405}
406
d4b7780e
AV		 407/* ......................... ADDRESS MANAGEMENT ........................ */
408
409/*
410 * NOTE: Your bootloader must always set the MAC address correctly before
411 * booting into Linux.
412 *
413 * - It must always set the MAC address after reset, even if it doesn't
414 * happen to access the Ethernet while it's booting. Some versions of
415 * U-Boot on the AT91RM9200-DK do not do this.
416 *
417 * - Likewise it must store the addresses in the correct byte order.
418 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
419 * continues to do so, for bug-compatibility).
420 */
421
422static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
423{
424 char addr[6];
425
426 if (machine_is_csb337()) {
427 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
428 addr[4] = (lo & 0xff00) >> 8;
429 addr[3] = (lo & 0xff0000) >> 16;
430 addr[2] = (lo & 0xff000000) >> 24;
431 addr[1] = (hi & 0xff);
432 addr[0] = (hi & 0xff00) >> 8;
433 }
434 else {
435 addr[0] = (lo & 0xff);
436 addr[1] = (lo & 0xff00) >> 8;
437 addr[2] = (lo & 0xff0000) >> 16;
438 addr[3] = (lo & 0xff000000) >> 24;
439 addr[4] = (hi & 0xff);
440 addr[5] = (hi & 0xff00) >> 8;
441 }
442
443 if (is_valid_ether_addr(addr)) {
444 memcpy(dev->dev_addr, &addr, 6);
445 return 1;
446 }
447 return 0;
448}
449
450/*
451 * Set the ethernet MAC address in dev->dev_addr
452 */
453static void __init get_mac_address(struct net_device *dev)
454{
455 /* Check Specific-Address 1 */
456 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
457 return;
458 /* Check Specific-Address 2 */
459 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
460 return;
461 /* Check Specific-Address 3 */
462 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
463 return;
464 /* Check Specific-Address 4 */
465 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
466 return;
467
468 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
469}
470
471/*
472 * Program the hardware MAC address from dev->dev_addr.
473 */
474static void update_mac_address(struct net_device *dev)
475{
476 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
477 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
478
479 at91_emac_write(AT91_EMAC_SA2L, 0);
480 at91_emac_write(AT91_EMAC_SA2H, 0);
481}
482
483/*
484 * Store the new hardware address in dev->dev_addr, and update the MAC.
485 */
486static int set_mac_address(struct net_device *dev, void* addr)
487{
488 struct sockaddr *address = addr;
489
490 if (!is_valid_ether_addr(address->sa_data))
491 return -EADDRNOTAVAIL;
492
493 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
494 update_mac_address(dev);
495
e174961c
JB		 496 printk("%s: Setting MAC address to %pM\n", dev->name,
497 dev->dev_addr);
d4b7780e
AV		 498
499 return 0;
500}
501
502static int inline hash_bit_value(int bitnr, __u8 *addr)
503{
504 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
505 return 1;
506 return 0;
507}
508
509/*
510 * The hash address register is 64 bits long and takes up two locations in the memory map.
511 * The least significant bits are stored in EMAC_HSL and the most significant
512 * bits in EMAC_HSH.
513 *
514 * The unicast hash enable and the multicast hash enable bits in the network configuration
515 * register enable the reception of hash matched frames. The destination address is
516 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
517 * The hash function is an exclusive or of every sixth bit of the destination address.
518 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
519 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
520 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
521 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
522 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
523 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
524 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
525 * unicast indicator, and da[47] represents the most significant bit of the last byte
526 * received.
527 * If the hash index points to a bit that is set in the hash register then the frame will be
528 * matched according to whether the frame is multicast or unicast.
529 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
530 * the hash index points to a bit set in the hash register.
531 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
532 * hash index points to a bit set in the hash register.
533 * To receive all multicast frames, the hash register should be set with all ones and the
534 * multicast hash enable bit should be set in the network configuration register.
535 */
536
537/*
538 * Return the hash index value for the specified address.
539 */
540static int hash_get_index(__u8 *addr)
541{
542 int i, j, bitval;
543 int hash_index = 0;
544
545 for (j = 0; j < 6; j++) {
546 for (i = 0, bitval = 0; i < 8; i++)
547 bitval ^= hash_bit_value(i*6 + j, addr);
548
549 hash_index |= (bitval << j);
550 }
551
427d269f 552 return hash_index;
d4b7780e
AV		 553}
554
555/*
556 * Add multicast addresses to the internal multicast-hash table.
557 */
558static void at91ether_sethashtable(struct net_device *dev)
559{
560 struct dev_mc_list *curr;
561 unsigned long mc_filter[2];
3b9a7728 562 unsigned int bitnr;
d4b7780e
AV		 563
564 mc_filter[0] = mc_filter[1] = 0;
565
3b9a7728 566 netdev_for_each_mc_addr(curr, dev) {
d4b7780e
AV		 567 bitnr = hash_get_index(curr->dmi_addr);
568 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
569 }
570
8bc35473
AV		 571 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
572 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
d4b7780e
AV		 573}
574
575/*
576 * Enable/Disable promiscuous and multicast modes.
577 */
531c6804 578static void at91ether_set_multicast_list(struct net_device *dev)
d4b7780e
AV		 579{
580 unsigned long cfg;
581
582 cfg = at91_emac_read(AT91_EMAC_CFG);
583
584 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
585 cfg |= AT91_EMAC_CAF;
586 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
587 cfg &= ~AT91_EMAC_CAF;
588
589 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
590 at91_emac_write(AT91_EMAC_HSH, -1);
591 at91_emac_write(AT91_EMAC_HSL, -1);
592 cfg |= AT91_EMAC_MTI;
4cd24eaf 593 } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
d4b7780e
AV		 594 at91ether_sethashtable(dev);
595 cfg |= AT91_EMAC_MTI;
596 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
597 at91_emac_write(AT91_EMAC_HSH, 0);
598 at91_emac_write(AT91_EMAC_HSL, 0);
599 cfg &= ~AT91_EMAC_MTI;
600 }
601
602 at91_emac_write(AT91_EMAC_CFG, cfg);
603}
604
d4b7780e
AV		 605/* ......................... ETHTOOL SUPPORT ........................... */
606
d4b7780e
AV		 607static int mdio_read(struct net_device *dev, int phy_id, int location)
608{
609 unsigned int value;
610
611 read_phy(phy_id, location, &value);
612 return value;
613}
614
615static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
616{
617 write_phy(phy_id, location, value);
618}
619
620static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
621{
c57ee096 622 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 623 int ret;
624
625 spin_lock_irq(&lp->lock);
626 enable_mdi();
627
628 ret = mii_ethtool_gset(&lp->mii, cmd);
629
630 disable_mdi();
631 spin_unlock_irq(&lp->lock);
632
633 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
634 cmd->supported = SUPPORTED_FIBRE;
635 cmd->port = PORT_FIBRE;
636 }
637
638 return ret;
639}
640
641static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
642{
c57ee096 643 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 644 int ret;
645
646 spin_lock_irq(&lp->lock);
647 enable_mdi();
648
649 ret = mii_ethtool_sset(&lp->mii, cmd);
650
651 disable_mdi();
652 spin_unlock_irq(&lp->lock);
653
654 return ret;
655}
656
657static int at91ether_nwayreset(struct net_device *dev)
658{
c57ee096 659 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 660 int ret;
661
662 spin_lock_irq(&lp->lock);
663 enable_mdi();
664
665 ret = mii_nway_restart(&lp->mii);
666
667 disable_mdi();
668 spin_unlock_irq(&lp->lock);
669
670 return ret;
671}
672
673static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
674{
675 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
676 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3f978704 677 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
d4b7780e
AV		 678}
679
7282d491 680static const struct ethtool_ops at91ether_ethtool_ops = {
d4b7780e
AV		 681 .get_settings = at91ether_get_settings,
682 .set_settings = at91ether_set_settings,
683 .get_drvinfo = at91ether_get_drvinfo,
684 .nway_reset = at91ether_nwayreset,
685 .get_link = ethtool_op_get_link,
686};
687
ca5585ed
AV		 688static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
689{
c57ee096 690 struct at91_private *lp = netdev_priv(dev);
ca5585ed
AV		 691 int res;
692
693 if (!netif_running(dev))
694 return -EINVAL;
695
696 spin_lock_irq(&lp->lock);
697 enable_mdi();
698 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
699 disable_mdi();
700 spin_unlock_irq(&lp->lock);
701
702 return res;
703}
d4b7780e
AV		 704
705/* ................................ MAC ................................ */
706
707/*
708 * Initialize and start the Receiver and Transmit subsystems
709 */
710static void at91ether_start(struct net_device *dev)
711{
c57ee096 712 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 713 struct recv_desc_bufs *dlist, *dlist_phys;
714 int i;
715 unsigned long ctl;
716
717 dlist = lp->dlist;
718 dlist_phys = lp->dlist_phys;
719
720 for (i = 0; i < MAX_RX_DESCR; i++) {
721 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
722 dlist->descriptors[i].size = 0;
723 }
724
725 /* Set the Wrap bit on the last descriptor */
726 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
727
728 /* Reset buffer index */
729 lp->rxBuffIndex = 0;
730
731 /* Program address of descriptor list in Rx Buffer Queue register */
732 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
733
734 /* Enable Receive and Transmit */
735 ctl = at91_emac_read(AT91_EMAC_CTL);
736 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
737}
738
739/*
740 * Open the ethernet interface
741 */
742static int at91ether_open(struct net_device *dev)
743{
c57ee096 744 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 745 unsigned long ctl;
746
427d269f
AV		 747 if (!is_valid_ether_addr(dev->dev_addr))
748 return -EADDRNOTAVAIL;
d4b7780e 749
427d269f 750 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
d4b7780e
AV		 751
752 /* Clear internal statistics */
753 ctl = at91_emac_read(AT91_EMAC_CTL);
754 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
755
756 /* Update the MAC address (incase user has changed it) */
757 update_mac_address(dev);
758
759 /* Enable PHY interrupt */
760 enable_phyirq(dev);
761
762 /* Enable MAC interrupts */
763 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
764 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
765 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
766
767 /* Determine current link speed */
768 spin_lock_irq(&lp->lock);
769 enable_mdi();
775637df 770 update_linkspeed(dev, 0);
d4b7780e
AV		 771 disable_mdi();
772 spin_unlock_irq(&lp->lock);
773
774 at91ether_start(dev);
775 netif_start_queue(dev);
776 return 0;
777}
778
779/*
780 * Close the interface
781 */
782static int at91ether_close(struct net_device *dev)
783{
c57ee096 784 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 785 unsigned long ctl;
786
787 /* Disable Receiver and Transmitter */
788 ctl = at91_emac_read(AT91_EMAC_CTL);
789 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
790
791 /* Disable PHY interrupt */
792 disable_phyirq(dev);
793
794 /* Disable MAC interrupts */
795 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
796 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
797 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
798
799 netif_stop_queue(dev);
800
427d269f 801 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
d4b7780e
AV		 802
803 return 0;
804}
805
806/*
807 * Transmit packet.
808 */
531c6804 809static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
d4b7780e 810{
c57ee096 811 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 812
813 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
814 netif_stop_queue(dev);
815
816 /* Store packet information (to free when Tx completed) */
817 lp->skb = skb;
818 lp->skb_length = skb->len;
819 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
7a2f53ee 820 dev->stats.tx_bytes += skb->len;
d4b7780e
AV		 821
822 /* Set address of the data in the Transmit Address register */
823 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
824 /* Set length of the packet in the Transmit Control register */
825 at91_emac_write(AT91_EMAC_TCR, skb->len);
826
827 dev->trans_start = jiffies;
828 } else {
531c6804 829 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
5b548140 830 return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
d4b7780e
AV		 831 on this skb, he also reports -ENETDOWN and printk's, so either
832 we free and return(0) or don't free and return 1 */
833 }
834
6ed10654 835 return NETDEV_TX_OK;
d4b7780e
AV		 836}
837
838/*
839 * Update the current statistics from the internal statistics registers.
840 */
841static struct net_device_stats *at91ether_stats(struct net_device *dev)
842{
d4b7780e
AV		 843 int ale, lenerr, seqe, lcol, ecol;
844
845 if (netif_running(dev)) {
7a2f53ee 846 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
d4b7780e 847 ale = at91_emac_read(AT91_EMAC_ALE);
7a2f53ee 848 dev->stats.rx_frame_errors += ale; /* Alignment errors */
d4b7780e 849 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
7a2f53ee 850 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
d4b7780e 851 seqe = at91_emac_read(AT91_EMAC_SEQE);
7a2f53ee
PZ		 852 dev->stats.rx_crc_errors += seqe; /* CRC error */
853 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
854 dev->stats.rx_errors += (ale + lenerr + seqe
d4b7780e
AV		 855 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
856
7a2f53ee
PZ		 857 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
858 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
859 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
860 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
d4b7780e
AV		 861
862 lcol = at91_emac_read(AT91_EMAC_LCOL);
863 ecol = at91_emac_read(AT91_EMAC_ECOL);
7a2f53ee
PZ		 864 dev->stats.tx_window_errors += lcol; /* Late collisions */
865 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
d4b7780e 866
7a2f53ee 867 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
d4b7780e 868 }
7a2f53ee 869 return &dev->stats;
d4b7780e
AV		 870}
871
872/*
873 * Extract received frame from buffer descriptors and sent to upper layers.
874 * (Called from interrupt context)
875 */
876static void at91ether_rx(struct net_device *dev)
877{
c57ee096 878 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 879 struct recv_desc_bufs *dlist;
880 unsigned char *p_recv;
881 struct sk_buff *skb;
882 unsigned int pktlen;
883
884 dlist = lp->dlist;
885 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
886 p_recv = dlist->recv_buf[lp->rxBuffIndex];
887 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
a3f63e4f 888 skb = dev_alloc_skb(pktlen + 2);
d4b7780e
AV		 889 if (skb != NULL) {
890 skb_reserve(skb, 2);
891 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
892
d4b7780e 893 skb->protocol = eth_type_trans(skb, dev);
7a2f53ee 894 dev->stats.rx_bytes += pktlen;
d4b7780e
AV		 895 netif_rx(skb);
896 }
897 else {
7a2f53ee 898 dev->stats.rx_dropped += 1;
d4b7780e
AV		 899 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
900 }
901
902 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
7a2f53ee 903 dev->stats.multicast++;
d4b7780e
AV		 904
905 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
906 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
907 lp->rxBuffIndex = 0;
908 else
909 lp->rxBuffIndex++;
910 }
911}
912
913/*
914 * MAC interrupt handler
915 */
7d12e780 916static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
d4b7780e
AV		 917{
918 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 919 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 920 unsigned long intstatus, ctl;
921
922 /* MAC Interrupt Status register indicates what interrupts are pending.
923 It is automatically cleared once read. */
924 intstatus = at91_emac_read(AT91_EMAC_ISR);
925
926 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
927 at91ether_rx(dev);
928
427d269f 929 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
d4b7780e
AV		 930 /* The TCOM bit is set even if the transmission failed. */
931 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
7a2f53ee 932 dev->stats.tx_errors += 1;
d4b7780e
AV		 933
934 if (lp->skb) {
935 dev_kfree_skb_irq(lp->skb);
936 lp->skb = NULL;
937 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
938 }
939 netif_wake_queue(dev);
940 }
941
942 /* Work-around for Errata #11 */
943 if (intstatus & AT91_EMAC_RBNA) {
944 ctl = at91_emac_read(AT91_EMAC_CTL);
945 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
946 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
947 }
948
949 if (intstatus & AT91_EMAC_ROVR)
950 printk("%s: ROVR error\n", dev->name);
951
952 return IRQ_HANDLED;
953}
954
51cc2104
AV		 955#ifdef CONFIG_NET_POLL_CONTROLLER
956static void at91ether_poll_controller(struct net_device *dev)
957{
958 unsigned long flags;
959
960 local_irq_save(flags);
961 at91ether_interrupt(dev->irq, dev);
962 local_irq_restore(flags);
963}
964#endif
965
531c6804
AB		 966static const struct net_device_ops at91ether_netdev_ops = {
967 .ndo_open = at91ether_open,
968 .ndo_stop = at91ether_close,
969 .ndo_start_xmit = at91ether_start_xmit,
970 .ndo_get_stats = at91ether_stats,
971 .ndo_set_multicast_list = at91ether_set_multicast_list,
972 .ndo_set_mac_address = set_mac_address,
973 .ndo_do_ioctl = at91ether_ioctl,
974 .ndo_validate_addr = eth_validate_addr,
975 .ndo_change_mtu = eth_change_mtu,
976#ifdef CONFIG_NET_POLL_CONTROLLER
977 .ndo_poll_controller = at91ether_poll_controller,
978#endif
979};
980
d4b7780e
AV		 981/*
982 * Initialize the ethernet interface
983 */
427d269f
AV		 984static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
985 struct platform_device *pdev, struct clk *ether_clk)
d4b7780e
AV		 986{
987 struct at91_eth_data *board_data = pdev->dev.platform_data;
988 struct net_device *dev;
989 struct at91_private *lp;
990 unsigned int val;
991 int res;
992
d4b7780e
AV		 993 dev = alloc_etherdev(sizeof(struct at91_private));
994 if (!dev)
995 return -ENOMEM;
996
997 dev->base_addr = AT91_VA_BASE_EMAC;
72729910 998 dev->irq = AT91RM9200_ID_EMAC;
d4b7780e
AV		 999
1000 /* Install the interrupt handler */
1001 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
1002 free_netdev(dev);
1003 return -EBUSY;
1004 }
1005
1006 /* Allocate memory for DMA Receive descriptors */
c57ee096 1007 lp = netdev_priv(dev);
d4b7780e
AV		 1008 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
1009 if (lp->dlist == NULL) {
1010 free_irq(dev->irq, dev);
1011 free_netdev(dev);
1012 return -ENOMEM;
1013 }
1014 lp->board_data = *board_data;
427d269f 1015 lp->ether_clk = ether_clk;
d4b7780e
AV		 1016 platform_set_drvdata(pdev, dev);
1017
1018 spin_lock_init(&lp->lock);
1019
1020 ether_setup(dev);
531c6804 1021 dev->netdev_ops = &at91ether_netdev_ops;
d4b7780e
AV		 1022 dev->ethtool_ops = &at91ether_ethtool_ops;
1023
1024 SET_NETDEV_DEV(dev, &pdev->dev);
1025
1026 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1027 update_mac_address(dev); /* Program ethernet address into MAC */
1028
1029 at91_emac_write(AT91_EMAC_CTL, 0);
1030
1031 if (lp->board_data.is_rmii)
1032 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
1033 else
1034 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
1035
1036 /* Perform PHY-specific initialization */
1037 spin_lock_irq(&lp->lock);
1038 enable_mdi();
1039 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1040 read_phy(phy_address, MII_DSCR_REG, &val);
1041 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1042 lp->phy_media = PORT_FIBRE;
1043 } else if (machine_is_csb337()) {
1044 /* mix link activity status into LED2 link state */
1045 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
2f036ac6
AV		 1046 } else if (machine_is_ecbat91())
1047 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
1048
d4b7780e
AV		 1049 disable_mdi();
1050 spin_unlock_irq(&lp->lock);
1051
1052 lp->mii.dev = dev; /* Support for ethtool */
1053 lp->mii.mdio_read = mdio_read;
1054 lp->mii.mdio_write = mdio_write;
ca5585ed
AV		 1055 lp->mii.phy_id = phy_address;
1056 lp->mii.phy_id_mask = 0x1f;
1057 lp->mii.reg_num_mask = 0x1f;
d4b7780e
AV		 1058
1059 lp->phy_type = phy_type; /* Type of PHY connected */
1060 lp->phy_address = phy_address; /* MDI address of PHY */
1061
1062 /* Register the network interface */
1063 res = register_netdev(dev);
1064 if (res) {
1065 free_irq(dev->irq, dev);
1066 free_netdev(dev);
1067 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1068 return res;
1069 }
d4b7780e
AV		 1070
1071 /* Determine current link speed */
1072 spin_lock_irq(&lp->lock);
1073 enable_mdi();
775637df 1074 update_linkspeed(dev, 0);
d4b7780e
AV		 1075 disable_mdi();
1076 spin_unlock_irq(&lp->lock);
1077 netif_carrier_off(dev); /* will be enabled in open() */
1078
775637df
AV		 1079 /* If board has no PHY IRQ, use a timer to poll the PHY */
1080 if (!lp->board_data.phy_irq_pin) {
cf42553a
AV		 1081 init_timer(&lp->check_timer);
1082 lp->check_timer.data = (unsigned long)dev;
1083 lp->check_timer.function = at91ether_check_link;
71527ef4
DB		 1084 } else if (lp->board_data.phy_irq_pin >= 32)
1085 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
775637df 1086
d4b7780e 1087 /* Display ethernet banner */
e174961c 1088 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
0795af57
JP		 1089 dev->name, (uint) dev->base_addr, dev->irq,
1090 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1091 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
e174961c 1092 dev->dev_addr);
d4b7780e 1093 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
427d269f 1094 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
d4b7780e
AV		 1095 else if (phy_type == MII_LXT971A_ID)
1096 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1097 else if (phy_type == MII_RTL8201_ID)
1098 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1099 else if (phy_type == MII_BCM5221_ID)
1100 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1101 else if (phy_type == MII_DP83847_ID)
1102 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
6b4aea73
AV		 1103 else if (phy_type == MII_DP83848_ID)
1104 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
d4b7780e
AV		 1105 else if (phy_type == MII_AC101L_ID)
1106 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1107 else if (phy_type == MII_KS8721_ID)
1108 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
6b4aea73
AV		 1109 else if (phy_type == MII_T78Q21x3_ID)
1110 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1111 else if (phy_type == MII_LAN83C185_ID)
1112 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
d4b7780e
AV		 1113
1114 return 0;
1115}
1116
1117/*
1118 * Detect MAC and PHY and perform initialization
1119 */
1120static int __init at91ether_probe(struct platform_device *pdev)
1121{
1122 unsigned int phyid1, phyid2;
1123 int detected = -1;
1124 unsigned long phy_id;
1125 unsigned short phy_address = 0;
427d269f 1126 struct clk *ether_clk;
d4b7780e
AV		 1127
1128 ether_clk = clk_get(&pdev->dev, "ether_clk");
427d269f 1129 if (IS_ERR(ether_clk)) {
d4b7780e
AV		 1130 printk(KERN_ERR "at91_ether: no clock defined\n");
1131 return -ENODEV;
1132 }
1133 clk_enable(ether_clk); /* Enable Peripheral clock */
1134
1135 while ((detected != 0) && (phy_address < 32)) {
1136 /* Read the PHY ID registers */
1137 enable_mdi();
1138 read_phy(phy_address, MII_PHYSID1, &phyid1);
1139 read_phy(phy_address, MII_PHYSID2, &phyid2);
1140 disable_mdi();
1141
1142 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1143 switch (phy_id) {
1144 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1145 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1146 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1147 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1148 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1149 case MII_DP83847_ID: /* National Semiconductor DP83847: */
6b4aea73 1150 case MII_DP83848_ID: /* National Semiconductor DP83848: */
d4b7780e
AV		 1151 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1152 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
6b4aea73
AV		 1153 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1154 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
427d269f 1155 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
d4b7780e
AV		 1156 break;
1157 }
1158
1159 phy_address++;
1160 }
1161
1162 clk_disable(ether_clk); /* Disable Peripheral clock */
1163
1164 return detected;
1165}
1166
1167static int __devexit at91ether_remove(struct platform_device *pdev)
1168{
c57ee096
AV		 1169 struct net_device *dev = platform_get_drvdata(pdev);
1170 struct at91_private *lp = netdev_priv(dev);
d4b7780e 1171
71527ef4
DB		 1172 if (lp->board_data.phy_irq_pin >= 32)
1173 gpio_free(lp->board_data.phy_irq_pin);
1174
c57ee096
AV		 1175 unregister_netdev(dev);
1176 free_irq(dev->irq, dev);
d4b7780e 1177 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
427d269f 1178 clk_put(lp->ether_clk);
d4b7780e 1179
c57ee096
AV		 1180 platform_set_drvdata(pdev, NULL);
1181 free_netdev(dev);
d4b7780e
AV		 1182 return 0;
1183}
1184
00e5edcb
AV		 1185#ifdef CONFIG_PM
1186
1187static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1188{
00e5edcb 1189 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1190 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV		 1191 int phy_irq = lp->board_data.phy_irq_pin;
1192
1193 if (netif_running(net_dev)) {
1194 if (phy_irq)
1195 disable_irq(phy_irq);
1196
1197 netif_stop_queue(net_dev);
1198 netif_device_detach(net_dev);
1199
1200 clk_disable(lp->ether_clk);
1201 }
1202 return 0;
1203}
1204
1205static int at91ether_resume(struct platform_device *pdev)
1206{
00e5edcb 1207 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1208 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV		 1209 int phy_irq = lp->board_data.phy_irq_pin;
1210
1211 if (netif_running(net_dev)) {
1212 clk_enable(lp->ether_clk);
1213
1214 netif_device_attach(net_dev);
1215 netif_start_queue(net_dev);
1216
1217 if (phy_irq)
1218 enable_irq(phy_irq);
1219 }
1220 return 0;
1221}
1222
1223#else
1224#define at91ether_suspend NULL
1225#define at91ether_resume NULL
1226#endif
1227
d4b7780e 1228static struct platform_driver at91ether_driver = {
d4b7780e 1229 .remove = __devexit_p(at91ether_remove),
00e5edcb
AV		 1230 .suspend = at91ether_suspend,
1231 .resume = at91ether_resume,
d4b7780e
AV		 1232 .driver = {
1233 .name = DRV_NAME,
1234 .owner = THIS_MODULE,
1235 },
1236};
1237
1238static int __init at91ether_init(void)
1239{
78a9c9c9 1240 return platform_driver_probe(&at91ether_driver, at91ether_probe);
d4b7780e
AV		 1241}
1242
1243static void __exit at91ether_exit(void)
1244{
1245 platform_driver_unregister(&at91ether_driver);
1246}
1247
1248module_init(at91ether_init)
1249module_exit(at91ether_exit)
1250
1251MODULE_LICENSE("GPL");
1252MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1253MODULE_AUTHOR("Andrew Victor");
72abb461 1254MODULE_ALIAS("platform:" DRV_NAME);
kernel source for telekom puls (alcatel/mediatek)