[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / 3c527.h

/*
 *	3COM "EtherLink MC/32" Descriptions
 */

/*
 *	Registers
 */

#define HOST_CMD		0
#define         HOST_CMD_START_RX   (1<<3)
#define         HOST_CMD_SUSPND_RX  (3<<3)
#define         HOST_CMD_RESTRT_RX  (5<<3)

#define         HOST_CMD_SUSPND_TX  3
#define         HOST_CMD_RESTRT_TX  5


#define HOST_STATUS		2
#define		HOST_STATUS_CRR	(1<<6)
#define		HOST_STATUS_CWR	(1<<5)


#define HOST_CTRL		6
#define		HOST_CTRL_ATTN	(1<<7)
#define 	HOST_CTRL_RESET	(1<<6)
#define 	HOST_CTRL_INTE	(1<<2)

#define HOST_RAMPAGE		8

#define HALTED 0
#define RUNNING 1

struct mc32_mailbox
{
 	u16 mbox;
 	u16 data[1];
} __packed;

struct skb_header
{
	u8 status;
	u8 control;
	u16 next;	/* Do not change! */
	u16 length;
	u32 data;
} __packed;

struct mc32_stats
{
	/* RX Errors */
	u32 rx_crc_errors;
	u32 rx_alignment_errors;
	u32 rx_overrun_errors;
	u32 rx_tooshort_errors;
	u32 rx_toolong_errors;
	u32 rx_outofresource_errors;

	u32 rx_discarded;  /* via card pattern match filter */

	/* TX Errors */
	u32 tx_max_collisions;
	u32 tx_carrier_errors;
	u32 tx_underrun_errors;
	u32 tx_cts_errors;
	u32 tx_timeout_errors;

	/* various cruft */
	u32 dataA[6];
	u16 dataB[5];
	u32 dataC[14];
} __packed;

#define STATUS_MASK	0x0F
#define COMPLETED	(1<<7)
#define COMPLETED_OK	(1<<6)
#define BUFFER_BUSY	(1<<5)

#define CONTROL_EOP	(1<<7)	/* End Of Packet */
#define CONTROL_EOL	(1<<6)	/* End of List */

#define MCA_MC32_ID	0x0041	/* Our MCA ident */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* 3COM "EtherLink MC/32" Descriptions
	3	*/
	4
	5	/*
	6	* Registers
	7	*/
6aa20a22	8
1da177e4 LT	9	#define HOST_CMD 0
	10	#define HOST_CMD_START_RX (1<<3)
	11	#define HOST_CMD_SUSPND_RX (3<<3)
	12	#define HOST_CMD_RESTRT_RX (5<<3)
	13
	14	#define HOST_CMD_SUSPND_TX 3
	15	#define HOST_CMD_RESTRT_TX 5
	16
	17
	18	#define HOST_STATUS 2
	19	#define HOST_STATUS_CRR (1<<6)
	20	#define HOST_STATUS_CWR (1<<5)
	21
	22
	23	#define HOST_CTRL 6
	24	#define HOST_CTRL_ATTN (1<<7)
	25	#define HOST_CTRL_RESET (1<<6)
	26	#define HOST_CTRL_INTE (1<<2)
	27
	28	#define HOST_RAMPAGE 8
	29
	30	#define HALTED 0
	31	#define RUNNING 1
	32
	33	struct mc32_mailbox
	34	{
6a878184 JB	35	u16 mbox;
6a878184 JB	36	u16 data[1];
ba2d3587	37	} __packed;
1da177e4 LT	38
	39	struct skb_header
	40	{
6a878184 JB	41	u8 status;
	42	u8 control;
	43	u16 next; /* Do not change! */
	44	u16 length;
	45	u32 data;
ba2d3587	46	} __packed;
1da177e4 LT	47
	48	struct mc32_stats
	49	{
	50	/* RX Errors */
6a878184 JB	51	u32 rx_crc_errors;
	52	u32 rx_alignment_errors;
	53	u32 rx_overrun_errors;
	54	u32 rx_tooshort_errors;
	55	u32 rx_toolong_errors;
	56	u32 rx_outofresource_errors;
1da177e4	57
6a878184	58	u32 rx_discarded; /* via card pattern match filter */
1da177e4 LT	59
1da177e4 LT	60	/* TX Errors */
6a878184 JB	61	u32 tx_max_collisions;
	62	u32 tx_carrier_errors;
	63	u32 tx_underrun_errors;
	64	u32 tx_cts_errors;
	65	u32 tx_timeout_errors;
6aa20a22	66
1da177e4	67	/* various cruft */
6a878184 JB	68	u32 dataA[6];
	69	u16 dataB[5];
	70	u32 dataC[14];
ba2d3587	71	} __packed;
1da177e4 LT	72
	73	#define STATUS_MASK 0x0F
	74	#define COMPLETED (1<<7)
	75	#define COMPLETED_OK (1<<6)
	76	#define BUFFER_BUSY (1<<5)
	77
	78	#define CONTROL_EOP (1<<7) /* End Of Packet */
	79	#define CONTROL_EOL (1<<6) /* End of List */
	80
	81	#define MCA_MC32_ID 0x0041 /* Our MCA ident */