[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / onenand / onenand_sim.c

/*
 *  linux/drivers/mtd/onenand/onenand_sim.c
 *
 *  The OneNAND simulator
 *
 *  Copyright © 2005-2007 Samsung Electronics
 *  Kyungmin Park <kyungmin.park@samsung.com>
 *
 *  Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
 *  Flex-OneNAND simulator support
 *  Copyright (C) Samsung Electronics, 2008
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>

#include <linux/io.h>

#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
#define CONFIG_ONENAND_SIM_MANUFACTURER         0xec
#endif

#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
#define CONFIG_ONENAND_SIM_DEVICE_ID            0x04
#endif

#define CONFIG_FLEXONENAND ((CONFIG_ONENAND_SIM_DEVICE_ID >> 9) & 1)

#ifndef CONFIG_ONENAND_SIM_VERSION_ID
#define CONFIG_ONENAND_SIM_VERSION_ID           0x1e
#endif

#ifndef CONFIG_ONENAND_SIM_TECHNOLOGY_ID
#define CONFIG_ONENAND_SIM_TECHNOLOGY_ID CONFIG_FLEXONENAND
#endif

/* Initial boundary values for Flex-OneNAND Simulator */
#ifndef CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY
#define CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY	0x01
#endif

#ifndef CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY
#define CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY	0x01
#endif

static int manuf_id	= CONFIG_ONENAND_SIM_MANUFACTURER;
static int device_id	= CONFIG_ONENAND_SIM_DEVICE_ID;
static int version_id	= CONFIG_ONENAND_SIM_VERSION_ID;
static int technology_id = CONFIG_ONENAND_SIM_TECHNOLOGY_ID;
static int boundary[] = {
	CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY,
	CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY,
};

struct onenand_flash {
	void __iomem *base;
	void __iomem *data;
};

#define ONENAND_CORE(flash)		(flash->data)
#define ONENAND_CORE_SPARE(flash, this, offset)				\
	((flash->data) + (this->chipsize) + (offset >> 5))

#define ONENAND_MAIN_AREA(this, offset)					\
	(this->base + ONENAND_DATARAM + offset)

#define ONENAND_SPARE_AREA(this, offset)				\
	(this->base + ONENAND_SPARERAM + offset)

#define ONENAND_GET_WP_STATUS(this)					\
	(readw(this->base + ONENAND_REG_WP_STATUS))

#define ONENAND_SET_WP_STATUS(v, this)					\
	(writew(v, this->base + ONENAND_REG_WP_STATUS))

/* It has all 0xff chars */
#define MAX_ONENAND_PAGESIZE		(4096 + 128)
static unsigned char *ffchars;

#if CONFIG_FLEXONENAND
#define PARTITION_NAME "Flex-OneNAND simulator partition"
#else
#define PARTITION_NAME "OneNAND simulator partition"
#endif

static struct mtd_partition os_partitions[] = {
	{
		.name		= PARTITION_NAME,
		.offset		= 0,
		.size		= MTDPART_SIZ_FULL,
	},
};

/*
 * OneNAND simulator mtd
 */
struct onenand_info {
	struct mtd_info		mtd;
	struct mtd_partition	*parts;
	struct onenand_chip	onenand;
	struct onenand_flash	flash;
};

static struct onenand_info *info;

#define DPRINTK(format, args...)					\
do {									\
	printk(KERN_DEBUG "%s[%d]: " format "\n", __func__,		\
			   __LINE__, ##args);				\
} while (0)

/**
 * onenand_lock_handle - Handle Lock scheme
 * @this:		OneNAND device structure
 * @cmd:		The command to be sent
 *
 * Send lock command to OneNAND device.
 * The lock scheme depends on chip type.
 */
static void onenand_lock_handle(struct onenand_chip *this, int cmd)
{
	int block_lock_scheme;
	int status;

	status = ONENAND_GET_WP_STATUS(this);
	block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK);

	switch (cmd) {
	case ONENAND_CMD_UNLOCK:
	case ONENAND_CMD_UNLOCK_ALL:
		if (block_lock_scheme)
			ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
		else
			ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this);
		break;

	case ONENAND_CMD_LOCK:
		if (block_lock_scheme)
			ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
		else
			ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this);
		break;

	case ONENAND_CMD_LOCK_TIGHT:
		if (block_lock_scheme)
			ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
		else
			ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS, this);
		break;

	default:
		break;
	}
}

/**
 * onenand_bootram_handle - Handle BootRAM area
 * @this:		OneNAND device structure
 * @cmd:		The command to be sent
 *
 * Emulate BootRAM area. It is possible to do basic operation using BootRAM.
 */
static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
{
	switch (cmd) {
	case ONENAND_CMD_READID:
		writew(manuf_id, this->base);
		writew(device_id, this->base + 2);
		writew(version_id, this->base + 4);
		break;

	default:
		/* REVIST: Handle other commands */
		break;
	}
}

/**
 * onenand_update_interrupt - Set interrupt register
 * @this:         OneNAND device structure
 * @cmd:          The command to be sent
 *
 * Update interrupt register. The status depends on command.
 */
static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
{
	int interrupt = ONENAND_INT_MASTER;

	switch (cmd) {
	case ONENAND_CMD_READ:
	case ONENAND_CMD_READOOB:
		interrupt |= ONENAND_INT_READ;
		break;

	case ONENAND_CMD_PROG:
	case ONENAND_CMD_PROGOOB:
		interrupt |= ONENAND_INT_WRITE;
		break;

	case ONENAND_CMD_ERASE:
		interrupt |= ONENAND_INT_ERASE;
		break;

	case ONENAND_CMD_RESET:
		interrupt |= ONENAND_INT_RESET;
		break;

	default:
		break;
	}

	writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
}

/**
 * onenand_check_overwrite - Check if over-write happened
 * @dest:		The destination pointer
 * @src:		The source pointer
 * @count:		The length to be check
 *
 * Returns:		0 on same, otherwise 1
 *
 * Compare the source with destination
 */
static int onenand_check_overwrite(void *dest, void *src, size_t count)
{
	unsigned int *s = (unsigned int *) src;
	unsigned int *d = (unsigned int *) dest;
	int i;

	count >>= 2;
	for (i = 0; i < count; i++)
		if ((*s++ ^ *d++) != 0)
			return 1;

	return 0;
}

/**
 * onenand_data_handle - Handle OneNAND Core and DataRAM
 * @this:		OneNAND device structure
 * @cmd:		The command to be sent
 * @dataram:		Which dataram used
 * @offset:		The offset to OneNAND Core
 *
 * Copy data from OneNAND Core to DataRAM (read)
 * Copy data from DataRAM to OneNAND Core (write)
 * Erase the OneNAND Core (erase)
 */
static void onenand_data_handle(struct onenand_chip *this, int cmd,
				int dataram, unsigned int offset)
{
	struct mtd_info *mtd = &info->mtd;
	struct onenand_flash *flash = this->priv;
	int main_offset, spare_offset, die = 0;
	void __iomem *src;
	void __iomem *dest;
	unsigned int i;
	static int pi_operation;
	int erasesize, rgn;

	if (dataram) {
		main_offset = mtd->writesize;
		spare_offset = mtd->oobsize;
	} else {
		main_offset = 0;
		spare_offset = 0;
	}

	if (pi_operation) {
		die = readw(this->base + ONENAND_REG_START_ADDRESS2);
		die >>= ONENAND_DDP_SHIFT;
	}

	switch (cmd) {
	case FLEXONENAND_CMD_PI_ACCESS:
		pi_operation = 1;
		break;

	case ONENAND_CMD_RESET:
		pi_operation = 0;
		break;

	case ONENAND_CMD_READ:
		src = ONENAND_CORE(flash) + offset;
		dest = ONENAND_MAIN_AREA(this, main_offset);
		if (pi_operation) {
			writew(boundary[die], this->base + ONENAND_DATARAM);
			break;
		}
		memcpy(dest, src, mtd->writesize);
		/* Fall through */

	case ONENAND_CMD_READOOB:
		src = ONENAND_CORE_SPARE(flash, this, offset);
		dest = ONENAND_SPARE_AREA(this, spare_offset);
		memcpy(dest, src, mtd->oobsize);
		break;

	case ONENAND_CMD_PROG:
		src = ONENAND_MAIN_AREA(this, main_offset);
		dest = ONENAND_CORE(flash) + offset;
		if (pi_operation) {
			boundary[die] = readw(this->base + ONENAND_DATARAM);
			break;
		}
		/* To handle partial write */
		for (i = 0; i < (1 << mtd->subpage_sft); i++) {
			int off = i * this->subpagesize;
			if (!memcmp(src + off, ffchars, this->subpagesize))
				continue;
			if (memcmp(dest + off, ffchars, this->subpagesize) &&
			    onenand_check_overwrite(dest + off, src + off, this->subpagesize))
				printk(KERN_ERR "over-write happend at 0x%08x\n", offset);
			memcpy(dest + off, src + off, this->subpagesize);
		}
		/* Fall through */

	case ONENAND_CMD_PROGOOB:
		src = ONENAND_SPARE_AREA(this, spare_offset);
		/* Check all data is 0xff chars */
		if (!memcmp(src, ffchars, mtd->oobsize))
			break;

		dest = ONENAND_CORE_SPARE(flash, this, offset);
		if (memcmp(dest, ffchars, mtd->oobsize) &&
		    onenand_check_overwrite(dest, src, mtd->oobsize))
			printk(KERN_ERR "OOB: over-write happend at 0x%08x\n",
			       offset);
		memcpy(dest, src, mtd->oobsize);
		break;

	case ONENAND_CMD_ERASE:
		if (pi_operation)
			break;

		if (FLEXONENAND(this)) {
			rgn = flexonenand_region(mtd, offset);
			erasesize = mtd->eraseregions[rgn].erasesize;
		} else
			erasesize = mtd->erasesize;

		memset(ONENAND_CORE(flash) + offset, 0xff, erasesize);
		memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff,
		       (erasesize >> 5));
		break;

	default:
		break;
	}
}

/**
 * onenand_command_handle - Handle command
 * @this:		OneNAND device structure
 * @cmd:		The command to be sent
 *
 * Emulate OneNAND command.
 */
static void onenand_command_handle(struct onenand_chip *this, int cmd)
{
	unsigned long offset = 0;
	int block = -1, page = -1, bufferram = -1;
	int dataram = 0;

	switch (cmd) {
	case ONENAND_CMD_UNLOCK:
	case ONENAND_CMD_LOCK:
	case ONENAND_CMD_LOCK_TIGHT:
	case ONENAND_CMD_UNLOCK_ALL:
		onenand_lock_handle(this, cmd);
		break;

	case ONENAND_CMD_BUFFERRAM:
		/* Do nothing */
		return;

	default:
		block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
		if (block & (1 << ONENAND_DDP_SHIFT)) {
			block &= ~(1 << ONENAND_DDP_SHIFT);
			/* The half of chip block */
			block += this->chipsize >> (this->erase_shift + 1);
		}
		if (cmd == ONENAND_CMD_ERASE)
			break;

		page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
		page = (page >> ONENAND_FPA_SHIFT);
		bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);
		bufferram >>= ONENAND_BSA_SHIFT;
		bufferram &= ONENAND_BSA_DATARAM1;
		dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
		break;
	}

	if (block != -1)
		offset = onenand_addr(this, block);

	if (page != -1)
		offset += page << this->page_shift;

	onenand_data_handle(this, cmd, dataram, offset);

	onenand_update_interrupt(this, cmd);
}

/**
 * onenand_writew - [OneNAND Interface] Emulate write operation
 * @value:		value to write
 * @addr:		address to write
 *
 * Write OneNAND register with value
 */
static void onenand_writew(unsigned short value, void __iomem * addr)
{
	struct onenand_chip *this = info->mtd.priv;

	/* BootRAM handling */
	if (addr < this->base + ONENAND_DATARAM) {
		onenand_bootram_handle(this, value);
		return;
	}
	/* Command handling */
	if (addr == this->base + ONENAND_REG_COMMAND)
		onenand_command_handle(this, value);

	writew(value, addr);
}

/**
 * flash_init - Initialize OneNAND simulator
 * @flash:		OneNAND simulator data strucutres
 *
 * Initialize OneNAND simulator.
 */
static int __init flash_init(struct onenand_flash *flash)
{
	int density, size;
	int buffer_size;

	flash->base = kzalloc(131072, GFP_KERNEL);
	if (!flash->base) {
		printk(KERN_ERR "Unable to allocate base address.\n");
		return -ENOMEM;
	}

	density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
	density &= ONENAND_DEVICE_DENSITY_MASK;
	size = ((16 << 20) << density);

	ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
	if (!ONENAND_CORE(flash)) {
		printk(KERN_ERR "Unable to allocate nand core address.\n");
		kfree(flash->base);
		return -ENOMEM;
	}

	memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));

	/* Setup registers */
	writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
	writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
	writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
	writew(technology_id, flash->base + ONENAND_REG_TECHNOLOGY);

	if (density < 2 && (!CONFIG_FLEXONENAND))
		buffer_size = 0x0400;	/* 1KiB page */
	else
		buffer_size = 0x0800;	/* 2KiB page */
	writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);

	return 0;
}

/**
 * flash_exit - Clean up OneNAND simulator
 * @flash:		OneNAND simulator data structures
 *
 * Clean up OneNAND simulator.
 */
static void flash_exit(struct onenand_flash *flash)
{
	vfree(ONENAND_CORE(flash));
	kfree(flash->base);
}

static int __init onenand_sim_init(void)
{
	/* Allocate all 0xff chars pointer */
	ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
	if (!ffchars) {
		printk(KERN_ERR "Unable to allocate ff chars.\n");
		return -ENOMEM;
	}
	memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);

	/* Allocate OneNAND simulator mtd pointer */
	info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL);
	if (!info) {
		printk(KERN_ERR "Unable to allocate core structures.\n");
		kfree(ffchars);
		return -ENOMEM;
	}

	/* Override write_word function */
	info->onenand.write_word = onenand_writew;

	if (flash_init(&info->flash)) {
		printk(KERN_ERR "Unable to allocate flash.\n");
		kfree(ffchars);
		kfree(info);
		return -ENOMEM;
	}

	info->parts = os_partitions;

	info->onenand.base = info->flash.base;
	info->onenand.priv = &info->flash;

	info->mtd.name = "OneNAND simulator";
	info->mtd.priv = &info->onenand;
	info->mtd.owner = THIS_MODULE;

	if (onenand_scan(&info->mtd, 1)) {
		flash_exit(&info->flash);
		kfree(ffchars);
		kfree(info);
		return -ENXIO;
	}

	add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions));

	return 0;
}

static void __exit onenand_sim_exit(void)
{
	struct onenand_chip *this = info->mtd.priv;
	struct onenand_flash *flash = this->priv;

	onenand_release(&info->mtd);
	flash_exit(flash);
	kfree(ffchars);
	kfree(info);
}

module_init(onenand_sim_init);
module_exit(onenand_sim_exit);

MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
MODULE_DESCRIPTION("The OneNAND flash simulator");
MODULE_LICENSE("GPL");
Commit	Line	Data
8dab169b KP	1	/*
	2	* linux/drivers/mtd/onenand/onenand_sim.c
	3	*
	4	* The OneNAND simulator
	5	*
16adce7b	6	* Copyright © 2005-2007 Samsung Electronics
8dab169b KP	7	* Kyungmin Park <kyungmin.park@samsung.com>
8dab169b KP	8	*
5988af23 RH	9	* Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
	10	* Flex-OneNAND simulator support
	11	* Copyright (C) Samsung Electronics, 2008
	12	*
8dab169b KP	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17
	18	#include <linux/kernel.h>
5a0e3ad6	19	#include <linux/slab.h>
8dab169b KP	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/vmalloc.h>
	23	#include <linux/mtd/mtd.h>
	24	#include <linux/mtd/partitions.h>
	25	#include <linux/mtd/onenand.h>
	26
16adce7b	27	#include <linux/io.h>
8dab169b KP	28
	29	#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
	30	#define CONFIG_ONENAND_SIM_MANUFACTURER 0xec
	31	#endif
5988af23	32
8dab169b KP	33	#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
	34	#define CONFIG_ONENAND_SIM_DEVICE_ID 0x04
	35	#endif
5988af23 RH	36
	37	#define CONFIG_FLEXONENAND ((CONFIG_ONENAND_SIM_DEVICE_ID >> 9) & 1)
	38
8dab169b KP	39	#ifndef CONFIG_ONENAND_SIM_VERSION_ID
	40	#define CONFIG_ONENAND_SIM_VERSION_ID 0x1e
	41	#endif
	42
5988af23 RH	43	#ifndef CONFIG_ONENAND_SIM_TECHNOLOGY_ID
	44	#define CONFIG_ONENAND_SIM_TECHNOLOGY_ID CONFIG_FLEXONENAND
	45	#endif
	46
	47	/* Initial boundary values for Flex-OneNAND Simulator */
	48	#ifndef CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY
	49	#define CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY 0x01
	50	#endif
	51
	52	#ifndef CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY
	53	#define CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY 0x01
	54	#endif
	55
8dab169b KP	56	static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER;
	57	static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID;
	58	static int version_id = CONFIG_ONENAND_SIM_VERSION_ID;
5988af23 RH	59	static int technology_id = CONFIG_ONENAND_SIM_TECHNOLOGY_ID;
	60	static int boundary[] = {
	61	CONFIG_FLEXONENAND_SIM_DIE0_BOUNDARY,
	62	CONFIG_FLEXONENAND_SIM_DIE1_BOUNDARY,
	63	};
8dab169b KP	64
	65	struct onenand_flash {
	66	void __iomem *base;
	67	void __iomem *data;
	68	};
	69
	70	#define ONENAND_CORE(flash) (flash->data)
	71	#define ONENAND_CORE_SPARE(flash, this, offset) \
	72	((flash->data) + (this->chipsize) + (offset >> 5))
	73
	74	#define ONENAND_MAIN_AREA(this, offset) \
	75	(this->base + ONENAND_DATARAM + offset)
	76
	77	#define ONENAND_SPARE_AREA(this, offset) \
	78	(this->base + ONENAND_SPARERAM + offset)
	79
	80	#define ONENAND_GET_WP_STATUS(this) \
	81	(readw(this->base + ONENAND_REG_WP_STATUS))
	82
	83	#define ONENAND_SET_WP_STATUS(v, this) \
	84	(writew(v, this->base + ONENAND_REG_WP_STATUS))
	85
	86	/* It has all 0xff chars */
5988af23	87	#define MAX_ONENAND_PAGESIZE (4096 + 128)
8dab169b KP	88	static unsigned char *ffchars;
8dab169b KP	89
5988af23 RH	90	#if CONFIG_FLEXONENAND
	91	#define PARTITION_NAME "Flex-OneNAND simulator partition"
	92	#else
	93	#define PARTITION_NAME "OneNAND simulator partition"
	94	#endif
	95
8dab169b KP	96	static struct mtd_partition os_partitions[] = {
8dab169b KP	97	{
5988af23	98	.name = PARTITION_NAME,
8dab169b KP	99	.offset = 0,
	100	.size = MTDPART_SIZ_FULL,
	101	},
	102	};
	103
	104	/*
	105	* OneNAND simulator mtd
	106	*/
	107	struct onenand_info {
	108	struct mtd_info mtd;
	109	struct mtd_partition *parts;
	110	struct onenand_chip onenand;
	111	struct onenand_flash flash;
	112	};
	113
73ff0075	114	static struct onenand_info *info;
8dab169b KP	115
	116	#define DPRINTK(format, args...) \
	117	do { \
16adce7b DW	118	printk(KERN_DEBUG "%s[%d]: " format "\n", __func__, \
16adce7b DW	119	__LINE__, ##args); \
8dab169b KP	120	} while (0)
	121
	122	/**
	123	* onenand_lock_handle - Handle Lock scheme
19e75ea7 RD	124	* @this: OneNAND device structure
19e75ea7 RD	125	* @cmd: The command to be sent
8dab169b KP	126	*
8dab169b KP	127	* Send lock command to OneNAND device.
19e75ea7	128	* The lock scheme depends on chip type.
8dab169b KP	129	*/
	130	static void onenand_lock_handle(struct onenand_chip *this, int cmd)
	131	{
	132	int block_lock_scheme;
	133	int status;
	134
	135	status = ONENAND_GET_WP_STATUS(this);
	136	block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK);
	137
	138	switch (cmd) {
	139	case ONENAND_CMD_UNLOCK:
5988af23	140	case ONENAND_CMD_UNLOCK_ALL:
8dab169b KP	141	if (block_lock_scheme)
	142	ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
	143	else
	144	ONENAND_SET_WP_STATUS(status \| ONENAND_WP_US, this);
	145	break;
	146
	147	case ONENAND_CMD_LOCK:
	148	if (block_lock_scheme)
	149	ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
	150	else
	151	ONENAND_SET_WP_STATUS(status \| ONENAND_WP_LS, this);
	152	break;
	153
	154	case ONENAND_CMD_LOCK_TIGHT:
	155	if (block_lock_scheme)
	156	ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
	157	else
	158	ONENAND_SET_WP_STATUS(status \| ONENAND_WP_LTS, this);
	159	break;
	160
	161	default:
	162	break;
	163	}
	164	}
	165
	166	/**
	167	* onenand_bootram_handle - Handle BootRAM area
19e75ea7 RD	168	* @this: OneNAND device structure
19e75ea7 RD	169	* @cmd: The command to be sent
8dab169b KP	170	*
	171	* Emulate BootRAM area. It is possible to do basic operation using BootRAM.
	172	*/
	173	static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
	174	{
	175	switch (cmd) {
	176	case ONENAND_CMD_READID:
	177	writew(manuf_id, this->base);
	178	writew(device_id, this->base + 2);
	179	writew(version_id, this->base + 4);
	180	break;
	181
	182	default:
	183	/* REVIST: Handle other commands */
	184	break;
	185	}
	186	}
	187
	188	/**
	189	* onenand_update_interrupt - Set interrupt register
19e75ea7 RD	190	* @this: OneNAND device structure
19e75ea7 RD	191	* @cmd: The command to be sent
8dab169b	192	*
19e75ea7	193	* Update interrupt register. The status depends on command.
8dab169b KP	194	*/
	195	static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
	196	{
	197	int interrupt = ONENAND_INT_MASTER;
	198
	199	switch (cmd) {
	200	case ONENAND_CMD_READ:
	201	case ONENAND_CMD_READOOB:
	202	interrupt \|= ONENAND_INT_READ;
	203	break;
	204
	205	case ONENAND_CMD_PROG:
	206	case ONENAND_CMD_PROGOOB:
	207	interrupt \|= ONENAND_INT_WRITE;
	208	break;
	209
	210	case ONENAND_CMD_ERASE:
	211	interrupt \|= ONENAND_INT_ERASE;
	212	break;
	213
	214	case ONENAND_CMD_RESET:
	215	interrupt \|= ONENAND_INT_RESET;
	216	break;
	217
	218	default:
	219	break;
	220	}
	221
	222	writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
	223	}
	224
	225	/**
19e75ea7 RD	226	* onenand_check_overwrite - Check if over-write happened
	227	* @dest: The destination pointer
	228	* @src: The source pointer
	229	* @count: The length to be check
	230	*
	231	* Returns: 0 on same, otherwise 1
8dab169b KP	232	*
	233	* Compare the source with destination
	234	*/
	235	static int onenand_check_overwrite(void dest, void src, size_t count)
	236	{
	237	unsigned int s = (unsigned int ) src;
	238	unsigned int d = (unsigned int ) dest;
	239	int i;
	240
	241	count >>= 2;
	242	for (i = 0; i < count; i++)
	243	if ((s++ ^ d++) != 0)
	244	return 1;
	245
	246	return 0;
	247	}
	248
	249	/**
	250	* onenand_data_handle - Handle OneNAND Core and DataRAM
19e75ea7 RD	251	* @this: OneNAND device structure
	252	* @cmd: The command to be sent
	253	* @dataram: Which dataram used
	254	* @offset: The offset to OneNAND Core
8dab169b KP	255	*
	256	* Copy data from OneNAND Core to DataRAM (read)
	257	* Copy data from DataRAM to OneNAND Core (write)
	258	* Erase the OneNAND Core (erase)
	259	*/
	260	static void onenand_data_handle(struct onenand_chip *this, int cmd,
	261	int dataram, unsigned int offset)
	262	{
	263	struct mtd_info *mtd = &info->mtd;
	264	struct onenand_flash *flash = this->priv;
5988af23	265	int main_offset, spare_offset, die = 0;
8dab169b KP	266	void __iomem *src;
	267	void __iomem *dest;
	268	unsigned int i;
5988af23 RH	269	static int pi_operation;
5988af23 RH	270	int erasesize, rgn;
8dab169b KP	271
	272	if (dataram) {
	273	main_offset = mtd->writesize;
	274	spare_offset = mtd->oobsize;
	275	} else {
	276	main_offset = 0;
	277	spare_offset = 0;
	278	}
	279
5988af23 RH	280	if (pi_operation) {
	281	die = readw(this->base + ONENAND_REG_START_ADDRESS2);
	282	die >>= ONENAND_DDP_SHIFT;
	283	}
	284
8dab169b	285	switch (cmd) {
5988af23 RH	286	case FLEXONENAND_CMD_PI_ACCESS:
	287	pi_operation = 1;
	288	break;
	289
	290	case ONENAND_CMD_RESET:
	291	pi_operation = 0;
	292	break;
	293
8dab169b KP	294	case ONENAND_CMD_READ:
	295	src = ONENAND_CORE(flash) + offset;
	296	dest = ONENAND_MAIN_AREA(this, main_offset);
5988af23 RH	297	if (pi_operation) {
	298	writew(boundary[die], this->base + ONENAND_DATARAM);
	299	break;
	300	}
8dab169b KP	301	memcpy(dest, src, mtd->writesize);
	302	/* Fall through */
	303
	304	case ONENAND_CMD_READOOB:
	305	src = ONENAND_CORE_SPARE(flash, this, offset);
	306	dest = ONENAND_SPARE_AREA(this, spare_offset);
	307	memcpy(dest, src, mtd->oobsize);
	308	break;
	309
	310	case ONENAND_CMD_PROG:
	311	src = ONENAND_MAIN_AREA(this, main_offset);
	312	dest = ONENAND_CORE(flash) + offset;
5988af23 RH	313	if (pi_operation) {
	314	boundary[die] = readw(this->base + ONENAND_DATARAM);
	315	break;
	316	}
8dab169b KP	317	/* To handle partial write */
	318	for (i = 0; i < (1 << mtd->subpage_sft); i++) {
	319	int off = i * this->subpagesize;
	320	if (!memcmp(src + off, ffchars, this->subpagesize))
	321	continue;
	322	if (memcmp(dest + off, ffchars, this->subpagesize) &&
	323	onenand_check_overwrite(dest + off, src + off, this->subpagesize))
	324	printk(KERN_ERR "over-write happend at 0x%08x\n", offset);
	325	memcpy(dest + off, src + off, this->subpagesize);
	326	}
	327	/* Fall through */
	328
	329	case ONENAND_CMD_PROGOOB:
	330	src = ONENAND_SPARE_AREA(this, spare_offset);
	331	/* Check all data is 0xff chars */
	332	if (!memcmp(src, ffchars, mtd->oobsize))
	333	break;
	334
	335	dest = ONENAND_CORE_SPARE(flash, this, offset);
	336	if (memcmp(dest, ffchars, mtd->oobsize) &&
	337	onenand_check_overwrite(dest, src, mtd->oobsize))
	338	printk(KERN_ERR "OOB: over-write happend at 0x%08x\n",
	339	offset);
	340	memcpy(dest, src, mtd->oobsize);
	341	break;
	342
	343	case ONENAND_CMD_ERASE:
5988af23 RH	344	if (pi_operation)
	345	break;
	346
	347	if (FLEXONENAND(this)) {
	348	rgn = flexonenand_region(mtd, offset);
	349	erasesize = mtd->eraseregions[rgn].erasesize;
	350	} else
	351	erasesize = mtd->erasesize;
	352
	353	memset(ONENAND_CORE(flash) + offset, 0xff, erasesize);
8dab169b	354	memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff,
5988af23	355	(erasesize >> 5));
8dab169b KP	356	break;
	357
	358	default:
	359	break;
	360	}
	361	}
	362
	363	/**
	364	* onenand_command_handle - Handle command
19e75ea7 RD	365	* @this: OneNAND device structure
19e75ea7 RD	366	* @cmd: The command to be sent
8dab169b KP	367	*
	368	* Emulate OneNAND command.
	369	*/
	370	static void onenand_command_handle(struct onenand_chip *this, int cmd)
	371	{
	372	unsigned long offset = 0;
	373	int block = -1, page = -1, bufferram = -1;
	374	int dataram = 0;
	375
	376	switch (cmd) {
	377	case ONENAND_CMD_UNLOCK:
	378	case ONENAND_CMD_LOCK:
	379	case ONENAND_CMD_LOCK_TIGHT:
	380	case ONENAND_CMD_UNLOCK_ALL:
	381	onenand_lock_handle(this, cmd);
	382	break;
	383
	384	case ONENAND_CMD_BUFFERRAM:
	385	/* Do nothing */
	386	return;
	387
	388	default:
	389	block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
	390	if (block & (1 << ONENAND_DDP_SHIFT)) {
	391	block &= ~(1 << ONENAND_DDP_SHIFT);
	392	/* The half of chip block */
	393	block += this->chipsize >> (this->erase_shift + 1);
	394	}
	395	if (cmd == ONENAND_CMD_ERASE)
	396	break;
	397
	398	page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
	399	page = (page >> ONENAND_FPA_SHIFT);
	400	bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);
	401	bufferram >>= ONENAND_BSA_SHIFT;
	402	bufferram &= ONENAND_BSA_DATARAM1;
	403	dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
	404	break;
	405	}
	406
	407	if (block != -1)
5988af23	408	offset = onenand_addr(this, block);
8dab169b KP	409
	410	if (page != -1)
	411	offset += page << this->page_shift;
	412
	413	onenand_data_handle(this, cmd, dataram, offset);
	414
	415	onenand_update_interrupt(this, cmd);
	416	}
	417
	418	/**
	419	* onenand_writew - [OneNAND Interface] Emulate write operation
19e75ea7 RD	420	* @value: value to write
19e75ea7 RD	421	* @addr: address to write
8dab169b KP	422	*
	423	* Write OneNAND register with value
	424	*/
	425	static void onenand_writew(unsigned short value, void __iomem * addr)
	426	{
	427	struct onenand_chip *this = info->mtd.priv;
	428
	429	/* BootRAM handling */
	430	if (addr < this->base + ONENAND_DATARAM) {
	431	onenand_bootram_handle(this, value);
	432	return;
	433	}
	434	/* Command handling */
	435	if (addr == this->base + ONENAND_REG_COMMAND)
	436	onenand_command_handle(this, value);
	437
	438	writew(value, addr);
	439	}
	440
	441	/**
	442	* flash_init - Initialize OneNAND simulator
19e75ea7	443	* @flash: OneNAND simulator data strucutres
8dab169b KP	444	*
	445	* Initialize OneNAND simulator.
	446	*/
	447	static int __init flash_init(struct onenand_flash *flash)
	448	{
	449	int density, size;
	450	int buffer_size;
	451
16adce7b	452	flash->base = kzalloc(131072, GFP_KERNEL);
8dab169b	453	if (!flash->base) {
16adce7b	454	printk(KERN_ERR "Unable to allocate base address.\n");
8dab169b KP	455	return -ENOMEM;
	456	}
	457
	458	density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
5988af23	459	density &= ONENAND_DEVICE_DENSITY_MASK;
8dab169b KP	460	size = ((16 << 20) << density);
	461
	462	ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
	463	if (!ONENAND_CORE(flash)) {
16adce7b	464	printk(KERN_ERR "Unable to allocate nand core address.\n");
8dab169b KP	465	kfree(flash->base);
	466	return -ENOMEM;
	467	}
	468
	469	memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));
	470
	471	/* Setup registers */
	472	writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
	473	writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
	474	writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
5988af23	475	writew(technology_id, flash->base + ONENAND_REG_TECHNOLOGY);
8dab169b	476
5988af23	477	if (density < 2 && (!CONFIG_FLEXONENAND))
16adce7b	478	buffer_size = 0x0400; /* 1KiB page */
8dab169b	479	else
16adce7b	480	buffer_size = 0x0800; /* 2KiB page */
8dab169b KP	481	writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);
	482
	483	return 0;
	484	}
	485
	486	/**
	487	* flash_exit - Clean up OneNAND simulator
19e75ea7	488	* @flash: OneNAND simulator data structures
8dab169b KP	489	*
	490	* Clean up OneNAND simulator.
	491	*/
	492	static void flash_exit(struct onenand_flash *flash)
	493	{
	494	vfree(ONENAND_CORE(flash));
	495	kfree(flash->base);
8dab169b KP	496	}
	497
	498	static int __init onenand_sim_init(void)
	499	{
	500	/* Allocate all 0xff chars pointer */
	501	ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
	502	if (!ffchars) {
	503	printk(KERN_ERR "Unable to allocate ff chars.\n");
	504	return -ENOMEM;
	505	}
	506	memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);
	507
	508	/* Allocate OneNAND simulator mtd pointer */
	509	info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL);
	510	if (!info) {
	511	printk(KERN_ERR "Unable to allocate core structures.\n");
	512	kfree(ffchars);
	513	return -ENOMEM;
	514	}
	515
	516	/* Override write_word function */
	517	info->onenand.write_word = onenand_writew;
	518
	519	if (flash_init(&info->flash)) {
19e75ea7	520	printk(KERN_ERR "Unable to allocate flash.\n");
8dab169b KP	521	kfree(ffchars);
	522	kfree(info);
	523	return -ENOMEM;
	524	}
	525
	526	info->parts = os_partitions;
	527
	528	info->onenand.base = info->flash.base;
	529	info->onenand.priv = &info->flash;
	530
	531	info->mtd.name = "OneNAND simulator";
	532	info->mtd.priv = &info->onenand;
	533	info->mtd.owner = THIS_MODULE;
	534
	535	if (onenand_scan(&info->mtd, 1)) {
	536	flash_exit(&info->flash);
	537	kfree(ffchars);
	538	kfree(info);
	539	return -ENXIO;
	540	}
	541
	542	add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions));
	543
	544	return 0;
	545	}
	546
	547	static void __exit onenand_sim_exit(void)
	548	{
	549	struct onenand_chip *this = info->mtd.priv;
	550	struct onenand_flash *flash = this->priv;
	551
	552	onenand_release(&info->mtd);
	553	flash_exit(flash);
	554	kfree(ffchars);
	555	kfree(info);
	556	}
	557
	558	module_init(onenand_sim_init);
	559	module_exit(onenand_sim_exit);
	560
	561	MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
	562	MODULE_DESCRIPTION("The OneNAND flash simulator");
	563	MODULE_LICENSE("GPL");