[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / chips / Kconfig

menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targeted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP

config MTD_CFI_NOSWAP
	bool "NO"
	---help---
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

	  If you have a LART, on which the data (and address) lines were
	  connected in a fashion which ensured that the nets were as short
	  as possible, resulting in a bit-shuffling which seems utterly
	  random to the untrained eye, you need the LART_ENDIAN_BYTE option.

	  Yes, there really exists something sicker than PDP-endian :)

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	select HAVE_MTD_OTP
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for Intel/Sharp flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on Intel
	  StrataFlash and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for AMD/Fujitsu/Spansion flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on chips
	  including the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for ST (Advanced Architecture) flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
1da177e4 LT	1	menu "RAM/ROM/Flash chip drivers"
	2	depends on MTD!=n
	3
	4	config MTD_CFI
	5	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4	6	select MTD_GEN_PROBE
5e706469	7	select MTD_CFI_UTIL
1da177e4 LT	8	help
	9	The Common Flash Interface specification was developed by Intel,
	10	AMD and other flash manufactures that provides a universal method
	11	for probing the capabilities of flash devices. If you wish to
	12	support any device that is CFI-compliant, you need to enable this
	13	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	14	for more information on CFI.
	15
	16	config MTD_JEDECPROBE
	17	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4 LT	18	select MTD_GEN_PROBE
	19	help
	20	This option enables JEDEC-style probing of flash chips which are not
	21	compatible with the Common Flash Interface, but will use the common
25985edc	22	CFI-targeted flash drivers for any chips which are identified which
1da177e4	23	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	24	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	25	Intel chips.
1da177e4 LT	26
	27	config MTD_GEN_PROBE
	28	tristate
	29
	30	config MTD_CFI_ADV_OPTIONS
	31	bool "Flash chip driver advanced configuration options"
	32	depends on MTD_GEN_PROBE
	33	help
	34	If you need to specify a specific endianness for access to flash
	35	chips, or if you wish to reduce the size of the kernel by including
	36	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	37	option does not directly affect the code, but will enable other
1da177e4 LT	38	configuration options which allow you to do so.
	39
	40	If unsure, say 'N'.
	41
	42	choice
	43	prompt "Flash cmd/query data swapping"
	44	depends on MTD_CFI_ADV_OPTIONS
	45	default MTD_CFI_NOSWAP
	46
	47	config MTD_CFI_NOSWAP
	48	bool "NO"
	49	---help---
	50	This option defines the way in which the CPU attempts to arrange
	51	data bits when writing the 'magic' commands to the chips. Saying
	52	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	53	enabled, means that the CPU will not do any swapping; the chips
1f948b43	54	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	55	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	56	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	57
	58	If you have a LART, on which the data (and address) lines were
	59	connected in a fashion which ensured that the nets were as short
	60	as possible, resulting in a bit-shuffling which seems utterly
	61	random to the untrained eye, you need the LART_ENDIAN_BYTE option.
	62
	63	Yes, there really exists something sicker than PDP-endian :)
	64
	65	config MTD_CFI_BE_BYTE_SWAP
	66	bool "BIG_ENDIAN_BYTE"
	67
	68	config MTD_CFI_LE_BYTE_SWAP
	69	bool "LITTLE_ENDIAN_BYTE"
	70
	71	endchoice
	72
	73	config MTD_CFI_GEOMETRY
	74	bool "Specific CFI Flash geometry selection"
	75	depends on MTD_CFI_ADV_OPTIONS
	76	help
1f948b43	77	This option does not affect the code directly, but will enable
1da177e4	78	some other configuration options which would allow you to reduce
1f948b43 TG	79	the size of the kernel by including support for only certain
1f948b43 TG	80	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	81	which are supported by the current code will be enabled.
	82
	83	config MTD_MAP_BANK_WIDTH_1
	84	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	85	default y
	86	help
	87	If you wish to support CFI devices on a physical bus which is
	88	8 bits wide, say 'Y'.
	89
	90	config MTD_MAP_BANK_WIDTH_2
	91	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	92	default y
	93	help
	94	If you wish to support CFI devices on a physical bus which is
	95	16 bits wide, say 'Y'.
	96
	97	config MTD_MAP_BANK_WIDTH_4
	98	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	99	default y
	100	help
	101	If you wish to support CFI devices on a physical bus which is
	102	32 bits wide, say 'Y'.
	103
	104	config MTD_MAP_BANK_WIDTH_8
	105	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	106	default n
	107	help
	108	If you wish to support CFI devices on a physical bus which is
	109	64 bits wide, say 'Y'.
	110
	111	config MTD_MAP_BANK_WIDTH_16
	112	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	113	default n
	114	help
	115	If you wish to support CFI devices on a physical bus which is
	116	128 bits wide, say 'Y'.
	117
	118	config MTD_MAP_BANK_WIDTH_32
	119	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	120	default n
	121	help
	122	If you wish to support CFI devices on a physical bus which is
	123	256 bits wide, say 'Y'.
	124
	125	config MTD_CFI_I1
	126	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	127	default y
	128	help
	129	If your flash chips are not interleaved - i.e. you only have one
	130	flash chip addressed by each bus cycle, then say 'Y'.
	131
	132	config MTD_CFI_I2
	133	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	134	default y
	135	help
	136	If your flash chips are interleaved in pairs - i.e. you have two
	137	flash chips addressed by each bus cycle, then say 'Y'.
	138
	139	config MTD_CFI_I4
	140	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	141	default n
	142	help
	143	If your flash chips are interleaved in fours - i.e. you have four
	144	flash chips addressed by each bus cycle, then say 'Y'.
145
146	config MTD_CFI_I8
147	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
148	default n
149	help
150	If your flash chips are interleaved in eights - i.e. you have eight
151	flash chips addressed by each bus cycle, then say 'Y'.
152
f77814dd NP	153	config MTD_OTP
	154	bool "Protection Registers aka one-time programmable (OTP) bits"
	155	depends on MTD_CFI_ADV_OPTIONS
34a82443	156	select HAVE_MTD_OTP
f77814dd NP	157	default n
	158	help
	159	This enables support for reading, writing and locking so called
	160	"Protection Registers" present on some flash chips.
	161	A subset of them are pre-programmed at the factory with a
	162	unique set of values. The rest is user-programmable.
	163
	164	The user-programmable Protection Registers contain one-time
	165	programmable (OTP) bits; when programmed, register bits cannot be
	166	erased. Each Protection Register can be accessed multiple times to
	167	program individual bits, as long as the register remains unlocked.
	168
	169	Each Protection Register has an associated Lock Register bit. When a
	170	Lock Register bit is programmed, the associated Protection Register
	171	can only be read; it can no longer be programmed. Additionally,
	172	because the Lock Register bits themselves are OTP, when programmed,
	173	Lock Register bits cannot be erased. Therefore, when a Protection
	174	Register is locked, it cannot be unlocked.
	175
	176	This feature should therefore be used with extreme care. Any mistake
	177	in the programming of OTP bits will waste them.
	178
1da177e4 LT	179	config MTD_CFI_INTELEXT
	180	tristate "Support for Intel/Sharp flash chips"
	181	depends on MTD_GEN_PROBE
	182	select MTD_CFI_UTIL
	183	help
	184	The Common Flash Interface defines a number of different command
	185	sets which a CFI-compliant chip may claim to implement. This code
	186	provides support for one of those command sets, used on Intel
	187	StrataFlash and other parts.
	188
	189	config MTD_CFI_AMDSTD
a0e7229e	190	tristate "Support for AMD/Fujitsu/Spansion flash chips"
1da177e4 LT	191	depends on MTD_GEN_PROBE
	192	select MTD_CFI_UTIL
	193	help
	194	The Common Flash Interface defines a number of different command
	195	sets which a CFI-compliant chip may claim to implement. This code
1f948b43	196	provides support for one of those command sets, used on chips
1da177e4 LT	197	including the AMD Am29LV320.
1da177e4 LT	198
1da177e4 LT	199	config MTD_CFI_STAA
	200	tristate "Support for ST (Advanced Architecture) flash chips"
	201	depends on MTD_GEN_PROBE
	202	select MTD_CFI_UTIL
	203	help
	204	The Common Flash Interface defines a number of different command
	205	sets which a CFI-compliant chip may claim to implement. This code
	206	provides support for one of those command sets.
	207
	208	config MTD_CFI_UTIL
	209	tristate
	210
	211	config MTD_RAM
	212	tristate "Support for RAM chips in bus mapping"
1da177e4	213	help
1f948b43	214	This option enables basic support for RAM chips accessed through
1da177e4 LT	215	a bus mapping driver.
	216
	217	config MTD_ROM
	218	tristate "Support for ROM chips in bus mapping"
1da177e4	219	help
1f948b43	220	This option enables basic support for ROM chips accessed through
1da177e4 LT	221	a bus mapping driver.
	222
	223	config MTD_ABSENT
	224	tristate "Support for absent chips in bus mapping"
1da177e4 LT	225	help
	226	This option enables support for a dummy probing driver used to
	227	allocated placeholder MTD devices on systems that have socketed
	228	or removable media. Use of this driver as a fallback chip probe
	229	preserves the expected registration order of MTD device nodes on
	230	the system regardless of media presence. Device nodes created
	231	with this driver will return -ENODEV upon access.
	232
1da177e4 LT	233	config MTD_XIP
1da177e4 LT	234	bool "XIP aware MTD support"
034d2f5a	235	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
1da177e4 LT	236	default y if XIP_KERNEL
	237	help
	238	This allows MTD support to work with flash memory which is also
	239	used for XIP purposes. If you're not sure what this is all about
	240	then say N.
	241
	242	endmenu