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mmc: make sdhci work with ricoh mmc controller
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/pci.h>
18#include <linux/dma-mapping.h>
5a0e3ad6 19#include <linux/slab.h>
ccc92c23 20#include <linux/device.h>
b8c86fc5
PO		 21
22#include <linux/mmc/host.h>
23
24#include <asm/scatterlist.h>
25#include <asm/io.h>
26
27#include "sdhci.h"
28
29/*
30 * PCI registers
31 */
32
33#define PCI_SDHCI_IFPIO 0x00
34#define PCI_SDHCI_IFDMA 0x01
35#define PCI_SDHCI_IFVENDOR 0x02
36
37#define PCI_SLOT_INFO 0x40 /* 8 bits */
38#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
39#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
40
41#define MAX_SLOTS 8
42
22606405 43struct sdhci_pci_chip;
4489428a 44struct sdhci_pci_slot;
22606405
PO		 45
46struct sdhci_pci_fixes {
47 unsigned int quirks;
48
49 int (*probe)(struct sdhci_pci_chip*);
45211e21 50
4489428a 51 int (*probe_slot)(struct sdhci_pci_slot*);
1e72859e 52 void (*remove_slot)(struct sdhci_pci_slot*, int);
4489428a
PO		 53
54 int (*suspend)(struct sdhci_pci_chip*,
55 pm_message_t);
45211e21 56 int (*resume)(struct sdhci_pci_chip*);
22606405
PO		 57};
58
59struct sdhci_pci_slot {
60 struct sdhci_pci_chip *chip;
61 struct sdhci_host *host;
b8c86fc5 62
22606405
PO		 63 int pci_bar;
64};
65
66struct sdhci_pci_chip {
67 struct pci_dev *pdev;
68
69 unsigned int quirks;
70 const struct sdhci_pci_fixes *fixes;
71
72 int num_slots; /* Slots on controller */
73 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
74};
75
76
77/*****************************************************************************\
78 * *
79 * Hardware specific quirk handling *
80 * *
81\*****************************************************************************/
82
83static int ricoh_probe(struct sdhci_pci_chip *chip)
84{
c99436fb
CB		 85 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
86 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 87 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 88 return 0;
89}
90
91static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
92{
93 slot->host->caps =
94 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
95 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 96
ccc92c23
ML		 97 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
98 & SDHCI_CLOCK_BASE_MASK) |
99
100 SDHCI_TIMEOUT_CLK_UNIT |
101 SDHCI_CAN_VDD_330 |
102 SDHCI_CAN_DO_SDMA;
103 return 0;
104}
105
106static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
107{
108 /* Apply a delay to allow controller to settle */
109 /* Otherwise it becomes confused if card state changed
110 during suspend */
111 msleep(500);
22606405
PO		 112 return 0;
113}
114
115static const struct sdhci_pci_fixes sdhci_ricoh = {
116 .probe = ricoh_probe,
84938294
VK		 117 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
118 SDHCI_QUIRK_FORCE_DMA |
119 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 120};
121
ccc92c23
ML		 122static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
123 .probe_slot = ricoh_mmc_probe_slot,
124 .resume = ricoh_mmc_resume,
125 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
126 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
127 SDHCI_QUIRK_NO_CARD_NO_RESET |
128 SDHCI_QUIRK_MISSING_CAPS
129};
130
22606405
PO		 131static const struct sdhci_pci_fixes sdhci_ene_712 = {
132 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
133 SDHCI_QUIRK_BROKEN_DMA,
134};
135
136static const struct sdhci_pci_fixes sdhci_ene_714 = {
137 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
138 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
139 SDHCI_QUIRK_BROKEN_DMA,
140};
141
142static const struct sdhci_pci_fixes sdhci_cafe = {
143 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 144 SDHCI_QUIRK_NO_BUSY_IRQ |
ee53ab5d 145 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 146};
147
45211e21
PO		 148static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
149{
150 u8 scratch;
151 int ret;
152
153 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
154 if (ret)
155 return ret;
156
157 /*
158 * Turn PMOS on [bit 0], set over current detection to 2.4 V
159 * [bit 1:2] and enable over current debouncing [bit 6].
160 */
161 if (on)
162 scratch |= 0x47;
163 else
164 scratch &= ~0x47;
165
166 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
167 if (ret)
168 return ret;
169
170 return 0;
171}
172
173static int jmicron_probe(struct sdhci_pci_chip *chip)
174{
175 int ret;
176
93fc48c7
PO		 177 if (chip->pdev->revision == 0) {
178 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
179 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 180 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 181 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 182 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 183 }
184
4489428a
PO		 185 /*
186 * JMicron chips can have two interfaces to the same hardware
187 * in order to work around limitations in Microsoft's driver.
188 * We need to make sure we only bind to one of them.
189 *
190 * This code assumes two things:
191 *
192 * 1. The PCI code adds subfunctions in order.
193 *
194 * 2. The MMC interface has a lower subfunction number
195 * than the SD interface.
196 */
197 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) {
198 struct pci_dev *sd_dev;
199
200 sd_dev = NULL;
201 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
202 PCI_DEVICE_ID_JMICRON_JMB38X_MMC, sd_dev)) != NULL) {
203 if ((PCI_SLOT(chip->pdev->devfn) ==
204 PCI_SLOT(sd_dev->devfn)) &&
205 (chip->pdev->bus == sd_dev->bus))
206 break;
207 }
208
209 if (sd_dev) {
210 pci_dev_put(sd_dev);
211 dev_info(&chip->pdev->dev, "Refusing to bind to "
212 "secondary interface.\n");
213 return -ENODEV;
214 }
215 }
216
45211e21
PO		 217 /*
218 * JMicron chips need a bit of a nudge to enable the power
219 * output pins.
220 */
221 ret = jmicron_pmos(chip, 1);
222 if (ret) {
223 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
224 return ret;
225 }
226
227 return 0;
228}
229
4489428a
PO		 230static void jmicron_enable_mmc(struct sdhci_host *host, int on)
231{
232 u8 scratch;
233
234 scratch = readb(host->ioaddr + 0xC0);
235
236 if (on)
237 scratch |= 0x01;
238 else
239 scratch &= ~0x01;
240
241 writeb(scratch, host->ioaddr + 0xC0);
242}
243
244static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
245{
2134a922
PO		 246 if (slot->chip->pdev->revision == 0) {
247 u16 version;
248
249 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
250 version = (version & SDHCI_VENDOR_VER_MASK) >>
251 SDHCI_VENDOR_VER_SHIFT;
252
253 /*
254 * Older versions of the chip have lots of nasty glitches
255 * in the ADMA engine. It's best just to avoid it
256 * completely.
257 */
258 if (version < 0xAC)
259 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
260 }
261
4489428a
PO		 262 /*
263 * The secondary interface requires a bit set to get the
264 * interrupts.
265 */
266 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
267 jmicron_enable_mmc(slot->host, 1);
268
269 return 0;
270}
271
1e72859e 272static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 273{
1e72859e
PO		 274 if (dead)
275 return;
276
4489428a
PO		 277 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
278 jmicron_enable_mmc(slot->host, 0);
279}
280
281static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
282{
283 int i;
284
285 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
286 for (i = 0;i < chip->num_slots;i++)
287 jmicron_enable_mmc(chip->slots[i]->host, 0);
288 }
289
290 return 0;
291}
292
45211e21
PO		 293static int jmicron_resume(struct sdhci_pci_chip *chip)
294{
4489428a
PO		 295 int ret, i;
296
297 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
298 for (i = 0;i < chip->num_slots;i++)
299 jmicron_enable_mmc(chip->slots[i]->host, 1);
300 }
45211e21
PO		 301
302 ret = jmicron_pmos(chip, 1);
303 if (ret) {
304 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
305 return ret;
306 }
307
308 return 0;
309}
310
22606405 311static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 312 .probe = jmicron_probe,
313
4489428a
PO		 314 .probe_slot = jmicron_probe_slot,
315 .remove_slot = jmicron_remove_slot,
316
317 .suspend = jmicron_suspend,
45211e21 318 .resume = jmicron_resume,
22606405
PO		 319};
320
a7a6186c
NP		 321/* SysKonnect CardBus2SDIO extra registers */
322#define SYSKT_CTRL 0x200
323#define SYSKT_RDFIFO_STAT 0x204
324#define SYSKT_WRFIFO_STAT 0x208
325#define SYSKT_POWER_DATA 0x20c
326#define SYSKT_POWER_330 0xef
327#define SYSKT_POWER_300 0xf8
328#define SYSKT_POWER_184 0xcc
329#define SYSKT_POWER_CMD 0x20d
330#define SYSKT_POWER_START (1 << 7)
331#define SYSKT_POWER_STATUS 0x20e
332#define SYSKT_POWER_STATUS_OK (1 << 0)
333#define SYSKT_BOARD_REV 0x210
334#define SYSKT_CHIP_REV 0x211
335#define SYSKT_CONF_DATA 0x212
336#define SYSKT_CONF_DATA_1V8 (1 << 2)
337#define SYSKT_CONF_DATA_2V5 (1 << 1)
338#define SYSKT_CONF_DATA_3V3 (1 << 0)
339
340static int syskt_probe(struct sdhci_pci_chip *chip)
341{
342 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
343 chip->pdev->class &= ~0x0000FF;
344 chip->pdev->class |= PCI_SDHCI_IFDMA;
345 }
346 return 0;
347}
348
349static int syskt_probe_slot(struct sdhci_pci_slot *slot)
350{
351 int tm, ps;
352
353 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
354 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
355 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
356 "board rev %d.%d, chip rev %d.%d\n",
357 board_rev >> 4, board_rev & 0xf,
358 chip_rev >> 4, chip_rev & 0xf);
359 if (chip_rev >= 0x20)
360 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
361
362 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
363 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
364 udelay(50);
365 tm = 10; /* Wait max 1 ms */
366 do {
367 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
368 if (ps & SYSKT_POWER_STATUS_OK)
369 break;
370 udelay(100);
371 } while (--tm);
372 if (!tm) {
373 dev_err(&slot->chip->pdev->dev,
374 "power regulator never stabilized");
375 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
376 return -ENODEV;
377 }
378
379 return 0;
380}
381
382static const struct sdhci_pci_fixes sdhci_syskt = {
383 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
384 .probe = syskt_probe,
385 .probe_slot = syskt_probe_slot,
386};
387
557b0697
HW		 388static int via_probe(struct sdhci_pci_chip *chip)
389{
390 if (chip->pdev->revision == 0x10)
391 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
392
393 return 0;
394}
395
396static const struct sdhci_pci_fixes sdhci_via = {
397 .probe = via_probe,
398};
399
22606405 400static const struct pci_device_id pci_ids[] __devinitdata = {
b8c86fc5
PO		 401 {
402 .vendor = PCI_VENDOR_ID_RICOH,
403 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 404 .subvendor = PCI_ANY_ID,
b8c86fc5 405 .subdevice = PCI_ANY_ID,
22606405 406 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 407 },
408
ccc92c23
ML		 409 {
410 .vendor = PCI_VENDOR_ID_RICOH,
411 .device = 0x843,
412 .subvendor = PCI_ANY_ID,
413 .subdevice = PCI_ANY_ID,
414 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
415 },
416
b8c86fc5
PO		 417 {
418 .vendor = PCI_VENDOR_ID_ENE,
419 .device = PCI_DEVICE_ID_ENE_CB712_SD,
420 .subvendor = PCI_ANY_ID,
421 .subdevice = PCI_ANY_ID,
22606405 422 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 423 },
424
425 {
426 .vendor = PCI_VENDOR_ID_ENE,
427 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
428 .subvendor = PCI_ANY_ID,
429 .subdevice = PCI_ANY_ID,
22606405 430 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 431 },
432
433 {
434 .vendor = PCI_VENDOR_ID_ENE,
435 .device = PCI_DEVICE_ID_ENE_CB714_SD,
436 .subvendor = PCI_ANY_ID,
437 .subdevice = PCI_ANY_ID,
22606405 438 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 439 },
440
441 {
442 .vendor = PCI_VENDOR_ID_ENE,
443 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
444 .subvendor = PCI_ANY_ID,
445 .subdevice = PCI_ANY_ID,
22606405 446 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 447 },
448
449 {
450 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 451 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 452 .subvendor = PCI_ANY_ID,
453 .subdevice = PCI_ANY_ID,
22606405 454 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 455 },
456
457 {
458 .vendor = PCI_VENDOR_ID_JMICRON,
459 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
460 .subvendor = PCI_ANY_ID,
461 .subdevice = PCI_ANY_ID,
22606405 462 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 463 },
464
4489428a
PO		 465 {
466 .vendor = PCI_VENDOR_ID_JMICRON,
467 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
468 .subvendor = PCI_ANY_ID,
469 .subdevice = PCI_ANY_ID,
470 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
471 },
472
a7a6186c
NP		 473 {
474 .vendor = PCI_VENDOR_ID_SYSKONNECT,
475 .device = 0x8000,
476 .subvendor = PCI_ANY_ID,
477 .subdevice = PCI_ANY_ID,
478 .driver_data = (kernel_ulong_t)&sdhci_syskt,
479 },
480
557b0697
HW		 481 {
482 .vendor = PCI_VENDOR_ID_VIA,
483 .device = 0x95d0,
484 .subvendor = PCI_ANY_ID,
485 .subdevice = PCI_ANY_ID,
486 .driver_data = (kernel_ulong_t)&sdhci_via,
487 },
488
b8c86fc5
PO		 489 { /* Generic SD host controller */
490 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
491 },
492
493 { /* end: all zeroes */ },
494};
495
496MODULE_DEVICE_TABLE(pci, pci_ids);
497
b8c86fc5
PO		 498/*****************************************************************************\
499 * *
500 * SDHCI core callbacks *
501 * *
502\*****************************************************************************/
503
504static int sdhci_pci_enable_dma(struct sdhci_host *host)
505{
506 struct sdhci_pci_slot *slot;
507 struct pci_dev *pdev;
508 int ret;
509
510 slot = sdhci_priv(host);
511 pdev = slot->chip->pdev;
512
513 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
514 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 515 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 516 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
517 "doesn't fully claim to support it.\n");
518 }
519
284901a9 520 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 521 if (ret)
522 return ret;
523
524 pci_set_master(pdev);
525
526 return 0;
527}
528
529static struct sdhci_ops sdhci_pci_ops = {
530 .enable_dma = sdhci_pci_enable_dma,
531};
532
533/*****************************************************************************\
534 * *
535 * Suspend/resume *
536 * *
537\*****************************************************************************/
538
539#ifdef CONFIG_PM
540
541static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
542{
543 struct sdhci_pci_chip *chip;
544 struct sdhci_pci_slot *slot;
2f4cbb3d 545 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 546 int i, ret;
547
548 chip = pci_get_drvdata(pdev);
549 if (!chip)
550 return 0;
551
552 for (i = 0;i < chip->num_slots;i++) {
553 slot = chip->slots[i];
554 if (!slot)
555 continue;
556
557 ret = sdhci_suspend_host(slot->host, state);
558
559 if (ret) {
560 for (i--;i >= 0;i--)
561 sdhci_resume_host(chip->slots[i]->host);
562 return ret;
563 }
2f4cbb3d
NP		 564
565 pm_flags |= slot->host->mmc->pm_flags;
b8c86fc5
PO		 566 }
567
4489428a
PO		 568 if (chip->fixes && chip->fixes->suspend) {
569 ret = chip->fixes->suspend(chip, state);
570 if (ret) {
571 for (i = chip->num_slots - 1;i >= 0;i--)
572 sdhci_resume_host(chip->slots[i]->host);
573 return ret;
574 }
575 }
576
b8c86fc5 577 pci_save_state(pdev);
2f4cbb3d
NP		 578 if (pm_flags & MMC_PM_KEEP_POWER) {
579 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
580 pci_enable_wake(pdev, PCI_D3hot, 1);
581 pci_set_power_state(pdev, PCI_D3hot);
582 } else {
583 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
584 pci_disable_device(pdev);
585 pci_set_power_state(pdev, pci_choose_state(pdev, state));
586 }
b8c86fc5
PO		 587
588 return 0;
589}
590
591static int sdhci_pci_resume (struct pci_dev *pdev)
592{
593 struct sdhci_pci_chip *chip;
594 struct sdhci_pci_slot *slot;
595 int i, ret;
596
597 chip = pci_get_drvdata(pdev);
598 if (!chip)
599 return 0;
600
601 pci_set_power_state(pdev, PCI_D0);
602 pci_restore_state(pdev);
603 ret = pci_enable_device(pdev);
604 if (ret)
605 return ret;
606
45211e21
PO		 607 if (chip->fixes && chip->fixes->resume) {
608 ret = chip->fixes->resume(chip);
609 if (ret)
610 return ret;
611 }
612
b8c86fc5
PO		 613 for (i = 0;i < chip->num_slots;i++) {
614 slot = chip->slots[i];
615 if (!slot)
616 continue;
617
618 ret = sdhci_resume_host(slot->host);
619 if (ret)
620 return ret;
621 }
622
623 return 0;
624}
625
626#else /* CONFIG_PM */
627
628#define sdhci_pci_suspend NULL
629#define sdhci_pci_resume NULL
630
631#endif /* CONFIG_PM */
632
633/*****************************************************************************\
634 * *
635 * Device probing/removal *
636 * *
637\*****************************************************************************/
638
639static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
640 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
641{
642 struct sdhci_pci_slot *slot;
643 struct sdhci_host *host;
644
645 resource_size_t addr;
646
647 int ret;
648
649 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
650 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
651 return ERR_PTR(-ENODEV);
652 }
653
654 if (pci_resource_len(pdev, bar) != 0x100) {
655 dev_err(&pdev->dev, "Invalid iomem size. You may "
656 "experience problems.\n");
657 }
658
659 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
660 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
661 return ERR_PTR(-ENODEV);
662 }
663
664 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
665 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
666 return ERR_PTR(-ENODEV);
667 }
668
669 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
670 if (IS_ERR(host)) {
c60a32cd 671 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 672 return ERR_CAST(host);
b8c86fc5
PO		 673 }
674
675 slot = sdhci_priv(host);
676
677 slot->chip = chip;
678 slot->host = host;
679 slot->pci_bar = bar;
680
681 host->hw_name = "PCI";
682 host->ops = &sdhci_pci_ops;
683 host->quirks = chip->quirks;
684
685 host->irq = pdev->irq;
686
687 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
688 if (ret) {
689 dev_err(&pdev->dev, "cannot request region\n");
c60a32cd 690 goto free;
b8c86fc5
PO		 691 }
692
693 addr = pci_resource_start(pdev, bar);
092f82ed 694 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 695 if (!host->ioaddr) {
696 dev_err(&pdev->dev, "failed to remap registers\n");
697 goto release;
698 }
699
4489428a
PO		 700 if (chip->fixes && chip->fixes->probe_slot) {
701 ret = chip->fixes->probe_slot(slot);
702 if (ret)
703 goto unmap;
704 }
705
2f4cbb3d
NP		 706 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
707
b8c86fc5
PO		 708 ret = sdhci_add_host(host);
709 if (ret)
4489428a 710 goto remove;
b8c86fc5
PO		 711
712 return slot;
713
4489428a
PO		 714remove:
715 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 716 chip->fixes->remove_slot(slot, 0);
4489428a 717
b8c86fc5
PO		 718unmap:
719 iounmap(host->ioaddr);
720
721release:
722 pci_release_region(pdev, bar);
c60a32cd
DC		 723
724free:
b8c86fc5
PO		 725 sdhci_free_host(host);
726
727 return ERR_PTR(ret);
728}
729
730static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
731{
1e72859e
PO		 732 int dead;
733 u32 scratch;
734
735 dead = 0;
736 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
737 if (scratch == (u32)-1)
738 dead = 1;
739
740 sdhci_remove_host(slot->host, dead);
4489428a
PO		 741
742 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 743 slot->chip->fixes->remove_slot(slot, dead);
4489428a 744
b8c86fc5 745 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 746
b8c86fc5
PO		 747 sdhci_free_host(slot->host);
748}
749
750static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
751 const struct pci_device_id *ent)
752{
753 struct sdhci_pci_chip *chip;
754 struct sdhci_pci_slot *slot;
755
756 u8 slots, rev, first_bar;
757 int ret, i;
758
759 BUG_ON(pdev == NULL);
760 BUG_ON(ent == NULL);
761
762 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
763
764 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
765 (int)pdev->vendor, (int)pdev->device, (int)rev);
766
767 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
768 if (ret)
769 return ret;
770
771 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
772 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
773 if (slots == 0)
774 return -ENODEV;
775
776 BUG_ON(slots > MAX_SLOTS);
777
778 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
779 if (ret)
780 return ret;
781
782 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
783
784 if (first_bar > 5) {
785 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
786 return -ENODEV;
787 }
788
789 ret = pci_enable_device(pdev);
790 if (ret)
791 return ret;
792
793 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
794 if (!chip) {
795 ret = -ENOMEM;
796 goto err;
797 }
798
799 chip->pdev = pdev;
22606405
PO		 800 chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
801 if (chip->fixes)
802 chip->quirks = chip->fixes->quirks;
b8c86fc5
PO		 803 chip->num_slots = slots;
804
805 pci_set_drvdata(pdev, chip);
806
22606405
PO		 807 if (chip->fixes && chip->fixes->probe) {
808 ret = chip->fixes->probe(chip);
809 if (ret)
810 goto free;
811 }
812
b8c86fc5
PO		 813 for (i = 0;i < slots;i++) {
814 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
815 if (IS_ERR(slot)) {
816 for (i--;i >= 0;i--)
817 sdhci_pci_remove_slot(chip->slots[i]);
818 ret = PTR_ERR(slot);
819 goto free;
820 }
821
822 chip->slots[i] = slot;
823 }
824
825 return 0;
826
827free:
828 pci_set_drvdata(pdev, NULL);
829 kfree(chip);
830
831err:
832 pci_disable_device(pdev);
833 return ret;
834}
835
836static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
837{
838 int i;
839 struct sdhci_pci_chip *chip;
840
841 chip = pci_get_drvdata(pdev);
842
843 if (chip) {
844 for (i = 0;i < chip->num_slots; i++)
845 sdhci_pci_remove_slot(chip->slots[i]);
846
847 pci_set_drvdata(pdev, NULL);
848 kfree(chip);
849 }
850
851 pci_disable_device(pdev);
852}
853
854static struct pci_driver sdhci_driver = {
855 .name = "sdhci-pci",
856 .id_table = pci_ids,
857 .probe = sdhci_pci_probe,
858 .remove = __devexit_p(sdhci_pci_remove),
859 .suspend = sdhci_pci_suspend,
860 .resume = sdhci_pci_resume,
861};
862
863/*****************************************************************************\
864 * *
865 * Driver init/exit *
866 * *
867\*****************************************************************************/
868
869static int __init sdhci_drv_init(void)
870{
871 return pci_register_driver(&sdhci_driver);
872}
873
874static void __exit sdhci_drv_exit(void)
875{
876 pci_unregister_driver(&sdhci_driver);
877}
878
879module_init(sdhci_drv_init);
880module_exit(sdhci_drv_exit);
881
32710e8f 882MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 883MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
884MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)