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Merge branch 'rc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / mmci.c
CommitLineData
1da177e4 1/*
70f10482 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
1da177e4
LT		 3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
c8ebae37 5 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
613b152c 17#include <linux/kernel.h>
000bc9d5 18#include <linux/slab.h>
1da177e4
LT		 19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/highmem.h>
019a5f56 22#include <linux/log2.h>
70be208f 23#include <linux/mmc/pm.h>
1da177e4 24#include <linux/mmc/host.h>
34177802 25#include <linux/mmc/card.h>
a62c80e5 26#include <linux/amba/bus.h>
f8ce2547 27#include <linux/clk.h>
bd6dee6f 28#include <linux/scatterlist.h>
89001446 29#include <linux/gpio.h>
9a597016 30#include <linux/of_gpio.h>
34e84f39 31#include <linux/regulator/consumer.h>
c8ebae37
RK		 32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/amba/mmci.h>
1c3be369 35#include <linux/pm_runtime.h>
258aea76 36#include <linux/types.h>
a9a83785 37#include <linux/pinctrl/consumer.h>
1da177e4 38
7b09cdac 39#include <asm/div64.h>
1da177e4 40#include <asm/io.h>
c6b8fdad 41#include <asm/sizes.h>
1da177e4
LT		 42
43#include "mmci.h"
44
45#define DRIVER_NAME "mmci-pl18x"
46
1da177e4
LT		 47static unsigned int fmax = 515633;
48
4956e109
RV		 49/**
50 * struct variant_data - MMCI variant-specific quirks
51 * @clkreg: default value for MCICLOCK register
4380c14f 52 * @clkreg_enable: enable value for MMCICLOCK register
08458ef6 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register
8301bb68
RV		 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
55 * is asserted (likewise for RX)
56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
57 * is asserted (likewise for RX)
34177802 58 * @sdio: variant supports SDIO
b70a67f9 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm
1784b157 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
7d72a1d4 61 * @pwrreg_powerup: power up value for MMCIPOWER register
4d1a3a0d 62 * @signal_direction: input/out direction of bus signals can be indicated
f4670dae 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
4956e109
RV		 64 */
65struct variant_data {
66 unsigned int clkreg;
4380c14f 67 unsigned int clkreg_enable;
08458ef6 68 unsigned int datalength_bits;
8301bb68
RV		 69 unsigned int fifosize;
70 unsigned int fifohalfsize;
34177802 71 bool sdio;
b70a67f9 72 bool st_clkdiv;
1784b157 73 bool blksz_datactrl16;
7d72a1d4 74 u32 pwrreg_powerup;
4d1a3a0d 75 bool signal_direction;
f4670dae 76 bool pwrreg_clkgate;
4956e109
RV		 77};
78
79static struct variant_data variant_arm = {
8301bb68
RV		 80 .fifosize = 16 * 4,
81 .fifohalfsize = 8 * 4,
08458ef6 82 .datalength_bits = 16,
7d72a1d4 83 .pwrreg_powerup = MCI_PWR_UP,
4956e109
RV		 84};
85
768fbc18
PM		 86static struct variant_data variant_arm_extended_fifo = {
87 .fifosize = 128 * 4,
88 .fifohalfsize = 64 * 4,
89 .datalength_bits = 16,
7d72a1d4 90 .pwrreg_powerup = MCI_PWR_UP,
768fbc18
PM		 91};
92
3a37298a
PM		 93static struct variant_data variant_arm_extended_fifo_hwfc = {
94 .fifosize = 128 * 4,
95 .fifohalfsize = 64 * 4,
96 .clkreg_enable = MCI_ARM_HWFCEN,
97 .datalength_bits = 16,
98 .pwrreg_powerup = MCI_PWR_UP,
99};
100
4956e109 101static struct variant_data variant_u300 = {
8301bb68
RV		 102 .fifosize = 16 * 4,
103 .fifohalfsize = 8 * 4,
49ac215e 104 .clkreg_enable = MCI_ST_U300_HWFCEN,
08458ef6 105 .datalength_bits = 16,
34177802 106 .sdio = true,
7d72a1d4 107 .pwrreg_powerup = MCI_PWR_ON,
4d1a3a0d 108 .signal_direction = true,
f4670dae 109 .pwrreg_clkgate = true,
4956e109
RV		 110};
111
34fd4213
LW		 112static struct variant_data variant_nomadik = {
113 .fifosize = 16 * 4,
114 .fifohalfsize = 8 * 4,
115 .clkreg = MCI_CLK_ENABLE,
116 .datalength_bits = 24,
117 .sdio = true,
118 .st_clkdiv = true,
119 .pwrreg_powerup = MCI_PWR_ON,
120 .signal_direction = true,
f4670dae 121 .pwrreg_clkgate = true,
34fd4213
LW		 122};
123
4956e109 124static struct variant_data variant_ux500 = {
8301bb68
RV		 125 .fifosize = 30 * 4,
126 .fifohalfsize = 8 * 4,
4956e109 127 .clkreg = MCI_CLK_ENABLE,
49ac215e 128 .clkreg_enable = MCI_ST_UX500_HWFCEN,
08458ef6 129 .datalength_bits = 24,
34177802 130 .sdio = true,
b70a67f9 131 .st_clkdiv = true,
7d72a1d4 132 .pwrreg_powerup = MCI_PWR_ON,
4d1a3a0d 133 .signal_direction = true,
f4670dae 134 .pwrreg_clkgate = true,
4956e109 135};
b70a67f9 136
1784b157
PL		 137static struct variant_data variant_ux500v2 = {
138 .fifosize = 30 * 4,
139 .fifohalfsize = 8 * 4,
140 .clkreg = MCI_CLK_ENABLE,
141 .clkreg_enable = MCI_ST_UX500_HWFCEN,
142 .datalength_bits = 24,
143 .sdio = true,
144 .st_clkdiv = true,
145 .blksz_datactrl16 = true,
7d72a1d4 146 .pwrreg_powerup = MCI_PWR_ON,
4d1a3a0d 147 .signal_direction = true,
f4670dae 148 .pwrreg_clkgate = true,
1784b157
PL		 149};
150
653a761e
UH		 151/*
152 * Validate mmc prerequisites
153 */
154static int mmci_validate_data(struct mmci_host *host,
155 struct mmc_data *data)
156{
157 if (!data)
158 return 0;
159
160 if (!is_power_of_2(data->blksz)) {
161 dev_err(mmc_dev(host->mmc),
162 "unsupported block size (%d bytes)\n", data->blksz);
163 return -EINVAL;
164 }
165
166 return 0;
167}
168
7437cfa5
UH		 169/*
170 * This must be called with host->lock held
171 */
172static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
173{
174 if (host->clk_reg != clk) {
175 host->clk_reg = clk;
176 writel(clk, host->base + MMCICLOCK);
177 }
178}
179
180/*
181 * This must be called with host->lock held
182 */
183static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
184{
185 if (host->pwr_reg != pwr) {
186 host->pwr_reg = pwr;
187 writel(pwr, host->base + MMCIPOWER);
188 }
189}
190
a6a6464a
LW		 191/*
192 * This must be called with host->lock held
193 */
194static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
195{
4956e109
RV		 196 struct variant_data *variant = host->variant;
197 u32 clk = variant->clkreg;
a6a6464a
LW		 198
199 if (desired) {
200 if (desired >= host->mclk) {
991a86e1 201 clk = MCI_CLK_BYPASS;
399bc486
LW		 202 if (variant->st_clkdiv)
203 clk |= MCI_ST_UX500_NEG_EDGE;
a6a6464a 204 host->cclk = host->mclk;
b70a67f9
LW		 205 } else if (variant->st_clkdiv) {
206 /*
207 * DB8500 TRM says f = mclk / (clkdiv + 2)
208 * => clkdiv = (mclk / f) - 2
209 * Round the divider up so we don't exceed the max
210 * frequency
211 */
212 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
213 if (clk >= 256)
214 clk = 255;
215 host->cclk = host->mclk / (clk + 2);
a6a6464a 216 } else {
b70a67f9
LW		 217 /*
218 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
219 * => clkdiv = mclk / (2 * f) - 1
220 */
a6a6464a
LW		 221 clk = host->mclk / (2 * desired) - 1;
222 if (clk >= 256)
223 clk = 255;
224 host->cclk = host->mclk / (2 * (clk + 1));
225 }
4380c14f
RV		 226
227 clk |= variant->clkreg_enable;
a6a6464a
LW		 228 clk |= MCI_CLK_ENABLE;
229 /* This hasn't proven to be worthwhile */
230 /* clk |= MCI_CLK_PWRSAVE; */
231 }
232
9e6c82cd 233 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
771dc157
LW		 234 clk |= MCI_4BIT_BUS;
235 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
236 clk |= MCI_ST_8BIT_BUS;
9e6c82cd 237
6dbb6ee0
UH		 238 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
239 clk |= MCI_ST_UX500_NEG_EDGE;
240
7437cfa5 241 mmci_write_clkreg(host, clk);
a6a6464a
LW		 242}
243
1da177e4
LT		 244static void
245mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
246{
247 writel(0, host->base + MMCICOMMAND);
248
e47c222b
RK		 249 BUG_ON(host->data);
250
1da177e4
LT		 251 host->mrq = NULL;
252 host->cmd = NULL;
253
1da177e4 254 mmc_request_done(host->mmc, mrq);
2cd976c4
UH		 255
256 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
257 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
1da177e4
LT		 258}
259
2686b4b4
LW		 260static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
261{
262 void __iomem *base = host->base;
263
264 if (host->singleirq) {
265 unsigned int mask0 = readl(base + MMCIMASK0);
266
267 mask0 &= ~MCI_IRQ1MASK;
268 mask0 |= mask;
269
270 writel(mask0, base + MMCIMASK0);
271 }
272
273 writel(mask, base + MMCIMASK1);
274}
275
1da177e4
LT		 276static void mmci_stop_data(struct mmci_host *host)
277{
278 writel(0, host->base + MMCIDATACTRL);
2686b4b4 279 mmci_set_mask1(host, 0);
1da177e4
LT		 280 host->data = NULL;
281}
282
4ce1d6cb
RV		 283static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
284{
285 unsigned int flags = SG_MITER_ATOMIC;
286
287 if (data->flags & MMC_DATA_READ)
288 flags |= SG_MITER_TO_SG;
289 else
290 flags |= SG_MITER_FROM_SG;
291
292 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
293}
294
c8ebae37
RK		 295/*
296 * All the DMA operation mode stuff goes inside this ifdef.
297 * This assumes that you have a generic DMA device interface,
298 * no custom DMA interfaces are supported.
299 */
300#ifdef CONFIG_DMA_ENGINE
c3be1efd 301static void mmci_dma_setup(struct mmci_host *host)
c8ebae37
RK		 302{
303 struct mmci_platform_data *plat = host->plat;
304 const char *rxname, *txname;
305 dma_cap_mask_t mask;
306
307 if (!plat || !plat->dma_filter) {
308 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
309 return;
310 }
311
58c7ccbf
PF		 312 /* initialize pre request cookie */
313 host->next_data.cookie = 1;
314
c8ebae37
RK		 315 /* Try to acquire a generic DMA engine slave channel */
316 dma_cap_zero(mask);
317 dma_cap_set(DMA_SLAVE, mask);
318
319 /*
320 * If only an RX channel is specified, the driver will
321 * attempt to use it bidirectionally, however if it is
322 * is specified but cannot be located, DMA will be disabled.
323 */
324 if (plat->dma_rx_param) {
325 host->dma_rx_channel = dma_request_channel(mask,
326 plat->dma_filter,
327 plat->dma_rx_param);
328 /* E.g if no DMA hardware is present */
329 if (!host->dma_rx_channel)
330 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
331 }
332
333 if (plat->dma_tx_param) {
334 host->dma_tx_channel = dma_request_channel(mask,
335 plat->dma_filter,
336 plat->dma_tx_param);
337 if (!host->dma_tx_channel)
338 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
339 } else {
340 host->dma_tx_channel = host->dma_rx_channel;
341 }
342
343 if (host->dma_rx_channel)
344 rxname = dma_chan_name(host->dma_rx_channel);
345 else
346 rxname = "none";
347
348 if (host->dma_tx_channel)
349 txname = dma_chan_name(host->dma_tx_channel);
350 else
351 txname = "none";
352
353 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
354 rxname, txname);
355
356 /*
357 * Limit the maximum segment size in any SG entry according to
358 * the parameters of the DMA engine device.
359 */
360 if (host->dma_tx_channel) {
361 struct device *dev = host->dma_tx_channel->device->dev;
362 unsigned int max_seg_size = dma_get_max_seg_size(dev);
363
364 if (max_seg_size < host->mmc->max_seg_size)
365 host->mmc->max_seg_size = max_seg_size;
366 }
367 if (host->dma_rx_channel) {
368 struct device *dev = host->dma_rx_channel->device->dev;
369 unsigned int max_seg_size = dma_get_max_seg_size(dev);
370
371 if (max_seg_size < host->mmc->max_seg_size)
372 host->mmc->max_seg_size = max_seg_size;
373 }
374}
375
376/*
6e0ee714 377 * This is used in or so inline it
c8ebae37
RK		 378 * so it can be discarded.
379 */
380static inline void mmci_dma_release(struct mmci_host *host)
381{
382 struct mmci_platform_data *plat = host->plat;
383
384 if (host->dma_rx_channel)
385 dma_release_channel(host->dma_rx_channel);
386 if (host->dma_tx_channel && plat->dma_tx_param)
387 dma_release_channel(host->dma_tx_channel);
388 host->dma_rx_channel = host->dma_tx_channel = NULL;
389}
390
653a761e
UH		 391static void mmci_dma_data_error(struct mmci_host *host)
392{
393 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
394 dmaengine_terminate_all(host->dma_current);
395 host->dma_current = NULL;
396 host->dma_desc_current = NULL;
397 host->data->host_cookie = 0;
398}
399
c8ebae37
RK		 400static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
401{
653a761e 402 struct dma_chan *chan;
c8ebae37 403 enum dma_data_direction dir;
653a761e
UH		 404
405 if (data->flags & MMC_DATA_READ) {
406 dir = DMA_FROM_DEVICE;
407 chan = host->dma_rx_channel;
408 } else {
409 dir = DMA_TO_DEVICE;
410 chan = host->dma_tx_channel;
411 }
412
413 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
414}
415
416static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
417{
c8ebae37
RK		 418 u32 status;
419 int i;
420
421 /* Wait up to 1ms for the DMA to complete */
422 for (i = 0; ; i++) {
423 status = readl(host->base + MMCISTATUS);
424 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
425 break;
426 udelay(10);
427 }
428
429 /*
430 * Check to see whether we still have some data left in the FIFO -
431 * this catches DMA controllers which are unable to monitor the
432 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
433 * contiguous buffers. On TX, we'll get a FIFO underrun error.
434 */
435 if (status & MCI_RXDATAAVLBLMASK) {
653a761e 436 mmci_dma_data_error(host);
c8ebae37
RK		 437 if (!data->error)
438 data->error = -EIO;
439 }
440
58c7ccbf 441 if (!data->host_cookie)
653a761e 442 mmci_dma_unmap(host, data);
c8ebae37
RK		 443
444 /*
445 * Use of DMA with scatter-gather is impossible.
446 * Give up with DMA and switch back to PIO mode.
447 */
448 if (status & MCI_RXDATAAVLBLMASK) {
449 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
450 mmci_dma_release(host);
451 }
c8ebae37 452
653a761e
UH		 453 host->dma_current = NULL;
454 host->dma_desc_current = NULL;
c8ebae37
RK		 455}
456
653a761e
UH		 457/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
458static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
459 struct dma_chan **dma_chan,
460 struct dma_async_tx_descriptor **dma_desc)
c8ebae37
RK		 461{
462 struct variant_data *variant = host->variant;
463 struct dma_slave_config conf = {
464 .src_addr = host->phybase + MMCIFIFO,
465 .dst_addr = host->phybase + MMCIFIFO,
466 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
467 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
468 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
469 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
258aea76 470 .device_fc = false,
c8ebae37 471 };
c8ebae37
RK		 472 struct dma_chan *chan;
473 struct dma_device *device;
474 struct dma_async_tx_descriptor *desc;
05f5799c 475 enum dma_data_direction buffer_dirn;
c8ebae37
RK		 476 int nr_sg;
477
c8ebae37 478 if (data->flags & MMC_DATA_READ) {
05f5799c
VK		 479 conf.direction = DMA_DEV_TO_MEM;
480 buffer_dirn = DMA_FROM_DEVICE;
c8ebae37
RK		 481 chan = host->dma_rx_channel;
482 } else {
05f5799c
VK		 483 conf.direction = DMA_MEM_TO_DEV;
484 buffer_dirn = DMA_TO_DEVICE;
c8ebae37
RK		 485 chan = host->dma_tx_channel;
486 }
487
488 /* If there's no DMA channel, fall back to PIO */
489 if (!chan)
490 return -EINVAL;
491
492 /* If less than or equal to the fifo size, don't bother with DMA */
58c7ccbf 493 if (data->blksz * data->blocks <= variant->fifosize)
c8ebae37
RK		 494 return -EINVAL;
495
496 device = chan->device;
05f5799c 497 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
c8ebae37
RK		 498 if (nr_sg == 0)
499 return -EINVAL;
500
501 dmaengine_slave_config(chan, &conf);
16052827 502 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
c8ebae37
RK		 503 conf.direction, DMA_CTRL_ACK);
504 if (!desc)
505 goto unmap_exit;
506
653a761e
UH		 507 *dma_chan = chan;
508 *dma_desc = desc;
58c7ccbf
PF		 509
510 return 0;
c8ebae37 511
58c7ccbf 512 unmap_exit:
05f5799c 513 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
58c7ccbf
PF		 514 return -ENOMEM;
515}
516
653a761e
UH		 517static inline int mmci_dma_prep_data(struct mmci_host *host,
518 struct mmc_data *data)
519{
520 /* Check if next job is already prepared. */
521 if (host->dma_current && host->dma_desc_current)
522 return 0;
523
524 /* No job were prepared thus do it now. */
525 return __mmci_dma_prep_data(host, data, &host->dma_current,
526 &host->dma_desc_current);
527}
528
529static inline int mmci_dma_prep_next(struct mmci_host *host,
530 struct mmc_data *data)
531{
532 struct mmci_host_next *nd = &host->next_data;
533 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
534}
535
58c7ccbf
PF		 536static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
537{
538 int ret;
539 struct mmc_data *data = host->data;
540
653a761e 541 ret = mmci_dma_prep_data(host, host->data);
58c7ccbf
PF		 542 if (ret)
543 return ret;
544
545 /* Okay, go for it. */
c8ebae37
RK		 546 dev_vdbg(mmc_dev(host->mmc),
547 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
548 data->sg_len, data->blksz, data->blocks, data->flags);
58c7ccbf
PF		 549 dmaengine_submit(host->dma_desc_current);
550 dma_async_issue_pending(host->dma_current);
c8ebae37
RK		 551
552 datactrl |= MCI_DPSM_DMAENABLE;
553
554 /* Trigger the DMA transfer */
555 writel(datactrl, host->base + MMCIDATACTRL);
556
557 /*
558 * Let the MMCI say when the data is ended and it's time
559 * to fire next DMA request. When that happens, MMCI will
560 * call mmci_data_end()
561 */
562 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
563 host->base + MMCIMASK0);
564 return 0;
58c7ccbf 565}
c8ebae37 566
58c7ccbf
PF		 567static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
568{
569 struct mmci_host_next *next = &host->next_data;
570
653a761e
UH		 571 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
572 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
58c7ccbf
PF		 573
574 host->dma_desc_current = next->dma_desc;
575 host->dma_current = next->dma_chan;
58c7ccbf
PF		 576 next->dma_desc = NULL;
577 next->dma_chan = NULL;
c8ebae37 578}
58c7ccbf
PF		 579
580static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
581 bool is_first_req)
582{
583 struct mmci_host *host = mmc_priv(mmc);
584 struct mmc_data *data = mrq->data;
585 struct mmci_host_next *nd = &host->next_data;
586
587 if (!data)
588 return;
589
653a761e
UH		 590 BUG_ON(data->host_cookie);
591
592 if (mmci_validate_data(host, data))
58c7ccbf 593 return;
58c7ccbf 594
653a761e
UH		 595 if (!mmci_dma_prep_next(host, data))
596 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
58c7ccbf
PF		 597}
598
599static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
600 int err)
601{
602 struct mmci_host *host = mmc_priv(mmc);
603 struct mmc_data *data = mrq->data;
58c7ccbf 604
653a761e 605 if (!data || !data->host_cookie)
58c7ccbf
PF		 606 return;
607
653a761e 608 mmci_dma_unmap(host, data);
58c7ccbf 609
653a761e
UH		 610 if (err) {
611 struct mmci_host_next *next = &host->next_data;
612 struct dma_chan *chan;
613 if (data->flags & MMC_DATA_READ)
614 chan = host->dma_rx_channel;
615 else
616 chan = host->dma_tx_channel;
617 dmaengine_terminate_all(chan);
58c7ccbf 618
653a761e
UH		 619 next->dma_desc = NULL;
620 next->dma_chan = NULL;
58c7ccbf
PF		 621 }
622}
623
c8ebae37
RK		 624#else
625/* Blank functions if the DMA engine is not available */
58c7ccbf
PF		 626static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
627{
628}
c8ebae37
RK		 629static inline void mmci_dma_setup(struct mmci_host *host)
630{
631}
632
633static inline void mmci_dma_release(struct mmci_host *host)
634{
635}
636
637static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
638{
639}
640
653a761e
UH		 641static inline void mmci_dma_finalize(struct mmci_host *host,
642 struct mmc_data *data)
643{
644}
645
c8ebae37
RK		 646static inline void mmci_dma_data_error(struct mmci_host *host)
647{
648}
649
650static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
651{
652 return -ENOSYS;
653}
58c7ccbf
PF		 654
655#define mmci_pre_request NULL
656#define mmci_post_request NULL
657
c8ebae37
RK		 658#endif
659
1da177e4
LT		 660static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
661{
8301bb68 662 struct variant_data *variant = host->variant;
1da177e4 663 unsigned int datactrl, timeout, irqmask;
7b09cdac 664 unsigned long long clks;
1da177e4 665 void __iomem *base;
3bc87f24 666 int blksz_bits;
1da177e4 667
64de0289
LW		 668 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
669 data->blksz, data->blocks, data->flags);
1da177e4
LT		 670
671 host->data = data;
528320db 672 host->size = data->blksz * data->blocks;
51d4375d 673 data->bytes_xfered = 0;
1da177e4 674
7b09cdac
RK		 675 clks = (unsigned long long)data->timeout_ns * host->cclk;
676 do_div(clks, 1000000000UL);
677
678 timeout = data->timeout_clks + (unsigned int)clks;
1da177e4
LT		 679
680 base = host->base;
681 writel(timeout, base + MMCIDATATIMER);
682 writel(host->size, base + MMCIDATALENGTH);
683
3bc87f24
RK		 684 blksz_bits = ffs(data->blksz) - 1;
685 BUG_ON(1 << blksz_bits != data->blksz);
686
1784b157
PL		 687 if (variant->blksz_datactrl16)
688 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
689 else
690 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
c8ebae37
RK		 691
692 if (data->flags & MMC_DATA_READ)
1da177e4 693 datactrl |= MCI_DPSM_DIRECTION;
c8ebae37 694
7258db7e
UH		 695 /* The ST Micro variants has a special bit to enable SDIO */
696 if (variant->sdio && host->mmc->card)
06c1a121
UH		 697 if (mmc_card_sdio(host->mmc->card)) {
698 /*
699 * The ST Micro variants has a special bit
700 * to enable SDIO.
701 */
702 u32 clk;
703
7258db7e
UH		 704 datactrl |= MCI_ST_DPSM_SDIOEN;
705
06c1a121 706 /*
70ac0935
UH		 707 * The ST Micro variant for SDIO small write transfers
708 * needs to have clock H/W flow control disabled,
709 * otherwise the transfer will not start. The threshold
710 * depends on the rate of MCLK.
06c1a121 711 */
70ac0935
UH		 712 if (data->flags & MMC_DATA_WRITE &&
713 (host->size < 8 ||
714 (host->size <= 8 && host->mclk > 50000000)))
06c1a121
UH		 715 clk = host->clk_reg & ~variant->clkreg_enable;
716 else
717 clk = host->clk_reg | variant->clkreg_enable;
718
719 mmci_write_clkreg(host, clk);
720 }
721
6dbb6ee0
UH		 722 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
723 datactrl |= MCI_ST_DPSM_DDRMODE;
724
c8ebae37
RK		 725 /*
726 * Attempt to use DMA operation mode, if this
727 * should fail, fall back to PIO mode
728 */
729 if (!mmci_dma_start_data(host, datactrl))
730 return;
731
732 /* IRQ mode, map the SG list for CPU reading/writing */
733 mmci_init_sg(host, data);
734
735 if (data->flags & MMC_DATA_READ) {
1da177e4 736 irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142
RK		 737
738 /*
c4d877c1
RK		 739 * If we have less than the fifo 'half-full' threshold to
740 * transfer, trigger a PIO interrupt as soon as any data
741 * is available.
0425a142 742 */
c4d877c1 743 if (host->size < variant->fifohalfsize)
0425a142 744 irqmask |= MCI_RXDATAAVLBLMASK;
1da177e4
LT		 745 } else {
746 /*
747 * We don't actually need to include "FIFO empty" here
748 * since its implicit in "FIFO half empty".
749 */
750 irqmask = MCI_TXFIFOHALFEMPTYMASK;
751 }
752
753 writel(datactrl, base + MMCIDATACTRL);
754 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
2686b4b4 755 mmci_set_mask1(host, irqmask);
1da177e4
LT		 756}
757
758static void
759mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
760{
761 void __iomem *base = host->base;
762
64de0289 763 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1da177e4
LT		 764 cmd->opcode, cmd->arg, cmd->flags);
765
766 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
767 writel(0, base + MMCICOMMAND);
768 udelay(1);
769 }
770
771 c |= cmd->opcode | MCI_CPSM_ENABLE;
e9225176
RK		 772 if (cmd->flags & MMC_RSP_PRESENT) {
773 if (cmd->flags & MMC_RSP_136)
774 c |= MCI_CPSM_LONGRSP;
1da177e4 775 c |= MCI_CPSM_RESPONSE;
1da177e4
LT		 776 }
777 if (/*interrupt*/0)
778 c |= MCI_CPSM_INTERRUPT;
779
780 host->cmd = cmd;
781
782 writel(cmd->arg, base + MMCIARGUMENT);
783 writel(c, base + MMCICOMMAND);
784}
785
786static void
787mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
788 unsigned int status)
789{
f20f8f21 790 /* First check for errors */
b63038d6
UH		 791 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
792 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
8cb28155 793 u32 remain, success;
f20f8f21 794
c8ebae37 795 /* Terminate the DMA transfer */
653a761e 796 if (dma_inprogress(host)) {
c8ebae37 797 mmci_dma_data_error(host);
653a761e
UH		 798 mmci_dma_unmap(host, data);
799 }
e9c091b4
RK		 800
801 /*
c8afc9d5
RK		 802 * Calculate how far we are into the transfer. Note that
803 * the data counter gives the number of bytes transferred
804 * on the MMC bus, not on the host side. On reads, this
805 * can be as much as a FIFO-worth of data ahead. This
806 * matters for FIFO overruns only.
e9c091b4 807 */
f5a106d9 808 remain = readl(host->base + MMCIDATACNT);
8cb28155
LW		 809 success = data->blksz * data->blocks - remain;
810
c8afc9d5
RK		 811 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
812 status, success);
8cb28155
LW		 813 if (status & MCI_DATACRCFAIL) {
814 /* Last block was not successful */
c8afc9d5 815 success -= 1;
17b0429d 816 data->error = -EILSEQ;
8cb28155 817 } else if (status & MCI_DATATIMEOUT) {
17b0429d 818 data->error = -ETIMEDOUT;
757df746
LW		 819 } else if (status & MCI_STARTBITERR) {
820 data->error = -ECOMM;
c8afc9d5
RK		 821 } else if (status & MCI_TXUNDERRUN) {
822 data->error = -EIO;
823 } else if (status & MCI_RXOVERRUN) {
824 if (success > host->variant->fifosize)
825 success -= host->variant->fifosize;
826 else
827 success = 0;
17b0429d 828 data->error = -EIO;
4ce1d6cb 829 }
51d4375d 830 data->bytes_xfered = round_down(success, data->blksz);
1da177e4 831 }
f20f8f21 832
8cb28155
LW		 833 if (status & MCI_DATABLOCKEND)
834 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
f20f8f21 835
ccff9b51 836 if (status & MCI_DATAEND || data->error) {
c8ebae37 837 if (dma_inprogress(host))
653a761e 838 mmci_dma_finalize(host, data);
1da177e4
LT		 839 mmci_stop_data(host);
840
8cb28155
LW		 841 if (!data->error)
842 /* The error clause is handled above, success! */
51d4375d 843 data->bytes_xfered = data->blksz * data->blocks;
f20f8f21 844
1da177e4
LT		 845 if (!data->stop) {
846 mmci_request_end(host, data->mrq);
847 } else {
848 mmci_start_command(host, data->stop, 0);
849 }
850 }
851}
852
853static void
854mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
855 unsigned int status)
856{
857 void __iomem *base = host->base;
858
859 host->cmd = NULL;
860
1da177e4 861 if (status & MCI_CMDTIMEOUT) {
17b0429d 862 cmd->error = -ETIMEDOUT;
1da177e4 863 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
17b0429d 864 cmd->error = -EILSEQ;
9047b435
RKAL		 865 } else {
866 cmd->resp[0] = readl(base + MMCIRESPONSE0);
867 cmd->resp[1] = readl(base + MMCIRESPONSE1);
868 cmd->resp[2] = readl(base + MMCIRESPONSE2);
869 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1da177e4
LT		 870 }
871
17b0429d 872 if (!cmd->data || cmd->error) {
3b6e3c73
UH		 873 if (host->data) {
874 /* Terminate the DMA transfer */
653a761e 875 if (dma_inprogress(host)) {
3b6e3c73 876 mmci_dma_data_error(host);
653a761e
UH		 877 mmci_dma_unmap(host, host->data);
878 }
e47c222b 879 mmci_stop_data(host);
3b6e3c73 880 }
1da177e4
LT		 881 mmci_request_end(host, cmd->mrq);
882 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
883 mmci_start_data(host, cmd->data);
884 }
885}
886
887static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
888{
889 void __iomem *base = host->base;
890 char *ptr = buffer;
891 u32 status;
26eed9a5 892 int host_remain = host->size;
1da177e4
LT		 893
894 do {
26eed9a5 895 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
1da177e4
LT		 896
897 if (count > remain)
898 count = remain;
899
900 if (count <= 0)
901 break;
902
393e5e24
UH		 903 /*
904 * SDIO especially may want to send something that is
905 * not divisible by 4 (as opposed to card sectors
906 * etc). Therefore make sure to always read the last bytes
907 * while only doing full 32-bit reads towards the FIFO.
908 */
909 if (unlikely(count & 0x3)) {
910 if (count < 4) {
911 unsigned char buf[4];
4b85da08 912 ioread32_rep(base + MMCIFIFO, buf, 1);
393e5e24
UH		 913 memcpy(ptr, buf, count);
914 } else {
4b85da08 915 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24
UH		 916 count &= ~0x3;
917 }
918 } else {
4b85da08 919 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24 920 }
1da177e4
LT		 921
922 ptr += count;
923 remain -= count;
26eed9a5 924 host_remain -= count;
1da177e4
LT		 925
926 if (remain == 0)
927 break;
928
929 status = readl(base + MMCISTATUS);
930 } while (status & MCI_RXDATAAVLBL);
931
932 return ptr - buffer;
933}
934
935static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
936{
8301bb68 937 struct variant_data *variant = host->variant;
1da177e4
LT		 938 void __iomem *base = host->base;
939 char *ptr = buffer;
940
941 do {
942 unsigned int count, maxcnt;
943
8301bb68
RV		 944 maxcnt = status & MCI_TXFIFOEMPTY ?
945 variant->fifosize : variant->fifohalfsize;
1da177e4
LT		 946 count = min(remain, maxcnt);
947
34177802
LW		 948 /*
949 * SDIO especially may want to send something that is
950 * not divisible by 4 (as opposed to card sectors
951 * etc), and the FIFO only accept full 32-bit writes.
952 * So compensate by adding +3 on the count, a single
953 * byte become a 32bit write, 7 bytes will be two
954 * 32bit writes etc.
955 */
4b85da08 956 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1da177e4
LT		 957
958 ptr += count;
959 remain -= count;
960
961 if (remain == 0)
962 break;
963
964 status = readl(base + MMCISTATUS);
965 } while (status & MCI_TXFIFOHALFEMPTY);
966
967 return ptr - buffer;
968}
969
970/*
971 * PIO data transfer IRQ handler.
972 */
7d12e780 973static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1da177e4
LT		 974{
975 struct mmci_host *host = dev_id;
4ce1d6cb 976 struct sg_mapping_iter *sg_miter = &host->sg_miter;
8301bb68 977 struct variant_data *variant = host->variant;
1da177e4 978 void __iomem *base = host->base;
4ce1d6cb 979 unsigned long flags;
1da177e4
LT		 980 u32 status;
981
982 status = readl(base + MMCISTATUS);
983
64de0289 984 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1da177e4 985
4ce1d6cb
RV		 986 local_irq_save(flags);
987
1da177e4 988 do {
1da177e4
LT		 989 unsigned int remain, len;
990 char *buffer;
991
992 /*
993 * For write, we only need to test the half-empty flag
994 * here - if the FIFO is completely empty, then by
995 * definition it is more than half empty.
996 *
997 * For read, check for data available.
998 */
999 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1000 break;
1001
4ce1d6cb
RV		 1002 if (!sg_miter_next(sg_miter))
1003 break;
1004
1005 buffer = sg_miter->addr;
1006 remain = sg_miter->length;
1da177e4
LT		 1007
1008 len = 0;
1009 if (status & MCI_RXACTIVE)
1010 len = mmci_pio_read(host, buffer, remain);
1011 if (status & MCI_TXACTIVE)
1012 len = mmci_pio_write(host, buffer, remain, status);
1013
4ce1d6cb 1014 sg_miter->consumed = len;
1da177e4 1015
1da177e4
LT		 1016 host->size -= len;
1017 remain -= len;
1018
1019 if (remain)
1020 break;
1021
1da177e4
LT		 1022 status = readl(base + MMCISTATUS);
1023 } while (1);
1024
4ce1d6cb
RV		 1025 sg_miter_stop(sg_miter);
1026
1027 local_irq_restore(flags);
1028
1da177e4 1029 /*
c4d877c1
RK		 1030 * If we have less than the fifo 'half-full' threshold to transfer,
1031 * trigger a PIO interrupt as soon as any data is available.
1da177e4 1032 */
c4d877c1 1033 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
2686b4b4 1034 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1da177e4
LT		 1035
1036 /*
1037 * If we run out of data, disable the data IRQs; this
1038 * prevents a race where the FIFO becomes empty before
1039 * the chip itself has disabled the data path, and
1040 * stops us racing with our data end IRQ.
1041 */
1042 if (host->size == 0) {
2686b4b4 1043 mmci_set_mask1(host, 0);
1da177e4
LT		 1044 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1045 }
1046
1047 return IRQ_HANDLED;
1048}
1049
1050/*
1051 * Handle completion of command and data transfers.
1052 */
7d12e780 1053static irqreturn_t mmci_irq(int irq, void *dev_id)
1da177e4
LT		 1054{
1055 struct mmci_host *host = dev_id;
1056 u32 status;
1057 int ret = 0;
1058
1059 spin_lock(&host->lock);
1060
1061 do {
1062 struct mmc_command *cmd;
1063 struct mmc_data *data;
1064
1065 status = readl(host->base + MMCISTATUS);
2686b4b4
LW		 1066
1067 if (host->singleirq) {
1068 if (status & readl(host->base + MMCIMASK1))
1069 mmci_pio_irq(irq, dev_id);
1070
1071 status &= ~MCI_IRQ1MASK;
1072 }
1073
1da177e4
LT		 1074 status &= readl(host->base + MMCIMASK0);
1075 writel(status, host->base + MMCICLEAR);
1076
64de0289 1077 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1da177e4
LT		 1078
1079 data = host->data;
b63038d6
UH		 1080 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1081 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1082 MCI_DATABLOCKEND) && data)
1da177e4
LT		 1083 mmci_data_irq(host, data, status);
1084
1085 cmd = host->cmd;
1086 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1087 mmci_cmd_irq(host, cmd, status);
1088
1089 ret = 1;
1090 } while (status);
1091
1092 spin_unlock(&host->lock);
1093
1094 return IRQ_RETVAL(ret);
1095}
1096
1097static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1098{
1099 struct mmci_host *host = mmc_priv(mmc);
9e943021 1100 unsigned long flags;
1da177e4
LT		 1101
1102 WARN_ON(host->mrq != NULL);
1103
653a761e
UH		 1104 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1105 if (mrq->cmd->error) {
255d01af
PO		 1106 mmc_request_done(mmc, mrq);
1107 return;
1108 }
1109
1c3be369
RK		 1110 pm_runtime_get_sync(mmc_dev(mmc));
1111
9e943021 1112 spin_lock_irqsave(&host->lock, flags);
1da177e4
LT		 1113
1114 host->mrq = mrq;
1115
58c7ccbf
PF		 1116 if (mrq->data)
1117 mmci_get_next_data(host, mrq->data);
1118
1da177e4
LT		 1119 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1120 mmci_start_data(host, mrq->data);
1121
1122 mmci_start_command(host, mrq->cmd, 0);
1123
9e943021 1124 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 1125}
1126
1127static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1128{
1129 struct mmci_host *host = mmc_priv(mmc);
7d72a1d4 1130 struct variant_data *variant = host->variant;
a6a6464a
LW		 1131 u32 pwr = 0;
1132 unsigned long flags;
db90f91f 1133 int ret;
1da177e4 1134
2cd976c4
UH		 1135 pm_runtime_get_sync(mmc_dev(mmc));
1136
bc521818
UH		 1137 if (host->plat->ios_handler &&
1138 host->plat->ios_handler(mmc_dev(mmc), ios))
1139 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1140
1da177e4
LT		 1141 switch (ios->power_mode) {
1142 case MMC_POWER_OFF:
599c1d5c
UH		 1143 if (!IS_ERR(mmc->supply.vmmc))
1144 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
237fb5e6
LJ		 1145
1146 if (!IS_ERR(mmc->supply.vqmmc) &&
1147 regulator_is_enabled(mmc->supply.vqmmc))
1148 regulator_disable(mmc->supply.vqmmc);
1149
1da177e4
LT		 1150 break;
1151 case MMC_POWER_UP:
599c1d5c
UH		 1152 if (!IS_ERR(mmc->supply.vmmc))
1153 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1154
7d72a1d4
UH		 1155 /*
1156 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1157 * and instead uses MCI_PWR_ON so apply whatever value is
1158 * configured in the variant data.
1159 */
1160 pwr |= variant->pwrreg_powerup;
1161
1162 break;
1da177e4 1163 case MMC_POWER_ON:
237fb5e6 1164 if (!IS_ERR(mmc->supply.vqmmc) &&
db90f91f
LJ		 1165 !regulator_is_enabled(mmc->supply.vqmmc)) {
1166 ret = regulator_enable(mmc->supply.vqmmc);
1167 if (ret < 0)
1168 dev_err(mmc_dev(mmc),
1169 "failed to enable vqmmc regulator\n");
1170 }
237fb5e6 1171
1da177e4
LT		 1172 pwr |= MCI_PWR_ON;
1173 break;
1174 }
1175
4d1a3a0d
UH		 1176 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1177 /*
1178 * The ST Micro variant has some additional bits
1179 * indicating signal direction for the signals in
1180 * the SD/MMC bus and feedback-clock usage.
1181 */
1182 pwr |= host->plat->sigdir;
1183
1184 if (ios->bus_width == MMC_BUS_WIDTH_4)
1185 pwr &= ~MCI_ST_DATA74DIREN;
1186 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1187 pwr &= (~MCI_ST_DATA74DIREN &
1188 ~MCI_ST_DATA31DIREN &
1189 ~MCI_ST_DATA2DIREN);
1190 }
1191
cc30d60e 1192 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
f17a1f06 1193 if (host->hw_designer != AMBA_VENDOR_ST)
cc30d60e
LW		 1194 pwr |= MCI_ROD;
1195 else {
1196 /*
1197 * The ST Micro variant use the ROD bit for something
1198 * else and only has OD (Open Drain).
1199 */
1200 pwr |= MCI_OD;
1201 }
1202 }
1da177e4 1203
f4670dae
UH		 1204 /*
1205 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1206 * gating the clock, the MCI_PWR_ON bit is cleared.
1207 */
1208 if (!ios->clock && variant->pwrreg_clkgate)
1209 pwr &= ~MCI_PWR_ON;
1210
a6a6464a
LW		 1211 spin_lock_irqsave(&host->lock, flags);
1212
1213 mmci_set_clkreg(host, ios->clock);
7437cfa5 1214 mmci_write_pwrreg(host, pwr);
a6a6464a
LW		 1215
1216 spin_unlock_irqrestore(&host->lock, flags);
2cd976c4 1217
2cd976c4
UH		 1218 pm_runtime_mark_last_busy(mmc_dev(mmc));
1219 pm_runtime_put_autosuspend(mmc_dev(mmc));
1da177e4
LT		 1220}
1221
89001446
RK		 1222static int mmci_get_ro(struct mmc_host *mmc)
1223{
1224 struct mmci_host *host = mmc_priv(mmc);
1225
1226 if (host->gpio_wp == -ENOSYS)
1227 return -ENOSYS;
1228
18a06301 1229 return gpio_get_value_cansleep(host->gpio_wp);
89001446
RK		 1230}
1231
1232static int mmci_get_cd(struct mmc_host *mmc)
1233{
1234 struct mmci_host *host = mmc_priv(mmc);
29719445 1235 struct mmci_platform_data *plat = host->plat;
89001446
RK		 1236 unsigned int status;
1237
4b8caec0
RV		 1238 if (host->gpio_cd == -ENOSYS) {
1239 if (!plat->status)
1240 return 1; /* Assume always present */
1241
29719445 1242 status = plat->status(mmc_dev(host->mmc));
4b8caec0 1243 } else
18a06301
LW		 1244 status = !!gpio_get_value_cansleep(host->gpio_cd)
1245 ^ plat->cd_invert;
89001446 1246
74bc8093
RK		 1247 /*
1248 * Use positive logic throughout - status is zero for no card,
1249 * non-zero for card inserted.
1250 */
1251 return status;
89001446
RK		 1252}
1253
148b8b39
RV		 1254static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1255{
1256 struct mmci_host *host = dev_id;
1257
1258 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1259
1260 return IRQ_HANDLED;
1261}
1262
ab7aefd0 1263static const struct mmc_host_ops mmci_ops = {
1da177e4 1264 .request = mmci_request,
58c7ccbf
PF		 1265 .pre_req = mmci_pre_request,
1266 .post_req = mmci_post_request,
1da177e4 1267 .set_ios = mmci_set_ios,
89001446
RK		 1268 .get_ro = mmci_get_ro,
1269 .get_cd = mmci_get_cd,
1da177e4
LT		 1270};
1271
000bc9d5
LJ		 1272#ifdef CONFIG_OF
1273static void mmci_dt_populate_generic_pdata(struct device_node *np,
1274 struct mmci_platform_data *pdata)
1275{
1276 int bus_width = 0;
1277
9a597016 1278 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
9a597016 1279 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
000bc9d5
LJ		 1280
1281 if (of_get_property(np, "cd-inverted", NULL))
1282 pdata->cd_invert = true;
1283 else
1284 pdata->cd_invert = false;
1285
1286 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1287 if (!pdata->f_max)
1288 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1289
1290 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1291 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1292 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1293 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1294
1295 of_property_read_u32(np, "bus-width", &bus_width);
1296 switch (bus_width) {
1297 case 0 :
1298 /* No bus-width supplied. */
1299 break;
1300 case 4 :
1301 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1302 break;
1303 case 8 :
1304 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1305 break;
1306 default :
1307 pr_warn("%s: Unsupported bus width\n", np->full_name);
1308 }
1309}
c0a120a4
LJ		 1310#else
1311static void mmci_dt_populate_generic_pdata(struct device_node *np,
1312 struct mmci_platform_data *pdata)
1313{
1314 return;
1315}
000bc9d5
LJ		 1316#endif
1317
c3be1efd 1318static int mmci_probe(struct amba_device *dev,
aa25afad 1319 const struct amba_id *id)
1da177e4 1320{
6ef297f8 1321 struct mmci_platform_data *plat = dev->dev.platform_data;
000bc9d5 1322 struct device_node *np = dev->dev.of_node;
4956e109 1323 struct variant_data *variant = id->data;
1da177e4
LT		 1324 struct mmci_host *host;
1325 struct mmc_host *mmc;
1326 int ret;
1327
000bc9d5
LJ		 1328 /* Must have platform data or Device Tree. */
1329 if (!plat && !np) {
1330 dev_err(&dev->dev, "No plat data or DT found\n");
1331 return -EINVAL;
1da177e4
LT		 1332 }
1333
b9b52918
LJ		 1334 if (!plat) {
1335 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1336 if (!plat)
1337 return -ENOMEM;
1338 }
1339
000bc9d5
LJ		 1340 if (np)
1341 mmci_dt_populate_generic_pdata(np, plat);
1342
1da177e4
LT		 1343 ret = amba_request_regions(dev, DRIVER_NAME);
1344 if (ret)
1345 goto out;
1346
1347 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1348 if (!mmc) {
1349 ret = -ENOMEM;
1350 goto rel_regions;
1351 }
1352
1353 host = mmc_priv(mmc);
4ea580f1 1354 host->mmc = mmc;
012b7d33 1355
89001446
RK		 1356 host->gpio_wp = -ENOSYS;
1357 host->gpio_cd = -ENOSYS;
148b8b39 1358 host->gpio_cd_irq = -1;
89001446 1359
012b7d33
RK		 1360 host->hw_designer = amba_manf(dev);
1361 host->hw_revision = amba_rev(dev);
64de0289
LW		 1362 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1363 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
012b7d33 1364
ee569c43 1365 host->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 1366 if (IS_ERR(host->clk)) {
1367 ret = PTR_ERR(host->clk);
1368 host->clk = NULL;
1369 goto host_free;
1370 }
1371
ac940938 1372 ret = clk_prepare_enable(host->clk);
1da177e4 1373 if (ret)
a8d3584a 1374 goto clk_free;
1da177e4
LT		 1375
1376 host->plat = plat;
4956e109 1377 host->variant = variant;
1da177e4 1378 host->mclk = clk_get_rate(host->clk);
c8df9a53
LW		 1379 /*
1380 * According to the spec, mclk is max 100 MHz,
1381 * so we try to adjust the clock down to this,
1382 * (if possible).
1383 */
1384 if (host->mclk > 100000000) {
1385 ret = clk_set_rate(host->clk, 100000000);
1386 if (ret < 0)
1387 goto clk_disable;
1388 host->mclk = clk_get_rate(host->clk);
64de0289
LW		 1389 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1390 host->mclk);
c8df9a53 1391 }
c8ebae37 1392 host->phybase = dev->res.start;
dc890c2d 1393 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 1394 if (!host->base) {
1395 ret = -ENOMEM;
1396 goto clk_disable;
1397 }
1398
1399 mmc->ops = &mmci_ops;
7f294e49
LW		 1400 /*
1401 * The ARM and ST versions of the block have slightly different
1402 * clock divider equations which means that the minimum divider
1403 * differs too.
1404 */
1405 if (variant->st_clkdiv)
1406 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1407 else
1408 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
808d97cc
LW		 1409 /*
1410 * If the platform data supplies a maximum operating
1411 * frequency, this takes precedence. Else, we fall back
1412 * to using the module parameter, which has a (low)
1413 * default value in case it is not specified. Either
1414 * value must not exceed the clock rate into the block,
1415 * of course.
1416 */
1417 if (plat->f_max)
1418 mmc->f_max = min(host->mclk, plat->f_max);
1419 else
1420 mmc->f_max = min(host->mclk, fmax);
64de0289
LW		 1421 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1422
a9a83785
LW		 1423 host->pinctrl = devm_pinctrl_get(&dev->dev);
1424 if (IS_ERR(host->pinctrl)) {
1425 ret = PTR_ERR(host->pinctrl);
1426 goto clk_disable;
1427 }
1428
1429 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1430 PINCTRL_STATE_DEFAULT);
1431
1432 /* enable pins to be muxed in and configured */
1433 if (!IS_ERR(host->pins_default)) {
1434 ret = pinctrl_select_state(host->pinctrl, host->pins_default);
1435 if (ret)
1436 dev_warn(&dev->dev, "could not set default pins\n");
1437 } else
1438 dev_warn(&dev->dev, "could not get default pinstate\n");
1439
599c1d5c
UH		 1440 /* Get regulators and the supported OCR mask */
1441 mmc_regulator_get_supply(mmc);
1442 if (!mmc->ocr_avail)
34e84f39 1443 mmc->ocr_avail = plat->ocr_mask;
599c1d5c
UH		 1444 else if (plat->ocr_mask)
1445 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1446
9e6c82cd 1447 mmc->caps = plat->capabilities;
5a092627 1448 mmc->caps2 = plat->capabilities2;
1da177e4 1449
70be208f
UH		 1450 /* We support these PM capabilities. */
1451 mmc->pm_caps = MMC_PM_KEEP_POWER;
1452
1da177e4
LT		 1453 /*
1454 * We can do SGIO
1455 */
a36274e0 1456 mmc->max_segs = NR_SG;
1da177e4
LT		 1457
1458 /*
08458ef6
RV		 1459 * Since only a certain number of bits are valid in the data length
1460 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1461 * single request.
1da177e4 1462 */
08458ef6 1463 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1da177e4
LT		 1464
1465 /*
1466 * Set the maximum segment size. Since we aren't doing DMA
1467 * (yet) we are only limited by the data length register.
1468 */
55db890a 1469 mmc->max_seg_size = mmc->max_req_size;
1da177e4 1470
fe4a3c7a
PO		 1471 /*
1472 * Block size can be up to 2048 bytes, but must be a power of two.
1473 */
8f7f6b7e 1474 mmc->max_blk_size = 1 << 11;
fe4a3c7a 1475
55db890a 1476 /*
8f7f6b7e
WD		 1477 * Limit the number of blocks transferred so that we don't overflow
1478 * the maximum request size.
55db890a 1479 */
8f7f6b7e 1480 mmc->max_blk_count = mmc->max_req_size >> 11;
55db890a 1481
1da177e4
LT		 1482 spin_lock_init(&host->lock);
1483
1484 writel(0, host->base + MMCIMASK0);
1485 writel(0, host->base + MMCIMASK1);
1486 writel(0xfff, host->base + MMCICLEAR);
1487
2805b9ab
RS		 1488 if (plat->gpio_cd == -EPROBE_DEFER) {
1489 ret = -EPROBE_DEFER;
1490 goto err_gpio_cd;
1491 }
89001446
RK		 1492 if (gpio_is_valid(plat->gpio_cd)) {
1493 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1494 if (ret == 0)
1495 ret = gpio_direction_input(plat->gpio_cd);
1496 if (ret == 0)
1497 host->gpio_cd = plat->gpio_cd;
1498 else if (ret != -ENOSYS)
1499 goto err_gpio_cd;
148b8b39 1500
17ee083b
LW		 1501 /*
1502 * A gpio pin that will detect cards when inserted and removed
1503 * will most likely want to trigger on the edges if it is
1504 * 0 when ejected and 1 when inserted (or mutatis mutandis
1505 * for the inverted case) so we request triggers on both
1506 * edges.
1507 */
148b8b39 1508 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
17ee083b
LW		 1509 mmci_cd_irq,
1510 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1511 DRIVER_NAME " (cd)", host);
148b8b39
RV		 1512 if (ret >= 0)
1513 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
89001446 1514 }
2805b9ab
RS		 1515 if (plat->gpio_wp == -EPROBE_DEFER) {
1516 ret = -EPROBE_DEFER;
1517 goto err_gpio_wp;
1518 }
89001446
RK		 1519 if (gpio_is_valid(plat->gpio_wp)) {
1520 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1521 if (ret == 0)
1522 ret = gpio_direction_input(plat->gpio_wp);
1523 if (ret == 0)
1524 host->gpio_wp = plat->gpio_wp;
1525 else if (ret != -ENOSYS)
1526 goto err_gpio_wp;
1527 }
1528
4b8caec0
RV		 1529 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1530 && host->gpio_cd_irq < 0)
148b8b39
RV		 1531 mmc->caps |= MMC_CAP_NEEDS_POLL;
1532
dace1453 1533 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1da177e4
LT		 1534 if (ret)
1535 goto unmap;
1536
dfb85185 1537 if (!dev->irq[1])
2686b4b4
LW		 1538 host->singleirq = true;
1539 else {
1540 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1541 DRIVER_NAME " (pio)", host);
1542 if (ret)
1543 goto irq0_free;
1544 }
1da177e4 1545
8cb28155 1546 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1da177e4
LT		 1547
1548 amba_set_drvdata(dev, mmc);
1549
c8ebae37
RK		 1550 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1551 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1552 amba_rev(dev), (unsigned long long)dev->res.start,
1553 dev->irq[0], dev->irq[1]);
1554
1555 mmci_dma_setup(host);
1da177e4 1556
2cd976c4
UH		 1557 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1558 pm_runtime_use_autosuspend(&dev->dev);
1c3be369
RK		 1559 pm_runtime_put(&dev->dev);
1560
8c11a94d
RK		 1561 mmc_add_host(mmc);
1562
1da177e4
LT		 1563 return 0;
1564
1565 irq0_free:
1566 free_irq(dev->irq[0], host);
1567 unmap:
89001446
RK		 1568 if (host->gpio_wp != -ENOSYS)
1569 gpio_free(host->gpio_wp);
1570 err_gpio_wp:
148b8b39
RV		 1571 if (host->gpio_cd_irq >= 0)
1572 free_irq(host->gpio_cd_irq, host);
89001446
RK		 1573 if (host->gpio_cd != -ENOSYS)
1574 gpio_free(host->gpio_cd);
1575 err_gpio_cd:
1da177e4
LT		 1576 iounmap(host->base);
1577 clk_disable:
ac940938 1578 clk_disable_unprepare(host->clk);
1da177e4
LT		 1579 clk_free:
1580 clk_put(host->clk);
1581 host_free:
1582 mmc_free_host(mmc);
1583 rel_regions:
1584 amba_release_regions(dev);
1585 out:
1586 return ret;
1587}
1588
6e0ee714 1589static int mmci_remove(struct amba_device *dev)
1da177e4
LT		 1590{
1591 struct mmc_host *mmc = amba_get_drvdata(dev);
1592
1593 amba_set_drvdata(dev, NULL);
1594
1595 if (mmc) {
1596 struct mmci_host *host = mmc_priv(mmc);
1597
1c3be369
RK		 1598 /*
1599 * Undo pm_runtime_put() in probe. We use the _sync
1600 * version here so that we can access the primecell.
1601 */
1602 pm_runtime_get_sync(&dev->dev);
1603
1da177e4
LT		 1604 mmc_remove_host(mmc);
1605
1606 writel(0, host->base + MMCIMASK0);
1607 writel(0, host->base + MMCIMASK1);
1608
1609 writel(0, host->base + MMCICOMMAND);
1610 writel(0, host->base + MMCIDATACTRL);
1611
c8ebae37 1612 mmci_dma_release(host);
1da177e4 1613 free_irq(dev->irq[0], host);
2686b4b4
LW		 1614 if (!host->singleirq)
1615 free_irq(dev->irq[1], host);
1da177e4 1616
89001446
RK		 1617 if (host->gpio_wp != -ENOSYS)
1618 gpio_free(host->gpio_wp);
148b8b39
RV		 1619 if (host->gpio_cd_irq >= 0)
1620 free_irq(host->gpio_cd_irq, host);
89001446
RK		 1621 if (host->gpio_cd != -ENOSYS)
1622 gpio_free(host->gpio_cd);
1623
1da177e4 1624 iounmap(host->base);
ac940938 1625 clk_disable_unprepare(host->clk);
1da177e4
LT		 1626 clk_put(host->clk);
1627
1628 mmc_free_host(mmc);
1629
1630 amba_release_regions(dev);
1631 }
1632
1633 return 0;
1634}
1635
48fa7003
UH		 1636#ifdef CONFIG_SUSPEND
1637static int mmci_suspend(struct device *dev)
1da177e4 1638{
48fa7003
UH		 1639 struct amba_device *adev = to_amba_device(dev);
1640 struct mmc_host *mmc = amba_get_drvdata(adev);
1da177e4
LT		 1641 int ret = 0;
1642
1643 if (mmc) {
1644 struct mmci_host *host = mmc_priv(mmc);
1645
1a13f8fa 1646 ret = mmc_suspend_host(mmc);
2cd976c4
UH		 1647 if (ret == 0) {
1648 pm_runtime_get_sync(dev);
1da177e4 1649 writel(0, host->base + MMCIMASK0);
2cd976c4 1650 }
1da177e4
LT		 1651 }
1652
1653 return ret;
1654}
1655
48fa7003 1656static int mmci_resume(struct device *dev)
1da177e4 1657{
48fa7003
UH		 1658 struct amba_device *adev = to_amba_device(dev);
1659 struct mmc_host *mmc = amba_get_drvdata(adev);
1da177e4
LT		 1660 int ret = 0;
1661
1662 if (mmc) {
1663 struct mmci_host *host = mmc_priv(mmc);
1664
1665 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
2cd976c4 1666 pm_runtime_put(dev);
1da177e4
LT		 1667
1668 ret = mmc_resume_host(mmc);
1669 }
1670
1671 return ret;
1672}
1da177e4
LT		 1673#endif
1674
8259293a
UH		 1675#ifdef CONFIG_PM_RUNTIME
1676static int mmci_runtime_suspend(struct device *dev)
1677{
1678 struct amba_device *adev = to_amba_device(dev);
1679 struct mmc_host *mmc = amba_get_drvdata(adev);
1680
1681 if (mmc) {
1682 struct mmci_host *host = mmc_priv(mmc);
1683 clk_disable_unprepare(host->clk);
1684 }
1685
1686 return 0;
1687}
1688
1689static int mmci_runtime_resume(struct device *dev)
1690{
1691 struct amba_device *adev = to_amba_device(dev);
1692 struct mmc_host *mmc = amba_get_drvdata(adev);
1693
1694 if (mmc) {
1695 struct mmci_host *host = mmc_priv(mmc);
1696 clk_prepare_enable(host->clk);
1697 }
1698
1699 return 0;
1700}
1701#endif
1702
48fa7003
UH		 1703static const struct dev_pm_ops mmci_dev_pm_ops = {
1704 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
8259293a 1705 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
48fa7003
UH		 1706};
1707
1da177e4
LT		 1708static struct amba_id mmci_ids[] = {
1709 {
1710 .id = 0x00041180,
768fbc18 1711 .mask = 0xff0fffff,
4956e109 1712 .data = &variant_arm,
1da177e4 1713 },
768fbc18
PM		 1714 {
1715 .id = 0x01041180,
1716 .mask = 0xff0fffff,
1717 .data = &variant_arm_extended_fifo,
1718 },
3a37298a
PM		 1719 {
1720 .id = 0x02041180,
1721 .mask = 0xff0fffff,
1722 .data = &variant_arm_extended_fifo_hwfc,
1723 },
1da177e4
LT		 1724 {
1725 .id = 0x00041181,
1726 .mask = 0x000fffff,
4956e109 1727 .data = &variant_arm,
1da177e4 1728 },
cc30d60e
LW		 1729 /* ST Micro variants */
1730 {
1731 .id = 0x00180180,
1732 .mask = 0x00ffffff,
4956e109 1733 .data = &variant_u300,
cc30d60e 1734 },
34fd4213
LW		 1735 {
1736 .id = 0x10180180,
1737 .mask = 0xf0ffffff,
1738 .data = &variant_nomadik,
1739 },
cc30d60e
LW		 1740 {
1741 .id = 0x00280180,
1742 .mask = 0x00ffffff,
4956e109
RV		 1743 .data = &variant_u300,
1744 },
1745 {
1746 .id = 0x00480180,
1784b157 1747 .mask = 0xf0ffffff,
4956e109 1748 .data = &variant_ux500,
cc30d60e 1749 },
1784b157
PL		 1750 {
1751 .id = 0x10480180,
1752 .mask = 0xf0ffffff,
1753 .data = &variant_ux500v2,
1754 },
1da177e4
LT		 1755 { 0, 0 },
1756};
1757
9f99835f
DM		 1758MODULE_DEVICE_TABLE(amba, mmci_ids);
1759
1da177e4
LT		 1760static struct amba_driver mmci_driver = {
1761 .drv = {
1762 .name = DRIVER_NAME,
48fa7003 1763 .pm = &mmci_dev_pm_ops,
1da177e4
LT		 1764 },
1765 .probe = mmci_probe,
0433c143 1766 .remove = mmci_remove,
1da177e4
LT		 1767 .id_table = mmci_ids,
1768};
1769
9e5ed094 1770module_amba_driver(mmci_driver);
1da177e4 1771
1da177e4
LT		 1772module_param(fmax, uint, 0444);
1773
1774MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1775MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)