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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / xhci_test / xhci.h
CommitLineData
6fa3eb70
S		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __LINUX_TEST_XHCI_HCD_H
24#define __LINUX_TEST_XHCI_HCD_H
25
26#include <linux/usb.h>
27#include <linux/timer.h>
28#include <linux/kernel.h>
29#include <linux/usb/hcd.h>
30
31/* Code sharing between pci-quirks and xhci hcd */
32#include "xhci-ext-caps.h"
33
34/* xHCI PCI Configuration Registers */
35#define XHCI_SBRN_OFFSET (0x60)
36
37/* Max number of USB devices for any host controller - limit in section 6.1 */
38#define MAX_HC_SLOTS 256
39/* Section 5.3.3 - MaxPorts */
40#define MAX_HC_PORTS 127
41
42/*
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
46 */
47
48/**
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
57 */
58struct xhci_cap_regs {
59 u32 hc_capbase;
60 u32 hcs_params1;
61 u32 hcs_params2;
62 u32 hcs_params3;
63 u32 hcc_params;
64 u32 db_off;
65 u32 run_regs_off;
66 /* Reserved up to (CAPLENGTH - 0x1C) */
67};
68
69/* hc_capbase bitmasks */
70/* bits 7:0 - how long is the Capabilities register */
71#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
72/* bits 31:16 */
73#define HC_VERSION(p) (((p) >> 16) & 0xffff)
74
75/* HCSPARAMS1 - hcs_params1 - bitmasks */
76/* bits 0:7, Max Device Slots */
77#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78#define HCS_SLOTS_MASK 0xff
79/* bits 8:18, Max Interrupters */
80#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
83
84/* HCSPARAMS2 - hcs_params2 - bitmasks */
85/* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87#define HCS_IST(p) (((p) >> 0) & 0xf)
88/* bits 4:7, max number of Event Ring segments */
89#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
92#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
93
94/* HCSPARAMS3 - hcs_params3 - bitmasks */
95/* bits 0:7, Max U1 to U0 latency for the roothub ports */
96#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97/* bits 16:31, Max U2 to U0 latency for the roothub ports */
98#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
99
100/* HCCPARAMS - hcc_params - bitmasks */
101/* true: HC can use 64-bit address pointers */
102#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103/* true: HC can do bandwidth negotiation */
104#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105/* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
107 */
108#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109/* true: HC has port power switches */
110#define HCC_PPC(p) ((p) & (1 << 3))
111/* true: HC has port indicators */
112#define HCS_INDICATOR(p) ((p) & (1 << 4))
113/* true: HC has Light HC Reset Capability */
114#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115/* true: HC supports latency tolerance messaging */
116#define HCC_LTC(p) ((p) & (1 << 6))
117/* true: no secondary Stream ID Support */
118#define HCC_NSS(p) ((p) & (1 << 7))
119/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
121/* Extended Capabilities pointer from PCI base - section 5.3.6 */
122#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130
131/* Number of registers per port */
132#define NUM_PORT_REGS 4
133
134/**
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
149 * register.
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
154 * devices.
155 */
156struct xhci_op_regs {
157 u32 command;
158 u32 status;
159 u32 page_size;
160 u32 reserved1;
161 u32 reserved2;
162 u32 dev_notification;
163 u64 cmd_ring;
164 /* rsvd: offset 0x20-2F */
165 u32 reserved3[4];
166 u64 dcbaa_ptr;
167 u32 config_reg;
168 /* rsvd: offset 0x3C-3FF */
169 u32 reserved4[241];
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
172 u32 port_power_base;
173 u32 port_link_base;
174 /* reference ssub_xHCI_u2_port_csr.xlsm for the configure fields */
175 u32 port_lpm_ctrl_base;
176 u32 reserved5;
177 /* registers for ports 2-255 */
178 u32 reserved6[NUM_PORT_REGS*254];
179};
180
181/* USBCMD - USB command - command bitmasks */
182/* start/stop HC execution - do not write unless HC is halted*/
183#define CMD_RUN XHCI_CMD_RUN
184/* Reset HC - resets internal HC state machine and all registers (except
185 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
186 * The xHCI driver must reinitialize the xHC after setting this bit.
187 */
188#define CMD_RESET (1 << 1)
189/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
190#define CMD_EIE XHCI_CMD_EIE
191/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
192#define CMD_HSEIE XHCI_CMD_HSEIE
193/* bits 4:6 are reserved (and should be preserved on writes). */
194/* light reset (port status stays unchanged) - reset completed when this is 0 */
195#define CMD_LRESET (1 << 7)
196/* FIXME: ignoring host controller save/restore state for now. */
197#define CMD_CSS (1 << 8)
198#define CMD_CRS (1 << 9)
199/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
200#define CMD_EWE XHCI_CMD_EWE
201/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
202 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
203 * '0' means the xHC can power it off if all ports are in the disconnect,
204 * disabled, or powered-off state.
205 */
206#define CMD_PM_INDEX (1 << 11)
207/* bits 12:31 are reserved (and should be preserved on writes). */
208
209/* USBSTS - USB status - status bitmasks */
210/* HC not running - set to 1 when run/stop bit is cleared. */
211#define STS_HALT XHCI_STS_HALT
212/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
213#define STS_FATAL (1 << 2)
214/* event interrupt - clear this prior to clearing any IP flags in IR set*/
215#define STS_EINT (1 << 3)
216/* port change detect */
217#define STS_PORT (1 << 4)
218/* bits 5:7 reserved and zeroed */
219/* save state status - '1' means xHC is saving state */
220#define STS_SAVE (1 << 8)
221/* restore state status - '1' means xHC is restoring state */
222#define STS_RESTORE (1 << 9)
223/* true: save or restore error */
224#define STS_SRE (1 << 10)
225/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
226#define STS_CNR XHCI_STS_CNR
227/* true: internal Host Controller Error - SW needs to reset and reinitialize */
228#define STS_HCE (1 << 12)
229/* bits 13:31 reserved and should be preserved */
230
231/*
232 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
233 * Generate a device notification event when the HC sees a transaction with a
234 * notification type that matches a bit set in this bit field.
235 */
236#define DEV_NOTE_MASK (0xffff)
237#define ENABLE_DEV_NOTE(x) (1 << x)
238/* Most of the device notification types should only be used for debug.
239 * SW does need to pay attention to function wake notifications.
240 */
241#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
242
243/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
244/* bit 0 is the command ring cycle state */
245/* stop ring operation after completion of the currently executing command */
246#define CMD_RING_PAUSE (1 << 1)
247/* stop ring immediately - abort the currently executing command */
248#define CMD_RING_ABORT (1 << 2)
249/* true: command ring is running */
250#define CMD_RING_RUNNING (1 << 3)
251/* bits 4:5 reserved and should be preserved */
252/* Command Ring pointer - bit mask for the lower 32 bits. */
253#define CMD_RING_RSVD_BITS (0x3f)
254
255/* CONFIG - Configure Register - config_reg bitmasks */
256/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
257#define MAX_DEVS(p) ((p) & 0xff)
258/* bits 8:31 - reserved and should be preserved */
259
260/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
261/* true: device connected */
262#define PORT_CONNECT (1 << 0)
263/* true: port enabled */
264#define PORT_PE (1 << 1)
265/* bit 2 reserved and zeroed */
266/* true: port has an over-current condition */
267#define PORT_OC (1 << 3)
268/* true: port reset signaling asserted */
269#define PORT_RESET (1 << 4)
270#define PORT_PLS_VALUE(p) ((p>>5) & 0xf)
271/* Port Link State - bits 5:8
272 * A read gives the current link PM state of the port,
273 * a write with Link State Write Strobe set sets the link state.
274 */
275#define PORT_PLS(p) (p & (0xf << 5))
276#define PORT_PLS_MASK (0xf << 5)
277#define XDEV_U0 (0x0 << 5)
278#define XDEV_U3 (0x3 << 5)
279#define XDEV_RESUME (0xf << 5)
280#define XDEV_INACTIVE (0x6 << 5)
281
282/* true: port has power (see HCC_PPC) */
283#define PORT_POWER (1 << 9)
284/* bits 10:13 indicate device speed:
285 * 0 - undefined speed - port hasn't be initialized by a reset yet
286 * 1 - full speed
287 * 2 - low speed
288 * 3 - high speed
289 * 4 - super speed
290 * 5-15 reserved
291 */
292#define DEV_SPEED_MASK (0xf << 10)
293#define XDEV_FS (0x1 << 10)
294#define XDEV_LS (0x2 << 10)
295#define XDEV_HS (0x3 << 10)
296#define XDEV_SS (0x4 << 10)
297#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
298#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
299#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
300#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
301#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
302/* Bits 20:23 in the Slot Context are the speed for the device */
303#define SLOT_SPEED_FS (XDEV_FS << 10)
304#define SLOT_SPEED_LS (XDEV_LS << 10)
305#define SLOT_SPEED_HS (XDEV_HS << 10)
306#define SLOT_SPEED_SS (XDEV_SS << 10)
307/* Port Indicator Control */
308#define PORT_LED_OFF (0 << 14)
309#define PORT_LED_AMBER (1 << 14)
310#define PORT_LED_GREEN (2 << 14)
311#define PORT_LED_MASK (3 << 14)
312/* Port Link State Write Strobe - set this when changing link state */
313#define PORT_LINK_STROBE (1 << 16)
314/* true: connect status change */
315#define PORT_CSC (1 << 17)
316/* true: port enable change */
317#define PORT_PEC (1 << 18)
318/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
319 * into an enabled state, and the device into the default state. A "warm" reset
320 * also resets the link, forcing the device through the link training sequence.
321 * SW can also look at the Port Reset register to see when warm reset is done.
322 */
323#define PORT_WRC (1 << 19)
324/* true: over-current change */
325#define PORT_OCC (1 << 20)
326/* true: reset change - 1 to 0 transition of PORT_RESET */
327#define PORT_RC (1 << 21)
328/* port link status change - set on some port link state transitions:
329 * Transition Reason
330 * ------------------------------------------------------------------------------
331 * - U3 to Resume Wakeup signaling from a device
332 * - Resume to Recovery to U0 USB 3.0 device resume
333 * - Resume to U0 USB 2.0 device resume
334 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
335 * - U3 to U0 Software resume of USB 2.0 device complete
336 * - U2 to U0 L1 resume of USB 2.1 device complete
337 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
338 * - U0 to disabled L1 entry error with USB 2.1 device
339 * - Any state to inactive Error on USB 3.0 port
340 */
341#define PORT_PLC (1 << 22)
342/* port configure error change - port failed to configure its link partner */
343#define PORT_CEC (1 << 23)
344/* bit 24 reserved */
345/* wake on connect (enable) */
346#define PORT_WKCONN_E (1 << 25)
347/* wake on disconnect (enable) */
348#define PORT_WKDISC_E (1 << 26)
349/* wake on over-current (enable) */
350#define PORT_WKOC_E (1 << 27)
351/* bits 28:29 reserved */
352/* true: device is removable - for USB 3.0 roothub emulation */
353#define PORT_DEV_REMOVE (1 << 30)
354/* Initiate a warm port reset - complete when PORT_WRC is '1' */
355#define PORT_WR (1 << 31)
356
357/* Port Power Management Status and Control - port_power_base bitmasks */
358/* Inactivity timer value for transitions into U1, in microseconds.
359 * Timeout can be up to 127us. 0xFF means an infinite timeout.
360 */
361#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
362/* Inactivity timer value for transitions into U2 */
363#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
364/* Bits 24:31 for port testing */
365
366/* U2 port power */
367/* L1 status */
368#define L1S_INVALID 0
369#define L1S_SUCCESS 1
370#define L1S_NYET 2
371#define L1S_UNSUPPORTED 3
372#define L1S_ERROR_TIMEOUT 4
373#define L1S_UNDEFINED 5
374
375/* PORTSC */
376#define MSK_PLS (0xf<<5)
377#define PLS_VALUE_L0 0x0
378#define PLS_VALUE_L1 0x2
379#define PLS_VALUE_RESUME 0xf
380
381/* PORTPMSC */
382#define MSK_L1S (0x7<<0)
383#define MSK_RWE (0x1<<3)
384#define MSK_BESL (0xf<<4) /* HIRD, Host Initiated Resume Duration*/
385#define MSK_L1_DEV_SLOT (0xff<<8)
386#define MSK_HLE (0x1<<16)
387
388
389/*add by TH.fei for setup trb TRT Field*/
390#define TRB_TRT(p) ((p)<<16)
391#define TRT_NO_DATA 0
392#define TRT_RERV 1
393#define TRT_OUT_DATA 2
394#define TRT_IN_DATA 3
395
396
397/**
398 * struct xhci_intr_reg - Interrupt Register Set
399 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
400 * interrupts and check for pending interrupts.
401 * @irq_control: IMOD - Interrupt Moderation Register.
402 * Used to throttle interrupts.
403 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
404 * @erst_base: ERST base address.
405 * @erst_dequeue: Event ring dequeue pointer.
406 *
407 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
408 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
409 * multiple segments of the same size. The HC places events on the ring and
410 * "updates the Cycle bit in the TRBs to indicate to software the current
411 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
412 * updates the dequeue pointer.
413 */
414struct xhci_intr_reg {
415 u32 irq_pending;
416 u32 irq_control;
417 u32 erst_size;
418 u32 rsvd;
419 u64 erst_base;
420 u64 erst_dequeue;
421};
422
423/* irq_pending bitmasks */
424#define ER_IRQ_PENDING(p) ((p) & 0x1)
425/* bits 2:31 need to be preserved */
426/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
427#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
428#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
429#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
430
431/* irq_control bitmasks */
432/* Minimum interval between interrupts (in 250ns intervals). The interval
433 * between interrupts will be longer if there are no events on the event ring.
434 * Default is 4000 (1 ms).
435 */
436#define ER_IRQ_INTERVAL_MASK (0xffff)
437/* Counter used to count down the time to the next interrupt - HW use only */
438#define ER_IRQ_COUNTER_MASK (0xffff << 16)
439
440/* erst_size bitmasks */
441/* Preserve bits 16:31 of erst_size */
442#define ERST_SIZE_MASK (0xffff << 16)
443
444/* erst_dequeue bitmasks */
445/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
446 * where the current dequeue pointer lies. This is an optional HW hint.
447 */
448#define ERST_DESI_MASK (0x7)
449/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
450 * a work queue (or delayed service routine)?
451 */
452#define ERST_EHB (1 << 3)
453#define ERST_PTR_MASK (0xf)
454
455/**
456 * struct xhci_run_regs
457 * @microframe_index:
458 * MFINDEX - current microframe number
459 *
460 * Section 5.5 Host Controller Runtime Registers:
461 * "Software should read and write these registers using only Dword (32 bit)
462 * or larger accesses"
463 */
464struct xhci_run_regs {
465 u32 microframe_index;
466 u32 rsvd[7];
467 struct xhci_intr_reg ir_set[128];
468};
469
470/**
471 * struct doorbell_array
472 *
473 * Section 5.6
474 */
475struct xhci_doorbell_array {
476 u32 doorbell[256];
477};
478
479#define DB_TARGET_MASK 0xFFFFFF00
480#define DB_STREAM_ID_MASK 0x0000FFFF
481#define DB_TARGET_HOST 0x0
482#define DB_STREAM_ID_HOST 0x0
483#define DB_MASK (0xff << 8)
484
485/* Endpoint Target - bits 0:7 */
486#define EPI_TO_DB(p) (((p) + 1) & 0xff)
487#define STREAM_ID_TO_DB(p) (((p) & 0xffff) << 16)
488
489
490/**
491 * struct xhci_container_ctx
492 * @type: Type of context. Used to calculated offsets to contained contexts.
493 * @size: Size of the context data
494 * @bytes: The raw context data given to HW
495 * @dma: dma address of the bytes
496 *
497 * Represents either a Device or Input context. Holds a pointer to the raw
498 * memory used for the context (bytes) and dma address of it (dma).
499 */
500
501#define XHCI_CTX_TYPE_DEVICE 0x1
502#define XHCI_CTX_TYPE_INPUT 0x2
503
504struct xhci_container_ctx {
505 unsigned type;
506 int size;
507 u8 *bytes;
508 dma_addr_t dma;
509};
510
511/**
512 * struct xhci_slot_ctx
513 * @dev_info: Route string, device speed, hub info, and last valid endpoint
514 * @dev_info2: Max exit latency for device number, root hub port number
515 * @tt_info: tt_info is used to construct split transaction tokens
516 * @dev_state: slot state and device address
517 *
518 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
519 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
520 * reserved at the end of the slot context for HC internal use.
521 */
522struct xhci_slot_ctx {
523 u32 dev_info;
524 u32 dev_info2;
525 u32 tt_info;
526 u32 dev_state;
527 /* offset 0x10 to 0x1f reserved for HC internal use */
528 u32 reserved[4];
529};
530
531/* dev_info bitmasks */
532/* Route String - 0:19 */
533#define ROUTE_STRING_MASK (0xfffff)
534/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
535#define DEV_SPEED (0xf << 20)
536/* bit 24 reserved */
537/* Is this LS/FS device connected through a HS hub? - bit 25 */
538#define DEV_MTT (0x1 << 25)
539/* Set if the device is a hub - bit 26 */
540#define DEV_HUB (0x1 << 26)
541/* Index of the last valid endpoint context in this device context - 27:31 */
542#define LAST_CTX_MASK (0x1f << 27)
543#define LAST_CTX(p) ((p) << 27)
544#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
545#define SLOT_FLAG (1 << 0)
546#define EP0_FLAG (1 << 1)
547
548/* dev_info2 bitmasks */
549/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
550#define MAX_EXIT (0xffff)
551/* Root hub port number that is needed to access the USB device */
552#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
553/* Maximum number of ports under a hub device */
554#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
555
556/* tt_info bitmasks */
557/*
558 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
559 * The Slot ID of the hub that isolates the high speed signaling from
560 * this low or full-speed device. '0' if attached to root hub port.
561 */
562#define TT_SLOT (0xff)
563/*
564 * The number of the downstream facing port of the high-speed hub
565 * '0' if the device is not low or full speed.
566 */
567#define TT_PORT (0xff << 8)
568#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
569
570/* dev_state bitmasks */
571/* USB device address - assigned by the HC */
572#define DEV_ADDR_MASK (0xff)
573/* bits 8:26 reserved */
574/* Slot state */
575#define SLOT_STATE (0x1f << 27)
576#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
577/* slot state value */
578#define SLOT_STATE_ENABLE_DISABLE 0
579#define SLOT_STATE_DEFAULT 1
580#define SLOT_STATE_ADDRESSED 2
581#define SLOT_STATE_CONFIGURED 3
582
583/**
584 * struct xhci_ep_ctx
585 * @ep_info: endpoint state, streams, mult, and interval information.
586 * @ep_info2: information on endpoint type, max packet size, max burst size,
587 * error count, and whether the HC will force an event for all
588 * transactions.
589 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
590 * defines one stream, this points to the endpoint transfer ring.
591 * Otherwise, it points to a stream context array, which has a
592 * ring pointer for each flow.
593 * @tx_info:
594 * Average TRB lengths for the endpoint ring and
595 * max payload within an Endpoint Service Interval Time (ESIT).
596 *
597 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
598 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
599 * reserved at the end of the endpoint context for HC internal use.
600 */
601struct xhci_ep_ctx {
602 u32 ep_info;
603 u32 ep_info2;
604 u64 deq;
605 u32 tx_info;
606 /* offset 0x14 - 0x1f reserved for HC internal use */
607 u32 reserved[3];
608};
609
610/* ep_info bitmasks */
611/*
612 * Endpoint State - bits 0:2
613 * 0 - disabled
614 * 1 - running
615 * 2 - halted due to halt condition - ok to manipulate endpoint ring
616 * 3 - stopped
617 * 4 - TRB error
618 * 5-7 - reserved
619 */
620#define EP_STATE_MASK (0xf)
621#define EP_STATE_DISABLED 0
622#define EP_STATE_RUNNING 1
623#define EP_STATE_HALTED 2
624#define EP_STATE_STOPPED 3
625#define EP_STATE_ERROR 4
626/* Mult - Max number of burtst within an interval, in EP companion desc. */
627#define EP_MULT(p) ((p & 0x3) << 8)
628/* bits 10:14 are Max Primary Streams */
629/* bit 15 is Linear Stream Array */
630/* Interval - period between requests to an endpoint - 125u increments. */
631#define EP_INTERVAL(p) ((p & 0xff) << 16)
632#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
633#define EP_MAXPSTREAMS_MASK (0x1f << 10)
634#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
635/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
636#define EP_HAS_LSA (1 << 15)
637
638/* ep_info2 bitmasks */
639/*
640 * Force Event - generate transfer events for all TRBs for this endpoint
641 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
642 */
643#define FORCE_EVENT (0x1)
644#define ERROR_COUNT(p) (((p) & 0x3) << 1)
645#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
646#define EP_TYPE(p) ((p) << 3)
647#define ISOC_OUT_EP 1
648#define BULK_OUT_EP 2
649#define INT_OUT_EP 3
650#define CTRL_EP 4
651#define ISOC_IN_EP 5
652#define BULK_IN_EP 6
653#define INT_IN_EP 7
654/* bit 6 reserved */
655/* bit 7 is Host Initiate Disable - for disabling stream selection */
656#define MAX_BURST(p) (((p)&0xff) << 8)
657#define MAX_PACKET(p) (((p)&0xffff) << 16)
658#define MAX_PACKET_MASK (0xffff << 16)
659#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
660
661/* tx_info bitmasks */
662#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
663#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
664
665/* deq bitmasks */
666#define EP_CTX_CYCLE_MASK (1 << 0)
667
668
669/**
670 * struct xhci_input_control_context
671 * Input control context; see section 6.2.5.
672 *
673 * @drop_context: set the bit of the endpoint context you want to disable
674 * @add_context: set the bit of the endpoint context you want to enable
675 */
676struct xhci_input_control_ctx {
677 u32 drop_flags;
678 u32 add_flags;
679 u32 rsvd2[6];
680};
681
682/* Represents everything that is needed to issue a command on the command ring.
683 * It's useful to pre-allocate these for commands that cannot fail due to
684 * out-of-memory errors, like freeing streams.
685 */
686struct xhci_command {
687 /* Input context for changing device state */
688 struct xhci_container_ctx *in_ctx;
689 u32 status;
690 /* If completion is null, no one is waiting on this command
691 * and the structure can be freed after the command completes.
692 */
693 struct completion *completion;
694 union xhci_trb *command_trb;
695 struct list_head cmd_list;
696};
697
698/* drop context bitmasks */
699#define DROP_EP(x) (0x1 << x)
700/* add context bitmasks */
701#define ADD_EP(x) (0x1 << x)
702
703struct xhci_stream_ctx {
704 /* 64-bit stream ring address, cycle state, and stream type */
705 u64 stream_ring;
706 /* offset 0x14 - 0x1f reserved for HC internal use */
707 u32 reserved[2];
708};
709
710/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
711#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
712/* Secondary stream array type, dequeue pointer is to a transfer ring */
713#define SCT_SEC_TR 0
714/* Primary stream array type, dequeue pointer is to a transfer ring */
715#define SCT_PRI_TR 1
716/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
717#define SCT_SSA_8 2
718#define SCT_SSA_16 3
719#define SCT_SSA_32 4
720#define SCT_SSA_64 5
721#define SCT_SSA_128 6
722#define SCT_SSA_256 7
723
724/* Assume no secondary streams for now */
725struct xhci_stream_info {
726 struct xhci_ring **stream_rings;
727 /* Number of streams, including stream 0 (which drivers can't use) */
728 unsigned int num_streams;
729 /* The stream context array may be bigger than
730 * the number of streams the driver asked for
731 */
732 struct xhci_stream_ctx *stream_ctx_array;
733 unsigned int num_stream_ctxs;
734 dma_addr_t ctx_array_dma;
735 /* For mapping physical TRB addresses to segments in stream rings */
736 struct radix_tree_root trb_address_map;
737 struct xhci_command *free_streams_command;
738};
739
740#define SMALL_STREAM_ARRAY_SIZE 256
741#define MEDIUM_STREAM_ARRAY_SIZE 1024
742
743struct xhci_virt_ep {
744 struct xhci_ring *ring;
745 /* Related to endpoints that are configured to use stream IDs only */
746 struct xhci_stream_info *stream_info;
747 /* Temporary storage in case the configure endpoint command fails and we
748 * have to restore the device state to the previous state
749 */
750 struct xhci_ring *new_ring;
751 unsigned int ep_state;
752#define SET_DEQ_PENDING (1 << 0)
753#define EP_HALTED (1 << 1) /* For stall handling */
754#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
755/* Transitioning the endpoint to using streams, don't enqueue URBs */
756#define EP_GETTING_STREAMS (1 << 3)
757#define EP_HAS_STREAMS (1 << 4)
758/* Transitioning the endpoint to not using streams, don't enqueue URBs */
759#define EP_GETTING_NO_STREAMS (1 << 5)
760 /* ---- Related to URB cancellation ---- */
761 struct list_head cancelled_td_list;
762 /* The TRB that was last reported in a stopped endpoint ring */
763 union xhci_trb *stopped_trb;
764 struct xhci_td *stopped_td;
765 unsigned int stopped_stream;
766 /* Watchdog timer for stop endpoint command to cancel URBs */
767 struct timer_list stop_cmd_timer;
768 int stop_cmds_pending;
769 struct xhci_hcd *xhci;
770 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
771 * command. We'll need to update the ring's dequeue segment and dequeue
772 * pointer after the command completes.
773 */
774 struct xhci_segment *queued_deq_seg;
775 union xhci_trb *queued_deq_ptr;
776 /*
777 * Sometimes the xHC can not process isochronous endpoint ring quickly
778 * enough, and it will miss some isoc tds on the ring and generate
779 * a Missed Service Error Event.
780 * Set skip flag when receive a Missed Service Error Event and
781 * process the missed tds on the endpoint ring.
782 */
783 bool skip;
784};
785
786#define XHCI_MAX_RINGS_CACHED 31
787
788struct xhci_virt_device {
789 /*
790 * Commands to the hardware are passed an "input context" that
791 * tells the hardware what to change in its data structures.
792 * The hardware will return changes in an "output context" that
793 * software must allocate for the hardware. We need to keep
794 * track of input and output contexts separately because
795 * these commands might fail and we don't trust the hardware.
796 */
797 struct xhci_container_ctx *out_ctx;
798 /* Used for addressing devices and configuration changes */
799 struct xhci_container_ctx *in_ctx;
800 /* Rings saved to ensure old alt settings can be re-instated */
801 struct xhci_ring **ring_cache;
802 int num_rings_cached;
803 struct xhci_virt_ep eps[31];
804 struct completion cmd_completion;
805 /* Status of the last command issued for this device */
806 u32 cmd_status;
807 struct list_head cmd_list;
808};
809
810
811/**
812 * struct xhci_device_context_array
813 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
814 */
815struct xhci_device_context_array {
816 /* 64-bit device addresses; we only write 32-bit addresses */
817 u64 dev_context_ptrs[MAX_HC_SLOTS];
818 /* private xHCD pointers */
819 dma_addr_t dma;
820};
821/* TODO: write function to set the 64-bit device DMA address */
822/*
823 * TODO: change this to be dynamically sized at HC mem init time since the HC
824 * might not be able to handle the maximum number of devices possible.
825 */
826
827
828struct xhci_transfer_event {
829 /* 64-bit buffer address, or immediate data */
830 u64 buffer;
831 u32 transfer_len;
832 /* This field is interpreted differently based on the type of TRB */
833 u32 flags;
834};
835
836struct urb_priv {
837 int length;
838 int td_cnt;
839 struct xhci_td *td[0];
840};
841
842/** Transfer Event bit fields **/
843#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
844#define GET_TRANSFER_LENGTH(p) ((p) & 0xffffff)
845/* Completion Code - only applicable for some types of TRBs */
846#define COMP_CODE_MASK (0xff << 24)
847#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
848#define COMP_SUCCESS 1
849/* Data Buffer Error */
850#define COMP_DB_ERR 2
851/* Babble Detected Error */
852#define COMP_BABBLE 3
853/* USB Transaction Error */
854#define COMP_TX_ERR 4
855/* TRB Error - some TRB field is invalid */
856#define COMP_TRB_ERR 5
857/* Stall Error - USB device is stalled */
858#define COMP_STALL 6
859/* Resource Error - HC doesn't have memory for that device configuration */
860#define COMP_ENOMEM 7
861/* Bandwidth Error - not enough room in schedule for this dev config */
862#define COMP_BW_ERR 8
863/* No Slots Available Error - HC ran out of device slots */
864#define COMP_ENOSLOTS 9
865/* Invalid Stream Type Error */
866#define COMP_STREAM_ERR 10
867/* Slot Not Enabled Error - doorbell rung for disabled device slot */
868#define COMP_EBADSLT 11
869/* Endpoint Not Enabled Error */
870#define COMP_EBADEP 12
871/* Short Packet */
872#define COMP_SHORT_TX 13
873/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
874#define COMP_UNDERRUN 14
875/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
876#define COMP_OVERRUN 15
877/* Virtual Function Event Ring Full Error */
878#define COMP_VF_FULL 16
879/* Parameter Error - Context parameter is invalid */
880#define COMP_EINVAL 17
881/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
882#define COMP_BW_OVER 18
883/* Context State Error - illegal context state transition requested */
884#define COMP_CTX_STATE 19
885/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
886#define COMP_PING_ERR 20
887/* Event Ring is full */
888#define COMP_ER_FULL 21
889/* Missed Service Error - HC couldn't service an isoc ep within interval */
890#define COMP_MISSED_INT 23
891/* Successfully stopped command ring */
892#define COMP_CMD_STOP 24
893/* Successfully aborted current command and stopped command ring */
894#define COMP_CMD_ABORT 25
895/* Stopped - transfer was terminated by a stop endpoint command */
896#define COMP_STOP 26
897/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
898#define COMP_STOP_INVAL 27
899/* Control Abort Error - Debug Capability - control pipe aborted */
900#define COMP_DBG_ABORT 28
901/* TRB type 29 and 30 reserved */
902/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
903#define COMP_BUFF_OVER 31
904/* Event Lost Error - xHC has an "internal event overrun condition" */
905#define COMP_ISSUES 32
906/* Undefined Error - reported when other error codes don't apply */
907#define COMP_UNKNOWN 33
908/* Invalid Stream ID Error */
909#define COMP_STRID_ERR 34
910/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
911/* FIXME - check for this */
912#define COMP_2ND_BW_ERR 35
913/* Split Transaction Error */
914#define COMP_SPLIT_ERR 36
915
916struct xhci_link_trb {
917 /* 64-bit segment pointer*/
918 u64 segment_ptr;
919 u32 intr_target;
920 u32 control;
921};
922
923/* control bitfields */
924#define LINK_TOGGLE (0x1<<1)
925
926/* Command completion event TRB */
927struct xhci_event_cmd {
928 /* Pointer to command TRB, or the value passed by the event data trb */
929 u64 cmd_trb;
930 u32 status;
931 u32 flags;
932};
933
934/* flags bitmasks */
935/* bits 16:23 are the virtual function ID */
936/* bits 24:31 are the slot ID */
937#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
938#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
939
940/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
941#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
942#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
943
944/* Set TR Dequeue Pointer command TRB fields */
945#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
946#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
947
948
949/* Port Status Change Event TRB fields */
950/* Port ID - bits 31:24 */
951#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
952
953/* Normal TRB fields */
954/* transfer_len bitmasks - bits 0:16 */
955#define TRB_LEN(p) ((p) & 0x1ffff)
956/* Interrupter Target - which MSI-X vector to target the completion event at */
957#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
958#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
959
960/* Cycle bit - indicates TRB ownership by HC or HCD */
961#define TRB_CYCLE (1<<0)
962/*
963 * Force next event data TRB to be evaluated before task switch.
964 * Used to pass OS data back after a TD completes.
965 */
966#define TRB_ENT (1<<1)
967/* Interrupt on short packet */
968#define TRB_ISP (1<<2)
969/* Set PCIe no snoop attribute */
970#define TRB_NO_SNOOP (1<<3)
971/* Chain multiple TRBs into a TD */
972#define TRB_CHAIN (1<<4)
973/* Interrupt on completion */
974#define TRB_IOC (1<<5)
975/* The buffer pointer contains immediate data */
976#define TRB_IDT (1<<6)
977
978#define TRB_BEI (1<<9)
979
980/* Control transfer TRB specific fields */
981#define TRB_DIR_IN (1<<16)
982
983/* Isochronous TRB specific fields */
984#define TRB_SIA (1<<31)
985
986struct xhci_generic_trb {
987 u32 field[4];
988};
989
990union xhci_trb {
991 struct xhci_link_trb link;
992 struct xhci_transfer_event trans_event;
993 struct xhci_event_cmd event_cmd;
994 struct xhci_generic_trb generic;
995};
996
997/* TRB bit mask */
998#define TRB_TYPE_BITMASK (0xfc00)
999#define TRB_TYPE(p) ((p) << 10)
1000#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1001/* TRB type IDs */
1002/* bulk, interrupt, isoc scatter/gather, and control data stage */
1003#define TRB_NORMAL 1
1004/* setup stage for control transfers */
1005#define TRB_SETUP 2
1006/* data stage for control transfers */
1007#define TRB_DATA 3
1008/* status stage for control transfers */
1009#define TRB_STATUS 4
1010/* isoc transfers */
1011#define TRB_ISOC 5
1012/* TRB for linking ring segments */
1013#define TRB_LINK 6
1014#define TRB_EVENT_DATA 7
1015/* Transfer Ring No-op (not for the command ring) */
1016#define TRB_TR_NOOP 8
1017/* Command TRBs */
1018/* Enable Slot Command */
1019#define TRB_ENABLE_SLOT 9
1020/* Disable Slot Command */
1021#define TRB_DISABLE_SLOT 10
1022/* Address Device Command */
1023#define TRB_ADDR_DEV 11
1024/* Configure Endpoint Command */
1025#define TRB_CONFIG_EP 12
1026/* Evaluate Context Command */
1027#define TRB_EVAL_CONTEXT 13
1028/* Reset Endpoint Command */
1029#define TRB_RESET_EP 14
1030/* Stop Transfer Ring Command */
1031#define TRB_STOP_RING 15
1032/* Set Transfer Ring Dequeue Pointer Command */
1033#define TRB_SET_DEQ 16
1034/* Reset Device Command */
1035#define TRB_RESET_DEV 17
1036/* Force Event Command (opt) */
1037#define TRB_FORCE_EVENT 18
1038/* Negotiate Bandwidth Command (opt) */
1039#define TRB_NEG_BANDWIDTH 19
1040/* Set Latency Tolerance Value Command (opt) */
1041#define TRB_SET_LT 20
1042/* Get port bandwidth Command */
1043#define TRB_GET_BW 21
1044/* Force Header Command - generate a transaction or link management packet */
1045#define TRB_FORCE_HEADER 22
1046/* No-op Command - not for transfer rings */
1047#define TRB_CMD_NOOP 23
1048/* TRB IDs 24-31 reserved */
1049/* Event TRBS */
1050/* Transfer Event */
1051#define TRB_TRANSFER 32
1052/* Command Completion Event */
1053#define TRB_COMPLETION 33
1054/* Port Status Change Event */
1055#define TRB_PORT_STATUS 34
1056/* Bandwidth Request Event (opt) */
1057#define TRB_BANDWIDTH_EVENT 35
1058/* Doorbell Event (opt) */
1059#define TRB_DOORBELL 36
1060/* Host Controller Event */
1061#define TRB_HC_EVENT 37
1062/* Device Notification Event - device sent function wake notification */
1063#define TRB_DEV_NOTE 38
1064/* MFINDEX Wrap Event - microframe counter wrapped */
1065#define TRB_MFINDEX_WRAP 39
1066/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1067
1068/* Nec vendor-specific command completion event. */
1069#define TRB_NEC_CMD_COMP 48
1070/* Get NEC firmware revision. */
1071#define TRB_NEC_GET_FW 49
1072
1073#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1074#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1075
1076#define TRB_DEV_NOTE_TYEP(p) (((p)>>4) & 0xf)
1077#define TRB_DEV_NOTE_VALUE_LO(p) ((p)>>8)
1078
1079/*
1080 * TRBS_PER_SEGMENT must be a multiple of 4,
1081 * since the command ring is 64-byte aligned.
1082 * It must also be greater than 16.
1083 */
1084#define TRBS_PER_SEGMENT 254
1085/* Allow two commands + a link TRB, along with any reserved command TRBs */
1086#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1087#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1088/* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1089 * Change this if you change TRBS_PER_SEGMENT!
1090 */
1091#define SEGMENT_SHIFT 10
1092/* TRB buffer pointers can't cross 64KB boundaries */
1093#define TRB_MAX_BUFF_SHIFT 16
1094//#define TRB_MAX_BUFF_SHIFT 8
1095#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1096
1097/* mtk scheduler bitmasks */
1098#define BPKTS(p) ((p) & 0x3f)
1099#define BCSCOUNT(p) (((p) & 0x7) << 8)
1100#define BBM(p) ((p) << 11)
1101#define BOFFSET(p) ((p) & 0x3fff)
1102#define BREPEAT(p) (((p) & 0x7fff) << 16)
1103
1104
1105struct xhci_segment {
1106 union xhci_trb *trbs;
1107 /* private to HCD */
1108 struct xhci_segment *next;
1109 dma_addr_t dma;
1110};
1111
1112struct xhci_td {
1113 struct list_head td_list;
1114 struct list_head cancelled_td_list;
1115 struct urb *urb;
1116 struct xhci_segment *start_seg;
1117 union xhci_trb *first_trb;
1118 union xhci_trb *last_trb;
1119};
1120
1121struct xhci_dequeue_state {
1122 struct xhci_segment *new_deq_seg;
1123 union xhci_trb *new_deq_ptr;
1124 int new_cycle_state;
1125};
1126
1127struct xhci_ring {
1128 struct xhci_segment *first_seg;
1129 union xhci_trb *enqueue;
1130 struct xhci_segment *enq_seg;
1131 unsigned int enq_updates;
1132 union xhci_trb *dequeue;
1133 struct xhci_segment *deq_seg;
1134 unsigned int deq_updates;
1135 struct list_head td_list;
1136 /*
1137 * Write the cycle state into the TRB cycle field to give ownership of
1138 * the TRB to the host controller (if we are the producer), or to check
1139 * if we own the TRB (if we are the consumer). See section 4.9.1.
1140 */
1141 u32 cycle_state;
1142 unsigned int stream_id;
1143// spinlock_t lock;
1144};
1145
1146struct xhci_erst_entry {
1147 /* 64-bit event ring segment address */
1148 u64 seg_addr;
1149 u32 seg_size;
1150 /* Set to zero */
1151 u32 rsvd;
1152};
1153
1154struct xhci_erst {
1155 struct xhci_erst_entry *entries;
1156 unsigned int num_entries;
1157 /* xhci->event_ring keeps track of segment dma addresses */
1158 dma_addr_t erst_dma_addr;
1159 /* Num entries the ERST can contain */
1160 unsigned int erst_size;
1161};
1162
1163struct xhci_scratchpad {
1164 u64 *sp_array;
1165 dma_addr_t sp_dma;
1166 void **sp_buffers;
1167 dma_addr_t *sp_dma_buffers;
1168};
1169
1170/*
1171 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1172 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1173 * meaning 64 ring segments.
1174 * Initial allocated size of the ERST, in number of entries */
1175#define ERST_NUM_SEGS 1
1176/* Initial allocated size of the ERST, in number of entries */
1177#define ERST_SIZE 64
1178/* Initial number of event segment rings allocated */
1179#define ERST_ENTRIES 1
1180/* Poll every 60 seconds */
1181#define POLL_TIMEOUT 60
1182/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1183#define XHCI_STOP_EP_CMD_TIMEOUT 5
1184/* XXX: Make these module parameters */
1185
1186
1187/* There is one ehci_hci structure per controller */
1188struct xhci_hcd {
1189 /* glue to PCI and HCD framework */
1190 struct xhci_cap_regs __iomem *cap_regs;
1191 struct xhci_op_regs __iomem *op_regs;
1192 struct xhci_run_regs __iomem *run_regs;
1193 struct xhci_doorbell_array __iomem *dba;
1194 /* Our HCD's current interrupter register set */
1195 struct xhci_intr_reg __iomem *ir_set;
1196
1197 /* Cached register copies of read-only HC data */
1198 __u32 hcs_params1;
1199 __u32 hcs_params2;
1200 __u32 hcs_params3;
1201 __u32 hcc_params;
1202
1203 spinlock_t lock;
1204
1205 /* packed release number */
1206 u8 sbrn;
1207 u16 hci_version;
1208 u8 max_slots;
1209 u8 max_interrupters;
1210 u8 max_ports;
1211 u8 isoc_threshold;
1212 int event_ring_max;
1213 int addr_64;
1214 /* 4KB min, 128MB max */
1215 int page_size;
1216 /* Valid values are 12 to 20, inclusive */
1217 int page_shift;
1218 /* only one MSI vector for now, but might need more later */
1219 int msix_count;
1220 struct msix_entry *msix_entries;
1221 /* data structures */
1222 struct xhci_device_context_array *dcbaa;
1223 struct xhci_ring *cmd_ring;
1224 unsigned int cmd_ring_reserved_trbs;
1225 struct xhci_ring *event_ring;
1226 struct xhci_erst erst;
1227 /* Scratchpad */
1228 struct xhci_scratchpad *scratchpad;
1229
1230 /* slot enabling and address device helpers */
1231 struct completion addr_dev;
1232 int slot_id;
1233 /* Internal mirror of the HW's dcbaa */
1234 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1235
1236 /* DMA pools */
1237 struct dma_pool *device_pool;
1238 struct dma_pool *segment_pool;
1239 struct dma_pool *small_streams_pool;
1240 struct dma_pool *medium_streams_pool;
1241
1242#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1243 /* Poll the rings - for debugging */
1244 struct timer_list event_ring_timer;
1245 int zombie;
1246#endif
1247 /* Host controller watchdog timer structures */
1248 unsigned int xhc_state;
1249/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1250 *
1251 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1252 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1253 * that sees this status (other than the timer that set it) should stop touching
1254 * hardware immediately. Interrupt handlers should return immediately when
1255 * they see this status (any time they drop and re-acquire xhci->lock).
1256 * mtktest_xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1257 * putting the TD on the canceled list, etc.
1258 *
1259 * There are no reports of xHCI host controllers that display this issue.
1260 */
1261#define XHCI_STATE_DYING (1 << 0)
1262 /* Statistics */
1263 int noops_submitted;
1264 int noops_handled;
1265 int error_bitmask;
1266 unsigned int quirks;
1267#define XHCI_LINK_TRB_QUIRK (1 << 0)
1268#define XHCI_RESET_EP_QUIRK (1 << 1)
1269#define XHCI_NEC_HOST (1 << 2)
1270};
1271
1272/* For testing purposes */
1273#define NUM_TEST_NOOPS 0
1274
1275/* convert between an HCD pointer and the corresponding EHCI_HCD */
1276static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1277{
1278 return (struct xhci_hcd *) (hcd->hcd_priv);
1279}
1280
1281static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1282{
1283 return container_of((void *) xhci, struct usb_hcd, hcd_priv);
1284}
1285
1286#define XHCI_DEBUG 0
1287
1288#define xhci_dbg(xhci, fmt, args...) \
1289 do { if (XHCI_DEBUG) printk( KERN_ERR "%s(%d):" fmt, __func__, __LINE__, ##args); } while (0)
1290#define xhci_info(xhci, fmt, args...) \
1291 do { if (XHCI_DEBUG) printk( KERN_ERR "%s(%d):" fmt, __func__, __LINE__, ##args); } while (0)
1292#define xhci_err(xhci, fmt, args...) \
1293 do { printk( KERN_ERR "%s(%d):" fmt, __func__, __LINE__, ##args); } while (0)
1294#define xhci_warn(xhci, fmt, args...) \
1295 do { if (1) printk( KERN_ERR fmt, ##args); } while (0)
1296
1297
1298#if 0
1299#define xhci_dbg(xhci, fmt, args...) \
1300 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1301#define xhci_info(xhci, fmt, args...) \
1302 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1303#define xhci_err(xhci, fmt, args...) \
1304 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1305#define xhci_warn(xhci, fmt, args...) \
1306 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1307#endif
1308/* TODO: copied from ehci.h - can be refactored? */
1309/* xHCI spec says all registers are little endian */
1310static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1311 __u32 __iomem *regs)
1312{
1313 return readl(regs);
1314}
1315static inline void xhci_writel(struct xhci_hcd *xhci,
1316 const unsigned int val, __u32 __iomem *regs)
1317{
1318 #if 0
1319 xhci_dbg(xhci,
1320 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1321 regs, val);
1322 #endif
1323 writel(val, regs);
1324}
1325
1326/*
1327 * Registers should always be accessed with double word or quad word accesses.
1328 *
1329 * Some xHCI implementations may support 64-bit address pointers. Registers
1330 * with 64-bit address pointers should be written to with dword accesses by
1331 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1332 * xHCI implementations that do not support 64-bit address pointers will ignore
1333 * the high dword, and write order is irrelevant.
1334 */
1335static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1336 __u64 __iomem *regs)
1337{
1338 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1339 u64 val_lo = readl(ptr);
1340 u64 val_hi = readl(ptr + 1);
1341 return val_lo + (val_hi << 32);
1342}
1343static inline void xhci_write_64(struct xhci_hcd *xhci,
1344 const u64 val, __u64 __iomem *regs)
1345{
1346 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1347 u32 val_lo = lower_32_bits(val);
1348 u32 val_hi = upper_32_bits(val);
1349
1350 xhci_dbg(xhci,
1351 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1352 regs, (long unsigned int) val);
1353 writel(val_lo, ptr);
1354 writel(val_hi, ptr + 1);
1355}
1356
1357static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1358{
1359 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1360 return ((HC_VERSION(temp) == 0x95) &&
1361 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1362}
1363
1364/* xHCI debugging */
1365void mtktest_xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
1366void mtktest_xhci_print_registers(struct xhci_hcd *xhci);
1367void mtktest_xhci_dbg_regs(struct xhci_hcd *xhci);
1368void mtktest_xhci_print_run_regs(struct xhci_hcd *xhci);
1369void mtktest_xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1370void mtktest_xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1371void mtktest_xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1372void mtktest_xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1373void mtktest_xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1374void mtktest_xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1375void mtktest_xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1376void mtktest_xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1377void mtktest_mtk_xhci_dbg_ctx(struct xhci_hcd *xhci,
1378 struct xhci_container_ctx *ctx,
1379 unsigned int last_ep);
1380char *mtktest_xhci_get_slot_state(struct xhci_hcd *xhci,
1381 struct xhci_container_ctx *ctx);
1382void mtktest_xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1383 unsigned int slot_id, unsigned int ep_index,
1384 struct xhci_virt_ep *ep);
1385
1386/* xHCI memory management */
1387void mtktest_xhci_mem_cleanup(struct xhci_hcd *xhci);
1388int mtktest_xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1389void mtktest_xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1390int mtktest_xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1391int mtktest_xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1392void mtktest_xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1393 struct usb_device *udev);
1394unsigned int mtktest_xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1395unsigned int mtktest_xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1396unsigned int mtktest_xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1397unsigned int mtktest_xhci_last_valid_endpoint(u32 added_ctxs);
1398void mtktest_xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1399void mtktest_xhci_endpoint_copy(struct xhci_hcd *xhci,
1400 struct xhci_container_ctx *in_ctx,
1401 struct xhci_container_ctx *out_ctx,
1402 unsigned int ep_index);
1403void mtktest_xhci_slot_copy(struct xhci_hcd *xhci,
1404 struct xhci_container_ctx *in_ctx,
1405 struct xhci_container_ctx *out_ctx);
1406int mtktest_xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1407 struct usb_device *udev, struct usb_host_endpoint *ep,
1408 gfp_t mem_flags);
1409void mtktest_xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1410void mtktest_xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1411 struct xhci_virt_device *virt_dev,
1412 unsigned int ep_index);
1413struct xhci_stream_info *mtktest_xhci_alloc_stream_info(struct xhci_hcd *xhci,
1414 unsigned int num_stream_ctxs,
1415 unsigned int num_streams, gfp_t flags);
1416void mtktest_xhci_free_stream_info(struct xhci_hcd *xhci,
1417 struct xhci_stream_info *stream_info);
1418void mtktest_xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1419 struct xhci_ep_ctx *ep_ctx,
1420 struct xhci_stream_info *stream_info);
1421void mtktest_xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1422 struct xhci_ep_ctx *ep_ctx,
1423 struct xhci_virt_ep *ep);
1424struct xhci_ring *mtktest_xhci_dma_to_transfer_ring(
1425 struct xhci_virt_ep *ep,
1426 u64 address);
1427struct xhci_ring *mtktest_xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1428 struct urb *urb);
1429struct xhci_ring *mtktest_xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1430 unsigned int slot_id, unsigned int ep_index,
1431 unsigned int stream_id);
1432struct xhci_ring *mtktest_xhci_stream_id_to_ring(
1433 struct xhci_virt_device *dev,
1434 unsigned int ep_index,
1435 unsigned int stream_id);
1436struct xhci_command *mtktest_xhci_alloc_command(struct xhci_hcd *xhci,
1437 bool allocate_in_ctx, bool allocate_completion,
1438 gfp_t mem_flags);
1439void mtktest_xhci_free_command(struct xhci_hcd *xhci,
1440 struct xhci_command *command);
1441void mtktest_xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1442
1443irqreturn_t mtktest_xhci_mtk_irq(struct usb_hcd *hcd);
1444//int xhci_mtk_pci_setup(struct usb_hcd *hcd);
1445int mtktest_xhci_mtk_run(struct usb_hcd *hcd);
1446void mtktest_xhci_mtk_stop(struct usb_hcd *hcd);
1447void mtktest_xhci_mtk_shutdown(struct usb_hcd *hcd);
1448int mtktest_xhci_mtk_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1449int mtktest_xhci_mtk_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1450int mtktest_xhci_mtk_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1451void mtktest_xhci_mtk_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1452int mtktest_xhci_mtk_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev
1453 , struct usb_host_endpoint **eps, unsigned int num_eps,
1454 unsigned int num_streams, gfp_t mem_flags);
1455int mtktest_xhci_mtk_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1456 struct usb_host_endpoint **eps, unsigned int num_eps,
1457 gfp_t mem_flags);
1458int mtktest_xhci_mtk_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1459int mtktest_xhci_mtk_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1460void mtktest_xhci_mtk_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1461int mtktest_xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1462void mtktest_xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1463int mtktest_xhci_mtk_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1464int mtktest_xhci_mtk_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1465 struct usb_tt *tt, gfp_t mem_flags);
1466int mtktest_xhci_mtk_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1467int mtktest_xhci_mtk_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1468 u16 wIndex, char *buf, u16 wLength);
1469int mtktest_xhci_mtk_hub_status_data(struct usb_hcd *hcd, char *buf);
1470int mtktest_xhci_mtk_get_frame(struct usb_hcd *hcd);
1471
1472void mtktest_xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev);
1473//int xhci_register_pci(void);
1474//void xhci_unregister_pci(void);
1475
1476
1477/* xHCI host controller glue */
1478void mtktest_xhci_quiesce(struct xhci_hcd *xhci);
1479int mtktest_xhci_halt(struct xhci_hcd *xhci);
1480int mtktest_xhci_reset(struct xhci_hcd *xhci);
1481int mtktest_xhci_init(struct usb_hcd *hcd);
1482int mtktest_xhci_run(struct usb_hcd *hcd);
1483void mtktest_xhci_stop(struct usb_hcd *hcd);
1484void mtktest_xhci_shutdown(struct usb_hcd *hcd);
1485int mtktest_xhci_get_frame(struct usb_hcd *hcd);
1486irqreturn_t mtktest_xhci_irq(struct usb_hcd *hcd);
1487int mtktest_xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1488void mtktest_xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1489int mtktest_xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1490 struct usb_host_endpoint **eps, unsigned int num_eps,
1491 unsigned int num_streams, gfp_t mem_flags);
1492int mtktest_xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1493 struct usb_host_endpoint **eps, unsigned int num_eps,
1494 gfp_t mem_flags);
1495int mtktest_xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1496int mtktest_xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1497 struct usb_tt *tt, gfp_t mem_flags);
1498int mtktest_xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1499int mtktest_xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1500int mtktest_xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1501int mtktest_xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1502void mtktest_xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1503int mtktest_xhci_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1504int mtktest_xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1505void mtktest_xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1506
1507/* xHCI ring, segment, TRB, and TD functions */
1508dma_addr_t mtktest_xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1509struct xhci_segment *mtktest_trb_in_td(struct xhci_segment *start_seg,
1510 union xhci_trb *start_trb, union xhci_trb *end_trb,
1511 dma_addr_t suspect_dma);
1512int mtktest_xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1513void mtktest_xhci_ring_cmd_db(struct xhci_hcd *xhci);
1514void *mtktest_xhci_setup_one_noop(struct xhci_hcd *xhci);
1515void *mtktest_mtk_xhci_setup_one_noop(struct xhci_hcd *xhci);
1516int mtktest_xhci_handle_event(struct xhci_hcd *xhci);
1517void mtktest_xhci_set_hc_event_deq(struct xhci_hcd *xhci);
1518int mtktest_xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1519int mtktest_xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1520 u32 slot_id, char isBSR);
1521int mtktest_xhci_queue_vendor_command(struct xhci_hcd *xhci,
1522 u32 field1, u32 field2, u32 field3, u32 field4);
1523int mtktest_xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1524 unsigned int ep_index);
1525int mtktest_xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1526 int slot_id, unsigned int ep_index);
1527int mtktest_xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1528 int slot_id, unsigned int ep_index);
1529int mtktest_xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1530 int slot_id, unsigned int ep_index);
1531int mtktest_xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1532 struct urb *urb, int slot_id, unsigned int ep_index);
1533int mtktest_xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1534 u32 slot_id, bool command_must_succeed);
1535int mtktest_xhci_queue_deconfigure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1536 u32 slot_id, bool command_must_succeed);
1537int mtktest_xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1538 u32 slot_id);
1539int mtktest_xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1540 unsigned int ep_index);
1541int mtktest_xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1542void mtktest_xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1543 unsigned int slot_id, unsigned int ep_index,
1544 unsigned int stream_id, struct xhci_td *cur_td,
1545 struct xhci_dequeue_state *state);
1546void mtktest_xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1547 unsigned int slot_id, unsigned int ep_index,
1548 unsigned int stream_id,
1549 struct xhci_dequeue_state *deq_state);
1550void mtktest_xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1551 struct usb_device *udev, unsigned int ep_index);
1552void mtktest_xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1553 unsigned int slot_id, unsigned int ep_index,
1554 struct xhci_dequeue_state *deq_state);
1555void mtktest_xhci_stop_endpoint_command_watchdog(unsigned long arg);
1556/* xHCI roothub code */
1557u32 mtktest_xhci_port_state_to_clear_change(u32 state);
1558int mtktest_xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1559 char *buf, u16 wLength);
1560//int mtktest_xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1561/* xHCI contexts */
1562struct xhci_input_control_ctx *mtktest_xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1563struct xhci_slot_ctx *mtktest_xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1564 struct xhci_ep_ctx *mtktest_xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1565
1566void mtktest_inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer);
1567
1568void mtktest_xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1569void mtktest_xhci_dbg_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1570struct xhci_segment *mtktest_xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags);
1571void mtktest_xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
1572 struct xhci_segment *next, bool link_trbs);
1573void mtktest_xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg);
1574unsigned int mtktest_xhci_port_speed(unsigned int port_status);
1575u32 mtktest_xhci_port_state_to_neutral(u32 state);
1576
1577void mtktest_setInitialReg(void);
1578
1579/* TRB MISC fields */
1580#define ADDRESS_TRB_BSR (1<<9)
1581#define CONFIG_EP_TRB_DC (1<<9)
1582#endif /* __LINUX_XHCI_HCD_H */
kernel source for telekom puls (alcatel/mediatek)