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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / xhci_test / mtk-test-lib.h
CommitLineData
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S		 1#ifndef __MTK_TEST_LIB_H
2#define __MTK_TEST_LIB_H
3#include "mtk-usb-hcd.h"
4#include <linux/mu3phy/mtk-phy.h>
5
6#define KERNEL_30 1 //if port to Linux 3.0, enable this
7#define TEST_OTG 1
8
9extern void __iomem *xhci_usbif_base;
10extern void __iomem *xhci_usbif_sif_base;
11extern int xhci_usbif_nirq;
12#define USB_XHCI_COMPATIBLE_NAME "mediatek,USB3_XHCI"
13
14#define SSUSB_U3_BASE xhci_usbif_base
15#define SSUSB_U3_XHCI_BASE SSUSB_U3_BASE
16#define SSUSB_U3_MAC_BASE (SSUSB_U3_BASE + 0x2400) /* U3 MAC */
17#define SSUSB_U3_SYS_BASE (SSUSB_U3_BASE + 0x2600) /* U3 sys */
18#define SSUSB_U2_SYS_BASE (SSUSB_U3_BASE + 0x3400) /* U2 MAC + SYS */
19 /* ref doc ssusb_xHCI_exclude_port_csr.xlsx */
20#define SSUSB_XHCI_EXCLUDE_BASE (SSUSB_U3_BASE + 0x900)
21
22#define SIFSLV_IPPC (xhci_usbif_sif_base + 0x700)
23
24#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
25#define U3_PIPE_LATCH_TX 0
26#define U3_PIPE_LATCH_RX 0
27
28#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
29#define U3_REF_CK_PAR 0xb0
30#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
31
32#define U3_RX_UX_EXIT_LFPS_REF 3 // 10MHz:3, 20MHz: 6, 25MHz: 8, 27MHz: 9, 50MHz: 15, 100MHz: 30
33#define U3_REF_CK_VAL 10 //MHz = value
34
35#define U3_TIMING_PULSE_CTRL 0xb4
36#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
37
38#define USB20_TIMING_PARAMETER 0x40
39#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
40#define USB20_LPM_ENTRY_COUNT (SSUSB_U2_SYS_BASE + 0x48)
41
42#define LINK_PM_TIMER 0x8
43#define PM_LC_TIMEOUT_VALUE 3
44
45 /* ref doc ssusb_xHCI_exclude_port_csr.xlsx */
46#define SSUSB_XHCI_HDMA_CFG (SSUSB_XHCI_EXCLUDE_BASE + 0x50)
47#define SSUSB_XHCI_U2PORT_CFG (SSUSB_XHCI_EXCLUDE_BASE + 0x78)
48#define SSUSB_XHCI_HSCH_CFG2 (SSUSB_XHCI_EXCLUDE_BASE + 0x7c)
49
50#define SSUSB_XHCI_ACTIVE_MASK 0x1f1f
51
52/******** Defined for PHY calibration ************/
53
54#define U3_CNR (1<<11)
55#define U3_PLS_OFFSET 5
56#define U3_P1_SC (SSUSB_U3_XHCI_BASE+0x420) //0xf0040420
57#define U3_P1_PMSC (SSUSB_U3_XHCI_BASE+0x424) //0xf0040424
58#define U3_P1_LTSSM (SSUSB_U3_MAC_BASE+0x134) //0xf0042534
59#define U3_LINK_ERR_COUNT (SSUSB_U3_SYS_BASE+0x14) //0xf0042614
60#define U3_RECOVERY_COUNT (SSUSB_U3_SYS_BASE+0xd8) //0xf00426d8
61#define U3_XHCI_CMD_ADDR (SSUSB_U3_XHCI_BASE+0x20)
62#define U3_XHCI_STS_ADDR (SSUSB_U3_XHCI_BASE+0x24)
63
64#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
65#define SSUSB_IP_SW_RST (1<<0)
66#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
67#define SSUSB_IP_PDN (1<<0)
68#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
69#define SSUSB_U3_PORT_DIS (1<<0)
70#define SSUSB_U3_PORT_PDN (1<<1)
71#define SSUSB_U3_PORT_HOST_SEL (1<<2)
72#define SSUSB_U3_PORT_CKBG_EN (1<<3)
73#define SSUSB_U3_PORT_MAC_RST (1<<4)
74#define SSUSB_U3_PORT_PHYD_RST (1<<5)
75#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
76#define SSUSB_U2_PORT_DIS (1<<0)
77#define SSUSB_U2_PORT_PDN (1<<1)
78#define SSUSB_U2_PORT_HOST_SEL (1<<2)
79#define SSUSB_U2_PORT_CKBG_EN (1<<3)
80#define SSUSB_U2_PORT_MAC_RST (1<<4)
81#define SSUSB_U2_PORT_PHYD_RST (1<<5)
82#define SSUSB_U2_PORT_OTG_HOST_VBUSVALID_SEL (1<<9)
83#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
84
85
86#define SSUSB_XHCI_RST_CTRL (SIFSLV_IPPC+0x0094)
87#define SSUSB_XHCI_SW_RST (0x1<<0) //0:0
88
89
90#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
91#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
92/***************************************************/
93/******* Defined for OTG usage ********************************************/
94#define SSUSB_OTG_STS (SIFSLV_IPPC+0x18)
95#define SSUSB_ATTACH_A_ROLE (1<<0)
96#define SSUSB_CHG_A_ROLE_A (1<<1)
97#define SSUSB_CHG_B_ROLE_A (1<<2)
98#define SSUSB_ATTACH_B_ROLE (1<<3)
99#define SSUSB_CHG_A_ROLE_B (1<<4)
100#define SSUSB_CHG_B_ROLE_B (1<<5)
101#define VBUS_CHG_INTR (1<<6)
102#define SSUSB_DEV_USBRST_INTR (1<<7)
103#define SSUSB_HOST_DEV_MODE (1<<8)
104#define SSUSB_VBUS_VALID (1<<9)
105#define SSUSB_IDDIG (1<<10)
106#define SSUSB_SRP_REQ_INTR (1<<11)
107#define SSUSB_DEV_DMA_REQ (1<<13)
108#define SSUSB_XHCI_MAS_DMA_REQ (1<<14)
109
110#define SSUSB_OTG_STS_CLR (SIFSLV_IPPC+0x1c)
111#define SSUSB_ATTACH_A_ROLE_CLR (1<<0)
112#define SSUSB_CHG_A_ROLE_A_CLR (1<<1)
113#define SSUSB_CHG_B_ROLE_A_CLR (1<<2)
114#define SSUSB_ATTACH_B_ROLE_CLR (1<<3)
115#define SSUSB_CHG_A_ROLE_B_CLR (1<<4)
116#define SSUSB_CHG_B_ROLE_B_CLR (1<<5)
117#define SSUSB_VBUS_INTR_CLR (1<<6)
118#define SSUSB_DEV_USBRST_INTR_CLR (1<<7)
119#define SSUSB_SRP_REQ_INTR_CLR (1<<11)
120
121#define SSUSB_OTG_INT_EN (SIFSLV_IPPC+0x2c)
122#define SSUSB_ATTACH_A_ROLE_INT_EN (1<<0)
123#define SSUSB_CHG_A_ROLE_A_INT_EN (1<<1)
124#define SSUSB_CHG_B_ROLE_A_INT_EN (1<<2)
125#define SSUSB_ATTACH_B_ROLE_INT_EN (1<<3)
126#define SSUSB_CHG_A_ROLE_B_INT_EN (1<<4)
127#define SSUSB_CHG_B_ROLE_B_INT_EN (1<<5)
128#define SSUSB_VBUS_CHG_INT_B_EN (1<<6)
129#define SSUSB_VBUS_CHG_INT_A_EN (1<<7)
130#define SSUSB_DEV_USBRST_INT_EN (1<<8)
131#define SSUSB_SRP_REQ_INTR_EN (1<<11)
132
133#define SSUSB_CSR_CK_CTRL (SIFSLV_IPPC+0x88)
134#define SSUSB_SIFSLV_MCU_BUS_CK_GATE_EN (1<<1)
135
136#define SSUSB_U2_PORT_OTG_SEL (1<<7)
137#define SSUSB_U2_PORT_OTG_MAC_AUTO_SEL (1<<8)
138#define SSUSB_U2_PORT_OTG_HOST_VBUSVALID_SEL (1<<9)
139
140#define DEVICE_CONTROL (SSUSB_U2_SYS_BASE+0xc)
141#define DEVICE_CONTROL_session (1<<0)
142#define DEVICE_CONTROL_hostreq (1<<1)
143#define DEVICE_CONTROL_vbus (3<<3)
144#define DEVICE_CONTROL_b_dev (1<<7)
145
146#define POWER_MANAGEMENT (SSUSB_U2_SYS_BASE+04)
147#define HS_ENABLE (1<<5)
148
149
150#define USB2_TEST_MODE (SSUSB_U2_SYS_BASE+014)
151#define USB2_TEST_NAK_MODE (1<<0)
152#define USB2_TEST_J (1<<1)
153#define USB2_TEST_K (1<<2)
154#define USB2_TEST_PACKET (1<<3)
155#define USB2_FORCE_HS (1<<4)
156#define USB2_FORCE_FS (1<<5)
157#define USB2_FORCE_HOST (1<<7)
158
159
160
161
162
163/****************************************************************/
164
165struct ixia_dev
166{
167 struct usb_device *udev;
168 int ep_out;
169 int ep_in;
170};
171
172int f_enable_port(int index);
173int f_disconnect_port(int index);
174int f_enable_slot(struct usb_device *dev);
175int f_disable_slot();
176int f_address_slot(char isBSR, struct usb_device *dev);
177int f_slot_reset_device(int slot_id, char isWarmReset);
178int f_udev_add_ep(struct usb_host_endpoint *ep, struct usb_device *udev);
179int f_xhci_config_ep(struct usb_device *udev);
180int f_evaluate_context(int max_exit_latency, int maxp0, int preping_mode, int preping, int besl, int besld);
181
182int f_power_suspend();
183int f_power_resume();
184int f_power_remotewakeup();
185int f_power_set_u1u2(int u_num, int value1, int value2);
186int f_power_send_fla(int value);
187
188int f_ring_stop_cmd();
189int f_ring_abort_cmd();
190int f_ring_enlarge(int ep_dir, int ep_num, int dev_num);
191int f_ring_stop_ep(int slot_id, int ep_index);
192int f_ring_set_tr_dequeue_pointer(int slot_id, int ep_index, struct urb *urb);
193
194int f_hub_setportfeature(int hdev_num, int wValue, int wIndex);
195int f_hub_clearportfeature(int hdev_num, int wValue, int wIndex);
196int f_hub_sethubfeature(int hdev_num, int wValue);
197int f_hub_config_subhub(int parent_hub_num, int hub_num, int port_num);
198int f_hub_configep(int hdev_num, int rh_port_index);
199int f_hub_configuredevice(int hub_num, int port_num, int dev_num
200 , int transfer_type, int maxp, int bInterval, char is_config_ep, char is_stress, int stress_config);
201int f_hub_reset_dev(struct usb_device *udev,int dev_num, int port_num, int speed);
202int f_hub_configure_eth_device(int hub_num, int port_num, int dev_num);
203
204int f_random_stop(int ep_1_num, int ep_2_num, int stop_count_1, int stop_count_2, int urb_dir_1, int urb_dir_2, int length);
205int f_add_random_stop_ep_thread(struct xhci_hcd *xhci, int slot_id, int ep_index);
206int f_add_random_ring_doorbell_thread(struct xhci_hcd *xhci, int slot_id, int ep_index);
207int f_config_ep(char ep_num,int ep_dir,int transfer_type, int maxp,int bInterval, int burst, int mult, struct usb_device *udev,int config_xhci);
208int f_deconfig_ep(char is_all, char ep_num,int ep_dir,struct usb_device *usbdev,int config_xhci);
209int f_add_str_threads(int dev_num, int ep_num, int maxp, char isCompare, struct usb_device *usbdev, char isEP0);
210int f_add_ixia_thread(struct xhci_hcd *xhci, int dev_num, struct ixia_dev *ix_dev);
211int f_fill_urb(struct urb *urb,int ep_num,int data_length, int start_add,int dir, int iso_num_packets, int psize, struct usb_device *usbdev);
212int f_fill_urb_with_buffer(struct urb *urb,int ep_num,int data_length,void *buffer,int start_add,int dir, int iso_num_packets, int psize
213 , dma_addr_t dma_mapping, struct usb_device *usbdev);
214int f_queue_urb(struct urb *urb,int wait, struct usb_device *dev);
215int f_update_hub_device(struct usb_device *udev, int num_ports);
216
217int f_loopback_loop(int ep_out, int ep_in, int data_length, int start_add, struct usb_device *usbdev);
218int f_loopback_sg_loop(int ep_out, int ep_in, int data_length, int start_add, int sg_len, struct usb_device *usbdev);
219int f_loopback_loop_gpd(int ep_out, int ep_in, int data_length, int start_add, int gpd_length, struct usb_device *usbdev);
220int f_loopback_sg_loop_gpd(int ep_out, int ep_in, int data_length, int start_add, int sg_len, int gpd_length, struct usb_device *usbdev);
221
222int mtk_xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
223 u32 mask, u32 done, int msec);
224
225int otg_dev_A_host_thread(void *data);
226int otg_dev_B_hnp(void * data);
227int otg_dev_A_hnp(void * data);
228int otg_dev_A_hnp_back(void * data);
229int otg_dev_B_hnp_back(void *data);
230int otg_dev_A_srp(void * data);
231int otg_opt_uut_a(void *data);
232int otg_opt_uut_b(void *data);
233int otg_pet_uut_a(void *data);
234int otg_pet_uut_b(void *data);
235
236int f_test_lib_init();
237int f_test_lib_cleanup();
238
239int f_drv_vbus();
240int f_stop_vbus();
241
242struct urb *alloc_ctrl_urb(struct usb_ctrlrequest *dr, char *buffer, struct usb_device *udev);
243int f_ctrlrequest(struct urb *urb, struct usb_device *udev);
244
245int get_port_index(int port_id);
246void print_speed(int speed);
247int wait_event_on_timeout(int *ptr, int done, int msecs);
248//int poll_event_on_timeout(int *ptr, int done, int msecs);
249
250void start_port_reenabled(int index, int speed);
251int f_reenable_port(int index);
252
253int f_enable_dev_note();
254
255int f_add_rdn_len_str_threads(int dev_num, int ep_num, int maxp, char isCompare, struct usb_device *usbdev, char isEP0);
256int f_add_random_access_reg_thread(struct xhci_hcd *xhci, int port_id, int port_rev
257 , int power_required);
258int f_power_reset_u1u2_counter(int u_num);
259int f_power_get_u1u2_counter(int u_num);
260int f_power_config_lpm(u32 slot_id, u32 hirdm, u32 L1_timeout, u32 rwe, u32 besl, u32 besld, u32 hle
261 , u32 int_nak_active, u32 bulk_nyet_active);
262int f_power_reset_L1_counter(int direct);
263int f_power_get_L1_counter(int direct);
264int f_port_set_pls(int port_id, int pls);
265int f_ctrlrequest_nowait(struct urb *urb, struct usb_device *udev);
266
267int f_host_test_mode(int case_num) ;
268
269int f_host_test_mode_stop() ;
270
271int wait_not_event_on_timeout(int *ptr, int value, int msecs);
272
273/* IP configuration */
274#define RH_PORT_NUM 2
275#define DEV_NUM 4
276#define HUB_DEV_NUM 4
277
278/* constant define */
279#define MAX_DATA_LENGTH 65535
280
281/* timeout */
282#define ATTACH_TIMEOUT 20000
283#define CMD_TIMEOUT 80
284#define TRANS_TIMEOUT 100
285#define SYNC_DELAY 100
286
287/* return code */
288#define RET_SUCCESS 0
289#define RET_FAIL 1
290
291/* command stage */
292#define CMD_RUNNING 0
293#define CMD_DONE 1
294#define CMD_FAIL 2
295
296/* transfer stage */
297#define TRANS_INPROGRESS 0
298#define TRANS_DONE 1
299
300/* loopback stage */
301#define LOOPBACK_OUT 0
302#define LOOPBACK_IN 1
303
304/* USB spec constant */
305/* EP descriptor */
306#define EPADD_NUM(n) ((n)<<0)
307#define EPADD_OUT 0
308#define EPADD_IN (1<<7)
309
310#define EPATT_CTRL 0
311#define EPATT_ISO 1
312#define EPATT_BULK 2
313#define EPATT_INT 3
314
315#define MAX_DATA_LENGTH 65535
316
317/* control request code */
318#define REQ_GET_STATUS 0
319#define REQ_SET_FEATURE 3
320#define REQ_CLEAR_FEATURE 1
321
322/* hub request code */
323#define HUB_FEATURE_PORT_POWER 8
324#define HUB_FEATURE_PORT_RESET 4
325#define HUB_FEATURE_PORT_SUSPEND 2
326#define HUB_FEATURE_C_PORT_CONNECTION 16
327#define HUB_FEATURE_C_PORT_RESET 20
328
329#define HUB_FEATURE_PORT_LINK_STATE 5
330
331/*macro for USB-IF for OTG driver*/
332#define OTG_CMD_E_ENABLE_VBUS 0x00
333#define OTG_CMD_E_ENABLE_SRP 0x01
334#define OTG_CMD_E_START_DET_SRP 0x02
335#define OTG_CMD_E_START_DET_VBUS 0x03
336#define OTG_CMD_P_A_UUT 0x04
337#define OTG_CMD_P_B_UUT 0x05
338#define HOST_CMD_TEST_SE0_NAK 0x6
339#define HOST_CMD_TEST_J 0x7
340#define HOST_CMD_TEST_K 0x8
341#define HOST_CMD_TEST_PACKET 0x9
342#define HOST_CMD_SUSPEND_RESUME 0xa
343#define HOST_CMD_GET_DESCRIPTOR 0xb
344#define HOST_CMD_SET_FEATURE 0xc
345#define OTG_CMD_P_B_UUT_TD59 0xd
346#define HOST_CMD_ENV_INIT 0xe
347#define HOST_CMD_ENV_EXIT 0xf
348
349/* global structure */
350typedef enum
351{
352 DISCONNECTED = 0,
353 CONNECTED,
354 RESET,
355 ENABLED
356}XHCI_PORT_STATUS;
357
358struct xhci_port
359{
360 int port_id;
361 XHCI_PORT_STATUS port_status;
362 int port_speed;
363 int port_reenabled;
364};
365
366/* for stress test */
367#define TOTAL_URB 30
368#define URB_STATUS_IDLE 150
369#define URB_STATUS_RX 151
370#define GPD_LENGTH (16*1024)
371#define GPD_LENGTH_RDN (10*1024)
372
373/* global parameters */
374#ifdef MTK_TEST_LIB
375#define AUTOEXT
376#else
377#define AUTOEXT extern
378#endif
379AUTOEXT volatile int g_port_connect;
380AUTOEXT volatile int g_port_reset;
381AUTOEXT volatile int g_port_id;
382AUTOEXT volatile int g_slot_id;
383AUTOEXT volatile int g_speed;
384AUTOEXT volatile int g_cmd_status;
385AUTOEXT volatile char g_event_full;
386AUTOEXT volatile char g_got_event_full;
387AUTOEXT volatile int g_device_reconnect;
388AUTOEXT struct usb_device *dev_list[DEV_NUM];
389AUTOEXT struct usb_device *hdev_list[HUB_DEV_NUM];
390AUTOEXT struct usb_hcd *my_hcd;
391AUTOEXT struct xhci_port *rh_port[RH_PORT_NUM];
392AUTOEXT volatile int g_stress_status;
393AUTOEXT struct ixia_dev *ix_dev_list[4];
394AUTOEXT volatile char g_exec_done;
395AUTOEXT volatile char g_stopped;
396AUTOEXT volatile char g_correct;
397AUTOEXT volatile int g_dev_notification;
398AUTOEXT volatile long g_dev_not_value;
399AUTOEXT volatile long g_intr_handled;
400AUTOEXT volatile int g_mfindex_event;
401AUTOEXT volatile char g_port_occ;
402AUTOEXT volatile char g_is_bei;
403AUTOEXT volatile char g_td_to_noop;
404AUTOEXT volatile char g_iso_frame;
405AUTOEXT volatile char g_test_random_stop_ep;
406AUTOEXT volatile char g_stopping_ep;
407AUTOEXT volatile char g_port_resume;
408AUTOEXT volatile int g_cmd_ring_pointer1;
409AUTOEXT volatile int g_cmd_ring_pointer2;
410AUTOEXT volatile char g_idt_transfer;
411AUTOEXT volatile char g_port_plc;
412AUTOEXT volatile char g_power_down_allowed;
413AUTOEXT volatile char g_hs_block_reset;
414AUTOEXT volatile char g_concurrent_resume;
415AUTOEXT volatile int g_otg_test;
416AUTOEXT volatile int g_otg_dev_B;
417AUTOEXT volatile int g_otg_hnp_become_host;
418AUTOEXT volatile int g_otg_hnp_become_dev;
419AUTOEXT volatile int g_otg_srp_pend;
420AUTOEXT volatile int g_otg_pet_status;
421AUTOEXT volatile int g_otg_csc;
422AUTOEXT volatile int g_otg_iddig;
423AUTOEXT volatile int g_otg_wait_con;
424AUTOEXT volatile int g_otg_dev_conf_len;
425AUTOEXT volatile int g_otg_unsupported_dev;
426AUTOEXT volatile int g_otg_slot_enabled;
427AUTOEXT volatile int g_otg_iddig_toggled;
428typedef enum
429{
430 OTG_DISCONNECTED = 0,
431 OTG_POLLING_STATUS,
432 OTG_SET_NHP,
433 OTG_HNP_INIT,
434 OTG_HNP_SUSPEND,
435 OTG_HNP_DEV,
436 OTG_HNP_DISCONNECTED,
437 OTG_DEV
438
439}PET_STATUS;
440
441
442// Billionton Definition
443#define AX_CMD_SET_SW_MII 0x06
444#define AX_CMD_READ_MII_REG 0x07
445#define AX_CMD_WRITE_MII_REG 0x08
446#define AX_CMD_READ_MII_OPERATION_MODE 0x09
447#define AX_CMD_SET_HW_MII 0x0a
448#define AX_CMD_READ_EEPROM 0x0b
449#define AX_CMD_WRITE_EEPROM 0x0c
450#define AX_CMD_READ_RX_CONTROL_REG 0x0f
451#define AX_CMD_WRITE_RX_CTL 0x10
452#define AX_CMD_READ_IPG012 0x11
453#define AX_CMD_WRITE_IPG0 0x12
454#define AX_CMD_WRITE_IPG1 0x13
455#define AX_CMD_WRITE_IPG2 0x14
456#define AX_CMD_READ_MULTIFILTER_ARRAY 0x15
457#define AX_CMD_WRITE_MULTI_FILTER 0x16
458#define AX_CMD_READ_NODE_ID 0x17
459#define AX_CMD_READ_PHY_ID 0x19
460#define AX_CMD_READ_MEDIUM_MODE 0x1a
461#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
462#define AX_CMD_READ_MONITOR_MODE 0x1c
463#define AX_CMD_WRITE_MONITOR_MODE 0x1d
464#define AX_CMD_READ_GPIOS 0x1e
465#define AX_CMD_WRITE_GPIOS 0x1f
466
467#define AX_CMD_GUSBKR3_BREQ 0x05
468#define AX_CMD_GUSBKR3_12e 0x12e
469#define AX_CMD_GUSBKR3_120 0x120
470#define AX_CMD_GUSBKR3_126 0x126
471#define AX_CMD_GUSBKR3_134 0x134
472#define AX_CMD_GUSBKR3_12f 0x12f
473#define AX_CMD_GUSBKR3_130 0x130
474#define AX_CMD_GUSBKR3_137 0x137
475#define AX_CMD_GUSBKR3_02 0x02
476#define AX_CMD_GUSBKR3_13e 0x13e
477
478/*
479* USB directions
480*/
481#define MUSB_DIR_OUT 0
482#define MUSB_DIR_IN 0x80
483
484/*
485* USB request types
486*/
487#define MUSB_TYPE_MASK (0x03 << 5)
488#define MUSB_TYPE_STANDARD (0x00 << 5)
489#define MUSB_TYPE_CLASS (0x01 << 5)
490#define MUSB_TYPE_VENDOR (0x02 << 5)
491#define MUSB_TYPE_RESERVED (0x03 << 5)
492
493/*
494* USB recipients
495*/
496#define MUSB_RECIP_MASK 0x1f
497#define MUSB_RECIP_DEVICE 0x00
498#define MUSB_RECIP_INTERFACE 0x01
499#define MUSB_RECIP_ENDPOINT 0x02
500#define MUSB_RECIP_OTHER 0x03
501
502/*
503* Standard requests
504*/
505#define MUSB_REQ_GET_STATUS 0x00
506#define MUSB_REQ_CLEAR_FEATURE 0x01
507#define MUSB_REQ_SET_FEATURE 0x03
508#define MUSB_REQ_SET_ADDRESS 0x05
509#define MUSB_REQ_GET_DESCRIPTOR 0x06
510#define MUSB_REQ_SET_DESCRIPTOR 0x07
511#define MUSB_REQ_GET_CONFIGURATION 0x08
512#define MUSB_REQ_SET_CONFIGURATION 0x09
513#define MUSB_REQ_GET_INTERFACE 0x0A
514#define MUSB_REQ_SET_INTERFACE 0x0B
515#define MUSB_REQ_SYNCH_FRAME 0x0C
516#define VENDOR_CONTROL_NAKTIMEOUT_TX 0x20
517#define VENDOR_CONTROL_NAKTIMEOUT_RX 0x21
518#define VENDOR_CONTROL_DISPING 0x22
519#define VENDOR_CONTROL_ERROR 0x23
520#define VENDOR_CONTROL_RXSTALL 0x24
521
522/*
523* Descriptor types
524*/
525#define MUSB_DT_DEVICE 0x01
526#define MUSB_DT_CONFIG 0x02
527#define MUSB_DT_STRING 0x03
528#define MUSB_DT_INTERFACE 0x04
529#define MUSB_DT_ENDPOINT 0x05
530#define MUSB_DT_DEVICE_QUALIFIER 0x06
531#define MUSB_DT_OTHER_SPEED 0X07
532#define MUSB_DT_INTERFACE_POWER 0x08
533#define MUSB_DT_OTG 0x09
534
535struct MUSB_DeviceRequest
536{
537 unsigned char bmRequestType;
538 unsigned char bRequest;
539 unsigned short wValue;
540 unsigned short wIndex;
541 unsigned short wLength;
542};
543
544
545struct ethenumeration_t
546{
547 unsigned char* pDesciptor;
548 struct MUSB_DeviceRequest sDevReq;
549};
550
551struct MUSB_ConfigurationDescriptor
552{
553 unsigned char bLength;
554 unsigned char bDescriptorType;
555 unsigned short wTotalLength;
556 unsigned char bNumInterfaces;
557 unsigned char bConfigurationValue;
558 unsigned char iConfiguration;
559 unsigned char bmAttributes;
560 unsigned char bMaxPower;
561};
562
563struct MUSB_InterfaceDescriptor
564{
565 unsigned char bLength;
566 unsigned char bDescriptorType;
567 unsigned char bInterfaceNumber;
568 unsigned char bAlternateSetting;
569 unsigned char bNumEndpoints;
570 unsigned char bInterfaceClass;
571 unsigned char bInterfaceSubClass;
572 unsigned char bInterfaceProtocol;
573 unsigned char iInterface;
574};
575
576struct MUSB_EndpointDescriptor
577{
578 unsigned char bLength;
579 unsigned char bDescriptorType;
580 unsigned char bEndpointAddress;
581 unsigned char bmAttributes;
582 unsigned short wMaxPacketSize;
583 unsigned char bInterval;
584};
585
586struct MUSB_DeviceDescriptor
587{
588 unsigned char bLength;
589 unsigned char bDescriptorType;
590 unsigned short bcdUSB;
591 unsigned char bDeviceClass;
592 unsigned char bDeviceSubClass;
593 unsigned char bDeviceProtocol;
594 unsigned char bMaxPacketSize0;
595 unsigned short idVendor;
596 unsigned short idProduct;
597 unsigned short bcdDevice;
598 unsigned char iManufacturer;
599 unsigned char iProduct;
600 unsigned char iSerialNumber;
601 unsigned char bNumConfigurations;
602};
603
604#define MTK_TEST_DBG
605
606#ifdef MTK_TEST_DBG
607#define mtk_test_dbg(fmt, args...) \
608 do { printk("%s(%d):" fmt, __func__, __LINE__, ##args); } while (0)
609#else
610#define mtk_test_dbg(fmt, args...)
611#endif
612
613
614#endif
kernel source for telekom puls (alcatel/mediatek)