[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / sound / mt8127 / AudDrv_Ana_6397.h

/*
 * Copyright (C) 2007 The Android Open Source Project
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/*******************************************************************************
 *
 * Filename:
 * ---------
 *   AudDrv_Ana.h
 *
 * Project:
 * --------
 *   MT6397 Audio Driver Digital/Analog
 *
 * Description:
 * ------------
 *   Audio register
 *
 * Author:
 * -------
 *   Luke Liu
 *   Daniel Hsiao (mtk00469)
 *   Chipeng Chang (mtk02308)
 *
 *------------------------------------------------------------------------------
 * $Revision: #1 $
 * $Modtime:$
 * $Log:$
 *
 *
 *******************************************************************************/

#ifndef _AUDDRV_ANA_H_
#define _AUDDRV_ANA_H_

/*****************************************************************************
 *                     C O M P I L E R   F L A G S
 *****************************************************************************/


/*****************************************************************************
 *                E X T E R N A L   R E F E R E N C E S
 *****************************************************************************/

#include "AudDrv_Common.h"
#include "AudDrv_Def.h"


/*****************************************************************************
 *                         D A T A   T Y P E S
 *****************************************************************************/


/*****************************************************************************
 *                         M A C R O
 *****************************************************************************/

/*****************************************************************************
 *                  R E G I S T E R       D E F I N I T I O N
 *****************************************************************************/
 
//---------------digital pmic register define start -------------------------------------------
#define AFE_PMICDIG_AUDIO_BASE        (0x4000)
#define AFE_UL_DL_CON0               (AFE_PMICDIG_AUDIO_BASE+0x0000)
#define AFE_DL_SRC2_CON0_H     (AFE_PMICDIG_AUDIO_BASE+0x0002)
#define AFE_DL_SRC2_CON0_L     (AFE_PMICDIG_AUDIO_BASE+0x0004)
#define AFE_DL_SDM_CON0             (AFE_PMICDIG_AUDIO_BASE + 0x0006)
#define AFE_DL_SDM_CON1             (AFE_PMICDIG_AUDIO_BASE + 0x0008)
#define AFE_UL_SRC_CON0_H           (AFE_PMICDIG_AUDIO_BASE + 0x000A)
#define AFE_UL_SRC_CON0_L           (AFE_PMICDIG_AUDIO_BASE + 0x000C)
#define AFE_UL_SRC_CON1_H           (AFE_PMICDIG_AUDIO_BASE + 0x000E)
#define AFE_UL_SRC_CON1_L           (AFE_PMICDIG_AUDIO_BASE + 0x0010)
#define ANA_AFE_TOP_CON0            (AFE_PMICDIG_AUDIO_BASE + 0x0012)
#define ANA_AUDIO_TOP_CON0          (AFE_PMICDIG_AUDIO_BASE + 0x0014)
#define AFE_DL_SRC_MON0             (AFE_PMICDIG_AUDIO_BASE + 0x0016)
#define AFE_DL_SDM_TEST0            (AFE_PMICDIG_AUDIO_BASE + 0x0018)
#define AFE_MON_DEBUG0              (AFE_PMICDIG_AUDIO_BASE + 0x001A)
#define AFUNC_AUD_CON0              (AFE_PMICDIG_AUDIO_BASE + 0x001C)
#define AFUNC_AUD_CON1              (AFE_PMICDIG_AUDIO_BASE + 0x001E)
#define AFUNC_AUD_CON2              (AFE_PMICDIG_AUDIO_BASE + 0x0020)
#define AFUNC_AUD_CON3              (AFE_PMICDIG_AUDIO_BASE + 0x0022)
#define AFUNC_AUD_CON4              (AFE_PMICDIG_AUDIO_BASE + 0x0024)
#define AFUNC_AUD_MON0              (AFE_PMICDIG_AUDIO_BASE + 0x0026)
#define AFUNC_AUD_MON1              (AFE_PMICDIG_AUDIO_BASE + 0x0028)
#define AUDRC_TUNE_MON0             (AFE_PMICDIG_AUDIO_BASE + 0x002A)
#define AFE_UP8X_FIFO_CFG0          (AFE_PMICDIG_AUDIO_BASE + 0x002C) //6397 new
#define AFE_UP8X_FIFO_LOG_MON0      (AFE_PMICDIG_AUDIO_BASE + 0x002E) //6397 new
#define AFE_UP8X_FIFO_LOG_MON1      (AFE_PMICDIG_AUDIO_BASE + 0x0030) //6397 new
#define AFE_DL_DC_COMP_CFG0         (AFE_PMICDIG_AUDIO_BASE + 0x0032)
#define AFE_DL_DC_COMP_CFG1         (AFE_PMICDIG_AUDIO_BASE + 0x0034)
#define AFE_DL_DC_COMP_CFG2         (AFE_PMICDIG_AUDIO_BASE + 0x0036)
#define AFE_PMIC_NEWIF_CFG0         (AFE_PMICDIG_AUDIO_BASE + 0x0038)
#define AFE_PMIC_NEWIF_CFG1         (AFE_PMICDIG_AUDIO_BASE + 0x003A)
#define AFE_PMIC_NEWIF_CFG2         (AFE_PMICDIG_AUDIO_BASE + 0x003C)
#define AFE_PMIC_NEWIF_CFG3         (AFE_PMICDIG_AUDIO_BASE + 0x003E)
#define AFE_SGEN_CFG0               (AFE_PMICDIG_AUDIO_BASE + 0x0040)
#define AFE_SGEN_CFG1               (AFE_PMICDIG_AUDIO_BASE + 0x0042)
//---------------digital pmic  register define end ---------------------------------------

/* The valid range of audio digital hardware in PMIC */
#define AFE_ADDR_START	AFE_UL_DL_CON0
#define AFE_ADDR_END		AFE_SGEN_CFG1

//---------------analog pmic  register define start --------------------------------------
#if 0
#define AFE_PMICANA_AUDIO_BASE        (0x0)

#define TOP_CKPDN                   (AFE_PMICANA_AUDIO_BASE + 0x0102)
#define TOP_CKPDN_SET               (AFE_PMICANA_AUDIO_BASE + 0x0104)
#define TOP_CKPDN_CLR               (AFE_PMICANA_AUDIO_BASE + 0x0106)
#define TOP_CKPDN2                  (AFE_PMICANA_AUDIO_BASE + 0x0108)
#define TOP_CKPDN2_SET              (AFE_PMICANA_AUDIO_BASE + 0x010a)
#define TOP_CKPDN2_CLR              (AFE_PMICANA_AUDIO_BASE + 0x010c)
#define TOP_CKCON1                  (AFE_PMICANA_AUDIO_BASE + 0x0128)

#define SPK_CON0                    (AFE_PMICANA_AUDIO_BASE + 0x0600)
#define SPK_CON1                    (AFE_PMICANA_AUDIO_BASE + 0x0602)
#define SPK_CON2                    (AFE_PMICANA_AUDIO_BASE + 0x0604)
#define SPK_CON3                    (AFE_PMICANA_AUDIO_BASE + 0x0606)
#define SPK_CON4                    (AFE_PMICANA_AUDIO_BASE + 0x0608)
#define SPK_CON5                    (AFE_PMICANA_AUDIO_BASE + 0x060A)
#define SPK_CON6                    (AFE_PMICANA_AUDIO_BASE + 0x060C)
#define SPK_CON7                    (AFE_PMICANA_AUDIO_BASE + 0x060E)
#define SPK_CON8                    (AFE_PMICANA_AUDIO_BASE + 0x0610)
#define SPK_CON9                    (AFE_PMICANA_AUDIO_BASE + 0x0612)
#define SPK_CON10                   (AFE_PMICANA_AUDIO_BASE + 0x0614)
#define SPK_CON11                   (AFE_PMICANA_AUDIO_BASE + 0x0616)

#define AUDDAC_CON0                 (AFE_PMICANA_AUDIO_BASE + 0x0700)
#define AUDBUF_CFG0                 (AFE_PMICANA_AUDIO_BASE + 0x0702)
#define AUDBUF_CFG1                 (AFE_PMICANA_AUDIO_BASE + 0x0704)
#define AUDBUF_CFG2                 (AFE_PMICANA_AUDIO_BASE + 0x0706)
#define AUDBUF_CFG3                 (AFE_PMICANA_AUDIO_BASE + 0x0708)
#define AUDBUF_CFG4                 (AFE_PMICANA_AUDIO_BASE + 0x070a)
#define IBIASDIST_CFG0              (AFE_PMICANA_AUDIO_BASE + 0x070c)
#define AUDACCDEPOP_CFG0            (AFE_PMICANA_AUDIO_BASE + 0x070e)
#define AUD_IV_CFG0                 (AFE_PMICANA_AUDIO_BASE + 0x0710)
#define AUDCLKGEN_CFG0              (AFE_PMICANA_AUDIO_BASE + 0x0712)
#define AUDLDO_CFG0                 (AFE_PMICANA_AUDIO_BASE + 0x0714)
#define AUDLDO_CFG1                 (AFE_PMICANA_AUDIO_BASE + 0x0716)
#define AUDNVREGGLB_CFG0            (AFE_PMICANA_AUDIO_BASE + 0x0718)
#define AUD_NCP0                    (AFE_PMICANA_AUDIO_BASE + 0x071a)
#define AUDPREAMP_CON0              (AFE_PMICANA_AUDIO_BASE + 0x071c)
#define AUDADC_CON0                 (AFE_PMICANA_AUDIO_BASE + 0x071e)
#define AUDADC_CON1                 (AFE_PMICANA_AUDIO_BASE + 0x0720)
#define AUDADC_CON2                 (AFE_PMICANA_AUDIO_BASE + 0x0722)
#define AUDADC_CON3                 (AFE_PMICANA_AUDIO_BASE + 0x0724)
#define AUDADC_CON4                 (AFE_PMICANA_AUDIO_BASE + 0x0726)
#define AUDADC_CON5                 (AFE_PMICANA_AUDIO_BASE + 0x0728)
#define AUDADC_CON6                 (AFE_PMICANA_AUDIO_BASE + 0x072a)
#define AUDDIGMI_CON0               (AFE_PMICANA_AUDIO_BASE + 0x072c)
#define AUDLSBUF_CON0               (AFE_PMICANA_AUDIO_BASE + 0x072e)
#define AUDLSBUF_CON1               (AFE_PMICANA_AUDIO_BASE + 0x0730)
#define AUDENCSPARE_CON0            (AFE_PMICANA_AUDIO_BASE + 0x0732)
#define AUDENCCLKSQ_CON0            (AFE_PMICANA_AUDIO_BASE + 0x0734)
#define AUDPREAMPGAIN_CON0          (AFE_PMICANA_AUDIO_BASE + 0x0736)
#define ZCD_CON0                    (AFE_PMICANA_AUDIO_BASE + 0x0738)
#define ZCD_CON1                    (AFE_PMICANA_AUDIO_BASE + 0x073a)
#define ZCD_CON2                    (AFE_PMICANA_AUDIO_BASE + 0x073c)
#define ZCD_CON3                    (AFE_PMICANA_AUDIO_BASE + 0x073e)
#define ZCD_CON4                    (AFE_PMICANA_AUDIO_BASE + 0x0740)
#define ZCD_CON5                    (AFE_PMICANA_AUDIO_BASE + 0x0742)
#define NCP_CLKDIV_CON0             (AFE_PMICANA_AUDIO_BASE + 0x0744)
#define NCP_CLKDIV_CON1             (AFE_PMICANA_AUDIO_BASE + 0x0746)
#else
#include <mach/upmu_hw.h>
#endif

/* The valid range of audio analog hardware in PMIC */
#define AUDTOP_MAX_ADDR_OFFSET		(0x079A)
//---------------analog pmic register define end ---------------------------------------

typedef struct
{
volatile uint16 Suspend_Ana_AFE_UL_DL_CON0;
volatile uint16 Suspend_Ana_AFE_DL_SRC2_CON0_H;
volatile uint16 Suspend_Ana_AFE_DL_SRC2_CON0_L;
volatile uint16 Suspend_Ana_AFE_DL_SDM_CON0;
volatile uint16 Suspend_Ana_AFE_DL_SDM_CON1;
volatile uint16 Suspend_Ana_AFE_UL_SRC_CON0_H;
volatile uint16 Suspend_Ana_AFE_UL_SRC_CON0_L;
volatile uint16 Suspend_Ana_AFE_UL_SRC_CON1_H;
volatile uint16 Suspend_Ana_AFE_UL_SRC_CON1_L;
volatile uint16 Suspend_Ana_AFE_TOP_CON0;
volatile uint16 Suspend_Ana_AUDIO_TOP_CON0;                                                 
volatile uint16 Suspend_Ana_AFUNC_AUD_CON0;
volatile uint16 Suspend_Ana_AFUNC_AUD_CON1;
volatile uint16 Suspend_Ana_AFUNC_AUD_CON2;
volatile uint16 Suspend_Ana_AFUNC_AUD_CON3;
volatile uint16 Suspend_Ana_AFUNC_AUD_CON4;
volatile uint16 Suspend_Ana_AFE_UP8X_FIFO_CFG0;
volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG0;
volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG1;
volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG2;
volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG0;
volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG1;
volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG2;
volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG3;
volatile uint16 Suspend_Ana_AFE_SGEN_CFG0;
volatile uint16 Suspend_Ana_AFE_SGEN_CFG1;

volatile uint16 Suspend_Ana_TOP_CKPDN;
volatile uint16 Suspend_Ana_TOP_CKPDN_SET;
volatile uint16 Suspend_Ana_TOP_CKPDN_CLR;
volatile uint16 Suspend_Ana_TOP_CKPDN2;
volatile uint16 Suspend_Ana_TOP_CKPDN2_SET;
volatile uint16 Suspend_Ana_TOP_CKPDN2_CLR;
volatile uint16 Suspend_Ana_TOP_CKCON1;
    volatile uint16 Suspend_Ana_SPK_CON0;
    volatile uint16 Suspend_Ana_SPK_CON1;
    volatile uint16 Suspend_Ana_SPK_CON2;
volatile uint16 Suspend_Ana_SPK_CON3;
volatile uint16 Suspend_Ana_SPK_CON4;
volatile uint16 Suspend_Ana_SPK_CON5;
    volatile uint16 Suspend_Ana_SPK_CON6;
    volatile uint16 Suspend_Ana_SPK_CON7;
    volatile uint16 Suspend_Ana_SPK_CON8;
    volatile uint16 Suspend_Ana_SPK_CON9;
    volatile uint16 Suspend_Ana_SPK_CON10;
    volatile uint16 Suspend_Ana_SPK_CON11;
volatile uint16 Suspend_Ana_AUDDAC_CON0;
volatile uint16 Suspend_Ana_AUDBUF_CFG0;
volatile uint16 Suspend_Ana_AUDBUF_CFG1;
volatile uint16 Suspend_Ana_AUDBUF_CFG2;
volatile uint16 Suspend_Ana_AUDBUF_CFG3;
volatile uint16 Suspend_Ana_AUDBUF_CFG4;
volatile uint16 Suspend_Ana_IBIASDIST_CFG0;
volatile uint16 Suspend_Ana_AUDACCDEPOP_CFG0;
volatile uint16 Suspend_Ana_AUD_IV_CFG0;
volatile uint16 Suspend_Ana_AUDCLKGEN_CFG0;
volatile uint16 Suspend_Ana_AUDLDO_CFG0;
volatile uint16 Suspend_Ana_AUDLDO_CFG1;
volatile uint16 Suspend_Ana_AUDNVREGGLB_CFG0;
volatile uint16 Suspend_Ana_AUD_NCP0;
volatile uint16 Suspend_Ana_AUDPREAMP_CON0;
volatile uint16 Suspend_Ana_AUDADC_CON0;
volatile uint16 Suspend_Ana_AUDADC_CON1;
volatile uint16 Suspend_Ana_AUDADC_CON2;
volatile uint16 Suspend_Ana_AUDADC_CON3;
volatile uint16 Suspend_Ana_AUDADC_CON4;
volatile uint16 Suspend_Ana_AUDADC_CON5;
volatile uint16 Suspend_Ana_AUDADC_CON6;
volatile uint16 Suspend_Ana_AUDDIGMI_CON0;
volatile uint16 Suspend_Ana_AUDLSBUF_CON0;
volatile uint16 Suspend_Ana_AUDLSBUF_CON1;
volatile uint16 Suspend_Ana_AUDENCSPARE_CON0;
volatile uint16 Suspend_Ana_AUDENCCLKSQ_CON0;
volatile uint16 Suspend_Ana_AUDPREAMPGAIN_CON0;
volatile uint16 Suspend_Ana_ZCD_CON0;
volatile uint16 Suspend_Ana_ZCD_CON1;
volatile uint16 Suspend_Ana_ZCD_CON2;
volatile uint16 Suspend_Ana_ZCD_CON3;
volatile uint16 Suspend_Ana_ZCD_CON4;
volatile uint16 Suspend_Ana_ZCD_CON5;
volatile uint16 Suspend_Ana_NCP_CLKDIV_CON0;
volatile uint16 Suspend_Ana_NCP_CLKDIV_CON1;

} AudAna_Suspend_Reg;

void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask);
uint32  Ana_Get_Reg(uint32 offset);
void AudDrv_Store_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);
void AudDrv_Recover_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);


// for debug usage
void Ana_Log_Print(void);

#endif
Commit	Line	Data
6fa3eb70 S	1	/*
	2	* Copyright (C) 2007 The Android Open Source Project
	3	*
	4	* Licensed under the Apache License, Version 2.0 (the "License");
	5	* you may not use this file except in compliance with the License.
	6	* You may obtain a copy of the License at
	7	*
	8	* http://www.apache.org/licenses/LICENSE-2.0
	9	*
	10	* Unless required by applicable law or agreed to in writing, software
	11	* distributed under the License is distributed on an "AS IS" BASIS,
	12	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	* See the License for the specific language governing permissions and
	14	* limitations under the License.
	15	*/
	16	/*******************************************************************************
	17	*
	18	* Filename:
	19	* ---------
	20	* AudDrv_Ana.h
	21	*
	22	* Project:
	23	* --------
	24	* MT6397 Audio Driver Digital/Analog
	25	*
	26	* Description:
	27	* ------------
	28	* Audio register
	29	*
	30	* Author:
	31	* -------
	32	* Luke Liu
	33	* Daniel Hsiao (mtk00469)
	34	* Chipeng Chang (mtk02308)
	35	*
	36	*------------------------------------------------------------------------------
	37	* $Revision: #1 $
	38	* $Modtime:$
	39	* $Log:$
	40	*
	41	*
	42	*******************************************************************************/
	43
	44	#ifndef _AUDDRV_ANA_H_
	45	#define _AUDDRV_ANA_H_
	46
	47	/*****************************************************************************
	48	* C O M P I L E R F L A G S
	49	*****************************************************************************/
	50
	51
	52	/*****************************************************************************
	53	* E X T E R N A L R E F E R E N C E S
	54	*****************************************************************************/
	55
	56	#include "AudDrv_Common.h"
	57	#include "AudDrv_Def.h"
	58
	59
	60	/*****************************************************************************
	61	* D A T A T Y P E S
	62	*****************************************************************************/
	63
	64
65	/*****************************************************************************
66	* M A C R O
67	*****************************************************************************/
68
69	/*****************************************************************************
70	* R E G I S T E R D E F I N I T I O N
71	*****************************************************************************/
4b9e9796	72
6fa3eb70 S	73	//---------------digital pmic register define start -------------------------------------------
	74	#define AFE_PMICDIG_AUDIO_BASE (0x4000)
	75	#define AFE_UL_DL_CON0 (AFE_PMICDIG_AUDIO_BASE+0x0000)
	76	#define AFE_DL_SRC2_CON0_H (AFE_PMICDIG_AUDIO_BASE+0x0002)
	77	#define AFE_DL_SRC2_CON0_L (AFE_PMICDIG_AUDIO_BASE+0x0004)
	78	#define AFE_DL_SDM_CON0 (AFE_PMICDIG_AUDIO_BASE + 0x0006)
	79	#define AFE_DL_SDM_CON1 (AFE_PMICDIG_AUDIO_BASE + 0x0008)
	80	#define AFE_UL_SRC_CON0_H (AFE_PMICDIG_AUDIO_BASE + 0x000A)
	81	#define AFE_UL_SRC_CON0_L (AFE_PMICDIG_AUDIO_BASE + 0x000C)
	82	#define AFE_UL_SRC_CON1_H (AFE_PMICDIG_AUDIO_BASE + 0x000E)
	83	#define AFE_UL_SRC_CON1_L (AFE_PMICDIG_AUDIO_BASE + 0x0010)
	84	#define ANA_AFE_TOP_CON0 (AFE_PMICDIG_AUDIO_BASE + 0x0012)
	85	#define ANA_AUDIO_TOP_CON0 (AFE_PMICDIG_AUDIO_BASE + 0x0014)
	86	#define AFE_DL_SRC_MON0 (AFE_PMICDIG_AUDIO_BASE + 0x0016)
	87	#define AFE_DL_SDM_TEST0 (AFE_PMICDIG_AUDIO_BASE + 0x0018)
	88	#define AFE_MON_DEBUG0 (AFE_PMICDIG_AUDIO_BASE + 0x001A)
	89	#define AFUNC_AUD_CON0 (AFE_PMICDIG_AUDIO_BASE + 0x001C)
	90	#define AFUNC_AUD_CON1 (AFE_PMICDIG_AUDIO_BASE + 0x001E)
	91	#define AFUNC_AUD_CON2 (AFE_PMICDIG_AUDIO_BASE + 0x0020)
	92	#define AFUNC_AUD_CON3 (AFE_PMICDIG_AUDIO_BASE + 0x0022)
	93	#define AFUNC_AUD_CON4 (AFE_PMICDIG_AUDIO_BASE + 0x0024)
	94	#define AFUNC_AUD_MON0 (AFE_PMICDIG_AUDIO_BASE + 0x0026)
	95	#define AFUNC_AUD_MON1 (AFE_PMICDIG_AUDIO_BASE + 0x0028)
	96	#define AUDRC_TUNE_MON0 (AFE_PMICDIG_AUDIO_BASE + 0x002A)
	97	#define AFE_UP8X_FIFO_CFG0 (AFE_PMICDIG_AUDIO_BASE + 0x002C) //6397 new
	98	#define AFE_UP8X_FIFO_LOG_MON0 (AFE_PMICDIG_AUDIO_BASE + 0x002E) //6397 new
	99	#define AFE_UP8X_FIFO_LOG_MON1 (AFE_PMICDIG_AUDIO_BASE + 0x0030) //6397 new
	100	#define AFE_DL_DC_COMP_CFG0 (AFE_PMICDIG_AUDIO_BASE + 0x0032)
	101	#define AFE_DL_DC_COMP_CFG1 (AFE_PMICDIG_AUDIO_BASE + 0x0034)
	102	#define AFE_DL_DC_COMP_CFG2 (AFE_PMICDIG_AUDIO_BASE + 0x0036)
	103	#define AFE_PMIC_NEWIF_CFG0 (AFE_PMICDIG_AUDIO_BASE + 0x0038)
	104	#define AFE_PMIC_NEWIF_CFG1 (AFE_PMICDIG_AUDIO_BASE + 0x003A)
	105	#define AFE_PMIC_NEWIF_CFG2 (AFE_PMICDIG_AUDIO_BASE + 0x003C)
	106	#define AFE_PMIC_NEWIF_CFG3 (AFE_PMICDIG_AUDIO_BASE + 0x003E)
	107	#define AFE_SGEN_CFG0 (AFE_PMICDIG_AUDIO_BASE + 0x0040)
	108	#define AFE_SGEN_CFG1 (AFE_PMICDIG_AUDIO_BASE + 0x0042)
	109	//---------------digital pmic register define end ---------------------------------------
	110
4b9e9796 S	111	/* The valid range of audio digital hardware in PMIC */
	112	#define AFE_ADDR_START AFE_UL_DL_CON0
	113	#define AFE_ADDR_END AFE_SGEN_CFG1
	114
6fa3eb70 S	115	//---------------analog pmic register define start --------------------------------------
	116	#if 0
	117	#define AFE_PMICANA_AUDIO_BASE (0x0)
	118
	119	#define TOP_CKPDN (AFE_PMICANA_AUDIO_BASE + 0x0102)
	120	#define TOP_CKPDN_SET (AFE_PMICANA_AUDIO_BASE + 0x0104)
	121	#define TOP_CKPDN_CLR (AFE_PMICANA_AUDIO_BASE + 0x0106)
	122	#define TOP_CKPDN2 (AFE_PMICANA_AUDIO_BASE + 0x0108)
	123	#define TOP_CKPDN2_SET (AFE_PMICANA_AUDIO_BASE + 0x010a)
	124	#define TOP_CKPDN2_CLR (AFE_PMICANA_AUDIO_BASE + 0x010c)
	125	#define TOP_CKCON1 (AFE_PMICANA_AUDIO_BASE + 0x0128)
	126
	127	#define SPK_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0600)
	128	#define SPK_CON1 (AFE_PMICANA_AUDIO_BASE + 0x0602)
	129	#define SPK_CON2 (AFE_PMICANA_AUDIO_BASE + 0x0604)
	130	#define SPK_CON3 (AFE_PMICANA_AUDIO_BASE + 0x0606)
	131	#define SPK_CON4 (AFE_PMICANA_AUDIO_BASE + 0x0608)
	132	#define SPK_CON5 (AFE_PMICANA_AUDIO_BASE + 0x060A)
	133	#define SPK_CON6 (AFE_PMICANA_AUDIO_BASE + 0x060C)
	134	#define SPK_CON7 (AFE_PMICANA_AUDIO_BASE + 0x060E)
	135	#define SPK_CON8 (AFE_PMICANA_AUDIO_BASE + 0x0610)
	136	#define SPK_CON9 (AFE_PMICANA_AUDIO_BASE + 0x0612)
	137	#define SPK_CON10 (AFE_PMICANA_AUDIO_BASE + 0x0614)
	138	#define SPK_CON11 (AFE_PMICANA_AUDIO_BASE + 0x0616)
	139
	140	#define AUDDAC_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0700)
	141	#define AUDBUF_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x0702)
	142	#define AUDBUF_CFG1 (AFE_PMICANA_AUDIO_BASE + 0x0704)
	143	#define AUDBUF_CFG2 (AFE_PMICANA_AUDIO_BASE + 0x0706)
	144	#define AUDBUF_CFG3 (AFE_PMICANA_AUDIO_BASE + 0x0708)
	145	#define AUDBUF_CFG4 (AFE_PMICANA_AUDIO_BASE + 0x070a)
	146	#define IBIASDIST_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x070c)
	147	#define AUDACCDEPOP_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x070e)
	148	#define AUD_IV_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x0710)
	149	#define AUDCLKGEN_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x0712)
	150	#define AUDLDO_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x0714)
	151	#define AUDLDO_CFG1 (AFE_PMICANA_AUDIO_BASE + 0x0716)
	152	#define AUDNVREGGLB_CFG0 (AFE_PMICANA_AUDIO_BASE + 0x0718)
	153	#define AUD_NCP0 (AFE_PMICANA_AUDIO_BASE + 0x071a)
	154	#define AUDPREAMP_CON0 (AFE_PMICANA_AUDIO_BASE + 0x071c)
	155	#define AUDADC_CON0 (AFE_PMICANA_AUDIO_BASE + 0x071e)
	156	#define AUDADC_CON1 (AFE_PMICANA_AUDIO_BASE + 0x0720)
	157	#define AUDADC_CON2 (AFE_PMICANA_AUDIO_BASE + 0x0722)
	158	#define AUDADC_CON3 (AFE_PMICANA_AUDIO_BASE + 0x0724)
	159	#define AUDADC_CON4 (AFE_PMICANA_AUDIO_BASE + 0x0726)
	160	#define AUDADC_CON5 (AFE_PMICANA_AUDIO_BASE + 0x0728)
	161	#define AUDADC_CON6 (AFE_PMICANA_AUDIO_BASE + 0x072a)
	162	#define AUDDIGMI_CON0 (AFE_PMICANA_AUDIO_BASE + 0x072c)
	163	#define AUDLSBUF_CON0 (AFE_PMICANA_AUDIO_BASE + 0x072e)
	164	#define AUDLSBUF_CON1 (AFE_PMICANA_AUDIO_BASE + 0x0730)
	165	#define AUDENCSPARE_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0732)
	166	#define AUDENCCLKSQ_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0734)
	167	#define AUDPREAMPGAIN_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0736)
	168	#define ZCD_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0738)
	169	#define ZCD_CON1 (AFE_PMICANA_AUDIO_BASE + 0x073a)
	170	#define ZCD_CON2 (AFE_PMICANA_AUDIO_BASE + 0x073c)
	171	#define ZCD_CON3 (AFE_PMICANA_AUDIO_BASE + 0x073e)
	172	#define ZCD_CON4 (AFE_PMICANA_AUDIO_BASE + 0x0740)
	173	#define ZCD_CON5 (AFE_PMICANA_AUDIO_BASE + 0x0742)
	174	#define NCP_CLKDIV_CON0 (AFE_PMICANA_AUDIO_BASE + 0x0744)
	175	#define NCP_CLKDIV_CON1 (AFE_PMICANA_AUDIO_BASE + 0x0746)
	176	#else
	177	#include <mach/upmu_hw.h>
	178	#endif
179
4b9e9796 S	180	/* The valid range of audio analog hardware in PMIC */
4b9e9796 S	181	#define AUDTOP_MAX_ADDR_OFFSET (0x079A)
6fa3eb70 S	182	//---------------analog pmic register define end ---------------------------------------
	183
	184	typedef struct
	185	{
	186	volatile uint16 Suspend_Ana_AFE_UL_DL_CON0;
	187	volatile uint16 Suspend_Ana_AFE_DL_SRC2_CON0_H;
	188	volatile uint16 Suspend_Ana_AFE_DL_SRC2_CON0_L;
	189	volatile uint16 Suspend_Ana_AFE_DL_SDM_CON0;
	190	volatile uint16 Suspend_Ana_AFE_DL_SDM_CON1;
	191	volatile uint16 Suspend_Ana_AFE_UL_SRC_CON0_H;
	192	volatile uint16 Suspend_Ana_AFE_UL_SRC_CON0_L;
	193	volatile uint16 Suspend_Ana_AFE_UL_SRC_CON1_H;
	194	volatile uint16 Suspend_Ana_AFE_UL_SRC_CON1_L;
	195	volatile uint16 Suspend_Ana_AFE_TOP_CON0;
	196	volatile uint16 Suspend_Ana_AUDIO_TOP_CON0;
	197	volatile uint16 Suspend_Ana_AFUNC_AUD_CON0;
	198	volatile uint16 Suspend_Ana_AFUNC_AUD_CON1;
	199	volatile uint16 Suspend_Ana_AFUNC_AUD_CON2;
	200	volatile uint16 Suspend_Ana_AFUNC_AUD_CON3;
	201	volatile uint16 Suspend_Ana_AFUNC_AUD_CON4;
	202	volatile uint16 Suspend_Ana_AFE_UP8X_FIFO_CFG0;
	203	volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG0;
	204	volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG1;
	205	volatile uint16 Suspend_Ana_AFE_DL_DC_COMP_CFG2;
	206	volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG0;
	207	volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG1;
	208	volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG2;
	209	volatile uint16 Suspend_Ana_AFE_PMIC_NEWIF_CFG3;
	210	volatile uint16 Suspend_Ana_AFE_SGEN_CFG0;
	211	volatile uint16 Suspend_Ana_AFE_SGEN_CFG1;
	212
	213	volatile uint16 Suspend_Ana_TOP_CKPDN;
	214	volatile uint16 Suspend_Ana_TOP_CKPDN_SET;
	215	volatile uint16 Suspend_Ana_TOP_CKPDN_CLR;
	216	volatile uint16 Suspend_Ana_TOP_CKPDN2;
	217	volatile uint16 Suspend_Ana_TOP_CKPDN2_SET;
	218	volatile uint16 Suspend_Ana_TOP_CKPDN2_CLR;
	219	volatile uint16 Suspend_Ana_TOP_CKCON1;
	220	volatile uint16 Suspend_Ana_SPK_CON0;
	221	volatile uint16 Suspend_Ana_SPK_CON1;
	222	volatile uint16 Suspend_Ana_SPK_CON2;
	223	volatile uint16 Suspend_Ana_SPK_CON3;
	224	volatile uint16 Suspend_Ana_SPK_CON4;
	225	volatile uint16 Suspend_Ana_SPK_CON5;
	226	volatile uint16 Suspend_Ana_SPK_CON6;
	227	volatile uint16 Suspend_Ana_SPK_CON7;
	228	volatile uint16 Suspend_Ana_SPK_CON8;
	229	volatile uint16 Suspend_Ana_SPK_CON9;
	230	volatile uint16 Suspend_Ana_SPK_CON10;
	231	volatile uint16 Suspend_Ana_SPK_CON11;
	232	volatile uint16 Suspend_Ana_AUDDAC_CON0;
	233	volatile uint16 Suspend_Ana_AUDBUF_CFG0;
	234	volatile uint16 Suspend_Ana_AUDBUF_CFG1;
	235	volatile uint16 Suspend_Ana_AUDBUF_CFG2;
	236	volatile uint16 Suspend_Ana_AUDBUF_CFG3;
	237	volatile uint16 Suspend_Ana_AUDBUF_CFG4;
	238	volatile uint16 Suspend_Ana_IBIASDIST_CFG0;
	239	volatile uint16 Suspend_Ana_AUDACCDEPOP_CFG0;
	240	volatile uint16 Suspend_Ana_AUD_IV_CFG0;
	241	volatile uint16 Suspend_Ana_AUDCLKGEN_CFG0;
	242	volatile uint16 Suspend_Ana_AUDLDO_CFG0;
	243	volatile uint16 Suspend_Ana_AUDLDO_CFG1;
	244	volatile uint16 Suspend_Ana_AUDNVREGGLB_CFG0;
	245	volatile uint16 Suspend_Ana_AUD_NCP0;
246	volatile uint16 Suspend_Ana_AUDPREAMP_CON0;
247	volatile uint16 Suspend_Ana_AUDADC_CON0;
248	volatile uint16 Suspend_Ana_AUDADC_CON1;
249	volatile uint16 Suspend_Ana_AUDADC_CON2;
250	volatile uint16 Suspend_Ana_AUDADC_CON3;
251	volatile uint16 Suspend_Ana_AUDADC_CON4;
252	volatile uint16 Suspend_Ana_AUDADC_CON5;
253	volatile uint16 Suspend_Ana_AUDADC_CON6;
254	volatile uint16 Suspend_Ana_AUDDIGMI_CON0;
255	volatile uint16 Suspend_Ana_AUDLSBUF_CON0;
256	volatile uint16 Suspend_Ana_AUDLSBUF_CON1;
257	volatile uint16 Suspend_Ana_AUDENCSPARE_CON0;
258	volatile uint16 Suspend_Ana_AUDENCCLKSQ_CON0;
259	volatile uint16 Suspend_Ana_AUDPREAMPGAIN_CON0;
260	volatile uint16 Suspend_Ana_ZCD_CON0;
261	volatile uint16 Suspend_Ana_ZCD_CON1;
262	volatile uint16 Suspend_Ana_ZCD_CON2;
263	volatile uint16 Suspend_Ana_ZCD_CON3;
264	volatile uint16 Suspend_Ana_ZCD_CON4;
265	volatile uint16 Suspend_Ana_ZCD_CON5;
266	volatile uint16 Suspend_Ana_NCP_CLKDIV_CON0;
267	volatile uint16 Suspend_Ana_NCP_CLKDIV_CON1;
268
269	} AudAna_Suspend_Reg;
270
271	void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask);
272	uint32 Ana_Get_Reg(uint32 offset);
273	void AudDrv_Store_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);
274	void AudDrv_Recover_reg_ANA(AudAna_Suspend_Reg *pBackup_reg);
275
276
277
278	// for debug usage
279	void Ana_Log_Print(void);
280
281	#endif
282