[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpu / mt8127 / mali / mali / regs / mali_200_regs.h

/*
 * This confidential and proprietary software may be used only as
 * authorised by a licensing agreement from ARM Limited
 * (C) COPYRIGHT 2007-2010, 2012-2015 ARM Limited
 * ALL RIGHTS RESERVED
 * The entire notice above must be reproduced on all authorised
 * copies and copies may only be made to the extent permitted
 * by a licensing agreement from ARM Limited.
 */

#ifndef _MALI200_REGS_H_
#define _MALI200_REGS_H_

/**
 *  Enum for management register addresses.
 */
enum mali200_mgmt_reg {
	MALI200_REG_ADDR_MGMT_VERSION                              = 0x1000,
	MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR               = 0x1004,
	MALI200_REG_ADDR_MGMT_STATUS                               = 0x1008,
	MALI200_REG_ADDR_MGMT_CTRL_MGMT                            = 0x100c,

	MALI200_REG_ADDR_MGMT_INT_RAWSTAT                          = 0x1020,
	MALI200_REG_ADDR_MGMT_INT_CLEAR                            = 0x1024,
	MALI200_REG_ADDR_MGMT_INT_MASK                             = 0x1028,
	MALI200_REG_ADDR_MGMT_INT_STATUS                           = 0x102c,

	MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS                     = 0x1050,

	MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE                    = 0x1080,
	MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC                       = 0x1084,
	MALI200_REG_ADDR_MGMT_PERF_CNT_0_LIMIT                     = 0x1088,
	MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE                     = 0x108c,

	MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE                    = 0x10a0,
	MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC                       = 0x10a4,
	MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE                     = 0x10ac,

	MALI200_REG_ADDR_MGMT_PERFMON_CONTR                        = 0x10b0,
	MALI200_REG_ADDR_MGMT_PERFMON_BASE                         = 0x10b4,

	MALI200_REG_SIZEOF_REGISTER_BANK                           = 0x10f0

};

#define MALI200_REG_VAL_PERF_CNT_ENABLE 1

enum mali200_mgmt_ctrl_mgmt {
	MALI200_REG_VAL_CTRL_MGMT_STOP_BUS         = (1 << 0),
	MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES     = (1 << 3),
	MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET      = (1 << 5),
	MALI200_REG_VAL_CTRL_MGMT_START_RENDERING  = (1 << 6),
	MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET     = (1 << 7), /* Only valid for Mali-300 and later */
};

enum mali200_mgmt_irq {
	MALI200_REG_VAL_IRQ_END_OF_FRAME          = (1 << 0),
	MALI200_REG_VAL_IRQ_END_OF_TILE           = (1 << 1),
	MALI200_REG_VAL_IRQ_HANG                  = (1 << 2),
	MALI200_REG_VAL_IRQ_FORCE_HANG            = (1 << 3),
	MALI200_REG_VAL_IRQ_BUS_ERROR             = (1 << 4),
	MALI200_REG_VAL_IRQ_BUS_STOP              = (1 << 5),
	MALI200_REG_VAL_IRQ_CNT_0_LIMIT           = (1 << 6),
	MALI200_REG_VAL_IRQ_CNT_1_LIMIT           = (1 << 7),
	MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR  = (1 << 8),
	MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1 << 9),
	MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW  = (1 << 10),
	MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW   = (1 << 11),
	MALI400PP_REG_VAL_IRQ_RESET_COMPLETED       = (1 << 12),
};

#define MALI200_REG_VAL_IRQ_MASK_ALL  ((enum mali200_mgmt_irq) (\
				       MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
				       MALI200_REG_VAL_IRQ_END_OF_TILE                            |\
				       MALI200_REG_VAL_IRQ_HANG                                   |\
				       MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
				       MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
				       MALI200_REG_VAL_IRQ_BUS_STOP                               |\
				       MALI200_REG_VAL_IRQ_CNT_0_LIMIT                            |\
				       MALI200_REG_VAL_IRQ_CNT_1_LIMIT                            |\
				       MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR                   |\
				       MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND                  |\
				       MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW                   |\
				       MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW                    |\
				       MALI400PP_REG_VAL_IRQ_RESET_COMPLETED))

#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
				       MALI200_REG_VAL_IRQ_END_OF_FRAME                           |\
				       MALI200_REG_VAL_IRQ_FORCE_HANG                             |\
				       MALI200_REG_VAL_IRQ_BUS_ERROR                              |\
				       MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR                   |\
				       MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND                  |\
				       MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW                   |\
				       MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW))

#define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0))

enum mali200_mgmt_status {
	MALI200_REG_VAL_STATUS_RENDERING_ACTIVE     = (1 << 0),
	MALI200_REG_VAL_STATUS_BUS_STOPPED          = (1 << 4),
};

enum mali200_render_unit {
	MALI200_REG_ADDR_FRAME = 0x0000,
	MALI200_REG_ADDR_RSW   = 0x0004,
	MALI200_REG_ADDR_STACK = 0x0030,
	MALI200_REG_ADDR_STACK_SIZE = 0x0034,
	MALI200_REG_ADDR_ORIGIN_OFFSET_X  = 0x0040
};

enum mali200_wb_unit {
	MALI200_REG_ADDR_WB0 = 0x0100,
	MALI200_REG_ADDR_WB1 = 0x0200,
	MALI200_REG_ADDR_WB2 = 0x0300
};

enum mali200_wb_unit_regs {
	MALI200_REG_ADDR_WB_SOURCE_SELECT = 0x0000,
	MALI200_REG_ADDR_WB_SOURCE_ADDR   = 0x0004,
};

/* This should be in the top 16 bit of the version register of Mali PP */
#define MALI200_PP_PRODUCT_ID 0xC807
#define MALI300_PP_PRODUCT_ID 0xCE07
#define MALI400_PP_PRODUCT_ID 0xCD07
#define MALI450_PP_PRODUCT_ID 0xCF07
#define MALI470_PP_PRODUCT_ID 0xCF08


#endif /* _MALI200_REGS_H_ */
Commit	Line	Data
6fa3eb70 S	1	/*
	2	* This confidential and proprietary software may be used only as
	3	* authorised by a licensing agreement from ARM Limited
02af6beb	4	* (C) COPYRIGHT 2007-2010, 2012-2015 ARM Limited
6fa3eb70 S	5	* ALL RIGHTS RESERVED
	6	* The entire notice above must be reproduced on all authorised
	7	* copies and copies may only be made to the extent permitted
	8	* by a licensing agreement from ARM Limited.
	9	*/
	10
	11	#ifndef _MALI200_REGS_H_
	12	#define _MALI200_REGS_H_
	13
	14	/**
	15	* Enum for management register addresses.
	16	*/
	17	enum mali200_mgmt_reg {
	18	MALI200_REG_ADDR_MGMT_VERSION = 0x1000,
	19	MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x1004,
	20	MALI200_REG_ADDR_MGMT_STATUS = 0x1008,
	21	MALI200_REG_ADDR_MGMT_CTRL_MGMT = 0x100c,
	22
	23	MALI200_REG_ADDR_MGMT_INT_RAWSTAT = 0x1020,
	24	MALI200_REG_ADDR_MGMT_INT_CLEAR = 0x1024,
	25	MALI200_REG_ADDR_MGMT_INT_MASK = 0x1028,
	26	MALI200_REG_ADDR_MGMT_INT_STATUS = 0x102c,
	27
6fa3eb70 S	28	MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS = 0x1050,
	29
	30	MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x1080,
	31	MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x1084,
02af6beb	32	MALI200_REG_ADDR_MGMT_PERF_CNT_0_LIMIT = 0x1088,
6fa3eb70 S	33	MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x108c,
	34
	35	MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x10a0,
	36	MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x10a4,
	37	MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x10ac,
	38
	39	MALI200_REG_ADDR_MGMT_PERFMON_CONTR = 0x10b0,
	40	MALI200_REG_ADDR_MGMT_PERFMON_BASE = 0x10b4,
	41
	42	MALI200_REG_SIZEOF_REGISTER_BANK = 0x10f0
	43
	44	};
	45
	46	#define MALI200_REG_VAL_PERF_CNT_ENABLE 1
	47
	48	enum mali200_mgmt_ctrl_mgmt {
02af6beb S	49	MALI200_REG_VAL_CTRL_MGMT_STOP_BUS = (1 << 0),
	50	MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES = (1 << 3),
	51	MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET = (1 << 5),
	52	MALI200_REG_VAL_CTRL_MGMT_START_RENDERING = (1 << 6),
	53	MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET = (1 << 7), /* Only valid for Mali-300 and later */
6fa3eb70 S	54	};
	55
	56	enum mali200_mgmt_irq {
02af6beb S	57	MALI200_REG_VAL_IRQ_END_OF_FRAME = (1 << 0),
	58	MALI200_REG_VAL_IRQ_END_OF_TILE = (1 << 1),
	59	MALI200_REG_VAL_IRQ_HANG = (1 << 2),
	60	MALI200_REG_VAL_IRQ_FORCE_HANG = (1 << 3),
	61	MALI200_REG_VAL_IRQ_BUS_ERROR = (1 << 4),
	62	MALI200_REG_VAL_IRQ_BUS_STOP = (1 << 5),
	63	MALI200_REG_VAL_IRQ_CNT_0_LIMIT = (1 << 6),
	64	MALI200_REG_VAL_IRQ_CNT_1_LIMIT = (1 << 7),
	65	MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR = (1 << 8),
	66	MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1 << 9),
	67	MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW = (1 << 10),
	68	MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW = (1 << 11),
	69	MALI400PP_REG_VAL_IRQ_RESET_COMPLETED = (1 << 12),
6fa3eb70 S	70	};
	71
	72	#define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\
02af6beb S	73	MALI200_REG_VAL_IRQ_END_OF_FRAME \|\
	74	MALI200_REG_VAL_IRQ_END_OF_TILE \|\
	75	MALI200_REG_VAL_IRQ_HANG \|\
	76	MALI200_REG_VAL_IRQ_FORCE_HANG \|\
	77	MALI200_REG_VAL_IRQ_BUS_ERROR \|\
	78	MALI200_REG_VAL_IRQ_BUS_STOP \|\
	79	MALI200_REG_VAL_IRQ_CNT_0_LIMIT \|\
	80	MALI200_REG_VAL_IRQ_CNT_1_LIMIT \|\
	81	MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR \|\
	82	MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND \|\
	83	MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW \|\
	84	MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW \|\
	85	MALI400PP_REG_VAL_IRQ_RESET_COMPLETED))
6fa3eb70 S	86
6fa3eb70 S	87	#define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
02af6beb S	88	MALI200_REG_VAL_IRQ_END_OF_FRAME \|\
	89	MALI200_REG_VAL_IRQ_FORCE_HANG \|\
	90	MALI200_REG_VAL_IRQ_BUS_ERROR \|\
	91	MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR \|\
	92	MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND \|\
	93	MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW \|\
	94	MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW))
6fa3eb70 S	95
	96	#define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0))
	97
	98	enum mali200_mgmt_status {
02af6beb S	99	MALI200_REG_VAL_STATUS_RENDERING_ACTIVE = (1 << 0),
02af6beb S	100	MALI200_REG_VAL_STATUS_BUS_STOPPED = (1 << 4),
6fa3eb70 S	101	};
	102
	103	enum mali200_render_unit {
	104	MALI200_REG_ADDR_FRAME = 0x0000,
	105	MALI200_REG_ADDR_RSW = 0x0004,
	106	MALI200_REG_ADDR_STACK = 0x0030,
	107	MALI200_REG_ADDR_STACK_SIZE = 0x0034,
	108	MALI200_REG_ADDR_ORIGIN_OFFSET_X = 0x0040
	109	};
	110
	111	enum mali200_wb_unit {
	112	MALI200_REG_ADDR_WB0 = 0x0100,
	113	MALI200_REG_ADDR_WB1 = 0x0200,
	114	MALI200_REG_ADDR_WB2 = 0x0300
	115	};
	116
	117	enum mali200_wb_unit_regs {
	118	MALI200_REG_ADDR_WB_SOURCE_SELECT = 0x0000,
	119	MALI200_REG_ADDR_WB_SOURCE_ADDR = 0x0004,
	120	};
	121
	122	/* This should be in the top 16 bit of the version register of Mali PP */
	123	#define MALI200_PP_PRODUCT_ID 0xC807
	124	#define MALI300_PP_PRODUCT_ID 0xCE07
	125	#define MALI400_PP_PRODUCT_ID 0xCD07
	126	#define MALI450_PP_PRODUCT_ID 0xCF07
02af6beb S	127	#define MALI470_PP_PRODUCT_ID 0xCF08
02af6beb S	128
6fa3eb70 S	129
	130
	131	#endif /* _MALI200_REGS_H_ */