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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpu / mt8127 / mali / mali / include / linux / mali / mali_utgard.h
CommitLineData
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S		 1/*
2 * This confidential and proprietary software may be used only as
3 * authorised by a licensing agreement from ARM Limited
02af6beb 4 * (C) COPYRIGHT 2012-2015 ARM Limited
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S		 5 * ALL RIGHTS RESERVED
6 * The entire notice above must be reproduced on all authorised
7 * copies and copies may only be made to the extent permitted
8 * by a licensing agreement from ARM Limited.
9 */
10
11/**
12 * @file mali_utgard.h
13 * Defines types and interface exposed by the Mali Utgard device driver
14 */
15
16#ifndef __MALI_UTGARD_H__
17#define __MALI_UTGARD_H__
18
19#include "mali_osk_types.h"
20
21#define MALI_GPU_NAME_UTGARD "mali-utgard"
22
6fa3eb70 23
02af6beb
S		 24#define MALI_OFFSET_GP 0x00000
25#define MALI_OFFSET_GP_MMU 0x03000
26
27#define MALI_OFFSET_PP0 0x08000
28#define MALI_OFFSET_PP0_MMU 0x04000
29#define MALI_OFFSET_PP1 0x0A000
30#define MALI_OFFSET_PP1_MMU 0x05000
31#define MALI_OFFSET_PP2 0x0C000
32#define MALI_OFFSET_PP2_MMU 0x06000
33#define MALI_OFFSET_PP3 0x0E000
34#define MALI_OFFSET_PP3_MMU 0x07000
35
36#define MALI_OFFSET_PP4 0x28000
37#define MALI_OFFSET_PP4_MMU 0x1C000
38#define MALI_OFFSET_PP5 0x2A000
39#define MALI_OFFSET_PP5_MMU 0x1D000
40#define MALI_OFFSET_PP6 0x2C000
41#define MALI_OFFSET_PP6_MMU 0x1E000
42#define MALI_OFFSET_PP7 0x2E000
43#define MALI_OFFSET_PP7_MMU 0x1F000
44
45#define MALI_OFFSET_L2_RESOURCE0 0x01000
46#define MALI_OFFSET_L2_RESOURCE1 0x10000
47#define MALI_OFFSET_L2_RESOURCE2 0x11000
48
49#define MALI400_OFFSET_L2_CACHE0 MALI_OFFSET_L2_RESOURCE0
50#define MALI450_OFFSET_L2_CACHE0 MALI_OFFSET_L2_RESOURCE1
51#define MALI450_OFFSET_L2_CACHE1 MALI_OFFSET_L2_RESOURCE0
52#define MALI450_OFFSET_L2_CACHE2 MALI_OFFSET_L2_RESOURCE2
53#define MALI470_OFFSET_L2_CACHE1 MALI_OFFSET_L2_RESOURCE0
54
55#define MALI_OFFSET_BCAST 0x13000
56#define MALI_OFFSET_DLBU 0x14000
57
58#define MALI_OFFSET_PP_BCAST 0x16000
59#define MALI_OFFSET_PP_BCAST_MMU 0x15000
60
61#define MALI_OFFSET_PMU 0x02000
62#define MALI_OFFSET_DMA 0x12000
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S		 63
64/* Mali-300 */
65
66#define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
67 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
68
69#define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
70 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
71
72/* Mali-400 */
73
74#define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
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S		 75 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
76 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
77 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq)
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S		 78
79#define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
80 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
02af6beb 81 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
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S		 82
83#define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
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S		 84 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
85 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
86 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
87 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq)
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S		 88
89#define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
90 MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
02af6beb 91 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
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S		 92
93#define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
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S		 94 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
95 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
96 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
97 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
98 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq)
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S		 99
100#define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
101 MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
02af6beb 102 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU)
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S		 103
104#define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
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S		 105 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \
106 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
107 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
108 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
109 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
110 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq)
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S		 111
112#define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
113 MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
02af6beb 114 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
6fa3eb70 115
02af6beb 116 /* Mali-450 */
6fa3eb70 117#define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
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S		 118 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
119 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
120 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
121 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
122 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
123 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
124 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
125 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
126 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
127 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
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S		 128
129#define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
130 MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
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S		 131 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
132
6fa3eb70 133#define MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
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S		 134 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
135 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
136 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
137 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
138 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
139 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
140 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
141 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
142 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
143 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
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S		 144
145#define MALI_GPU_RESOURCES_MALI450_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
146 MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
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S		 147 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
148
6fa3eb70 149#define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
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S		 150 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
151 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
152 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
153 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
154 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
155 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
156 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \
157 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
158 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
159 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
160 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
161 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
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S		 162
163#define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
164 MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
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S		 165 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
166
6fa3eb70 167#define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
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S		 168 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
169 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
170 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
171 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
172 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
173 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
174 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \
175 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP4, pp3_irq, base_addr + MALI_OFFSET_PP4_MMU, pp3_mmu_irq) \
176 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP5, pp4_irq, base_addr + MALI_OFFSET_PP5_MMU, pp4_mmu_irq) \
177 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP6, pp5_irq, base_addr + MALI_OFFSET_PP6_MMU, pp5_mmu_irq) \
178 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
179 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
180 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
181 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
182 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
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S		 183
184#define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
185 MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
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S		 186 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
187
6fa3eb70 188#define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
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S		 189 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \
190 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
191 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \
192 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
193 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
194 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
195 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \
196 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \
197 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP4, pp4_irq, base_addr + MALI_OFFSET_PP4_MMU, pp4_mmu_irq) \
198 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP5, pp5_irq, base_addr + MALI_OFFSET_PP5_MMU, pp5_mmu_irq) \
199 MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + MALI_OFFSET_PP6, pp6_irq, base_addr + MALI_OFFSET_PP6_MMU, pp6_mmu_irq) \
200 MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + MALI_OFFSET_PP7, pp7_irq, base_addr + MALI_OFFSET_PP7_MMU, pp7_mmu_irq) \
201 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
202 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
203 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
204 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \
205 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA)
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S		 206
207#define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
208 MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
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S		 209 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
210
211 /* Mali - 470 */
212#define MALI_GPU_RESOURCES_MALI470_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \
213 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \
214 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
215 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
216 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
217 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
218 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
219 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
220
221#define MALI_GPU_RESOURCES_MALI470_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \
222 MALI_GPU_RESOURCES_MALI470_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \
223 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
224
225#define MALI_GPU_RESOURCES_MALI470_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
226 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \
227 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
228 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
229 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
230 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
231 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
232 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
233 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
234
235#define MALI_GPU_RESOURCES_MALI470_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
236 MALI_GPU_RESOURCES_MALI470_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
237 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
238
239#define MALI_GPU_RESOURCES_MALI470_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
240 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \
241 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
242 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
243 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
244 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
245 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
246 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
247 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
248 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
249
250#define MALI_GPU_RESOURCES_MALI470_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
251 MALI_GPU_RESOURCES_MALI470_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
252 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
253
254#define MALI_GPU_RESOURCES_MALI470_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
255 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \
256 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \
257 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \
258 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \
259 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \
260 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \
261 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \
262 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \
263 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \
264 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU)
265
266#define MALI_GPU_RESOURCES_MALI470_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
267 MALI_GPU_RESOURCES_MALI470_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
268 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \
269
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S		 270#define MALI_GPU_RESOURCE_L2(addr) \
271 { \
272 .name = "Mali_L2", \
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S		 273 .flags = IORESOURCE_MEM, \
274 .start = addr, \
275 .end = addr + 0x200, \
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S		 276 },
277
278#define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \
279 { \
280 .name = "Mali_GP", \
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S		 281 .flags = IORESOURCE_MEM, \
282 .start = gp_addr, \
283 .end = gp_addr + 0x100, \
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S		 284 }, \
285 { \
286 .name = "Mali_GP_IRQ", \
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S		 287 .flags = IORESOURCE_IRQ, \
288 .start = gp_irq, \
289 .end = gp_irq, \
6fa3eb70 290 }, \
02af6beb 291
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S		 292#define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \
293 { \
294 .name = "Mali_GP", \
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S		 295 .flags = IORESOURCE_MEM, \
296 .start = gp_addr, \
297 .end = gp_addr + 0x100, \
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S		 298 }, \
299 { \
300 .name = "Mali_GP_IRQ", \
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S		 301 .flags = IORESOURCE_IRQ, \
302 .start = gp_irq, \
303 .end = gp_irq, \
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S		 304 }, \
305 { \
306 .name = "Mali_GP_MMU", \
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S		 307 .flags = IORESOURCE_MEM, \
308 .start = gp_mmu_addr, \
309 .end = gp_mmu_addr + 0x100, \
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S		 310 }, \
311 { \
312 .name = "Mali_GP_MMU_IRQ", \
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S		 313 .flags = IORESOURCE_IRQ, \
314 .start = gp_mmu_irq, \
315 .end = gp_mmu_irq, \
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S		 316 },
317
318#define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \
319 { \
320 .name = "Mali_PP", \
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S		 321 .flags = IORESOURCE_MEM, \
322 .start = pp_addr, \
323 .end = pp_addr + 0x1100, \
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S		 324 }, \
325 { \
326 .name = "Mali_PP_IRQ", \
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S		 327 .flags = IORESOURCE_IRQ, \
328 .start = pp_irq, \
329 .end = pp_irq, \
6fa3eb70 330 }, \
02af6beb 331
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S		 332#define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \
333 { \
334 .name = "Mali_PP" #id, \
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S		 335 .flags = IORESOURCE_MEM, \
336 .start = pp_addr, \
337 .end = pp_addr + 0x1100, \
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S		 338 }, \
339 { \
340 .name = "Mali_PP" #id "_IRQ", \
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S		 341 .flags = IORESOURCE_IRQ, \
342 .start = pp_irq, \
343 .end = pp_irq, \
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S		 344 }, \
345 { \
346 .name = "Mali_PP" #id "_MMU", \
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S		 347 .flags = IORESOURCE_MEM, \
348 .start = pp_mmu_addr, \
349 .end = pp_mmu_addr + 0x100, \
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S		 350 }, \
351 { \
352 .name = "Mali_PP" #id "_MMU_IRQ", \
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S		 353 .flags = IORESOURCE_IRQ, \
354 .start = pp_mmu_irq, \
355 .end = pp_mmu_irq, \
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S		 356 },
357
358#define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \
359 { \
360 .name = "Mali_MMU", \
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S		 361 .flags = IORESOURCE_MEM, \
362 .start = mmu_addr, \
363 .end = mmu_addr + 0x100, \
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S		 364 }, \
365 { \
366 .name = "Mali_MMU_IRQ", \
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S		 367 .flags = IORESOURCE_IRQ, \
368 .start = mmu_irq, \
369 .end = mmu_irq, \
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S		 370 },
371
372#define MALI_GPU_RESOURCE_PMU(pmu_addr) \
373 { \
374 .name = "Mali_PMU", \
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S		 375 .flags = IORESOURCE_MEM, \
376 .start = pmu_addr, \
377 .end = pmu_addr + 0x100, \
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S		 378 },
379
380#define MALI_GPU_RESOURCE_DMA(dma_addr) \
381 { \
382 .name = "Mali_DMA", \
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S		 383 .flags = IORESOURCE_MEM, \
384 .start = dma_addr, \
385 .end = dma_addr + 0x100, \
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S		 386 },
387
388#define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \
389 { \
390 .name = "Mali_DLBU", \
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S		 391 .flags = IORESOURCE_MEM, \
392 .start = dlbu_addr, \
393 .end = dlbu_addr + 0x100, \
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S		 394 },
395
396#define MALI_GPU_RESOURCE_BCAST(bcast_addr) \
397 { \
398 .name = "Mali_Broadcast", \
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S		 399 .flags = IORESOURCE_MEM, \
400 .start = bcast_addr, \
401 .end = bcast_addr + 0x100, \
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S		 402 },
403
404#define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \
405 { \
406 .name = "Mali_PP_Broadcast", \
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S		 407 .flags = IORESOURCE_MEM, \
408 .start = pp_addr, \
409 .end = pp_addr + 0x1100, \
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S		 410 }, \
411 { \
412 .name = "Mali_PP_Broadcast_IRQ", \
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S		 413 .flags = IORESOURCE_IRQ, \
414 .start = pp_irq, \
415 .end = pp_irq, \
6fa3eb70 416 }, \
02af6beb 417
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S		 418#define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \
419 { \
420 .name = "Mali_PP_MMU_Broadcast", \
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S		 421 .flags = IORESOURCE_MEM, \
422 .start = pp_mmu_bcast_addr, \
423 .end = pp_mmu_bcast_addr + 0x100, \
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S		 424 },
425
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S		 426 struct mali_gpu_utilization_data {
427 unsigned int utilization_gpu; /* Utilization for GP and all PP cores combined, 0 = no utilization, 256 = full utilization */
428 unsigned int utilization_gp; /* Utilization for GP core only, 0 = no utilization, 256 = full utilization */
429 unsigned int utilization_pp; /* Utilization for all PP cores combined, 0 = no utilization, 256 = full utilization */
430 };
431
432 struct mali_gpu_clk_item {
433 unsigned int clock; /* unit(MHz) */
434 unsigned int vol;
435 };
436
437 struct mali_gpu_clock {
438 struct mali_gpu_clk_item *item;
439 unsigned int num_of_steps;
440 };
441
442 struct mali_gpu_device_data {
443 /* Shared GPU memory */
444 unsigned long shared_mem_size;
445
446 /*
447 * Mali PMU switch delay.
448 * Only needed if the power gates are connected to the PMU in a high fanout
449 * network. This value is the number of Mali clock cycles it takes to
450 * enable the power gates and turn on the power mesh.
451 * This value will have no effect if a daisy chain implementation is used.
452 */
453 u32 pmu_switch_delay;
454
455 /* Mali Dynamic power domain configuration in sequence from 0-11
456 * GP PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7, L2$0 L2$1 L2$2
457 */
458 u16 pmu_domain_config[12];
459
460 /* Dedicated GPU memory range (physical). */
461 unsigned long dedicated_mem_start;
462 unsigned long dedicated_mem_size;
463
464 /* Frame buffer memory to be accessible by Mali GPU (physical) */
465 unsigned long fb_start;
466 unsigned long fb_size;
467
468 /* Max runtime [ms] for jobs */
469 int max_job_runtime;
470
471 /* Report GPU utilization and related control in this interval (specified in ms) */
472 unsigned long control_interval;
473
474 /* Function that will receive periodic GPU utilization numbers */
475 void (*utilization_callback)(struct mali_gpu_utilization_data *data);
476
477 /* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */
478 int (*set_freq)(int setting_clock_step);
479 /* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */
480 void (*get_clock_info)(struct mali_gpu_clock **data);
481 /* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */
482 int (*get_freq)(void);
483 };
484
485 /**
486 * Pause the scheduling and power state changes of Mali device driver.
487 * mali_dev_resume() must always be called as soon as possible after this function
488 * in order to resume normal operation of the Mali driver.
6fa3eb70 489 */
02af6beb 490 void mali_dev_pause(void);
6fa3eb70 491
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S		 492 /**
493 * Resume scheduling and allow power changes in Mali device driver.
494 * This must always be called after mali_dev_pause().
6fa3eb70 495 */
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S		 496 void mali_dev_resume(void);
497
498 /** @brief Set the desired number of PP cores to use.
499 *
500 * The internal Mali PMU will be used, if present, to physically power off the PP cores.
501 *
502 * @param num_cores The number of desired cores
503 * @return 0 on success, otherwise error. -EINVAL means an invalid number of cores was specified.
504 */
505 int mali_perf_set_num_pp_cores(unsigned int num_cores);
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S		 506
507#endif
kernel source for telekom puls (alcatel/mediatek)