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import PULS_20180308
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / dispsys / mt8127 / ddp_debug.c
CommitLineData
6fa3eb70
S		 1#include <linux/string.h>
2#include <linux/uaccess.h>
3
4#include <linux/debugfs.h>
5
6#include <linux/aee.h>
7#include <linux/disp_assert_layer.h>
8//#include <linux/unistd.h>
9//#include <linux/fcntl.h>
10
11#include <linux/dma-mapping.h>
12#include "ddp_debug.h"
13#include "ddp_reg.h"
14#include "ddp_bls.h"
15#include "ddp_color.h"
16#include "ddp_drv.h"
17//#include "ddp_dpfd.h"
18//#include "ddp_rot.h"
19//#include "ddp_scl.h"
20#include "ddp_wdma.h"
21#include "ddp_hal.h"
22#include "ddp_path.h"
23
24#include "disp_drv_ddp.h"
25//#include "ddp_dpfd.h"
26#include <mach/m4u.h>
27#include "disp_drv.h"
28
29#ifdef CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT
30#include "tz_cross/trustzone.h"
31#include "tz_cross/ta_mem.h"
32#include "trustzone/kree/system.h"
33#include "trustzone/kree/mem.h"
34#include "tz_cross/tz_ddp.h"
35#endif
36
37#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
38#include "mobicore_driver_api.h"
39extern unsigned int tplay_handle_virt_addr;
40extern unsigned int init_tplay_handle(void);
41extern unsigned int get_tplay_handle();
42extern int set_tplay_handle_addr_request(void);
43
44extern enum mc_result late_init_session_tl(void);
45extern enum mc_result late_init_session_drv(void);
46extern enum mc_result late_open_mobicore_device(void);
47#endif
48
49// ---------------------------------------------------------------------------
50// External variable declarations
51// ---------------------------------------------------------------------------
52// ---------------------------------------------------------------------------
53// Debug Options
54// ---------------------------------------------------------------------------
55
56struct DDP_MMP_Events_t DDP_MMP_Events;
57
58struct dentry *debugfs = NULL;
59unsigned int gUltraLevel = 4; // RDMA ultra aggressive level
60unsigned int gEnableUltra = 0;
61
62static const long int DEFAULT_LOG_FPS_WND_SIZE = 30;
63
64
65unsigned char pq_debug_flag=0;
66unsigned char aal_debug_flag=0;
67
68#ifdef CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT
69// these 2 APIs are used for accessing ddp_session / ddp_mem_session with TEE
70extern KREE_SESSION_HANDLE ddp_session_handle(void);
71extern KREE_SESSION_HANDLE ddp_mem_session_handle(void);
72#endif
73
74
75/*for MTK_HDMI_MAIN_PATH*/
76unsigned char *disp_module_name[DISP_MODULE_MAX+1] = {
77 "DISP_MODULE_OVL", /* 0 DISP_MODULE_OVL*/
78 "DISP_MODULE_COLOR", /* 1 */
79 "DISP_MODULE_BLS",/* 2*/
80 "DISP_MODULE_WDMA",/* 3*/
81 "DISP_MODULE_RDMA0",/*4*/
82 "DISP_MODULE_RDMA1",/*5*/
83 "DISP_MODULE_DPI0",/*6*/
84 "DISP_MODULE_DPI1",/*7*/
85 "DISP_MODULE_DBI",
86 "DISP_MODULE_DSI_CMD",
87 "DISP_MODULE_DSI_VDO",
88 "DISP_MODULE_CONFIG",
89 "DISP_MODULE_MUTEX",
90 "DISP_MODULE_CMDQ",
91 "DISP_MODULE_G2D", /**/
92 "DISP_MODULE_SMI", /*15*/
93 "DISP_MODULE_MAX"
94};
95
96static char STR_HELP[] =
97 "\n"
98 "USAGE\n"
99 " echo [ACTION]... > dispsys\n"
100 "\n"
101 "ACTION\n"
102 " regr:addr\n"
103 "\n"
104 " regw:addr,value\n"
105 "\n"
106 " dbg_log:0|1\n"
107 "\n"
108 " irq_log:0|1\n"
109 "\n"
110 " irq_err_log:0|1\n"
111 "\n"
112 " backlight:level\n"
113 "\n"
114 " dump_aal:arg\n"
115 "\n"
116 " mmp\n"
117 "\n"
118 " dump_reg:moduleID\n"
119 "\n"
120 " dpfd_ut1:channel\n"
121 ;
122
123void ddp_enable_bls(int BLS_switch)
124{
125
126 DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
127
128 if(BLS_switch == FALSE)
129 DISP_REG_SET(DISP_REG_BLS_EN, 0x00010000);
130 else
131 DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001);
132
133 DISP_MSG("aal_debug_flag changed,aal_debug_flag=%d, set BLS_EN=%x", aal_debug_flag, DISP_REG_GET(DISP_REG_BLS_EN));
134 DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
135
136}
137
138void init_ddp_mmp_events(void)
139{
140 if (DDP_MMP_Events.DDP == 0)
141 {
142 DDP_MMP_Events.DDP = MMProfileRegisterEvent(MMP_RootEvent, "DDP");
143 DDP_MMP_Events.MutexParent = MMProfileRegisterEvent(DDP_MMP_Events.DDP, "Mutex");
144 DDP_MMP_Events.Mutex[0] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex0");
145 DDP_MMP_Events.Mutex[1] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex1");
146 DDP_MMP_Events.Mutex[2] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex2");
147 DDP_MMP_Events.Mutex[3] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex3");
148 DDP_MMP_Events.Mutex[4] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex4");
149 DDP_MMP_Events.Mutex[5] = MMProfileRegisterEvent(DDP_MMP_Events.MutexParent, "Mutex5");
150 DDP_MMP_Events.BackupReg = MMProfileRegisterEvent(DDP_MMP_Events.DDP, "BackupReg");
151 DDP_MMP_Events.DDP_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP, "DDP_IRQ");
152 DDP_MMP_Events.SCL_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "SCL_IRQ");
153 DDP_MMP_Events.ROT_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "ROT_IRQ");
154 DDP_MMP_Events.OVL_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "OVL_IRQ");
155 DDP_MMP_Events.WDMA0_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "WDMA0_IRQ");
156 DDP_MMP_Events.WDMA1_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "WDMA1_IRQ");
157 DDP_MMP_Events.RDMA0_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "RDMA0_IRQ");
158 DDP_MMP_Events.RDMA1_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "RDMA1_IRQ");
159 DDP_MMP_Events.COLOR_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "COLOR_IRQ");
160 DDP_MMP_Events.BLS_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "BLS_IRQ");
161 DDP_MMP_Events.TDSHP_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "TDSHP_IRQ");
162 DDP_MMP_Events.CMDQ_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "CMDQ_IRQ");
163 DDP_MMP_Events.Mutex_IRQ = MMProfileRegisterEvent(DDP_MMP_Events.DDP_IRQ, "Mutex_IRQ");
164 DDP_MMP_Events.WAIT_INTR = MMProfileRegisterEvent(DDP_MMP_Events.DDP, "WAIT_IRQ");
165 DDP_MMP_Events.Debug = MMProfileRegisterEvent(DDP_MMP_Events.DDP, "Debug");
166
167 MMProfileEnableEventRecursive(DDP_MMP_Events.MutexParent, 1);
168 MMProfileEnableEventRecursive(DDP_MMP_Events.BackupReg, 1);
169 //MMProfileEnableEventRecursive(DDP_MMP_Events.DDP_IRQ, 1);
170 MMProfileEnableEventRecursive(DDP_MMP_Events.WAIT_INTR, 1);
171 }
172}
173
174// ---------------------------------------------------------------------------
175// Command Processor
176// ---------------------------------------------------------------------------
177static char dbg_buf[2048];
178extern void mtkfb_dump_layer_info(void);
179extern unsigned int gNeedToRecover;
180extern unsigned int isAEEEnabled;
181static void process_dbg_opt(const char *opt)
182{
183 char *buf = dbg_buf + strlen(dbg_buf);
184 if (0 == strncmp(opt, "regr:", 5))
185 {
186 char *p = (char *)opt + 5;
187 unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
188
4b9e9796 189 if (addr >= 0xf4000000 && addr <= 0xf5000000)
6fa3eb70
S		 190 {
191 unsigned int regVal = DISP_REG_GET(addr);
192 DISP_MSG("regr: 0x%08X = 0x%08X\n", addr, regVal);
193 sprintf(buf, "regr: 0x%08X = 0x%08X\n", addr, regVal);
194 } else {
195 goto Error;
196 }
197 }
198 else if (0 == strncmp(opt, "regw:", 5))
199 {
200 char *p = (char *)opt + 5;
201 unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
202 unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
4b9e9796 203 if (addr >= 0xf4000000 && addr <= 0xf5000000)
6fa3eb70
S		 204 {
205 unsigned int regVal;
206 DISP_REG_SET(addr, val);
207 regVal = DISP_REG_GET(addr);
208 DISP_DBG("regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
209 sprintf(buf, "regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
210 } else {
211 goto Error;
212 }
213 }
214 else if (0 == strncmp(opt, "dbg_log:", 8))
215 {
216 char *p = (char *)opt + 8;
217 unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
218 if (enable)
219 dbg_log = 1;
220 else
221 dbg_log = 0;
222
223 sprintf(buf, "dbg_log: %d\n", dbg_log);
224 }
225 else if (0 == strncmp(opt, "irq_log:", 8))
226 {
227 char *p = (char *)opt + 8;
228 unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
229 if (enable)
230 irq_log = 1;
231 else
232 irq_log = 0;
233
234 sprintf(buf, "irq_log: %d\n", irq_log);
235 }
236#ifdef CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT
237 else if (0 == strncmp(opt, "tee_dbg_log:", 12))
238 {
239 char *p = (char *)opt + 12;
240 unsigned int value = (unsigned int)simple_strtoul(p, &p, 10);
241
242 MTEEC_PARAM param[4];
243 unsigned int paramTypes;
244 TZ_RESULT ret;
245
246 param[0].value.a = value;
247
248
249 paramTypes = TZ_ParamTypes1(TZPT_VALUE_INPUT);
250
251
252 ret = KREE_TeeServiceCall(ddp_session_handle(), TZCMD_DDP_SET_DEBUG_LOG, paramTypes, param);
253 if (ret!= TZ_RESULT_SUCCESS)
254 {
255 DISP_ERR("KREE_TeeServiceCall(TZCMD_DDP_SET_DEBUG_LOG) fail, ret=%d \n", ret);
256 }
257 }
258#endif
259 else if (0 == strncmp(opt, "irq_err_log:", 12))
260 {
261 char *p = (char *)opt + 12;
262 unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
263 if (enable)
264 irq_err_log = 1;
265 else
266 irq_err_log = 0;
267
268 sprintf(buf, "irq_err_log: %d\n", irq_err_log);
269 }
270 else if (0 == strncmp(opt, "backlight:", 10))
271 {
272 char *p = (char *)opt + 10;
273 unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
274
275 if (level)
276 {
277 disp_bls_set_backlight(level);
278 sprintf(buf, "backlight: %d\n", level);
279 } else {
280 goto Error;
281 }
282 }
283 else if (0 == strncmp(opt, "dump_reg:", 9))
284 {
285 char *p = (char *)opt + 9;
286 unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
287 DISP_MSG("process_dbg_opt, module=%d \n", module);
288 if (module<DISP_MODULE_MAX)
289 {
290 disp_dump_reg(module);
291 sprintf(buf, "dump_reg: %d\n", module);
292 } else {
293 DISP_MSG("process_dbg_opt2, module=%d \n", module);
294 goto Error;
295 }
296 }
297 else if (0 == strncmp(opt, "dump_aal:", 9))
298 {
299 char *p = (char *)opt + 9;
300 unsigned int arg = (unsigned int) simple_strtoul(p, &p, 10);
301 if (arg == 0)
302 {
303 int i;
304 unsigned int hist[LUMA_HIST_BIN];
305 disp_get_hist(hist);
306 for (i = 0; i < LUMA_HIST_BIN; i++)
307 {
308 DISP_DBG("LUMA_HIST_%02d: %d\n", i, hist[i]);
309 sprintf(dbg_buf + strlen(dbg_buf), "LUMA_HIST_%2d: %d\n", i, hist[i]);
310 }
311 }
312 else if (arg == 1)
313 {
314 int i;
315 DISP_AAL_PARAM param;
316
317 GetUpdateMutex();
318 memcpy(&param, get_aal_config(), sizeof(DISP_AAL_PARAM));
319 ReleaseUpdateMutex();
320
321 DISP_DBG("pwmDuty: %lu\n", param.pwmDuty);
322 sprintf(dbg_buf + strlen(dbg_buf), "pwmDuty: %lu\n", param.pwmDuty);
323 for (i = 0; i < LUMA_CURVE_POINT; i++)
324 {
325 DISP_DBG("lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
326 sprintf(dbg_buf + strlen(dbg_buf), "lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
327 }
328 }
329 }
330 else if (0 == strncmp(opt, "debug:", 6))
331 {
332 char *p = (char *)opt + 6;
333 unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
334 if(enable==1)
335 {
336 printk("[DDP] debug=1, trigger AEE\n");
337 aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
338 }
339 else if(enable==2)
340 {
341 ddp_mem_test();
342 }
343 else if(enable==3)
344 {
345 ddp_mem_test2();
346 }
347 else if(enable==4)
348 {
349 DDP_IRQ_ERR("test 4");
350 }
351 else if(enable==5)
352 {
353 DISP_MSG("SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x, \
354 color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
355 *(volatile unsigned int*)0xf4010450,
356 *(volatile unsigned int*)0xf4010454,
357 *(volatile unsigned int*)0xf4010000,
358 *(volatile unsigned int*)0xf4010600,
359 *(volatile unsigned int*)0xf4010604,
360 *(volatile unsigned int*)0xf4010610,
361 *(volatile unsigned int*)0xf4010614,
362 *(volatile unsigned int*)0xf400b404,
363 *(volatile unsigned int*)0xf400b408,
364 DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
365 DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
366 sprintf(dbg_buf + strlen(dbg_buf), "SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x,"
367 "color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
368 *(volatile unsigned int*)0xf4010450,
369 *(volatile unsigned int*)0xf4010454,
370 *(volatile unsigned int*)0xf4010000,
371 *(volatile unsigned int*)0xf4010600,
372 *(volatile unsigned int*)0xf4010604,
373 *(volatile unsigned int*)0xf4010610,
374 *(volatile unsigned int*)0xf4010614,
375 *(volatile unsigned int*)0xf400b404,
376 *(volatile unsigned int*)0xf400b408,
377 DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
378 DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
379 }
380 else if(enable==6)
381 {
382 mtkfb_dump_layer_info();
383 }
384 else if (enable == 7)
385 {
386 gNeedToRecover = 1;
387 }
388 else if(enable==8)
389 {
390 DISP_MSG("disp_clock_check start! \n");
391 disp_clock_check();
392 DISP_MSG("disp_clock_check end! \n");
393 }
394 else if(enable==9)
395 {
396 DISP_MSG("ddp dump info ! \n");
397 ddp_dump_info(DISP_MODULE_OVL);
398 ddp_dump_info(DISP_MODULE_RDMA0);
399 ddp_dump_info(DISP_MODULE_COLOR);
400 ddp_dump_info(DISP_MODULE_BLS);
401 ddp_dump_info(DISP_MODULE_CONFIG);
402 ddp_dump_info(DISP_MODULE_MUTEX);
403 ddp_dump_info(DISP_MODULE_RDMA1);
404 ddp_dump_info(DISP_MODULE_WDMA);
405 ddp_dump_info(DISP_MODULE_DSI_CMD);
406 ddp_dump_info(DISP_MODULE_DPI0);
407 }
408 else if(enable==10)
409 {
410 DISP_MSG("ddp dump reg ! \n");
411 disp_dump_reg(DISP_MODULE_OVL);
412 disp_dump_reg(DISP_MODULE_RDMA0);
413 disp_dump_reg(DISP_MODULE_COLOR);
414 disp_dump_reg(DISP_MODULE_BLS);
415 disp_dump_reg(DISP_MODULE_CONFIG);
416 disp_dump_reg(DISP_MODULE_MUTEX);
417 disp_dump_reg(DISP_MODULE_RDMA1);
418 disp_dump_reg(DISP_MODULE_WDMA);
419
420 disp_print_reg(DISP_MODULE_OVL);
421 disp_print_reg(DISP_MODULE_RDMA0);
422 disp_print_reg(DISP_MODULE_COLOR);
423 disp_print_reg(DISP_MODULE_BLS);
424 disp_print_reg(DISP_MODULE_CONFIG);
425 disp_print_reg(DISP_MODULE_MUTEX);
426 disp_print_reg(DISP_MODULE_RDMA1);
427 disp_print_reg(DISP_MODULE_WDMA);
428 disp_print_reg(DISP_MODULE_DSI_CMD);
429 disp_print_reg(DISP_MODULE_DPI0);
430 }
431 else if((enable>=11)&&(enable<=15))
432 {
433 gEnableUltra = 1;
434 gUltraLevel = enable - 11;
435 sprintf(buf, "gUltraLevel: %d, DISP_REG_RDMA_MEM_GMC_SETTING_0=0x%x, DISP_REG_RDMA_FIFO_CON=0x%x \n",
436 gUltraLevel,
437 DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
438 DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
439 DISP_MSG("ddp debug set gUltraLevel = %d, DISP_REG_RDMA_MEM_GMC_SETTING_0=0x%x, DISP_REG_RDMA_FIFO_CON=0x%x \n",
440 gUltraLevel,
441 DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
442 DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
443 }
444 else if(enable==21)
445 {
446 sprintf(buf, "base:\n\
447 config f4+0 \n\
448 ovl 7\n\
449 rdma 8\n\
450 rdma1 12\n\
451 wdma 9\n\
452 bls a\n\
453 color b\n\
454 dsi c\n\
455 dpi d\n\
456 mm_mutex e\n\
457 mm_cmdq f\n\
458 smi_larb0 10\n\
459 smi_common 11\n");
460 }
461 else if(enable==22)
462 {
463 sprintf(buf, "isAEEEnabled=%d \n",isAEEEnabled);
464 DISP_MSG("isAEEEnabled=%d \n", isAEEEnabled);
465 }
466 }
467
468 else if (0 == strncmp(opt, "mmp", 3))
469 {
470 init_ddp_mmp_events();
471 }
472 else if (0 == strncmp(opt, "dpfd_ut1:", 9))
473 {
474 //char *p = (char *)opt + 9;
475 //unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
476 //ddpk_testfunc_1(channel);
477 }
478 else if (0 == strncmp(opt, "dpfd_ut2:", 9))
479 {
480 //char *p = (char *)opt + 9;
481 //unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
482 //ddpk_testfunc_2(channel);
483 }
484 else if (0 == strncmp(opt, "dpfd:log", 8))
485 {
486 }
487 else if (0 == strncmp(opt, "pqon", 4))
488 {
489 pq_debug_flag=0;
490 sprintf(buf, "Turn on PQ %d\n", pq_debug_flag);
491 }
492 else if (0 == strncmp(opt, "pqoff", 5))
493 {
494 pq_debug_flag=1;
495 sprintf(buf, "Turn off PQ %d\n", pq_debug_flag);
496 }
497 else if (0 == strncmp(opt, "pqdemo", 6))
498 {
499 pq_debug_flag=2;
500 sprintf(buf, "Turn on PQ (demo) %d\n", pq_debug_flag);
501 }
502 else if (0 == strncmp(opt, "pqstop", 6))
503 {
504 pq_debug_flag=3;
505 sprintf(buf, "Stop mutex update %d\n", pq_debug_flag);
506 }
507 else if (0 == strncmp(opt, "aalon", 5))
508 {
509 aal_debug_flag=0;
510 sprintf(buf, "resume aal update %d\n", aal_debug_flag);
511 }
512 else if (0 == strncmp(opt, "aaloff", 6))
513 {
514 aal_debug_flag=1;
515 sprintf(buf, "suspend aal update %d\n", aal_debug_flag);
516 }
517 else if (0 == strncmp(opt, "color_win:", 10))
518 {
519 char *p = (char *)opt + 10;
520 unsigned int sat_upper, sat_lower, hue_upper, hue_lower;
521 sat_upper = (unsigned int) simple_strtoul(p, &p, 10);
522 p++;
523 sat_lower = (unsigned int) simple_strtoul(p, &p, 10);
524 p++;
525 hue_upper = (unsigned int) simple_strtoul(p, &p, 10);
526 p++;
527 hue_lower = (unsigned int) simple_strtoul(p, &p, 10);
528 DISP_MSG("Set color_win: %u, %u, %u, %u\n", sat_upper, sat_lower, hue_upper, hue_lower);
529 disp_color_set_window(sat_upper, sat_lower, hue_upper, hue_lower);
530 }
531#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
532 else if (0 == strncmp(opt, "handle_init", 11))
533 {
534 unsigned int va = init_tplay_handle();
535 DISP_MSG("debug handle_init, tplay_handle_virt_addr=0x%x \n", va);
536 }
537 else if (0 == strncmp(opt, "handle_check", 12))
538 {
539 unsigned int va = get_tplay_handle();
540 DISP_MSG("debug handle_check, tplay_handle_virt_addr=0x%x \n", va);
541 unsigned int *x = (unsigned int *)va;
542 *x = 0xff;
543 DISP_MSG("debug handle_check, write and read 0x%x \n", *x);
544 }
545 else if (0 == strncmp(opt, "handle_set", 10))
546 {
547 int ret = set_tplay_handle_addr_request();
548 DISP_MSG("debug handle_set, ret=%d \n", ret);
549 }
550 else if (0 == strncmp(opt, "svp_init", 8))
551 {
552 DISP_MSG("initialize svp-ddp sessions \n");
553 late_open_mobicore_device();
554 late_init_session_drv();
555 late_init_session_tl();
556 }
557#endif
558 else
559 {
560 goto Error;
561 }
562
563 return;
564
565Error:
566 DISP_ERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
567}
568
569
570static void process_dbg_cmd(char *cmd)
571{
572 char *tok;
573
574 DISP_DBG("cmd: %s\n", cmd);
575 memset(dbg_buf, 0, sizeof(dbg_buf));
576 while ((tok = strsep(&cmd, " ")) != NULL)
577 {
578 process_dbg_opt(tok);
579 }
580}
581
582
583// ---------------------------------------------------------------------------
584// Debug FileSystem Routines
585// ---------------------------------------------------------------------------
586
587static ssize_t debug_open(struct inode *inode, struct file *file)
588{
589 file->private_data = inode->i_private;
590 return 0;
591}
592
593
594static char cmd_buf[512];
595
596static ssize_t debug_read(struct file *file,
597 char __user *ubuf, size_t count, loff_t *ppos)
598{
599 if (strlen(dbg_buf))
600 return simple_read_from_buffer(ubuf, count, ppos, dbg_buf, strlen(dbg_buf));
601 else
602 return simple_read_from_buffer(ubuf, count, ppos, STR_HELP, strlen(STR_HELP));
603
604}
605
606
607static ssize_t debug_write(struct file *file,
608 const char __user *ubuf, size_t count, loff_t *ppos)
609{
610 const int debug_bufmax = sizeof(cmd_buf) - 1;
611 size_t ret;
612
613 ret = count;
614
615 if (count > debug_bufmax)
616 count = debug_bufmax;
617
618 if (copy_from_user(&cmd_buf, ubuf, count))
619 return -EFAULT;
620
621 cmd_buf[count] = 0;
622
623 process_dbg_cmd(cmd_buf);
624
625 return ret;
626}
627
628
629static struct file_operations debug_fops = {
630 .read = debug_read,
631 .write = debug_write,
632 .open = debug_open,
633};
634
635
636void ddp_debug_init(void)
637{
638#if 1
639debugfs = debugfs_create_file("dispsys",
640 S_IFREG|S_IRUGO, NULL, (void *)0, &debug_fops);
641#endif
642}
643
644
645void ddp_debug_exit(void)
646{
647#if 1
648debugfs_remove(debugfs);
649#endif
650}
651
652
653#include <linux/vmalloc.h>
654#define DDP_TEST_WIDTH 64
655#define DDP_TEST_HEIGHT 64
656#define DDP_TEST_BPP 3
657#define DDP_MUTEX_FOR_ROT_SCL_WDMA 1
658extern unsigned char data_rgb888_64x64[12288];
659extern unsigned char data_rgb888_64x64_golden[12288];
660int ddp_mem_test2(void)
661{
662 int result = 0;
663#if 0
664 unsigned int* pSrc;
665 unsigned int* pDst;
666 DdpkBitbltConfig pddp;
667
668 pSrc= vmalloc(DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
669 if(pSrc==0)
670 {
671 printk("[DDP] error: dma_alloc_coherent error! dma memory not available.\n");
672 return 0;
673 }
674 else
675 {
676 printk("[ddp] pSrc=0x%x \n", (unsigned int)pSrc);
677 }
678 memcpy((void*)pSrc, data_rgb888_64x64, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
679
680 pDst= vmalloc(DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
681 if(pDst==0)
682 {
683 printk("[DDP] error: dma_alloc_coherent error! dma memory not available.\n");
684 return 0;
685 }
686 else
687 {
688 printk("[ddp] pDst=0x%x\n", (unsigned int)pDst);
689 }
690 memset((void*)pDst, 0, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
691
692 /*
693 disp_power_on(DISP_MODULE_ROT);
694 disp_power_on(DISP_MODULE_SCL);
695 disp_power_on(DISP_MODULE_WDMA);
696 */
697 // config port to virtual
698 {
699 M4U_PORT_STRUCT sPort;
700 sPort.ePortID = M4U_PORT_ROT_EXT;
701 sPort.Virtuality = 1;
702 sPort.Security = 0;
703 sPort.Distance = 1;
704 sPort.Direction = 0;
705 m4u_config_port(&sPort);
706
707 sPort.ePortID = M4U_PORT_WDMA0;
708 sPort.Virtuality = 1;
709 sPort.Security = 0;
710 sPort.Distance = 1;
711 sPort.Direction = 0;
712 m4u_config_port(&sPort);
713 }
714
715 //config
716
717 pddp.srcX = 0;
718 pddp.srcY = 0;
719 pddp.srcW = DDP_TEST_WIDTH;
720 pddp.srcWStride = DDP_TEST_WIDTH;
721 pddp.srcH = DDP_TEST_HEIGHT;
722 pddp.srcHStride = DDP_TEST_HEIGHT;
723 pddp.srcAddr[0] = (unsigned int)pSrc;
724 pddp.srcFormat = eRGB888_K;
725 pddp.srcPlaneNum = 1;
726 pddp.srcBufferSize[0] = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
727
728 pddp.dstX = 0;
729 pddp.dstY = 0;
730 pddp.dstW = DDP_TEST_WIDTH;
731 pddp.dstWStride = DDP_TEST_WIDTH;
732 pddp.dstH = DDP_TEST_HEIGHT;
733 pddp.dstHStride = DDP_TEST_HEIGHT;
734 pddp.dstAddr[0] = (unsigned int)pDst;
735 pddp.dstFormat = eRGB888_K;
736 pddp.pitch = DDP_TEST_WIDTH;
737 pddp.dstPlaneNum = 1;
738 pddp.dstBufferSize[0] = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
739 pddp.orientation = 0;
740 result = DDPK_Bitblt_Config( DDPK_CH_HDMI_0, &pddp );
741 if(result)
742 {
743 printk("[DDP] error: DDPK_Bitblt_Config fail!, ret=%d\n", result);
744 }
745
746 printk("DDP, DDPK_Bitblt module setting: \n");
747 disp_dump_reg(DISP_MODULE_ROT);
748 disp_dump_reg(DISP_MODULE_SCL);
749 disp_dump_reg(DISP_MODULE_WDMA);
750 disp_dump_reg(DISP_MODULE_CONFIG);
751
752 result = DDPK_Bitblt( DDPK_CH_HDMI_0);
753 if(result)
754 {
755 printk("[DDP] error: DDPK_Bitblt() fail, result=%d \n", result);
756 }
757
758
759 // result verify
760 {
761 unsigned int diff_cnt = 0;
762 unsigned int t=0;
763 unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
764 for(t=0;t<size;t++)
765 {
766 if( *((unsigned char*)pSrc+t) != *((unsigned char*)data_rgb888_64x64+t) )
767 {
768 diff_cnt++;
769 printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
770 t,
771 diff_cnt,
772 *((unsigned char*)pSrc+t),
773 *((unsigned char*)data_rgb888_64x64+t) );
774 }
775
776 }
777 if(diff_cnt == 0)
778 printk("ddp_mem_test src compare result: success \n");
779 else
780 {
781 printk("[DDP] error: ddp_mem_test src compare result: fail \n");
782 printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
783 result = -1;
784 }
785 }
786
787 {
788 unsigned int diff_cnt = 0;
789 unsigned int t=0;
790 unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
791 for(t=0;t<size;t++)
792 {
793 if( *((unsigned char*)pDst+t) != *((unsigned char*)data_rgb888_64x64_golden+t) )
794 {
795 diff_cnt++;
796 printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
797 t,
798 diff_cnt,
799 *((unsigned char*)pDst+t),
800 *((unsigned char*)data_rgb888_64x64_golden+t) );
801 }
802
803 }
804 if(diff_cnt == 0)
805 printk("ddp_mem_test result: success \n");
806 else
807 {
808 printk("[DDP] error: ddp_mem_test result: fail \n");
809 printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
810 result = -1;
811 }
812 }
813 /*
814 disp_power_off(DISP_MODULE_ROT);
815 disp_power_off(DISP_MODULE_SCL);
816 disp_power_off(DISP_MODULE_WDMA);
817 */
818 //dealloc memory
819 vfree(pSrc);
820 vfree(pDst);
821
822#endif
823 return result;
824
825}
826
827int ddp_mem_test(void)
828{
829 int result = 0;
830#if 0
831 struct disp_path_config_struct config;
832 unsigned int* pSrc;
833 unsigned char* pSrcPa;
834 unsigned int* pDst;
835 unsigned char* pDstPa;
836
837 pSrc= dma_alloc_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, (dma_addr_t *)&pSrcPa, GFP_KERNEL);
838 if(pSrc==0 || pSrcPa==0)
839 {
840 printk("dma_alloc_coherent error! dma memory not available.\n");
841 return 0;
842 }
843 else
844 {
845 printk("[ddp] pSrc=0x%x, pSrcPa=0x%x \n", (unsigned int)pSrc, (unsigned int)pSrcPa);
846 }
847 memcpy((void*)pSrc, data_rgb888_64x64, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
848
849 pDst= dma_alloc_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, (dma_addr_t *)&pDstPa, GFP_KERNEL);
850 if(pDst==0 || pDstPa==0)
851 {
852 printk("dma_alloc_coherent error! dma memory not available.\n");
853 return 0;
854 }
855 else
856 {
857 printk("[ddp] pDst=0x%x, pDstPa=0x%x \n",(unsigned int) pDst, (unsigned int)pDstPa);
858 }
859 memset((void*)pDst, 0, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
860
861
862 // config port to physical
863 {
864 M4U_PORT_STRUCT sPort;
865 sPort.ePortID = M4U_PORT_ROT_EXT;
866 sPort.Virtuality = 0;
867 sPort.Security = 0;
868 sPort.Distance = 1;
869 sPort.Direction = 0;
870 m4u_config_port(&sPort);
871
872 sPort.ePortID = M4U_PORT_WDMA0;
873 sPort.Virtuality = 0;
874 sPort.Security = 0;
875 sPort.Distance = 1;
876 sPort.Direction = 0;
877 m4u_config_port(&sPort);
878 }
879
880 config.srcModule = DISP_MODULE_SCL;
881 config.addr = (unsigned int)pSrcPa;
882 config.inFormat = eRGB888;
883 config.pitch = DDP_TEST_WIDTH;
884 config.srcROI.x = 0;
885 config.srcROI.y = 0;
886 config.srcROI.width = DDP_TEST_WIDTH;
887 config.srcROI.height = DDP_TEST_HEIGHT;
888 config.srcWidth = DDP_TEST_WIDTH;
889 config.srcHeight = DDP_TEST_HEIGHT;
890 config.dstModule = DISP_MODULE_WDMA;
891 config.outFormat = eRGB888;
892 config.dstAddr = (unsigned int)pDstPa;
893 config.dstWidth = DDP_TEST_WIDTH;
894 config.dstHeight = DDP_TEST_HEIGHT;
895 config.dstPitch = DDP_TEST_WIDTH;
896 /*
897 disp_power_on(DISP_MODULE_ROT);
898 disp_power_on(DISP_MODULE_SCL);
899 disp_power_on(DISP_MODULE_WDMA);
900 */
901 disp_path_get_mutex_(DDP_MUTEX_FOR_ROT_SCL_WDMA);
902 disp_path_config_(&config, DDP_MUTEX_FOR_ROT_SCL_WDMA);
903
904 printk("*after ddp test config start: -------------------\n");
905 disp_dump_reg(DISP_MODULE_ROT);
906 disp_dump_reg(DISP_MODULE_SCL);
907 disp_dump_reg(DISP_MODULE_WDMA);
908 disp_dump_reg(DISP_MODULE_CONFIG);
909 printk("*after ddp test config end: ---------------------\n");
910
911 disp_path_release_mutex_(DDP_MUTEX_FOR_ROT_SCL_WDMA);
912 if(*(volatile unsigned int*)DISP_REG_CONFIG_MUTEX1 != 0)
913 {
914 *(volatile unsigned int*)DISP_REG_CONFIG_MUTEX1 = 0;
915 }
916
917 printk("ddp_mem_test wdma wait done... \n");
918 WDMAWait(0);
919 printk("ddp_mem_test wdma done! \n");
920
921 if(0) //compare source
922 {
923 unsigned int diff_cnt = 0;
924 unsigned int t=0;
925 unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
926 for(t=0;t<size;t++)
927 {
928 if( *((unsigned char*)pSrc+t) != *((unsigned char*)data_rgb888_64x64+t) )
929 {
930 diff_cnt++;
931 printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
932 t,
933 diff_cnt,
934 *((unsigned char*)pSrc+t),
935 *((unsigned char*)data_rgb888_64x64+t) );
936 }
937
938 }
939 if(diff_cnt == 0)
940 printk("ddp_mem_test src compare result: success \n");
941 else
942 {
943 printk("ddp_mem_test src compare result: fail \n");
944 printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
945 result = -1;
946 }
947 }
948
949 if(1) //compare dst
950 {
951 unsigned int diff_cnt = 0;
952 unsigned int t=0;
953 unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
954 for(t=0;t<size;t++)
955 {
956 if( *((unsigned char*)pDst+t) != *((unsigned char*)data_rgb888_64x64_golden+t) )
957 {
958 diff_cnt++;
959 printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
960 t,
961 diff_cnt,
962 *((unsigned char*)pDst+t),
963 *((unsigned char*)data_rgb888_64x64_golden+t) );
964 }
965
966 }
967 if(diff_cnt == 0)
968 printk("ddp_mem_test result: success \n");
969 else
970 {
971 printk("ddp_mem_test result: fail \n");
972 printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
973 result = -1;
974 }
975 }
976
977 // print out dst buffer to save as golden
978 if(0)
979 {
980 unsigned int t=0;
981 unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
982 for(t=0;t<size;t++)
983 {
984 printk("0x%x, ", *((unsigned char*)pDst+t));
985 if((t+1)%12==0)
986 {
987 printk("\n%05d: ", (t+1)/12);
988 }
989 }
990 }
991 /*
992 disp_power_off(DISP_MODULE_ROT);
993 disp_power_off(DISP_MODULE_SCL);
994 disp_power_off(DISP_MODULE_WDMA);
995 */
996 //dealloc memory
997 dma_free_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, pSrc, (dma_addr_t)&pSrcPa);
998 dma_free_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, pDst, (dma_addr_t)&pDstPa);
999#endif
1000
1001 return result;
1002
1003}
1004
1005
1006char* ddp_get_module_name(DISP_MODULE_ENUM module)
1007{
1008 switch(module)
1009 {
1010 case DISP_MODULE_OVL: return "ovl";
1011 case DISP_MODULE_COLOR: return "color";
1012 case DISP_MODULE_BLS: return "bls";
1013 case DISP_MODULE_WDMA: return "wdma0";
1014 case DISP_MODULE_RDMA0: return "rdma0";
1015 case DISP_MODULE_RDMA1: return "rdma1";
1016 case DISP_MODULE_DPI0: return "dpi0";
1017 case DISP_MODULE_DBI: return "dbi";
1018 case DISP_MODULE_DSI_CMD:
1019 case DISP_MODULE_DSI_VDO:
1020 return "dsi";
1021 case DISP_MODULE_CONFIG: return "config";
1022 case DISP_MODULE_MUTEX: return "mutex";
1023 case DISP_MODULE_CMDQ: return "cmdq";
1024 case DISP_MODULE_G2D: return "g2d";
1025 case DISP_MODULE_SMI: return "smi";
1026 default:
1027 DISP_MSG("invalid module id=%d", module);
1028 return "unknown";
1029 }
1030}
1031
1032char* ddp_get_fmt_name(DISP_MODULE_ENUM module, unsigned int fmt)
1033{
1034 if(module==DISP_MODULE_WDMA)
1035 {
1036 switch(fmt)
1037 {
1038 case 0x00: return "rgb565";
1039 case 0x01: return "rgb888";
1040 case 0x02: return "rgba8888";
1041 case 0x03: return "argb8888";
1042 case 0x04: return "uyvy";
1043 case 0x05: return "yuyv";
1044 case 0x07: return "yonly";
1045 case 0x08: return "iyuv";
1046 case 0x0c: return "nv12";
1047 default:
1048 DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
1049 return "unknown";
1050 }
1051 }
1052 else if(module==DISP_MODULE_OVL)
1053 {
1054 switch(fmt)
1055 {
1056 case 0: return "rgb888";
1057 case 1: return "rgb565";
1058 case 2: return "argb8888";
1059 case 3: return "pargb8888";
1060 case 4: return "xrgb8888";
1061 case 8: return "yuyv";
1062 case 9: return "uvvy";
1063 case 10: return "yvyu";
1064 case 11: return "vyuy";
1065 case 15: return "yuv444";
1066 default:
1067 DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
1068 return "unknown";
1069 }
1070 }
1071 else if(module==DISP_MODULE_RDMA0 || module==DISP_MODULE_RDMA1) // todo: confirm with designers
1072 {
1073 switch(fmt)
1074 {
1075 case 0: return "yuyv";
1076 case 1: return "uyvy";
1077 case 2: return "yvyu";
1078 case 3: return "vyuy";
1079 case 4: return "rgb565";
1080 case 8: return "rgb888";
1081 case 16: return "argb8888";
1082 case 32: return "yuv420_3p";
1083 case 40: return "yuv422_3p";
1084 case 48: return "yuv420_2p";
1085 case 56: return "yuv422_2p";
1086 default:
1087 DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
1088 return "unknown";
1089 }
1090 }
1091 else if(module==DISP_MODULE_MUTEX)
1092 {
1093 switch(fmt)
1094 {
1095 case 0: return "single";
1096 case 1: return "dsi_vdo";
1097 case 2: return "dpi0";
1098 case 3: return "dpi1";
1099
1100 default:
1101 DISP_MSG("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
1102 return "unknown";
1103 }
1104 }
1105 else
1106 {
1107 DISP_MSG("ddp_get_fmt_name, unknown module=%d \n", module);
1108 }
1109
1110 return "unknown";
1111}
1112
1113static char* ddp_get_mutex_module_name(unsigned int bit)
1114{
1115 switch(bit)
1116 {
1117 case 3: return "ovl";
1118 case 6: return "wdma0";
1119 case 7: return "color";
1120 case 9: return "bls";
1121 case 10: return "rdma0";
1122 case 12: return "rdma1";
1123 default:
1124 printk("error_bit=%d, ", bit);
1125 return "mutex-unknown";
1126 }
1127}
1128
1129static char* ddp_clock_0(int bit)
1130{
1131 switch(bit)
1132 {
1133 case 0: return "smi common";
1134 case 1: return "smi larb0";
1135 case 2: return "mm cmdq";
1136 case 3: return "mutex";
1137 case 4: return "disp_color";
1138 case 5: return "disp_bls";
1139 case 6: return "disp_wdma0";
1140 case 7: return "disp_rdma";
1141 case 8: return "disp_ovl";
1142 case 17: return "fake_eng";
1143 case 18: return "mutex_32k";
1144 case 19: return "disp_rdma1";
1145 default : return "";
1146 }
1147}
1148
1149static char* ddp_clock_1(int bit)
1150{
1151 switch(bit)
1152 {
1153 case 0: return "dsi_engine";
1154 case 1: return "dsi_digital";
1155 case 2: return "dpi_digital_lane";
1156 case 3: return "dpi_engine";
1157 default : return "";
1158 }
1159}
1160
1161char* ddp_ovl_get_status(unsigned int status)
1162{
1163 DISP_MSG("ovl_status: ");
1164 if(status&(1<<10)) printk("addcon_idle,");
1165 if(status&(1<<11)) printk("blend_idle,");
1166 if(status&(1<<15)) printk("out_idle,");
1167 if(status&(1<<16)) printk("rdma3_idle,");
1168 if(status&(1<<17)) printk("rdma2_idle,");
1169 if(status&(1<<18)) printk("rdma1_idle,");
1170 if(status&(1<<19)) printk("rdma0_idle,");
1171 if(status&(1<<20)) printk("rst,");
1172 if(status&(1<<21)) printk("trig,");
1173 if(status&(1<<23)) printk("frame_hwrst_done,");
1174 if(status&(1<<24)) printk("frame_swrst_done,");
1175 if(status&(1<<25)) printk("frame_underrun,");
1176 if(status&(1<<26)) printk("frame_done,");
1177 if(status&(1<<27)) printk("ovl_running,");
1178 if(status&(1<<28)) printk("ovl_start,");
1179 if(status&(1<<29)) printk("ovl_clr,");
1180 if(status&(1<<30)) printk("reg_update,");
1181 if(status&(1<<31)) printk("ovl_upd_reg,");
1182 printk("\n");
1183
1184 DISP_MSG("ovl_state_machine: ");
1185 switch(status&0x3ff)
1186 {
1187 case 0x1: printk("idle\n"); break;
1188 case 0x2: printk("wait_SOF\n"); break;
1189 case 0x4: printk("prepare\n"); break;
1190 case 0x8: printk("reg_update\n"); break;
1191 case 0x10: printk("eng_clr\n"); break;
1192 case 0x20: printk("processing\n"); break;
1193 case 0x40: printk("s_wait_w_rst\n"); break;
1194 case 0x80: printk("s_w_rst\n"); break;
1195 case 0x100:printk("h_wait_w_rst\n"); break;
1196 case 0x200:printk("h_w_rst\n"); break;
1197 default: printk("unknown\n");
1198 }
1199
1200 return NULL;
1201
1202}
1203
1204
1205char* ddp_wdma_get_status(unsigned int status)
1206{
1207 switch(status)
1208 {
1209 case 0x1: return "idle";
1210 case 0x2: return "clear";
1211 case 0x4: return "prepare";
1212 case 0x8: return "prepare";
1213 case 0x10: return "data_running";
1214 case 0x20: return "eof_wait";
1215 case 0x40: return "soft_reset_wait";
1216 case 0x80: return "eof_done";
1217 case 0x100: return "soft_reset_done";
1218 case 0x200: return "frame_complete";
1219 default: return "unknown";
1220 }
1221
1222}
1223
1224char* ddp_rdma_get_status(unsigned int status)
1225{
1226 switch(status)
1227 {
1228 case 0x1: return "idle";
1229 case 0x2: return "wait_sof";
1230 case 0x4: return "reg_update";
1231 case 0x8: return "clear0";
1232 case 0x10: return "clear1";
1233 case 0x20: return "int0";
1234 case 0x40: return "int1";
1235 case 0x80: return "data_running";
1236 case 0x100: return "wait_done";
1237 case 0x200: return "warm_reset";
1238 case 0x400: return "wait_reset";
1239 default: return "unknown";
1240 }
1241}
1242
1243char* ddp_dsi_get_status(unsigned int status)
1244{
1245 switch(status)
1246 {
1247 case 0x0001: return "Idle (wait for command)";
1248 case 0x0002: return "Reading command queue for header";
1249 case 0x0004: return "Sending type-0 command";
1250 case 0x0008: return "Waiting frame data from RDMA for type-1 command";
1251 case 0x0010: return "Sending type-1 command";
1252 case 0x0020: return "Sending type-2 command";
1253 case 0x0040: return "Reading command queue for data";
1254 case 0x0080: return "Sending type-3 command";
1255 case 0x0100: return "Sending BTA";
1256 case 0x0200: return "Waiting RX-read data";
1257 case 0x0400: return "Waiting SW RACK for RX-read data";
1258 case 0x0800: return "Waiting TE)";
1259 case 0x1000: return "Get TE";
1260 case 0x2000: return "Waiting external TE";
1261 case 0x4000: return "Waiting SW RACK for TE";
1262 default: return "unknown";
1263 }
1264}
1265
1266char* ddp_dsi_get_err(unsigned int reg)
1267{
1268 DISP_MSG("error_state=");
1269 if((reg&0xf2)!=0)
1270 {
1271 if((reg>>7)&0x1)
1272 printk("contention_err, ");
1273 if((reg>>6)&0x1)
1274 printk("false_ctrl_err, ");
1275 if((reg>>5)&0x1)
1276 printk("lpdt_sync_err, ");
1277 if((reg>>4)&0x1)
1278 printk("esc_entry_err, ");
1279 if((reg>>1)&0x1)
1280 printk("buffer_underrun");
1281
1282 printk("\n");
1283 }
1284 else
1285 {
1286 printk("none. \n");
1287 }
1288
1289 return NULL;
1290}
1291
1292char* ddp_get_rdma_mode(unsigned int con)
1293{
1294 if(((con>>1)&0x1)==1)
1295 return "mem_mode";
1296 else
1297 return "direct_link";
1298}
1299
1300int ddp_dump_info(DISP_MODULE_ENUM module)
1301{
1302 unsigned int index=0;
1303 unsigned int i=0;
1304 unsigned int j=0;
1305 unsigned int DISP_INDEX_OFFSET = 0xA000;
1306
1307 switch(module)
1308 {
1309 /* Dump WDMA Reg */
1310 case DISP_MODULE_WDMA:
1311 DISP_MSG("wdma0: en=%d, w=%d, h=%d, clip=(%d, %d, %d, %d), pitch=(%d,%d), addr=(0x%x,0x%x,0x%x), fmt=%s \n",
1312 DISP_REG_GET(DISP_REG_WDMA_EN),
1313 DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE)&0x3fff,
1314 (DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE)>>16)&0x3fff,
1315 DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD)&0x3fff,
1316 (DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD)>>16)&0x3fff,
1317 DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE)&0x3fff,
1318 (DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE)>>16)&0x3fff,
1319 DISP_REG_GET(DISP_REG_WDMA_DST_W_IN_BYTE),
1320 DISP_REG_GET(DISP_REG_WDMA_DST_UV_PITCH),
1321 DISP_REG_GET(DISP_REG_WDMA_DST_ADDR),
1322 DISP_REG_GET(DISP_REG_WDMA_DST_U_ADDR),
1323 DISP_REG_GET(DISP_REG_WDMA_DST_V_ADDR),
1324 ddp_get_fmt_name(DISP_MODULE_WDMA, (DISP_REG_GET(DISP_REG_WDMA_CFG)>>4)&0xf));
1325 DISP_MSG("wdma0: status=%s, total_pix=%d, output_pixel=(l:%d, p:%d), input_pixel=(l:%d, p:%d) \n",
1326 ddp_wdma_get_status(DISP_REG_GET(DISP_REG_WDMA_FLOW_CTRL_DBG)),
1327 (DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE)&0x3fff)*((DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE)>>16)&0x3fff),
1328 (DISP_REG_GET(DISP_REG_WDMA_EXEC_DBG)>>16)&0xffff,
1329 DISP_REG_GET(DISP_REG_WDMA_EXEC_DBG)&0xffff,
1330 (DISP_REG_GET(DISP_REG_WDMA_CLIP_DBG)>>16)&0xffff,
1331 DISP_REG_GET(DISP_REG_WDMA_CLIP_DBG)&0xffff);
1332 break;
1333
1334 /* Dump RDMA Reg */
1335 case DISP_MODULE_RDMA0:
1336 index = 0;
1337 DISP_MSG("rdma%d: en=%d, mode=%s, smi_busy=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d \n",
1338 index,
1339 DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)&0x1,
1340 ddp_get_rdma_mode(DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)),
1341 (DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON)>>12)&0x1,
1342 DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_INDEX_OFFSET*index)&0xfff,
1343 DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_INDEX_OFFSET*index)&0xfffff,
1344 DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_INDEX_OFFSET*index),
1345 DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_INDEX_OFFSET*index),
1346 ((DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)&0x2)==0) ? "rgb888" : ddp_get_fmt_name(DISP_MODULE_RDMA0, (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_INDEX_OFFSET*index)>>4)&0x3f),
1347 DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_INDEX_OFFSET*index));
1348 DISP_MSG("rdma%d: ack=%d, req=%d, status=%s, output_x=%d, output_y=%d \n",
1349 index,
1350 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>10)&0x1,
1351 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>11)&0x1,
1352 ddp_rdma_get_status((DISP_REG_GET(DISPSYS_RDMA1_BASE+0x408)>>8)&0x7ff),
1353 DISP_REG_GET(DISPSYS_RDMA1_BASE+0x4D0)&0x1fff,
1354 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>16)&0x1fff);
1355 break;
1356
1357 case DISP_MODULE_RDMA1:
1358 index = 1;
1359 DISP_MSG("rdma%d: en=%d, mode=%s, smi_busy=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d \n",
1360 index,
1361 DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)&0x1,
1362 ddp_get_rdma_mode(DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)),
1363 (DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON)>>12)&0x1,
1364 DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_INDEX_OFFSET*index)&0xfff,
1365 DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_INDEX_OFFSET*index)&0xfffff,
1366 DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_INDEX_OFFSET*index),
1367 DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_INDEX_OFFSET*index),
1368 ((DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_INDEX_OFFSET*index)&0x2)==0) ? "rgb888" : ddp_get_fmt_name(DISP_MODULE_RDMA1, (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_INDEX_OFFSET*index)>>4)&0x3f),
1369 DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_INDEX_OFFSET*index));
1370 DISP_MSG("rdma%d: ack=%d, req=%d, status=%s, output_x=%d, output_y=%d \n",
1371 index,
1372 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>10)&0x1,
1373 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>11)&0x1,
1374 ddp_rdma_get_status((DISP_REG_GET(DISPSYS_RDMA1_BASE+0x408)>>8)&0x7ff),
1375 DISP_REG_GET(DISPSYS_RDMA1_BASE+0x4D0)&0x1fff,
1376 (DISP_REG_GET(DISPSYS_RDMA1_BASE+0x400)>>16)&0x1fff);
1377 break;
1378
1379 /* Dump OVL Reg */
1380 case DISP_MODULE_OVL:
1381 DISP_MSG("ovl%d: en=%d, layer(%d,%d,%d,%d), bg_w=%d, bg_h=%d, cur_x=%d, cur_y=%d, layer_pix_hit(%d, %d, %d, %d) \n",
1382 index,
1383 DISP_REG_GET(DISP_REG_OVL_EN),
1384 DISP_REG_GET(DISP_REG_OVL_SRC_CON)&0x1,
1385 (DISP_REG_GET(DISP_REG_OVL_SRC_CON)>>1)&0x1,
1386 (DISP_REG_GET(DISP_REG_OVL_SRC_CON)>>2)&0x1,
1387 (DISP_REG_GET(DISP_REG_OVL_SRC_CON)>>3)&0x1,
1388 DISP_REG_GET(DISP_REG_OVL_ROI_SIZE)&0xfff,
1389 (DISP_REG_GET(DISP_REG_OVL_ROI_SIZE)>>16)&0xfff,
1390 DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)&0x1fff,
1391 (DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)>>16)&0x1fff,
1392 (DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)>>14)&0x1,
1393 (DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)>>15)&0x1,
1394 (DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)>>30)&0x1,
1395 (DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG)>>31)&0x1);
1396 ddp_ovl_get_status(DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
1397 DISP_MSG("ovl%d: greq(ovl_req_smi)=%d, valid(ovl_send_data)=%d, ready(follow_engine_req_data)=%d \n",
1398 index,
1399 DISP_REG_GET(DISP_REG_CONFIG_GREQ)&0x1,
1400 (DISP_REG_GET(DISP_REG_CONFIG_VALID)>>10)&0x1,
1401 (DISP_REG_GET(DISP_REG_CONFIG_READY)>>10)&0x1);
1402
1403 if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&0x1)
1404 {
1405 DISP_MSG("layer=%d, w=%d, h=%d, x=%d, y=%d, pitch=%d, addr=0x%x, fmt=%s \n",
1406 0,
1407 DISP_REG_GET(DISP_REG_OVL_L0_SRC_SIZE)&0xfff,
1408 (DISP_REG_GET(DISP_REG_OVL_L0_SRC_SIZE)>>16)&0xfff,
1409 DISP_REG_GET(DISP_REG_OVL_L0_OFFSET)&0xfff,
1410 (DISP_REG_GET(DISP_REG_OVL_L0_OFFSET)>>16)&0xfff,
1411 DISP_REG_GET(DISP_REG_OVL_L0_PITCH),
1412 DISP_REG_GET(DISP_REG_OVL_L0_ADDR),
1413 ddp_get_fmt_name(DISP_MODULE_OVL, (DISP_REG_GET(DISP_REG_OVL_L0_CON)>>12)&0xf));
1414 }
1415 if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&0x2)
1416 {
1417 DISP_MSG("layer=%d, w=%d, h=%d, x=%d, y=%d, pitch=%d, addr=0x%x, fmt=%s \n",
1418 1,
1419 DISP_REG_GET(DISP_REG_OVL_L1_SRC_SIZE)&0xfff,
1420 (DISP_REG_GET(DISP_REG_OVL_L1_SRC_SIZE)>>16)&0xfff,
1421 DISP_REG_GET(DISP_REG_OVL_L1_OFFSET)&0xfff,
1422 (DISP_REG_GET(DISP_REG_OVL_L1_OFFSET)>>16)&0xfff,
1423 DISP_REG_GET(DISP_REG_OVL_L1_PITCH),
1424 DISP_REG_GET(DISP_REG_OVL_L1_ADDR),
1425 ddp_get_fmt_name(DISP_MODULE_OVL, (DISP_REG_GET(DISP_REG_OVL_L1_CON)>>12)&0xf));
1426 }
1427 if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&0x4)
1428 {
1429 DISP_MSG("layer=%d, w=%d, h=%d, x=%d, y=%d, pitch=%d, addr=0x%x, fmt=%s \n",
1430 2,
1431 DISP_REG_GET(DISP_REG_OVL_L2_SRC_SIZE)&0xfff,
1432 (DISP_REG_GET(DISP_REG_OVL_L2_SRC_SIZE)>>16)&0xfff,
1433 DISP_REG_GET(DISP_REG_OVL_L2_OFFSET)&0xfff,
1434 (DISP_REG_GET(DISP_REG_OVL_L2_OFFSET)>>16)&0xfff,
1435 DISP_REG_GET(DISP_REG_OVL_L2_PITCH),
1436 DISP_REG_GET(DISP_REG_OVL_L2_ADDR),
1437 ddp_get_fmt_name(DISP_MODULE_OVL, (DISP_REG_GET(DISP_REG_OVL_L2_CON)>>12)&0xf));
1438 }
1439 if(DISP_REG_GET(DISP_REG_OVL_SRC_CON)&0x8)
1440 {
1441 DISP_MSG("layer=%d, w=%d, h=%d, x=%d, y=%d, pitch=%d, addr=0x%x, fmt=%s \n",
1442 3,
1443 DISP_REG_GET(DISP_REG_OVL_L3_SRC_SIZE)&0xfff,
1444 (DISP_REG_GET(DISP_REG_OVL_L3_SRC_SIZE)>>16)&0xfff,
1445 DISP_REG_GET(DISP_REG_OVL_L3_OFFSET)&0xfff,
1446 (DISP_REG_GET(DISP_REG_OVL_L3_OFFSET)>>16)&0xfff,
1447 DISP_REG_GET(DISP_REG_OVL_L3_PITCH),
1448 DISP_REG_GET(DISP_REG_OVL_L3_ADDR),
1449 ddp_get_fmt_name(DISP_MODULE_OVL, (DISP_REG_GET(DISP_REG_OVL_L3_CON)>>12)&0xf));
1450 }
1451 break;
1452
1453 /* Dump DPI0 Reg */
1454 case DISP_MODULE_DPI0:
1455 DISP_MSG("DPI0: \n");
1456 break;
1457
1458 /* Dump DPI0 Reg */
1459 case DISP_MODULE_BLS:
1460 DISP_MSG("BLS: \n");
1461 break;
1462
1463 /* Dump CONFIG Reg */
1464 case DISP_MODULE_CONFIG:
1465 // print whole data path
1466 DISP_MSG("clock:");
1467 {
1468 unsigned int i;
1469 unsigned int reg;
1470
1471 reg = DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0);
1472 for(i=0;i<9;i++)
1473 {
1474 if((reg&(1<<i))==0)
1475 printk("%s, ", ddp_clock_0(i));
1476 }
1477 for(i=17;i<20;i++)
1478 {
1479 if((reg&(1<<i))==0)
1480 printk("%s, ", ddp_clock_0(i));
1481 }
1482 printk("\n");
1483 reg = DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON1);
1484 for(i=0;i<4;i++)
1485 {
1486 if((reg&(1<<i))==0)
1487 printk("%s, ", ddp_clock_1(i));
1488 }
1489 printk("\n");
1490 }
1491 {
1492 unsigned int clock = (DISP_REG_GET(DISP_REG_CONFIG_CLOCK_DUMMY)>>7)&0x7;
1493 if(clock==3)
1494 DISP_MSG("clock ok\n");
1495 else if(clock==0)
1496 DISP_MSG("clock 80128\n");
1497 else if(clock==1)
1498 DISP_MSG("clock 6496\n");
1499 else if(clock==2)
1500 DISP_MSG("clock 4886\n");
1501 }
1502
1503 break;
1504
1505 case DISP_MODULE_MUTEX:
1506 DISP_MSG("mutex: \n");
1507 for(i=0;i<4;i++)
1508 {
1509 DISP_DBG("i=%d, mod=0x%x, en=%d \n",
1510 i,
1511 DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(i)),
1512 DISP_REG_GET(DISP_REG_CONFIG_MUTEX_EN(i)));
1513
1514 if( (DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(i))!=0) &&
1515 (DISP_REG_GET(DISP_REG_CONFIG_MUTEX_EN(i))==1) )
1516 {
1517 DISP_MSG("mutex%d, mode=%s, module=(", i, ddp_get_fmt_name(DISP_MODULE_MUTEX, DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(i))));
1518 for(j=3;j<=12;j++)
1519 {
1520 if((DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(i))>>j)&0x1)
1521 printk("%s,", ddp_get_mutex_module_name(j));
1522 }
1523 printk(")\n");
1524 }
1525 }
1526 break;
1527
1528 /* Dump COLOR Reg */
1529 case DISP_MODULE_COLOR:
1530 DISP_MSG("color: w=%d, h=%d, h_cnt=%d, line_cnt=%d \n",
1531 DISP_REG_GET(DISP_REG_COLOR_INTERNAL_IP_WIDTH),
1532 DISP_REG_GET(DISP_REG_COLOR_INTERNAL_IP_HEIGHT),
1533 DISP_REG_GET(DISP_REG_COLOR_H_CNT)&0xffff,
1534 DISP_REG_GET(DISP_REG_COLOR_L_CNT)&0xffff);
1535 break;
1536
1537 /* Dump DSI Reg */
1538 case DISP_MODULE_DSI_VDO:
1539 case DISP_MODULE_DSI_CMD:
1540 DISP_MSG("dsi: w=%d, h=%d, busy=%d, rdma_line_counter=%d, staus=%s, ",
1541 (DISP_REG_GET(DISPSYS_DSI_BASE+0x1c)&0x3fff)/3, //bpp=3
1542 DISP_REG_GET(DISPSYS_DSI_BASE+0x2c),
1543 (DISP_REG_GET(DISPSYS_DSI_BASE+0xc)>>31)&0x1,
1544 DISP_REG_GET(DISPSYS_DSI_BASE+0x16c)&0x3fffff,
1545 ddp_dsi_get_status(DISP_REG_GET(DISPSYS_DSI_BASE+0x160)&0xffff));
1546 ddp_dsi_get_err(DISP_REG_GET(DISPSYS_DSI_BASE+0x4));
1547 break;
1548
1549 default:
1550 DISP_MSG("DDP error, dump_info unknow module=%d \n", module);
1551 }
1552 return 0;
1553}
1554
kernel source for telekom puls (alcatel/mediatek)