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Input: stmpe-keypad - add support for Device Tree bindings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / stmpe.c
CommitLineData
27e34995 1/*
1a6e4b74
VK		 2 * ST Microelectronics MFD: stmpe's driver
3 *
27e34995
RV		 4 * Copyright (C) ST-Ericsson SA 2010
5 *
6 * License Terms: GNU General Public License, version 2
7 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
8 */
9
73de16db 10#include <linux/gpio.h>
dba61c8f 11#include <linux/export.h>
27e34995 12#include <linux/kernel.h>
27e34995
RV		 13#include <linux/interrupt.h>
14#include <linux/irq.h>
1a6e4b74 15#include <linux/pm.h>
27e34995 16#include <linux/slab.h>
27e34995 17#include <linux/mfd/core.h>
27e34995
RV		 18#include "stmpe.h"
19
20static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
21{
22 return stmpe->variant->enable(stmpe, blocks, true);
23}
24
25static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
26{
27 return stmpe->variant->enable(stmpe, blocks, false);
28}
29
30static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
31{
32 int ret;
33
1a6e4b74 34 ret = stmpe->ci->read_byte(stmpe, reg);
27e34995 35 if (ret < 0)
1a6e4b74 36 dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
27e34995
RV		 37
38 dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
39
40 return ret;
41}
42
43static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
44{
45 int ret;
46
47 dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
48
1a6e4b74 49 ret = stmpe->ci->write_byte(stmpe, reg, val);
27e34995 50 if (ret < 0)
1a6e4b74 51 dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
27e34995
RV		 52
53 return ret;
54}
55
56static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
57{
58 int ret;
59
60 ret = __stmpe_reg_read(stmpe, reg);
61 if (ret < 0)
62 return ret;
63
64 ret &= ~mask;
65 ret |= val;
66
67 return __stmpe_reg_write(stmpe, reg, ret);
68}
69
70static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
71 u8 *values)
72{
73 int ret;
74
1a6e4b74 75 ret = stmpe->ci->read_block(stmpe, reg, length, values);
27e34995 76 if (ret < 0)
1a6e4b74 77 dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
27e34995
RV		 78
79 dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
80 stmpe_dump_bytes("stmpe rd: ", values, length);
81
82 return ret;
83}
84
85static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
86 const u8 *values)
87{
88 int ret;
89
90 dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
91 stmpe_dump_bytes("stmpe wr: ", values, length);
92
1a6e4b74 93 ret = stmpe->ci->write_block(stmpe, reg, length, values);
27e34995 94 if (ret < 0)
1a6e4b74 95 dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
27e34995
RV		 96
97 return ret;
98}
99
100/**
101 * stmpe_enable - enable blocks on an STMPE device
102 * @stmpe: Device to work on
103 * @blocks: Mask of blocks (enum stmpe_block values) to enable
104 */
105int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
106{
107 int ret;
108
109 mutex_lock(&stmpe->lock);
110 ret = __stmpe_enable(stmpe, blocks);
111 mutex_unlock(&stmpe->lock);
112
113 return ret;
114}
115EXPORT_SYMBOL_GPL(stmpe_enable);
116
117/**
118 * stmpe_disable - disable blocks on an STMPE device
119 * @stmpe: Device to work on
120 * @blocks: Mask of blocks (enum stmpe_block values) to enable
121 */
122int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
123{
124 int ret;
125
126 mutex_lock(&stmpe->lock);
127 ret = __stmpe_disable(stmpe, blocks);
128 mutex_unlock(&stmpe->lock);
129
130 return ret;
131}
132EXPORT_SYMBOL_GPL(stmpe_disable);
133
134/**
135 * stmpe_reg_read() - read a single STMPE register
136 * @stmpe: Device to read from
137 * @reg: Register to read
138 */
139int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
140{
141 int ret;
142
143 mutex_lock(&stmpe->lock);
144 ret = __stmpe_reg_read(stmpe, reg);
145 mutex_unlock(&stmpe->lock);
146
147 return ret;
148}
149EXPORT_SYMBOL_GPL(stmpe_reg_read);
150
151/**
152 * stmpe_reg_write() - write a single STMPE register
153 * @stmpe: Device to write to
154 * @reg: Register to write
155 * @val: Value to write
156 */
157int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
158{
159 int ret;
160
161 mutex_lock(&stmpe->lock);
162 ret = __stmpe_reg_write(stmpe, reg, val);
163 mutex_unlock(&stmpe->lock);
164
165 return ret;
166}
167EXPORT_SYMBOL_GPL(stmpe_reg_write);
168
169/**
170 * stmpe_set_bits() - set the value of a bitfield in a STMPE register
171 * @stmpe: Device to write to
172 * @reg: Register to write
173 * @mask: Mask of bits to set
174 * @val: Value to set
175 */
176int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
177{
178 int ret;
179
180 mutex_lock(&stmpe->lock);
181 ret = __stmpe_set_bits(stmpe, reg, mask, val);
182 mutex_unlock(&stmpe->lock);
183
184 return ret;
185}
186EXPORT_SYMBOL_GPL(stmpe_set_bits);
187
188/**
189 * stmpe_block_read() - read multiple STMPE registers
190 * @stmpe: Device to read from
191 * @reg: First register
192 * @length: Number of registers
193 * @values: Buffer to write to
194 */
195int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
196{
197 int ret;
198
199 mutex_lock(&stmpe->lock);
200 ret = __stmpe_block_read(stmpe, reg, length, values);
201 mutex_unlock(&stmpe->lock);
202
203 return ret;
204}
205EXPORT_SYMBOL_GPL(stmpe_block_read);
206
207/**
208 * stmpe_block_write() - write multiple STMPE registers
209 * @stmpe: Device to write to
210 * @reg: First register
211 * @length: Number of registers
212 * @values: Values to write
213 */
214int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
215 const u8 *values)
216{
217 int ret;
218
219 mutex_lock(&stmpe->lock);
220 ret = __stmpe_block_write(stmpe, reg, length, values);
221 mutex_unlock(&stmpe->lock);
222
223 return ret;
224}
225EXPORT_SYMBOL_GPL(stmpe_block_write);
226
227/**
4dcaa6b6 228 * stmpe_set_altfunc()- set the alternate function for STMPE pins
27e34995
RV		 229 * @stmpe: Device to configure
230 * @pins: Bitmask of pins to affect
231 * @block: block to enable alternate functions for
232 *
233 * @pins is assumed to have a bit set for each of the bits whose alternate
234 * function is to be changed, numbered according to the GPIOXY numbers.
235 *
236 * If the GPIO module is not enabled, this function automatically enables it in
237 * order to perform the change.
238 */
239int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
240{
241 struct stmpe_variant_info *variant = stmpe->variant;
242 u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
243 int af_bits = variant->af_bits;
244 int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
27e34995
RV		 245 int mask = (1 << af_bits) - 1;
246 u8 regs[numregs];
7f7f4ea1
VK		 247 int af, afperreg, ret;
248
249 if (!variant->get_altfunc)
250 return 0;
27e34995 251
7f7f4ea1 252 afperreg = 8 / af_bits;
27e34995
RV		 253 mutex_lock(&stmpe->lock);
254
255 ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
256 if (ret < 0)
257 goto out;
258
259 ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
260 if (ret < 0)
261 goto out;
262
263 af = variant->get_altfunc(stmpe, block);
264
265 while (pins) {
266 int pin = __ffs(pins);
267 int regoffset = numregs - (pin / afperreg) - 1;
268 int pos = (pin % afperreg) * (8 / afperreg);
269
270 regs[regoffset] &= ~(mask << pos);
271 regs[regoffset] |= af << pos;
272
273 pins &= ~(1 << pin);
274 }
275
276 ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
277
278out:
279 mutex_unlock(&stmpe->lock);
280 return ret;
281}
282EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
283
284/*
285 * GPIO (all variants)
286 */
287
288static struct resource stmpe_gpio_resources[] = {
289 /* Start and end filled dynamically */
290 {
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct mfd_cell stmpe_gpio_cell = {
296 .name = "stmpe-gpio",
297 .resources = stmpe_gpio_resources,
298 .num_resources = ARRAY_SIZE(stmpe_gpio_resources),
299};
300
e31f9b82
CB		 301static struct mfd_cell stmpe_gpio_cell_noirq = {
302 .name = "stmpe-gpio",
303 /* gpio cell resources consist of an irq only so no resources here */
304};
305
27e34995
RV		 306/*
307 * Keypad (1601, 2401, 2403)
308 */
309
310static struct resource stmpe_keypad_resources[] = {
311 {
312 .name = "KEYPAD",
313 .start = 0,
314 .end = 0,
315 .flags = IORESOURCE_IRQ,
316 },
317 {
318 .name = "KEYPAD_OVER",
319 .start = 1,
320 .end = 1,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct mfd_cell stmpe_keypad_cell = {
326 .name = "stmpe-keypad",
6ea32387 327 .of_compatible = "st,stmpe-keypad",
27e34995
RV		 328 .resources = stmpe_keypad_resources,
329 .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
330};
331
7f7f4ea1
VK		 332/*
333 * STMPE801
334 */
335static const u8 stmpe801_regs[] = {
336 [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
337 [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
338 [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
339 [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
340 [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
341 [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
342 [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
343 [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
344
345};
346
347static struct stmpe_variant_block stmpe801_blocks[] = {
348 {
349 .cell = &stmpe_gpio_cell,
350 .irq = 0,
351 .block = STMPE_BLOCK_GPIO,
352 },
353};
354
e31f9b82
CB		 355static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
356 {
357 .cell = &stmpe_gpio_cell_noirq,
358 .block = STMPE_BLOCK_GPIO,
359 },
360};
361
7f7f4ea1
VK		 362static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
363 bool enable)
364{
365 if (blocks & STMPE_BLOCK_GPIO)
366 return 0;
367 else
368 return -EINVAL;
369}
370
371static struct stmpe_variant_info stmpe801 = {
372 .name = "stmpe801",
373 .id_val = STMPE801_ID,
374 .id_mask = 0xffff,
375 .num_gpios = 8,
376 .regs = stmpe801_regs,
377 .blocks = stmpe801_blocks,
378 .num_blocks = ARRAY_SIZE(stmpe801_blocks),
379 .num_irqs = STMPE801_NR_INTERNAL_IRQS,
380 .enable = stmpe801_enable,
381};
382
e31f9b82
CB		 383static struct stmpe_variant_info stmpe801_noirq = {
384 .name = "stmpe801",
385 .id_val = STMPE801_ID,
386 .id_mask = 0xffff,
387 .num_gpios = 8,
388 .regs = stmpe801_regs,
389 .blocks = stmpe801_blocks_noirq,
390 .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
391 .enable = stmpe801_enable,
392};
393
27e34995 394/*
1cda2394 395 * Touchscreen (STMPE811 or STMPE610)
27e34995
RV		 396 */
397
398static struct resource stmpe_ts_resources[] = {
399 {
400 .name = "TOUCH_DET",
401 .start = 0,
402 .end = 0,
403 .flags = IORESOURCE_IRQ,
404 },
405 {
406 .name = "FIFO_TH",
407 .start = 1,
408 .end = 1,
409 .flags = IORESOURCE_IRQ,
410 },
411};
412
413static struct mfd_cell stmpe_ts_cell = {
414 .name = "stmpe-ts",
037db524 415 .of_compatible = "st,stmpe-ts",
27e34995
RV		 416 .resources = stmpe_ts_resources,
417 .num_resources = ARRAY_SIZE(stmpe_ts_resources),
418};
419
420/*
1cda2394 421 * STMPE811 or STMPE610
27e34995
RV		 422 */
423
424static const u8 stmpe811_regs[] = {
425 [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
426 [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
427 [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
428 [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
429 [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
430 [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
431 [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
432 [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
433 [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
434 [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
435 [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
436 [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
437 [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
438 [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED,
439};
440
441static struct stmpe_variant_block stmpe811_blocks[] = {
442 {
443 .cell = &stmpe_gpio_cell,
444 .irq = STMPE811_IRQ_GPIOC,
445 .block = STMPE_BLOCK_GPIO,
446 },
447 {
448 .cell = &stmpe_ts_cell,
449 .irq = STMPE811_IRQ_TOUCH_DET,
450 .block = STMPE_BLOCK_TOUCHSCREEN,
451 },
452};
453
454static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
455 bool enable)
456{
457 unsigned int mask = 0;
458
459 if (blocks & STMPE_BLOCK_GPIO)
460 mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
461
462 if (blocks & STMPE_BLOCK_ADC)
463 mask |= STMPE811_SYS_CTRL2_ADC_OFF;
464
465 if (blocks & STMPE_BLOCK_TOUCHSCREEN)
466 mask |= STMPE811_SYS_CTRL2_TSC_OFF;
467
468 return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask,
469 enable ? 0 : mask);
470}
471
472static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
473{
474 /* 0 for touchscreen, 1 for GPIO */
475 return block != STMPE_BLOCK_TOUCHSCREEN;
476}
477
478static struct stmpe_variant_info stmpe811 = {
479 .name = "stmpe811",
480 .id_val = 0x0811,
481 .id_mask = 0xffff,
482 .num_gpios = 8,
483 .af_bits = 1,
484 .regs = stmpe811_regs,
485 .blocks = stmpe811_blocks,
486 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
487 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
488 .enable = stmpe811_enable,
489 .get_altfunc = stmpe811_get_altfunc,
490};
491
1cda2394
VK		 492/* Similar to 811, except number of gpios */
493static struct stmpe_variant_info stmpe610 = {
494 .name = "stmpe610",
495 .id_val = 0x0811,
496 .id_mask = 0xffff,
497 .num_gpios = 6,
498 .af_bits = 1,
499 .regs = stmpe811_regs,
500 .blocks = stmpe811_blocks,
501 .num_blocks = ARRAY_SIZE(stmpe811_blocks),
502 .num_irqs = STMPE811_NR_INTERNAL_IRQS,
503 .enable = stmpe811_enable,
504 .get_altfunc = stmpe811_get_altfunc,
505};
506
27e34995
RV		 507/*
508 * STMPE1601
509 */
510
511static const u8 stmpe1601_regs[] = {
512 [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
513 [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
514 [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
515 [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
516 [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
517 [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
518 [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
519 [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
520 [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
521 [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
522 [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
523 [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
524 [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
525 [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB,
526};
527
528static struct stmpe_variant_block stmpe1601_blocks[] = {
529 {
530 .cell = &stmpe_gpio_cell,
531 .irq = STMPE24XX_IRQ_GPIOC,
532 .block = STMPE_BLOCK_GPIO,
533 },
534 {
535 .cell = &stmpe_keypad_cell,
536 .irq = STMPE24XX_IRQ_KEYPAD,
537 .block = STMPE_BLOCK_KEYPAD,
538 },
539};
540
5981f4e6
SI		 541/* supported autosleep timeout delay (in msecs) */
542static const int stmpe_autosleep_delay[] = {
543 4, 16, 32, 64, 128, 256, 512, 1024,
544};
545
546static int stmpe_round_timeout(int timeout)
547{
548 int i;
549
550 for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
551 if (stmpe_autosleep_delay[i] >= timeout)
552 return i;
553 }
554
555 /*
556 * requests for delays longer than supported should not return the
557 * longest supported delay
558 */
559 return -EINVAL;
560}
561
562static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
563{
564 int ret;
565
566 if (!stmpe->variant->enable_autosleep)
567 return -ENOSYS;
568
569 mutex_lock(&stmpe->lock);
570 ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
571 mutex_unlock(&stmpe->lock);
572
573 return ret;
574}
575
576/*
577 * Both stmpe 1601/2403 support same layout for autosleep
578 */
579static int stmpe1601_autosleep(struct stmpe *stmpe,
580 int autosleep_timeout)
581{
582 int ret, timeout;
583
584 /* choose the best available timeout */
585 timeout = stmpe_round_timeout(autosleep_timeout);
586 if (timeout < 0) {
587 dev_err(stmpe->dev, "invalid timeout\n");
588 return timeout;
589 }
590
591 ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
592 STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
593 timeout);
594 if (ret < 0)
595 return ret;
596
597 return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2,
598 STPME1601_AUTOSLEEP_ENABLE,
599 STPME1601_AUTOSLEEP_ENABLE);
600}
601
27e34995
RV		 602static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
603 bool enable)
604{
605 unsigned int mask = 0;
606
607 if (blocks & STMPE_BLOCK_GPIO)
608 mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
609
610 if (blocks & STMPE_BLOCK_KEYPAD)
611 mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
612
613 return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask,
614 enable ? mask : 0);
615}
616
617static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
618{
619 switch (block) {
620 case STMPE_BLOCK_PWM:
621 return 2;
622
623 case STMPE_BLOCK_KEYPAD:
624 return 1;
625
626 case STMPE_BLOCK_GPIO:
627 default:
628 return 0;
629 }
630}
631
632static struct stmpe_variant_info stmpe1601 = {
633 .name = "stmpe1601",
634 .id_val = 0x0210,
635 .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
636 .num_gpios = 16,
637 .af_bits = 2,
638 .regs = stmpe1601_regs,
639 .blocks = stmpe1601_blocks,
640 .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
641 .num_irqs = STMPE1601_NR_INTERNAL_IRQS,
642 .enable = stmpe1601_enable,
643 .get_altfunc = stmpe1601_get_altfunc,
5981f4e6 644 .enable_autosleep = stmpe1601_autosleep,
27e34995
RV		 645};
646
647/*
648 * STMPE24XX
649 */
650
651static const u8 stmpe24xx_regs[] = {
652 [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
653 [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
654 [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
655 [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
656 [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
657 [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
658 [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
659 [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
660 [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
661 [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
662 [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
663 [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
664 [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
665 [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
666};
667
668static struct stmpe_variant_block stmpe24xx_blocks[] = {
669 {
670 .cell = &stmpe_gpio_cell,
671 .irq = STMPE24XX_IRQ_GPIOC,
672 .block = STMPE_BLOCK_GPIO,
673 },
674 {
675 .cell = &stmpe_keypad_cell,
676 .irq = STMPE24XX_IRQ_KEYPAD,
677 .block = STMPE_BLOCK_KEYPAD,
678 },
679};
680
681static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
682 bool enable)
683{
684 unsigned int mask = 0;
685
686 if (blocks & STMPE_BLOCK_GPIO)
687 mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
688
689 if (blocks & STMPE_BLOCK_KEYPAD)
690 mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
691
692 return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask,
693 enable ? mask : 0);
694}
695
696static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
697{
698 switch (block) {
699 case STMPE_BLOCK_ROTATOR:
700 return 2;
701
702 case STMPE_BLOCK_KEYPAD:
703 return 1;
704
705 case STMPE_BLOCK_GPIO:
706 default:
707 return 0;
708 }
709}
710
711static struct stmpe_variant_info stmpe2401 = {
712 .name = "stmpe2401",
713 .id_val = 0x0101,
714 .id_mask = 0xffff,
715 .num_gpios = 24,
716 .af_bits = 2,
717 .regs = stmpe24xx_regs,
718 .blocks = stmpe24xx_blocks,
719 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
720 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
721 .enable = stmpe24xx_enable,
722 .get_altfunc = stmpe24xx_get_altfunc,
723};
724
725static struct stmpe_variant_info stmpe2403 = {
726 .name = "stmpe2403",
727 .id_val = 0x0120,
728 .id_mask = 0xffff,
729 .num_gpios = 24,
730 .af_bits = 2,
731 .regs = stmpe24xx_regs,
732 .blocks = stmpe24xx_blocks,
733 .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
734 .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
735 .enable = stmpe24xx_enable,
736 .get_altfunc = stmpe24xx_get_altfunc,
5981f4e6 737 .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
27e34995
RV		 738};
739
e31f9b82 740static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
1cda2394 741 [STMPE610] = &stmpe610,
7f7f4ea1 742 [STMPE801] = &stmpe801,
27e34995
RV		 743 [STMPE811] = &stmpe811,
744 [STMPE1601] = &stmpe1601,
745 [STMPE2401] = &stmpe2401,
746 [STMPE2403] = &stmpe2403,
747};
748
e31f9b82
CB		 749/*
750 * These devices can be connected in a 'no-irq' configuration - the irq pin
751 * is not used and the device cannot interrupt the CPU. Here we only list
752 * devices which support this configuration - the driver will fail probing
753 * for any devices not listed here which are configured in this way.
754 */
755static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
756 [STMPE801] = &stmpe801_noirq,
757};
758
27e34995
RV		 759static irqreturn_t stmpe_irq(int irq, void *data)
760{
761 struct stmpe *stmpe = data;
762 struct stmpe_variant_info *variant = stmpe->variant;
763 int num = DIV_ROUND_UP(variant->num_irqs, 8);
764 u8 israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
765 u8 isr[num];
766 int ret;
767 int i;
768
7f7f4ea1
VK		 769 if (variant->id_val == STMPE801_ID) {
770 handle_nested_irq(stmpe->irq_base);
771 return IRQ_HANDLED;
772 }
773
27e34995
RV		 774 ret = stmpe_block_read(stmpe, israddr, num, isr);
775 if (ret < 0)
776 return IRQ_NONE;
777
778 for (i = 0; i < num; i++) {
779 int bank = num - i - 1;
780 u8 status = isr[i];
781 u8 clear;
782
783 status &= stmpe->ier[bank];
784 if (!status)
785 continue;
786
787 clear = status;
788 while (status) {
789 int bit = __ffs(status);
790 int line = bank * 8 + bit;
791
792 handle_nested_irq(stmpe->irq_base + line);
793 status &= ~(1 << bit);
794 }
795
796 stmpe_reg_write(stmpe, israddr + i, clear);
797 }
798
799 return IRQ_HANDLED;
800}
801
43b8c084 802static void stmpe_irq_lock(struct irq_data *data)
27e34995 803{
43b8c084 804 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
27e34995
RV		 805
806 mutex_lock(&stmpe->irq_lock);
807}
808
43b8c084 809static void stmpe_irq_sync_unlock(struct irq_data *data)
27e34995 810{
43b8c084 811 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
27e34995
RV		 812 struct stmpe_variant_info *variant = stmpe->variant;
813 int num = DIV_ROUND_UP(variant->num_irqs, 8);
814 int i;
815
816 for (i = 0; i < num; i++) {
817 u8 new = stmpe->ier[i];
818 u8 old = stmpe->oldier[i];
819
820 if (new == old)
821 continue;
822
823 stmpe->oldier[i] = new;
824 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new);
825 }
826
827 mutex_unlock(&stmpe->irq_lock);
828}
829
43b8c084 830static void stmpe_irq_mask(struct irq_data *data)
27e34995 831{
43b8c084
MB		 832 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
833 int offset = data->irq - stmpe->irq_base;
27e34995
RV		 834 int regoffset = offset / 8;
835 int mask = 1 << (offset % 8);
836
837 stmpe->ier[regoffset] &= ~mask;
838}
839
43b8c084 840static void stmpe_irq_unmask(struct irq_data *data)
27e34995 841{
43b8c084
MB		 842 struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
843 int offset = data->irq - stmpe->irq_base;
27e34995
RV		 844 int regoffset = offset / 8;
845 int mask = 1 << (offset % 8);
846
847 stmpe->ier[regoffset] |= mask;
848}
849
850static struct irq_chip stmpe_irq_chip = {
851 .name = "stmpe",
43b8c084
MB		 852 .irq_bus_lock = stmpe_irq_lock,
853 .irq_bus_sync_unlock = stmpe_irq_sync_unlock,
854 .irq_mask = stmpe_irq_mask,
855 .irq_unmask = stmpe_irq_unmask,
27e34995
RV		 856};
857
858static int __devinit stmpe_irq_init(struct stmpe *stmpe)
859{
7f7f4ea1 860 struct irq_chip *chip = NULL;
27e34995
RV		 861 int num_irqs = stmpe->variant->num_irqs;
862 int base = stmpe->irq_base;
863 int irq;
864
7f7f4ea1
VK		 865 if (stmpe->variant->id_val != STMPE801_ID)
866 chip = &stmpe_irq_chip;
867
27e34995 868 for (irq = base; irq < base + num_irqs; irq++) {
d5bb1221 869 irq_set_chip_data(irq, stmpe);
7f7f4ea1 870 irq_set_chip_and_handler(irq, chip, handle_edge_irq);
d5bb1221 871 irq_set_nested_thread(irq, 1);
27e34995
RV		 872#ifdef CONFIG_ARM
873 set_irq_flags(irq, IRQF_VALID);
874#else
d5bb1221 875 irq_set_noprobe(irq);
27e34995
RV		 876#endif
877 }
878
879 return 0;
880}
881
882static void stmpe_irq_remove(struct stmpe *stmpe)
883{
884 int num_irqs = stmpe->variant->num_irqs;
885 int base = stmpe->irq_base;
886 int irq;
887
888 for (irq = base; irq < base + num_irqs; irq++) {
889#ifdef CONFIG_ARM
890 set_irq_flags(irq, 0);
891#endif
d5bb1221
TG		 892 irq_set_chip_and_handler(irq, NULL, NULL);
893 irq_set_chip_data(irq, NULL);
27e34995
RV		 894 }
895}
896
897static int __devinit stmpe_chip_init(struct stmpe *stmpe)
898{
899 unsigned int irq_trigger = stmpe->pdata->irq_trigger;
5981f4e6 900 int autosleep_timeout = stmpe->pdata->autosleep_timeout;
27e34995 901 struct stmpe_variant_info *variant = stmpe->variant;
e31f9b82 902 u8 icr = 0;
27e34995
RV		 903 unsigned int id;
904 u8 data[2];
905 int ret;
906
907 ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
908 ARRAY_SIZE(data), data);
909 if (ret < 0)
910 return ret;
911
912 id = (data[0] << 8) | data[1];
913 if ((id & variant->id_mask) != variant->id_val) {
914 dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
915 return -EINVAL;
916 }
917
918 dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
919
920 /* Disable all modules -- subdrivers should enable what they need. */
921 ret = stmpe_disable(stmpe, ~0);
922 if (ret)
923 return ret;
924
e31f9b82 925 if (stmpe->irq >= 0) {
7f7f4ea1 926 if (id == STMPE801_ID)
e31f9b82 927 icr = STMPE801_REG_SYS_CTRL_INT_EN;
7f7f4ea1 928 else
e31f9b82 929 icr = STMPE_ICR_LSB_GIM;
27e34995 930
e31f9b82
CB		 931 /* STMPE801 doesn't support Edge interrupts */
932 if (id != STMPE801_ID) {
933 if (irq_trigger == IRQF_TRIGGER_FALLING ||
934 irq_trigger == IRQF_TRIGGER_RISING)
935 icr |= STMPE_ICR_LSB_EDGE;
936 }
937
938 if (irq_trigger == IRQF_TRIGGER_RISING ||
939 irq_trigger == IRQF_TRIGGER_HIGH) {
940 if (id == STMPE801_ID)
941 icr |= STMPE801_REG_SYS_CTRL_INT_HI;
942 else
943 icr |= STMPE_ICR_LSB_HIGH;
944 }
945
946 if (stmpe->pdata->irq_invert_polarity) {
947 if (id == STMPE801_ID)
948 icr ^= STMPE801_REG_SYS_CTRL_INT_HI;
949 else
950 icr ^= STMPE_ICR_LSB_HIGH;
951 }
7f7f4ea1 952 }
27e34995 953
5981f4e6
SI		 954 if (stmpe->pdata->autosleep) {
955 ret = stmpe_autosleep(stmpe, autosleep_timeout);
956 if (ret)
957 return ret;
958 }
959
27e34995
RV		 960 return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
961}
962
963static int __devinit stmpe_add_device(struct stmpe *stmpe,
964 struct mfd_cell *cell, int irq)
965{
966 return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
0848c94f 967 NULL, stmpe->irq_base + irq, NULL);
27e34995
RV		 968}
969
970static int __devinit stmpe_devices_init(struct stmpe *stmpe)
971{
972 struct stmpe_variant_info *variant = stmpe->variant;
973 unsigned int platform_blocks = stmpe->pdata->blocks;
974 int ret = -EINVAL;
975 int i;
976
977 for (i = 0; i < variant->num_blocks; i++) {
978 struct stmpe_variant_block *block = &variant->blocks[i];
979
980 if (!(platform_blocks & block->block))
981 continue;
982
983 platform_blocks &= ~block->block;
984 ret = stmpe_add_device(stmpe, block->cell, block->irq);
985 if (ret)
986 return ret;
987 }
988
989 if (platform_blocks)
990 dev_warn(stmpe->dev,
991 "platform wants blocks (%#x) not present on variant",
992 platform_blocks);
993
994 return ret;
995}
996
1a6e4b74 997/* Called from client specific probe routines */
8ad1a973 998int __devinit stmpe_probe(struct stmpe_client_info *ci, int partnum)
208c4343 999{
1a6e4b74 1000 struct stmpe_platform_data *pdata = dev_get_platdata(ci->dev);
27e34995
RV		 1001 struct stmpe *stmpe;
1002 int ret;
1003
1004 if (!pdata)
1005 return -EINVAL;
1006
1007 stmpe = kzalloc(sizeof(struct stmpe), GFP_KERNEL);
1008 if (!stmpe)
1009 return -ENOMEM;
1010
1011 mutex_init(&stmpe->irq_lock);
1012 mutex_init(&stmpe->lock);
1013
1a6e4b74
VK		 1014 stmpe->dev = ci->dev;
1015 stmpe->client = ci->client;
27e34995
RV		 1016 stmpe->pdata = pdata;
1017 stmpe->irq_base = pdata->irq_base;
1a6e4b74
VK		 1018 stmpe->ci = ci;
1019 stmpe->partnum = partnum;
1020 stmpe->variant = stmpe_variant_info[partnum];
27e34995
RV		 1021 stmpe->regs = stmpe->variant->regs;
1022 stmpe->num_gpios = stmpe->variant->num_gpios;
1a6e4b74 1023 dev_set_drvdata(stmpe->dev, stmpe);
27e34995 1024
1a6e4b74
VK		 1025 if (ci->init)
1026 ci->init(stmpe);
27e34995 1027
73de16db
VK		 1028 if (pdata->irq_over_gpio) {
1029 ret = gpio_request_one(pdata->irq_gpio, GPIOF_DIR_IN, "stmpe");
1030 if (ret) {
1031 dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
1032 ret);
1033 goto out_free;
1034 }
1035
1036 stmpe->irq = gpio_to_irq(pdata->irq_gpio);
1037 } else {
1a6e4b74 1038 stmpe->irq = ci->irq;
73de16db
VK		 1039 }
1040
e31f9b82
CB		 1041 if (stmpe->irq < 0) {
1042 /* use alternate variant info for no-irq mode, if supported */
1043 dev_info(stmpe->dev,
1044 "%s configured in no-irq mode by platform data\n",
1045 stmpe->variant->name);
1046 if (!stmpe_noirq_variant_info[stmpe->partnum]) {
1047 dev_err(stmpe->dev,
1048 "%s does not support no-irq mode!\n",
1049 stmpe->variant->name);
1050 ret = -ENODEV;
1051 goto free_gpio;
1052 }
1053 stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
1054 }
1055
27e34995
RV		 1056 ret = stmpe_chip_init(stmpe);
1057 if (ret)
73de16db 1058 goto free_gpio;
27e34995 1059
e31f9b82
CB		 1060 if (stmpe->irq >= 0) {
1061 ret = stmpe_irq_init(stmpe);
1062 if (ret)
1063 goto free_gpio;
27e34995 1064
e31f9b82
CB		 1065 ret = request_threaded_irq(stmpe->irq, NULL, stmpe_irq,
1066 pdata->irq_trigger | IRQF_ONESHOT,
1067 "stmpe", stmpe);
1068 if (ret) {
1069 dev_err(stmpe->dev, "failed to request IRQ: %d\n",
1070 ret);
1071 goto out_removeirq;
1072 }
27e34995
RV		 1073 }
1074
1075 ret = stmpe_devices_init(stmpe);
1076 if (ret) {
1077 dev_err(stmpe->dev, "failed to add children\n");
1078 goto out_removedevs;
1079 }
1080
1081 return 0;
1082
1083out_removedevs:
1084 mfd_remove_devices(stmpe->dev);
e31f9b82
CB		 1085 if (stmpe->irq >= 0)
1086 free_irq(stmpe->irq, stmpe);
27e34995 1087out_removeirq:
e31f9b82
CB		 1088 if (stmpe->irq >= 0)
1089 stmpe_irq_remove(stmpe);
73de16db
VK		 1090free_gpio:
1091 if (pdata->irq_over_gpio)
1092 gpio_free(pdata->irq_gpio);
27e34995
RV		 1093out_free:
1094 kfree(stmpe);
1095 return ret;
1096}
1097
1a6e4b74 1098int stmpe_remove(struct stmpe *stmpe)
27e34995 1099{
27e34995
RV		 1100 mfd_remove_devices(stmpe->dev);
1101
e31f9b82
CB		 1102 if (stmpe->irq >= 0) {
1103 free_irq(stmpe->irq, stmpe);
1104 stmpe_irq_remove(stmpe);
1105 }
27e34995 1106
73de16db
VK		 1107 if (stmpe->pdata->irq_over_gpio)
1108 gpio_free(stmpe->pdata->irq_gpio);
1109
27e34995
RV		 1110 kfree(stmpe);
1111
1112 return 0;
1113}
1114
208c4343 1115#ifdef CONFIG_PM
1a6e4b74
VK		 1116static int stmpe_suspend(struct device *dev)
1117{
1118 struct stmpe *stmpe = dev_get_drvdata(dev);
208c4343 1119
e31f9b82 1120 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1a6e4b74 1121 enable_irq_wake(stmpe->irq);
27e34995 1122
1a6e4b74 1123 return 0;
27e34995 1124}
27e34995 1125
1a6e4b74 1126static int stmpe_resume(struct device *dev)
27e34995 1127{
1a6e4b74
VK		 1128 struct stmpe *stmpe = dev_get_drvdata(dev);
1129
e31f9b82 1130 if (stmpe->irq >= 0 && device_may_wakeup(dev))
1a6e4b74
VK		 1131 disable_irq_wake(stmpe->irq);
1132
1133 return 0;
27e34995 1134}
27e34995 1135
1a6e4b74
VK		 1136const struct dev_pm_ops stmpe_dev_pm_ops = {
1137 .suspend = stmpe_suspend,
1138 .resume = stmpe_resume,
1139};
1140#endif
kernel source for telekom puls (alcatel/mediatek)