[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / ezx-pcap.c

/*
 * Driver for Motorola PCAP2 as present in EZX phones
 *
 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/ezx-pcap.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#define PCAP_ADC_MAXQ		8
struct pcap_adc_request {
	u8 bank;
	u8 ch[2];
	u32 flags;
	void (*callback)(void *, u16[]);
	void *data;
};

struct pcap_adc_sync_request {
	u16 res[2];
	struct completion completion;
};

struct pcap_chip {
	struct spi_device *spi;

	/* IO */
	u32 buf;
	struct mutex io_mutex;

	/* IRQ */
	unsigned int irq_base;
	u32 msr;
	struct work_struct isr_work;
	struct work_struct msr_work;
	struct workqueue_struct *workqueue;

	/* ADC */
	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	u8 adc_head;
	u8 adc_tail;
	struct mutex adc_mutex;
};

/* IO */
static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
{
	struct spi_transfer t;
	struct spi_message m;
	int status;

	memset(&t, 0, sizeof t);
	spi_message_init(&m);
	t.len = sizeof(u32);
	spi_message_add_tail(&t, &m);

	pcap->buf = *data;
	t.tx_buf = (u8 *) &pcap->buf;
	t.rx_buf = (u8 *) &pcap->buf;
	status = spi_sync(pcap->spi, &m);

	if (status == 0)
		*data = pcap->buf;

	return status;
}

int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
{
	int ret;

	mutex_lock(&pcap->io_mutex);
	value &= PCAP_REGISTER_VALUE_MASK;
	value |= PCAP_REGISTER_WRITE_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	ret = ezx_pcap_putget(pcap, &value);
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_write);

int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
{
	int ret;

	mutex_lock(&pcap->io_mutex);
	*value = PCAP_REGISTER_READ_OP_BIT
		| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, value);
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_read);

int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
{
	int ret;
	u32 tmp = PCAP_REGISTER_READ_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	mutex_lock(&pcap->io_mutex);
	ret = ezx_pcap_putget(pcap, &tmp);
	if (ret)
		goto out_unlock;

	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
		(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);

	ret = ezx_pcap_putget(pcap, &tmp);
out_unlock:
	mutex_unlock(&pcap->io_mutex);

	return ret;
}
EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);

/* IRQ */
int irq_to_pcap(struct pcap_chip *pcap, int irq)
{
	return irq - pcap->irq_base;
}
EXPORT_SYMBOL_GPL(irq_to_pcap);

int pcap_to_irq(struct pcap_chip *pcap, int irq)
{
	return pcap->irq_base + irq;
}
EXPORT_SYMBOL_GPL(pcap_to_irq);

static void pcap_mask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static void pcap_unmask_irq(struct irq_data *d)
{
	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);

	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
	queue_work(pcap->workqueue, &pcap->msr_work);
}

static struct irq_chip pcap_irq_chip = {
	.name		= "pcap",
	.irq_disable	= pcap_mask_irq,
	.irq_mask	= pcap_mask_irq,
	.irq_unmask	= pcap_unmask_irq,
};

static void pcap_msr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);

	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
}

static void pcap_isr_work(struct work_struct *work)
{
	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
	struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
	u32 msr, isr, int_sel, service;
	int irq;

	do {
		ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
		ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);

		/* We can't service/ack irqs that are assigned to port 2 */
		if (!(pdata->config & PCAP_SECOND_PORT)) {
			ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
			isr &= ~int_sel;
		}

		ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
		ezx_pcap_write(pcap, PCAP_REG_ISR, isr);

		local_irq_disable();
		service = isr & ~msr;
		for (irq = pcap->irq_base; service; service >>= 1, irq++) {
			if (service & 1)
				generic_handle_irq(irq);
		}
		local_irq_enable();
		ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	} while (gpio_get_value(pdata->gpio));
}

static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pcap_chip *pcap = irq_get_handler_data(irq);

	desc->irq_data.chip->irq_ack(&desc->irq_data);
	queue_work(pcap->workqueue, &pcap->isr_work);
	return;
}

/* ADC */
void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
{
	u32 tmp;

	mutex_lock(&pcap->adc_mutex);
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	mutex_unlock(&pcap->adc_mutex);
}
EXPORT_SYMBOL_GPL(pcap_set_ts_bits);

static void pcap_disable_adc(struct pcap_chip *pcap)
{
	u32 tmp;

	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
}

static void pcap_adc_trigger(struct pcap_chip *pcap)
{
	u32 tmp;
	u8 head;

	mutex_lock(&pcap->adc_mutex);
	head = pcap->adc_head;
	if (!pcap->adc_queue[head]) {
		/* queue is empty, save power */
		pcap_disable_adc(pcap);
		mutex_unlock(&pcap->adc_mutex);
		return;
	}
	/* start conversion on requested bank, save TS_M bits */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
	tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;

	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
		tmp |= PCAP_ADC_AD_SEL1;

	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	mutex_unlock(&pcap->adc_mutex);
	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
}

static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
{
	struct pcap_chip *pcap = _pcap;
	struct pcap_adc_request *req;
	u16 res[2];
	u32 tmp;

	mutex_lock(&pcap->adc_mutex);
	req = pcap->adc_queue[pcap->adc_head];

	if (WARN(!req, "adc irq without pending request\n")) {
		mutex_unlock(&pcap->adc_mutex);
		return IRQ_HANDLED;
	}

	/* read requested channels results */
	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
	tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;

	pcap->adc_queue[pcap->adc_head] = NULL;
	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
	mutex_unlock(&pcap->adc_mutex);

	/* pass the results and release memory */
	req->callback(req->data, res);
	kfree(req);

	/* trigger next conversion (if any) on queue */
	pcap_adc_trigger(pcap);

	return IRQ_HANDLED;
}

int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
						void *callback, void *data)
{
	struct pcap_adc_request *req;

	/* This will be freed after we have a result */
	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	if (!req)
		return -ENOMEM;

	req->bank = bank;
	req->flags = flags;
	req->ch[0] = ch[0];
	req->ch[1] = ch[1];
	req->callback = callback;
	req->data = data;

	mutex_lock(&pcap->adc_mutex);
	if (pcap->adc_queue[pcap->adc_tail]) {
		mutex_unlock(&pcap->adc_mutex);
		kfree(req);
		return -EBUSY;
	}
	pcap->adc_queue[pcap->adc_tail] = req;
	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
	mutex_unlock(&pcap->adc_mutex);

	/* start conversion */
	pcap_adc_trigger(pcap);

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_async);

static void pcap_adc_sync_cb(void *param, u16 res[])
{
	struct pcap_adc_sync_request *req = param;

	req->res[0] = res[0];
	req->res[1] = res[1];
	complete(&req->completion);
}

int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
								u16 res[])
{
	struct pcap_adc_sync_request sync_data;
	int ret;

	init_completion(&sync_data.completion);
	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
								&sync_data);
	if (ret)
		return ret;
	wait_for_completion(&sync_data.completion);
	res[0] = sync_data.res[0];
	res[1] = sync_data.res[1];

	return 0;
}
EXPORT_SYMBOL_GPL(pcap_adc_sync);

/* subdevs */
static int pcap_remove_subdev(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pcap_add_subdev(struct pcap_chip *pcap,
						struct pcap_subdev *subdev)
{
	struct platform_device *pdev;
	int ret;

	pdev = platform_device_alloc(subdev->name, subdev->id);
	if (!pdev)
		return -ENOMEM;

	pdev->dev.parent = &pcap->spi->dev;
	pdev->dev.platform_data = subdev->platform_data;

	ret = platform_device_add(pdev);
	if (ret)
		platform_device_put(pdev);

	return ret;
}

static int ezx_pcap_remove(struct spi_device *spi)
{
	struct pcap_chip *pcap = spi_get_drvdata(spi);
	struct pcap_platform_data *pdata = spi->dev.platform_data;
	int i, adc_irq;

	/* remove all registered subdevs */
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);

	/* cleanup ADC */
	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
				PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
	devm_free_irq(&spi->dev, adc_irq, pcap);
	mutex_lock(&pcap->adc_mutex);
	for (i = 0; i < PCAP_ADC_MAXQ; i++)
		kfree(pcap->adc_queue[i]);
	mutex_unlock(&pcap->adc_mutex);

	/* cleanup irqchip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);

	destroy_workqueue(pcap->workqueue);

	return 0;
}

static int ezx_pcap_probe(struct spi_device *spi)
{
	struct pcap_platform_data *pdata = spi->dev.platform_data;
	struct pcap_chip *pcap;
	int i, adc_irq;
	int ret = -ENODEV;

	/* platform data is required */
	if (!pdata)
		goto ret;

	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
	if (!pcap) {
		ret = -ENOMEM;
		goto ret;
	}

	mutex_init(&pcap->io_mutex);
	mutex_init(&pcap->adc_mutex);
	INIT_WORK(&pcap->isr_work, pcap_isr_work);
	INIT_WORK(&pcap->msr_work, pcap_msr_work);
	spi_set_drvdata(spi, pcap);

	/* setup spi */
	spi->bits_per_word = 32;
	spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	ret = spi_setup(spi);
	if (ret)
		goto ret;

	pcap->spi = spi;

	/* setup irq */
	pcap->irq_base = pdata->irq_base;
	pcap->workqueue = create_singlethread_workqueue("pcapd");
	if (!pcap->workqueue) {
		ret = -ENOMEM;
		dev_err(&spi->dev, "can't create pcap thread\n");
		goto ret;
	}

	/* redirect interrupts to AP, except adcdone2 */
	if (!(pdata->config & PCAP_SECOND_PORT))
		ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
					(1 << PCAP_IRQ_ADCDONE2));

	/* setup irq chip */
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
		irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
		irq_set_chip_data(i, pcap);
#ifdef CONFIG_ARM
		set_irq_flags(i, IRQF_VALID);
#else
		irq_set_noprobe(i);
#endif
	}

	/* mask/ack all PCAP interrupts */
	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	pcap->msr = PCAP_MASK_ALL_INTERRUPT;

	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
	irq_set_handler_data(spi->irq, pcap);
	irq_set_chained_handler(spi->irq, pcap_irq_handler);
	irq_set_irq_wake(spi->irq, 1);

	/* ADC */
	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
					PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);

	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
				pcap);
	if (ret)
		goto free_irqchip;

	/* setup subdevs */
	for (i = 0; i < pdata->num_subdevs; i++) {
		ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
		if (ret)
			goto remove_subdevs;
	}

	/* board specific quirks */
	if (pdata->init)
		pdata->init(pcap);

	return 0;

remove_subdevs:
	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
/* free_adc: */
	devm_free_irq(&spi->dev, adc_irq, pcap);
free_irqchip:
	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
		irq_set_chip_and_handler(i, NULL, NULL);
/* destroy_workqueue: */
	destroy_workqueue(pcap->workqueue);
ret:
	return ret;
}

static struct spi_driver ezxpcap_driver = {
	.probe	= ezx_pcap_probe,
	.remove = ezx_pcap_remove,
	.driver = {
		.name	= "ezx-pcap",
		.owner	= THIS_MODULE,
	},
};

static int __init ezx_pcap_init(void)
{
	return spi_register_driver(&ezxpcap_driver);
}

static void __exit ezx_pcap_exit(void)
{
	spi_unregister_driver(&ezxpcap_driver);
}

subsys_initcall(ezx_pcap_init);
module_exit(ezx_pcap_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
MODULE_ALIAS("spi:ezx-pcap");
Commit	Line	Data
13a09f93 DR	1	/*
	2	* Driver for Motorola PCAP2 as present in EZX phones
	3	*
	4	* Copyright (C) 2006 Harald Welte <laforge@openezx.org>
	5	* Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/mfd/ezx-pcap.h>
	19	#include <linux/spi/spi.h>
b1148fd4	20	#include <linux/gpio.h>
5a0e3ad6	21	#include <linux/slab.h>
13a09f93 DR	22
	23	#define PCAP_ADC_MAXQ 8
	24	struct pcap_adc_request {
	25	u8 bank;
	26	u8 ch[2];
	27	u32 flags;
	28	void (callback)(void , u16[]);
	29	void *data;
	30	};
	31
	32	struct pcap_adc_sync_request {
	33	u16 res[2];
	34	struct completion completion;
	35	};
	36
	37	struct pcap_chip {
	38	struct spi_device *spi;
	39
	40	/* IO */
	41	u32 buf;
	42	struct mutex io_mutex;
	43
	44	/* IRQ */
	45	unsigned int irq_base;
	46	u32 msr;
	47	struct work_struct isr_work;
	48	struct work_struct msr_work;
	49	struct workqueue_struct *workqueue;
	50
	51	/* ADC */
	52	struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
	53	u8 adc_head;
	54	u8 adc_tail;
	55	struct mutex adc_mutex;
	56	};
	57
	58	/* IO */
	59	static int ezx_pcap_putget(struct pcap_chip pcap, u32 data)
	60	{
	61	struct spi_transfer t;
	62	struct spi_message m;
	63	int status;
	64
	65	memset(&t, 0, sizeof t);
	66	spi_message_init(&m);
	67	t.len = sizeof(u32);
	68	spi_message_add_tail(&t, &m);
	69
	70	pcap->buf = *data;
	71	t.tx_buf = (u8 *) &pcap->buf;
	72	t.rx_buf = (u8 *) &pcap->buf;
	73	status = spi_sync(pcap->spi, &m);
	74
	75	if (status == 0)
	76	*data = pcap->buf;
	77
	78	return status;
	79	}
	80
	81	int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
	82	{
	83	int ret;
	84
	85	mutex_lock(&pcap->io_mutex);
86	value &= PCAP_REGISTER_VALUE_MASK;
87	value \|= PCAP_REGISTER_WRITE_OP_BIT
88	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
89	ret = ezx_pcap_putget(pcap, &value);
90	mutex_unlock(&pcap->io_mutex);
91
92	return ret;
93	}
94	EXPORT_SYMBOL_GPL(ezx_pcap_write);
95
96	int ezx_pcap_read(struct pcap_chip pcap, u8 reg_num, u32 value)
97	{
98	int ret;
99
100	mutex_lock(&pcap->io_mutex);
101	*value = PCAP_REGISTER_READ_OP_BIT
102	\| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
103
104	ret = ezx_pcap_putget(pcap, value);
105	mutex_unlock(&pcap->io_mutex);
106
107	return ret;
108	}
109	EXPORT_SYMBOL_GPL(ezx_pcap_read);
110
e9a22635 DR	111	int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
	112	{
	113	int ret;
	114	u32 tmp = PCAP_REGISTER_READ_OP_BIT \|
	115	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	116
	117	mutex_lock(&pcap->io_mutex);
	118	ret = ezx_pcap_putget(pcap, &tmp);
	119	if (ret)
	120	goto out_unlock;
	121
	122	tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
	123	tmp \|= (val & mask) \| PCAP_REGISTER_WRITE_OP_BIT \|
	124	(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
	125
	126	ret = ezx_pcap_putget(pcap, &tmp);
	127	out_unlock:
	128	mutex_unlock(&pcap->io_mutex);
	129
	130	return ret;
	131	}
	132	EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
	133
13a09f93	134	/* IRQ */
9f7b07d6	135	int irq_to_pcap(struct pcap_chip *pcap, int irq)
13a09f93	136	{
9f7b07d6	137	return irq - pcap->irq_base;
13a09f93	138	}
9f7b07d6	139	EXPORT_SYMBOL_GPL(irq_to_pcap);
13a09f93 DR	140
	141	int pcap_to_irq(struct pcap_chip *pcap, int irq)
	142	{
	143	return pcap->irq_base + irq;
	144	}
	145	EXPORT_SYMBOL_GPL(pcap_to_irq);
	146
c232f22f	147	static void pcap_mask_irq(struct irq_data *d)
13a09f93	148	{
c232f22f	149	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	150
c232f22f	151	pcap->msr \|= 1 << irq_to_pcap(pcap, d->irq);
13a09f93 DR	152	queue_work(pcap->workqueue, &pcap->msr_work);
	153	}
	154
c232f22f	155	static void pcap_unmask_irq(struct irq_data *d)
13a09f93	156	{
c232f22f	157	struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
13a09f93	158
c232f22f	159	pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
13a09f93 DR	160	queue_work(pcap->workqueue, &pcap->msr_work);
	161	}
	162
	163	static struct irq_chip pcap_irq_chip = {
c232f22f	164	.name = "pcap",
73a6839f	165	.irq_disable = pcap_mask_irq,
c232f22f LB	166	.irq_mask = pcap_mask_irq,
c232f22f LB	167	.irq_unmask = pcap_unmask_irq,
13a09f93 DR	168	};
	169
	170	static void pcap_msr_work(struct work_struct *work)
	171	{
	172	struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
	173
	174	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
	175	}
	176
	177	static void pcap_isr_work(struct work_struct *work)
	178	{
	179	struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
	180	struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
	181	u32 msr, isr, int_sel, service;
	182	int irq;
	183
b1148fd4 DR	184	do {
	185	ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
	186	ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
13a09f93	187
25985edc	188	/* We can't service/ack irqs that are assigned to port 2 */
b1148fd4 DR	189	if (!(pdata->config & PCAP_SECOND_PORT)) {
	190	ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
	191	isr &= ~int_sel;
	192	}
13a09f93	193
b1148fd4 DR	194	ezx_pcap_write(pcap, PCAP_REG_MSR, isr \| msr);
b1148fd4 DR	195	ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
13a09f93	196
b1148fd4 DR	197	local_irq_disable();
	198	service = isr & ~msr;
	199	for (irq = pcap->irq_base; service; service >>= 1, irq++) {
73a6839f TG	200	if (service & 1)
73a6839f TG	201	generic_handle_irq(irq);
13a09f93	202	}
b1148fd4 DR	203	local_irq_enable();
b1148fd4 DR	204	ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
59ee93a5	205	} while (gpio_get_value(pdata->gpio));
13a09f93 DR	206	}
	207
	208	static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
	209	{
d5bb1221	210	struct pcap_chip *pcap = irq_get_handler_data(irq);
13a09f93	211
c232f22f	212	desc->irq_data.chip->irq_ack(&desc->irq_data);
13a09f93 DR	213	queue_work(pcap->workqueue, &pcap->isr_work);
	214	return;
	215	}
	216
	217	/* ADC */
ecd78cbd DR	218	void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
	219	{
	220	u32 tmp;
	221
	222	mutex_lock(&pcap->adc_mutex);
	223	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	224	tmp &= ~(PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	225	tmp \|= bits & (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	226	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	227	mutex_unlock(&pcap->adc_mutex);
	228	}
	229	EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
	230
13a09f93 DR	231	static void pcap_disable_adc(struct pcap_chip *pcap)
	232	{
	233	u32 tmp;
	234
	235	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	236	tmp &= ~(PCAP_ADC_ADEN\|PCAP_ADC_BATT_I_ADC\|PCAP_ADC_BATT_I_POLARITY);
	237	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	238	}
	239
	240	static void pcap_adc_trigger(struct pcap_chip *pcap)
	241	{
	242	u32 tmp;
	243	u8 head;
	244
	245	mutex_lock(&pcap->adc_mutex);
	246	head = pcap->adc_head;
	247	if (!pcap->adc_queue[head]) {
	248	/* queue is empty, save power */
	249	pcap_disable_adc(pcap);
	250	mutex_unlock(&pcap->adc_mutex);
	251	return;
	252	}
ecd78cbd DR	253	/* start conversion on requested bank, save TS_M bits */
	254	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	255	tmp &= (PCAP_ADC_TS_M_MASK \| PCAP_ADC_TS_REF_LOWPWR);
	256	tmp \|= pcap->adc_queue[head]->flags \| PCAP_ADC_ADEN;
13a09f93 DR	257
	258	if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
	259	tmp \|= PCAP_ADC_AD_SEL1;
	260
	261	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
ecd78cbd	262	mutex_unlock(&pcap->adc_mutex);
13a09f93 DR	263	ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
	264	}
	265
	266	static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
	267	{
	268	struct pcap_chip *pcap = _pcap;
	269	struct pcap_adc_request *req;
	270	u16 res[2];
	271	u32 tmp;
	272
	273	mutex_lock(&pcap->adc_mutex);
	274	req = pcap->adc_queue[pcap->adc_head];
	275
e0084aa9	276	if (WARN(!req, "adc irq without pending request\n")) {
1c90ea2c	277	mutex_unlock(&pcap->adc_mutex);
13a09f93	278	return IRQ_HANDLED;
1c90ea2c	279	}
13a09f93 DR	280
	281	/* read requested channels results */
	282	ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
	283	tmp &= ~(PCAP_ADC_ADA1_MASK \| PCAP_ADC_ADA2_MASK);
	284	tmp \|= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
	285	tmp \|= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
	286	ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
	287	ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
	288	res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
	289	res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
	290
	291	pcap->adc_queue[pcap->adc_head] = NULL;
	292	pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
	293	mutex_unlock(&pcap->adc_mutex);
	294
	295	/* pass the results and release memory */
	296	req->callback(req->data, res);
	297	kfree(req);
	298
	299	/* trigger next conversion (if any) on queue */
	300	pcap_adc_trigger(pcap);
	301
	302	return IRQ_HANDLED;
	303	}
	304
	305	int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
	306	void callback, void data)
	307	{
	308	struct pcap_adc_request *req;
	309
	310	/* This will be freed after we have a result */
	311	req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
	312	if (!req)
	313	return -ENOMEM;
	314
	315	req->bank = bank;
	316	req->flags = flags;
	317	req->ch[0] = ch[0];
	318	req->ch[1] = ch[1];
	319	req->callback = callback;
	320	req->data = data;
	321
	322	mutex_lock(&pcap->adc_mutex);
	323	if (pcap->adc_queue[pcap->adc_tail]) {
	324	mutex_unlock(&pcap->adc_mutex);
	325	kfree(req);
	326	return -EBUSY;
	327	}
	328	pcap->adc_queue[pcap->adc_tail] = req;
	329	pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
	330	mutex_unlock(&pcap->adc_mutex);
	331
	332	/* start conversion */
	333	pcap_adc_trigger(pcap);
	334
	335	return 0;
	336	}
	337	EXPORT_SYMBOL_GPL(pcap_adc_async);
	338
	339	static void pcap_adc_sync_cb(void *param, u16 res[])
	340	{
	341	struct pcap_adc_sync_request *req = param;
	342
	343	req->res[0] = res[0];
344	req->res[1] = res[1];
345	complete(&req->completion);
346	}
347
348	int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
349	u16 res[])
350	{
351	struct pcap_adc_sync_request sync_data;
352	int ret;
353
354	init_completion(&sync_data.completion);
355	ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
356	&sync_data);
357	if (ret)
358	return ret;
359	wait_for_completion(&sync_data.completion);
360	res[0] = sync_data.res[0];
361	res[1] = sync_data.res[1];
362
363	return 0;
364	}
365	EXPORT_SYMBOL_GPL(pcap_adc_sync);
366
367	/* subdevs */
368	static int pcap_remove_subdev(struct device dev, void unused)
369	{
370	platform_device_unregister(to_platform_device(dev));
371	return 0;
372	}
373
f791be49	374	static int pcap_add_subdev(struct pcap_chip *pcap,
13a09f93 DR	375	struct pcap_subdev *subdev)
	376	{
	377	struct platform_device *pdev;
09ff21e0	378	int ret;
13a09f93 DR	379
13a09f93 DR	380	pdev = platform_device_alloc(subdev->name, subdev->id);
09ff21e0 AL	381	if (!pdev)
	382	return -ENOMEM;
	383
13a09f93 DR	384	pdev->dev.parent = &pcap->spi->dev;
13a09f93 DR	385	pdev->dev.platform_data = subdev->platform_data;
13a09f93	386
09ff21e0 AL	387	ret = platform_device_add(pdev);
	388	if (ret)
	389	platform_device_put(pdev);
	390
	391	return ret;
13a09f93 DR	392	}
13a09f93 DR	393
4740f73f	394	static int ezx_pcap_remove(struct spi_device *spi)
13a09f93	395	{
7c478b40	396	struct pcap_chip *pcap = spi_get_drvdata(spi);
13a09f93 DR	397	struct pcap_platform_data *pdata = spi->dev.platform_data;
	398	int i, adc_irq;
	399
	400	/* remove all registered subdevs */
	401	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
	402
	403	/* cleanup ADC */
	404	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
	405	PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
1ba895e0	406	devm_free_irq(&spi->dev, adc_irq, pcap);
13a09f93 DR	407	mutex_lock(&pcap->adc_mutex);
	408	for (i = 0; i < PCAP_ADC_MAXQ; i++)
	409	kfree(pcap->adc_queue[i]);
	410	mutex_unlock(&pcap->adc_mutex);
	411
	412	/* cleanup irqchip */
	413	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	414	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	415
	416	destroy_workqueue(pcap->workqueue);
	417
13a09f93 DR	418	return 0;
	419	}
	420
f791be49	421	static int ezx_pcap_probe(struct spi_device *spi)
13a09f93 DR	422	{
	423	struct pcap_platform_data *pdata = spi->dev.platform_data;
	424	struct pcap_chip *pcap;
	425	int i, adc_irq;
	426	int ret = -ENODEV;
	427
	428	/* platform data is required */
	429	if (!pdata)
	430	goto ret;
	431
1ba895e0	432	pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
13a09f93 DR	433	if (!pcap) {
	434	ret = -ENOMEM;
	435	goto ret;
	436	}
	437
	438	mutex_init(&pcap->io_mutex);
	439	mutex_init(&pcap->adc_mutex);
	440	INIT_WORK(&pcap->isr_work, pcap_isr_work);
	441	INIT_WORK(&pcap->msr_work, pcap_msr_work);
7c478b40	442	spi_set_drvdata(spi, pcap);
13a09f93 DR	443
	444	/* setup spi */
	445	spi->bits_per_word = 32;
	446	spi->mode = SPI_MODE_0 \| (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
	447	ret = spi_setup(spi);
	448	if (ret)
1ba895e0	449	goto ret;
13a09f93 DR	450
	451	pcap->spi = spi;
	452
	453	/* setup irq */
	454	pcap->irq_base = pdata->irq_base;
	455	pcap->workqueue = create_singlethread_workqueue("pcapd");
	456	if (!pcap->workqueue) {
47dabaee	457	ret = -ENOMEM;
25985edc	458	dev_err(&spi->dev, "can't create pcap thread\n");
1ba895e0	459	goto ret;
13a09f93 DR	460	}
	461
	462	/* redirect interrupts to AP, except adcdone2 */
	463	if (!(pdata->config & PCAP_SECOND_PORT))
	464	ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
	465	(1 << PCAP_IRQ_ADCDONE2));
	466
	467	/* setup irq chip */
	468	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
d5bb1221 TG	469	irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
d5bb1221 TG	470	irq_set_chip_data(i, pcap);
13a09f93 DR	471	#ifdef CONFIG_ARM
	472	set_irq_flags(i, IRQF_VALID);
	473	#else
d5bb1221	474	irq_set_noprobe(i);
13a09f93 DR	475	#endif
	476	}
	477
	478	/* mask/ack all PCAP interrupts */
	479	ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
	480	ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
	481	pcap->msr = PCAP_MASK_ALL_INTERRUPT;
	482
d5bb1221 TG	483	irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
	484	irq_set_handler_data(spi->irq, pcap);
	485	irq_set_chained_handler(spi->irq, pcap_irq_handler);
	486	irq_set_irq_wake(spi->irq, 1);
13a09f93 DR	487
	488	/* ADC */
	489	adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
	490	PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
	491
1ba895e0 JH	492	ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
1ba895e0 JH	493	pcap);
13a09f93 DR	494	if (ret)
	495	goto free_irqchip;
	496
	497	/* setup subdevs */
	498	for (i = 0; i < pdata->num_subdevs; i++) {
	499	ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
	500	if (ret)
	501	goto remove_subdevs;
	502	}
	503
	504	/* board specific quirks */
	505	if (pdata->init)
	506	pdata->init(pcap);
	507
	508	return 0;
	509
	510	remove_subdevs:
	511	device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
	512	/* free_adc: */
1ba895e0	513	devm_free_irq(&spi->dev, adc_irq, pcap);
13a09f93 DR	514	free_irqchip:
13a09f93 DR	515	for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
d5bb1221	516	irq_set_chip_and_handler(i, NULL, NULL);
13a09f93 DR	517	/* destroy_workqueue: */
13a09f93 DR	518	destroy_workqueue(pcap->workqueue);
13a09f93 DR	519	ret:
	520	return ret;
	521	}
	522
	523	static struct spi_driver ezxpcap_driver = {
	524	.probe = ezx_pcap_probe,
84449216	525	.remove = ezx_pcap_remove,
13a09f93 DR	526	.driver = {
	527	.name = "ezx-pcap",
	528	.owner = THIS_MODULE,
	529	},
	530	};
	531
	532	static int __init ezx_pcap_init(void)
	533	{
	534	return spi_register_driver(&ezxpcap_driver);
	535	}
	536
	537	static void __exit ezx_pcap_exit(void)
	538	{
	539	spi_unregister_driver(&ezxpcap_driver);
	540	}
	541
f078237b	542	subsys_initcall(ezx_pcap_init);
13a09f93 DR	543	module_exit(ezx_pcap_exit);
	544
	545	MODULE_LICENSE("GPL");
	546	MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
	547	MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
e0626e38	548	MODULE_ALIAS("spi:ezx-pcap");