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Merge branches 'pxa-ian' and 'pxa-xm270' into pxa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / common / tuners / tda18271-common.c
CommitLineData
59067f7e
MK		 1/*
2 tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include "tda18271-priv.h"
22
23static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
24{
25 struct tda18271_priv *priv = fe->tuner_priv;
26 enum tda18271_i2c_gate gate;
27 int ret = 0;
28
29 switch (priv->gate) {
30 case TDA18271_GATE_DIGITAL:
31 case TDA18271_GATE_ANALOG:
32 gate = priv->gate;
33 break;
34 case TDA18271_GATE_AUTO:
35 default:
36 switch (priv->mode) {
37 case TDA18271_DIGITAL:
38 gate = TDA18271_GATE_DIGITAL;
39 break;
40 case TDA18271_ANALOG:
41 default:
42 gate = TDA18271_GATE_ANALOG;
43 break;
44 }
45 }
46
47 switch (gate) {
48 case TDA18271_GATE_ANALOG:
49 if (fe->ops.analog_ops.i2c_gate_ctrl)
50 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
51 break;
52 case TDA18271_GATE_DIGITAL:
53 if (fe->ops.i2c_gate_ctrl)
54 ret = fe->ops.i2c_gate_ctrl(fe, enable);
55 break;
56 default:
57 ret = -EINVAL;
58 break;
59 }
60
61 return ret;
62};
63
64/*---------------------------------------------------------------------*/
65
66static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
67{
68 struct tda18271_priv *priv = fe->tuner_priv;
69 unsigned char *regs = priv->tda18271_regs;
70
71 tda_reg("=== TDA18271 REG DUMP ===\n");
72 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
73 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
74 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
75 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
76 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
77 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
78 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
79 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
80 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
81 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
82 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
83 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
84 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
85 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
86 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
87 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
88
89 /* only dump extended regs if DBG_ADV is set */
90 if (!(tda18271_debug & DBG_ADV))
91 return;
92
93 /* W indicates write-only registers.
94 * Register dump for write-only registers shows last value written. */
95
96 tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
97 tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
98 tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
99 tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
100 tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
101 tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
102 tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
103 tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
104 tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
105 tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
106 tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
107 tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
108 tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
109 tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
110 tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
111 tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
112 tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
113 tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
114 tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
115 tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
116 tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
117 tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
118 tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
119}
120
121int tda18271_read_regs(struct dvb_frontend *fe)
122{
123 struct tda18271_priv *priv = fe->tuner_priv;
124 unsigned char *regs = priv->tda18271_regs;
125 unsigned char buf = 0x00;
126 int ret;
127 struct i2c_msg msg[] = {
f9e315a1 128 { .addr = priv->i2c_props.addr, .flags = 0,
59067f7e 129 .buf = &buf, .len = 1 },
f9e315a1 130 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
59067f7e
MK		 131 .buf = regs, .len = 16 }
132 };
133
134 tda18271_i2c_gate_ctrl(fe, 1);
135
136 /* read all registers */
f9e315a1 137 ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
59067f7e
MK		 138
139 tda18271_i2c_gate_ctrl(fe, 0);
140
141 if (ret != 2)
142 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
143
144 if (tda18271_debug & DBG_REG)
145 tda18271_dump_regs(fe, 0);
146
147 return (ret == 2 ? 0 : ret);
148}
149
150int tda18271_read_extended(struct dvb_frontend *fe)
151{
152 struct tda18271_priv *priv = fe->tuner_priv;
153 unsigned char *regs = priv->tda18271_regs;
154 unsigned char regdump[TDA18271_NUM_REGS];
155 unsigned char buf = 0x00;
156 int ret, i;
157 struct i2c_msg msg[] = {
f9e315a1 158 { .addr = priv->i2c_props.addr, .flags = 0,
59067f7e 159 .buf = &buf, .len = 1 },
f9e315a1 160 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
59067f7e
MK		 161 .buf = regdump, .len = TDA18271_NUM_REGS }
162 };
163
164 tda18271_i2c_gate_ctrl(fe, 1);
165
166 /* read all registers */
f9e315a1 167 ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
59067f7e
MK		 168
169 tda18271_i2c_gate_ctrl(fe, 0);
170
171 if (ret != 2)
172 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
173
805d92df 174 for (i = 0; i < TDA18271_NUM_REGS; i++) {
59067f7e
MK		 175 /* don't update write-only registers */
176 if ((i != R_EB9) &&
177 (i != R_EB16) &&
178 (i != R_EB17) &&
179 (i != R_EB19) &&
180 (i != R_EB20))
181 regs[i] = regdump[i];
182 }
183
184 if (tda18271_debug & DBG_REG)
185 tda18271_dump_regs(fe, 1);
186
187 return (ret == 2 ? 0 : ret);
188}
189
190int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
191{
192 struct tda18271_priv *priv = fe->tuner_priv;
193 unsigned char *regs = priv->tda18271_regs;
194 unsigned char buf[TDA18271_NUM_REGS + 1];
f9e315a1 195 struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
59067f7e
MK		 196 .buf = buf, .len = len + 1 };
197 int i, ret;
198
199 BUG_ON((len == 0) || (idx + len > sizeof(buf)));
200
201 buf[0] = idx;
202 for (i = 1; i <= len; i++)
203 buf[i] = regs[idx - 1 + i];
204
205 tda18271_i2c_gate_ctrl(fe, 1);
206
207 /* write registers */
f9e315a1 208 ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
59067f7e
MK		 209
210 tda18271_i2c_gate_ctrl(fe, 0);
211
212 if (ret != 1)
213 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
214
215 return (ret == 1 ? 0 : ret);
216}
217
218/*---------------------------------------------------------------------*/
219
4efb0ca5
MK		 220int tda18271_charge_pump_source(struct dvb_frontend *fe,
221 enum tda18271_pll pll, int force)
222{
223 struct tda18271_priv *priv = fe->tuner_priv;
224 unsigned char *regs = priv->tda18271_regs;
225
226 int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
227
228 regs[r_cp] &= ~0x20;
229 regs[r_cp] |= ((force & 1) << 5);
4efb0ca5 230
d35fccaf 231 return tda18271_write_regs(fe, r_cp, 1);
4efb0ca5
MK		 232}
233
59067f7e
MK		 234int tda18271_init_regs(struct dvb_frontend *fe)
235{
236 struct tda18271_priv *priv = fe->tuner_priv;
237 unsigned char *regs = priv->tda18271_regs;
238
239 tda_dbg("initializing registers for device @ %d-%04x\n",
f9e315a1
MK		 240 i2c_adapter_id(priv->i2c_props.adap),
241 priv->i2c_props.addr);
59067f7e
MK		 242
243 /* initialize registers */
244 switch (priv->id) {
245 case TDA18271HDC1:
246 regs[R_ID] = 0x83;
247 break;
248 case TDA18271HDC2:
249 regs[R_ID] = 0x84;
250 break;
251 };
252
253 regs[R_TM] = 0x08;
254 regs[R_PL] = 0x80;
255 regs[R_EP1] = 0xc6;
256 regs[R_EP2] = 0xdf;
257 regs[R_EP3] = 0x16;
258 regs[R_EP4] = 0x60;
259 regs[R_EP5] = 0x80;
260 regs[R_CPD] = 0x80;
261 regs[R_CD1] = 0x00;
262 regs[R_CD2] = 0x00;
263 regs[R_CD3] = 0x00;
264 regs[R_MPD] = 0x00;
265 regs[R_MD1] = 0x00;
266 regs[R_MD2] = 0x00;
267 regs[R_MD3] = 0x00;
268
269 switch (priv->id) {
270 case TDA18271HDC1:
271 regs[R_EB1] = 0xff;
272 break;
273 case TDA18271HDC2:
274 regs[R_EB1] = 0xfc;
275 break;
276 };
277
278 regs[R_EB2] = 0x01;
279 regs[R_EB3] = 0x84;
280 regs[R_EB4] = 0x41;
281 regs[R_EB5] = 0x01;
282 regs[R_EB6] = 0x84;
283 regs[R_EB7] = 0x40;
284 regs[R_EB8] = 0x07;
285 regs[R_EB9] = 0x00;
286 regs[R_EB10] = 0x00;
287 regs[R_EB11] = 0x96;
288
289 switch (priv->id) {
290 case TDA18271HDC1:
291 regs[R_EB12] = 0x0f;
292 break;
293 case TDA18271HDC2:
294 regs[R_EB12] = 0x33;
295 break;
296 };
297
298 regs[R_EB13] = 0xc1;
299 regs[R_EB14] = 0x00;
300 regs[R_EB15] = 0x8f;
301 regs[R_EB16] = 0x00;
302 regs[R_EB17] = 0x00;
303
304 switch (priv->id) {
305 case TDA18271HDC1:
306 regs[R_EB18] = 0x00;
307 break;
308 case TDA18271HDC2:
309 regs[R_EB18] = 0x8c;
310 break;
311 };
312
313 regs[R_EB19] = 0x00;
314 regs[R_EB20] = 0x20;
315
316 switch (priv->id) {
317 case TDA18271HDC1:
318 regs[R_EB21] = 0x33;
319 break;
320 case TDA18271HDC2:
321 regs[R_EB21] = 0xb3;
322 break;
323 };
324
325 regs[R_EB22] = 0x48;
326 regs[R_EB23] = 0xb0;
327
5555309c
MK		 328 if (priv->small_i2c) {
329 tda18271_write_regs(fe, 0x00, 0x10);
330 tda18271_write_regs(fe, 0x10, 0x10);
331 tda18271_write_regs(fe, 0x20, 0x07);
332 } else
333 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
59067f7e
MK		 334
335 /* setup agc1 gain */
336 regs[R_EB17] = 0x00;
337 tda18271_write_regs(fe, R_EB17, 1);
338 regs[R_EB17] = 0x03;
339 tda18271_write_regs(fe, R_EB17, 1);
340 regs[R_EB17] = 0x43;
341 tda18271_write_regs(fe, R_EB17, 1);
342 regs[R_EB17] = 0x4c;
343 tda18271_write_regs(fe, R_EB17, 1);
344
345 /* setup agc2 gain */
346 if ((priv->id) == TDA18271HDC1) {
347 regs[R_EB20] = 0xa0;
348 tda18271_write_regs(fe, R_EB20, 1);
349 regs[R_EB20] = 0xa7;
350 tda18271_write_regs(fe, R_EB20, 1);
351 regs[R_EB20] = 0xe7;
352 tda18271_write_regs(fe, R_EB20, 1);
353 regs[R_EB20] = 0xec;
354 tda18271_write_regs(fe, R_EB20, 1);
355 }
356
357 /* image rejection calibration */
358
359 /* low-band */
360 regs[R_EP3] = 0x1f;
361 regs[R_EP4] = 0x66;
362 regs[R_EP5] = 0x81;
363 regs[R_CPD] = 0xcc;
364 regs[R_CD1] = 0x6c;
365 regs[R_CD2] = 0x00;
366 regs[R_CD3] = 0x00;
367 regs[R_MPD] = 0xcd;
368 regs[R_MD1] = 0x77;
369 regs[R_MD2] = 0x08;
370 regs[R_MD3] = 0x00;
371
e83ebb64 372 tda18271_write_regs(fe, R_EP3, 11);
59067f7e
MK		 373
374 if ((priv->id) == TDA18271HDC2) {
375 /* main pll cp source on */
4efb0ca5 376 tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1);
59067f7e
MK		 377 msleep(1);
378
379 /* main pll cp source off */
4efb0ca5 380 tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0);
59067f7e
MK		 381 }
382
383 msleep(5); /* pll locking */
384
385 /* launch detector */
386 tda18271_write_regs(fe, R_EP1, 1);
387 msleep(5); /* wanted low measurement */
388
389 regs[R_EP5] = 0x85;
390 regs[R_CPD] = 0xcb;
391 regs[R_CD1] = 0x66;
392 regs[R_CD2] = 0x70;
393
394 tda18271_write_regs(fe, R_EP3, 7);
395 msleep(5); /* pll locking */
396
397 /* launch optimization algorithm */
398 tda18271_write_regs(fe, R_EP2, 1);
399 msleep(30); /* image low optimization completion */
400
401 /* mid-band */
402 regs[R_EP5] = 0x82;
403 regs[R_CPD] = 0xa8;
404 regs[R_CD2] = 0x00;
405 regs[R_MPD] = 0xa9;
406 regs[R_MD1] = 0x73;
407 regs[R_MD2] = 0x1a;
408
409 tda18271_write_regs(fe, R_EP3, 11);
410 msleep(5); /* pll locking */
411
e83ebb64 412 /* launch detector */
59067f7e
MK		 413 tda18271_write_regs(fe, R_EP1, 1);
414 msleep(5); /* wanted mid measurement */
415
416 regs[R_EP5] = 0x86;
417 regs[R_CPD] = 0xa8;
418 regs[R_CD1] = 0x66;
419 regs[R_CD2] = 0xa0;
420
421 tda18271_write_regs(fe, R_EP3, 7);
422 msleep(5); /* pll locking */
423
424 /* launch optimization algorithm */
425 tda18271_write_regs(fe, R_EP2, 1);
426 msleep(30); /* image mid optimization completion */
427
428 /* high-band */
429 regs[R_EP5] = 0x83;
430 regs[R_CPD] = 0x98;
431 regs[R_CD1] = 0x65;
432 regs[R_CD2] = 0x00;
433 regs[R_MPD] = 0x99;
434 regs[R_MD1] = 0x71;
435 regs[R_MD2] = 0xcd;
436
437 tda18271_write_regs(fe, R_EP3, 11);
438 msleep(5); /* pll locking */
439
440 /* launch detector */
441 tda18271_write_regs(fe, R_EP1, 1);
442 msleep(5); /* wanted high measurement */
443
444 regs[R_EP5] = 0x87;
445 regs[R_CD1] = 0x65;
446 regs[R_CD2] = 0x50;
447
448 tda18271_write_regs(fe, R_EP3, 7);
449 msleep(5); /* pll locking */
450
451 /* launch optimization algorithm */
452 tda18271_write_regs(fe, R_EP2, 1);
453 msleep(30); /* image high optimization completion */
454
455 /* return to normal mode */
456 regs[R_EP4] = 0x64;
457 tda18271_write_regs(fe, R_EP4, 1);
458
459 /* synchronize */
460 tda18271_write_regs(fe, R_EP1, 1);
461
462 return 0;
463}
464
465/*---------------------------------------------------------------------*/
466
518d8739
MK		 467/*
468 * Standby modes, EP3 [7:5]
469 *
470 * | SM || SM_LT || SM_XT || mode description
471 * |=====\\=======\\=======\\===================================
472 * | 0 || 0 || 0 || normal mode
473 * |-----||-------||-------||-----------------------------------
474 * | || || || standby mode w/ slave tuner output
475 * | 1 || 0 || 0 || & loop thru & xtal oscillator on
476 * |-----||-------||-------||-----------------------------------
477 * | 1 || 1 || 0 || standby mode w/ xtal oscillator on
478 * |-----||-------||-------||-----------------------------------
479 * | 1 || 1 || 1 || power off
480 *
481 */
482
483int tda18271_set_standby_mode(struct dvb_frontend *fe,
484 int sm, int sm_lt, int sm_xt)
485{
486 struct tda18271_priv *priv = fe->tuner_priv;
487 unsigned char *regs = priv->tda18271_regs;
488
9c41d456
MK		 489 if (tda18271_debug & DBG_ADV)
490 tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
518d8739
MK		 491
492 regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
493 regs[R_EP3] |= sm ? (1 << 7) : 0 |
494 sm_lt ? (1 << 6) : 0 |
495 sm_xt ? (1 << 5) : 0;
496
d35fccaf 497 return tda18271_write_regs(fe, R_EP3, 1);
518d8739
MK		 498}
499
500/*---------------------------------------------------------------------*/
501
59067f7e
MK		 502int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
503{
504 /* sets main post divider & divider bytes, but does not write them */
505 struct tda18271_priv *priv = fe->tuner_priv;
506 unsigned char *regs = priv->tda18271_regs;
507 u8 d, pd;
508 u32 div;
509
510 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
4bd5d107 511 if (tda_fail(ret))
59067f7e
MK		 512 goto fail;
513
514 regs[R_MPD] = (0x77 & pd);
515
516 switch (priv->mode) {
517 case TDA18271_ANALOG:
518 regs[R_MPD] &= ~0x08;
519 break;
520 case TDA18271_DIGITAL:
521 regs[R_MPD] |= 0x08;
522 break;
523 }
524
525 div = ((d * (freq / 1000)) << 7) / 125;
526
527 regs[R_MD1] = 0x7f & (div >> 16);
528 regs[R_MD2] = 0xff & (div >> 8);
529 regs[R_MD3] = 0xff & div;
530fail:
531 return ret;
532}
533
534int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
535{
536 /* sets cal post divider & divider bytes, but does not write them */
537 struct tda18271_priv *priv = fe->tuner_priv;
538 unsigned char *regs = priv->tda18271_regs;
539 u8 d, pd;
540 u32 div;
541
542 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
4bd5d107 543 if (tda_fail(ret))
59067f7e
MK		 544 goto fail;
545
546 regs[R_CPD] = pd;
547
548 div = ((d * (freq / 1000)) << 7) / 125;
549
550 regs[R_CD1] = 0x7f & (div >> 16);
551 regs[R_CD2] = 0xff & (div >> 8);
552 regs[R_CD3] = 0xff & div;
553fail:
554 return ret;
555}
556
557/*---------------------------------------------------------------------*/
558
559int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
560{
561 /* sets bp filter bits, but does not write them */
562 struct tda18271_priv *priv = fe->tuner_priv;
563 unsigned char *regs = priv->tda18271_regs;
564 u8 val;
565
566 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
4bd5d107 567 if (tda_fail(ret))
59067f7e
MK		 568 goto fail;
569
570 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
571 regs[R_EP1] |= (0x07 & val);
572fail:
573 return ret;
574}
575
576int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
577{
578 /* sets K & M bits, but does not write them */
579 struct tda18271_priv *priv = fe->tuner_priv;
580 unsigned char *regs = priv->tda18271_regs;
581 u8 val;
582
583 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
4bd5d107 584 if (tda_fail(ret))
59067f7e
MK		 585 goto fail;
586
587 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
588 regs[R_EB13] |= (0x7c & val);
589fail:
590 return ret;
591}
592
593int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
594{
595 /* sets rf band bits, but does not write them */
596 struct tda18271_priv *priv = fe->tuner_priv;
597 unsigned char *regs = priv->tda18271_regs;
598 u8 val;
599
600 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
4bd5d107 601 if (tda_fail(ret))
59067f7e
MK		 602 goto fail;
603
604 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
605 regs[R_EP2] |= (0xe0 & (val << 5));
606fail:
607 return ret;
608}
609
610int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
611{
612 /* sets gain taper bits, but does not write them */
613 struct tda18271_priv *priv = fe->tuner_priv;
614 unsigned char *regs = priv->tda18271_regs;
615 u8 val;
616
617 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
4bd5d107 618 if (tda_fail(ret))
59067f7e
MK		 619 goto fail;
620
621 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
622 regs[R_EP2] |= (0x1f & val);
623fail:
624 return ret;
625}
626
627int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
628{
629 /* sets IR Meas bits, but does not write them */
630 struct tda18271_priv *priv = fe->tuner_priv;
631 unsigned char *regs = priv->tda18271_regs;
632 u8 val;
633
634 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
4bd5d107 635 if (tda_fail(ret))
59067f7e
MK		 636 goto fail;
637
638 regs[R_EP5] &= ~0x07;
639 regs[R_EP5] |= (0x07 & val);
640fail:
641 return ret;
642}
643
644int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
645{
646 /* sets rf cal byte (RFC_Cprog), but does not write it */
647 struct tda18271_priv *priv = fe->tuner_priv;
648 unsigned char *regs = priv->tda18271_regs;
649 u8 val;
650
fc60d6e2 651 int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
59067f7e
MK		 652
653 regs[R_EB14] = val;
d2c932a1 654
fc60d6e2 655 return ret;
59067f7e
MK		 656}
657
658/*
659 * Overrides for Emacs so that we follow Linus's tabbing style.
660 * ---------------------------------------------------------------------------
661 * Local variables:
662 * c-basic-offset: 8
663 * End:
664 */
kernel source for telekom puls (alcatel/mediatek)