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mISDN: Support DR6 indication in mISDNipac driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / isdn / hardware / mISDN / mISDNipac.c
CommitLineData
cae86d4a
KK		 1/*
2 * isac.c ISAC specific routines
3 *
4 * Author Karsten Keil <keil@isdn4linux.de>
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
a6b7a407 23#include <linux/irqreturn.h>
5a0e3ad6 24#include <linux/slab.h>
cae86d4a
KK		 25#include <linux/module.h>
26#include <linux/mISDNhw.h>
27#include "ipac.h"
28
29
30#define DBUSY_TIMER_VALUE 80
31#define ARCOFI_USE 1
32
33#define ISAC_REV "2.0"
34
35MODULE_AUTHOR("Karsten Keil");
36MODULE_VERSION(ISAC_REV);
37MODULE_LICENSE("GPL v2");
38
39#define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
40#define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
41#define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
42#define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
43#define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
44#define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
45
46static inline void
47ph_command(struct isac_hw *isac, u8 command)
48{
49 pr_debug("%s: ph_command %x\n", isac->name, command);
50 if (isac->type & IPAC_TYPE_ISACX)
51 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
52 else
53 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
54}
55
56static void
57isac_ph_state_change(struct isac_hw *isac)
58{
59 switch (isac->state) {
60 case (ISAC_IND_RS):
61 case (ISAC_IND_EI):
62 ph_command(isac, ISAC_CMD_DUI);
63 }
64 schedule_event(&isac->dch, FLG_PHCHANGE);
65}
66
67static void
68isac_ph_state_bh(struct dchannel *dch)
69{
70 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
71
72 switch (isac->state) {
73 case ISAC_IND_RS:
74 case ISAC_IND_EI:
75 dch->state = 0;
76 l1_event(dch->l1, HW_RESET_IND);
77 break;
78 case ISAC_IND_DID:
79 dch->state = 3;
80 l1_event(dch->l1, HW_DEACT_CNF);
81 break;
82 case ISAC_IND_DR:
54fbda50 83 case ISAC_IND_DR6:
cae86d4a
KK		 84 dch->state = 3;
85 l1_event(dch->l1, HW_DEACT_IND);
86 break;
87 case ISAC_IND_PU:
88 dch->state = 4;
89 l1_event(dch->l1, HW_POWERUP_IND);
90 break;
91 case ISAC_IND_RSY:
92 if (dch->state <= 5) {
93 dch->state = 5;
94 l1_event(dch->l1, ANYSIGNAL);
95 } else {
96 dch->state = 8;
97 l1_event(dch->l1, LOSTFRAMING);
98 }
99 break;
100 case ISAC_IND_ARD:
101 dch->state = 6;
102 l1_event(dch->l1, INFO2);
103 break;
104 case ISAC_IND_AI8:
105 dch->state = 7;
106 l1_event(dch->l1, INFO4_P8);
107 break;
108 case ISAC_IND_AI10:
109 dch->state = 7;
110 l1_event(dch->l1, INFO4_P10);
111 break;
112 }
113 pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
114}
115
116void
117isac_empty_fifo(struct isac_hw *isac, int count)
118{
119 u8 *ptr;
120
121 pr_debug("%s: %s %d\n", isac->name, __func__, count);
122
123 if (!isac->dch.rx_skb) {
124 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
125 if (!isac->dch.rx_skb) {
126 pr_info("%s: D receive out of memory\n", isac->name);
127 WriteISAC(isac, ISAC_CMDR, 0x80);
128 return;
129 }
130 }
131 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
132 pr_debug("%s: %s overrun %d\n", isac->name, __func__,
475be4d8 133 isac->dch.rx_skb->len + count);
cae86d4a
KK		 134 WriteISAC(isac, ISAC_CMDR, 0x80);
135 return;
136 }
137 ptr = skb_put(isac->dch.rx_skb, count);
138 isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
139 WriteISAC(isac, ISAC_CMDR, 0x80);
140 if (isac->dch.debug & DEBUG_HW_DFIFO) {
141 char pfx[MISDN_MAX_IDLEN + 16];
142
143 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
475be4d8 144 isac->name, count);
cae86d4a
KK		 145 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
146 }
147}
148
149static void
150isac_fill_fifo(struct isac_hw *isac)
151{
152 int count, more;
153 u8 *ptr;
154
155 if (!isac->dch.tx_skb)
156 return;
157 count = isac->dch.tx_skb->len - isac->dch.tx_idx;
158 if (count <= 0)
159 return;
160
161 more = 0;
162 if (count > 32) {
163 more = !0;
164 count = 32;
165 }
166 pr_debug("%s: %s %d\n", isac->name, __func__, count);
167 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
168 isac->dch.tx_idx += count;
169 isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
170 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
171 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
172 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
173 del_timer(&isac->dch.timer);
174 }
175 init_timer(&isac->dch.timer);
176 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
177 add_timer(&isac->dch.timer);
178 if (isac->dch.debug & DEBUG_HW_DFIFO) {
179 char pfx[MISDN_MAX_IDLEN + 16];
180
181 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
475be4d8 182 isac->name, count);
cae86d4a
KK		 183 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
184 }
185}
186
187static void
188isac_rme_irq(struct isac_hw *isac)
189{
190 u8 val, count;
191
192 val = ReadISAC(isac, ISAC_RSTA);
193 if ((val & 0x70) != 0x20) {
194 if (val & 0x40) {
195 pr_debug("%s: ISAC RDO\n", isac->name);
196#ifdef ERROR_STATISTIC
197 isac->dch.err_rx++;
198#endif
199 }
200 if (!(val & 0x20)) {
201 pr_debug("%s: ISAC CRC error\n", isac->name);
202#ifdef ERROR_STATISTIC
203 isac->dch.err_crc++;
204#endif
205 }
206 WriteISAC(isac, ISAC_CMDR, 0x80);
207 if (isac->dch.rx_skb)
208 dev_kfree_skb(isac->dch.rx_skb);
209 isac->dch.rx_skb = NULL;
210 } else {
211 count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
212 if (count == 0)
213 count = 32;
214 isac_empty_fifo(isac, count);
215 recv_Dchannel(&isac->dch);
216 }
217}
218
219static void
220isac_xpr_irq(struct isac_hw *isac)
221{
222 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
223 del_timer(&isac->dch.timer);
224 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
225 isac_fill_fifo(isac);
226 } else {
227 if (isac->dch.tx_skb)
228 dev_kfree_skb(isac->dch.tx_skb);
229 if (get_next_dframe(&isac->dch))
230 isac_fill_fifo(isac);
231 }
232}
233
234static void
235isac_retransmit(struct isac_hw *isac)
236{
237 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
238 del_timer(&isac->dch.timer);
239 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
240 /* Restart frame */
241 isac->dch.tx_idx = 0;
242 isac_fill_fifo(isac);
243 } else if (isac->dch.tx_skb) { /* should not happen */
244 pr_info("%s: tx_skb exist but not busy\n", isac->name);
245 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
246 isac->dch.tx_idx = 0;
247 isac_fill_fifo(isac);
248 } else {
249 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
250 if (get_next_dframe(&isac->dch))
251 isac_fill_fifo(isac);
252 }
253}
254
255static void
256isac_mos_irq(struct isac_hw *isac)
257{
258 u8 val;
259 int ret;
260
261 val = ReadISAC(isac, ISAC_MOSR);
262 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
263#if ARCOFI_USE
264 if (val & 0x08) {
265 if (!isac->mon_rx) {
266 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
267 if (!isac->mon_rx) {
268 pr_info("%s: ISAC MON RX out of memory!\n",
269 isac->name);
270 isac->mocr &= 0xf0;
271 isac->mocr |= 0x0a;
272 WriteISAC(isac, ISAC_MOCR, isac->mocr);
273 goto afterMONR0;
274 } else
275 isac->mon_rxp = 0;
276 }
277 if (isac->mon_rxp >= MAX_MON_FRAME) {
278 isac->mocr &= 0xf0;
279 isac->mocr |= 0x0a;
280 WriteISAC(isac, ISAC_MOCR, isac->mocr);
281 isac->mon_rxp = 0;
282 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
283 goto afterMONR0;
284 }
285 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
286 pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
475be4d8 287 isac->mon_rx[isac->mon_rxp - 1]);
cae86d4a
KK		 288 if (isac->mon_rxp == 1) {
289 isac->mocr |= 0x04;
290 WriteISAC(isac, ISAC_MOCR, isac->mocr);
291 }
292 }
293afterMONR0:
294 if (val & 0x80) {
295 if (!isac->mon_rx) {
296 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
297 if (!isac->mon_rx) {
298 pr_info("%s: ISAC MON RX out of memory!\n",
299 isac->name);
300 isac->mocr &= 0x0f;
301 isac->mocr |= 0xa0;
302 WriteISAC(isac, ISAC_MOCR, isac->mocr);
303 goto afterMONR1;
304 } else
305 isac->mon_rxp = 0;
306 }
307 if (isac->mon_rxp >= MAX_MON_FRAME) {
308 isac->mocr &= 0x0f;
309 isac->mocr |= 0xa0;
310 WriteISAC(isac, ISAC_MOCR, isac->mocr);
311 isac->mon_rxp = 0;
312 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
313 goto afterMONR1;
314 }
315 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
316 pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
475be4d8 317 isac->mon_rx[isac->mon_rxp - 1]);
cae86d4a
KK		 318 isac->mocr |= 0x40;
319 WriteISAC(isac, ISAC_MOCR, isac->mocr);
320 }
321afterMONR1:
322 if (val & 0x04) {
323 isac->mocr &= 0xf0;
324 WriteISAC(isac, ISAC_MOCR, isac->mocr);
325 isac->mocr |= 0x0a;
326 WriteISAC(isac, ISAC_MOCR, isac->mocr);
327 if (isac->monitor) {
328 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
475be4d8 329 isac->mon_rx, isac->mon_rxp);
cae86d4a
KK		 330 if (ret)
331 kfree(isac->mon_rx);
332 } else {
333 pr_info("%s: MONITOR 0 received %d but no user\n",
334 isac->name, isac->mon_rxp);
335 kfree(isac->mon_rx);
336 }
337 isac->mon_rx = NULL;
338 isac->mon_rxp = 0;
339 }
340 if (val & 0x40) {
341 isac->mocr &= 0x0f;
342 WriteISAC(isac, ISAC_MOCR, isac->mocr);
343 isac->mocr |= 0xa0;
344 WriteISAC(isac, ISAC_MOCR, isac->mocr);
345 if (isac->monitor) {
346 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
475be4d8 347 isac->mon_rx, isac->mon_rxp);
cae86d4a
KK		 348 if (ret)
349 kfree(isac->mon_rx);
350 } else {
351 pr_info("%s: MONITOR 1 received %d but no user\n",
352 isac->name, isac->mon_rxp);
353 kfree(isac->mon_rx);
354 }
355 isac->mon_rx = NULL;
356 isac->mon_rxp = 0;
357 }
358 if (val & 0x02) {
359 if ((!isac->mon_tx) || (isac->mon_txc &&
475be4d8 360 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
cae86d4a
KK		 361 isac->mocr &= 0xf0;
362 WriteISAC(isac, ISAC_MOCR, isac->mocr);
363 isac->mocr |= 0x0a;
364 WriteISAC(isac, ISAC_MOCR, isac->mocr);
365 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
366 if (isac->monitor)
367 ret = isac->monitor(isac->dch.hw,
475be4d8 368 MONITOR_TX_0, NULL, 0);
cae86d4a
KK		 369 }
370 kfree(isac->mon_tx);
371 isac->mon_tx = NULL;
372 isac->mon_txc = 0;
373 isac->mon_txp = 0;
374 goto AfterMOX0;
375 }
376 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
377 if (isac->monitor)
378 ret = isac->monitor(isac->dch.hw,
475be4d8 379 MONITOR_TX_0, NULL, 0);
cae86d4a
KK		 380 kfree(isac->mon_tx);
381 isac->mon_tx = NULL;
382 isac->mon_txc = 0;
383 isac->mon_txp = 0;
384 goto AfterMOX0;
385 }
386 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
387 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
475be4d8 388 isac->mon_tx[isac->mon_txp - 1]);
cae86d4a
KK		 389 }
390AfterMOX0:
391 if (val & 0x20) {
392 if ((!isac->mon_tx) || (isac->mon_txc &&
475be4d8 393 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
cae86d4a
KK		 394 isac->mocr &= 0x0f;
395 WriteISAC(isac, ISAC_MOCR, isac->mocr);
396 isac->mocr |= 0xa0;
397 WriteISAC(isac, ISAC_MOCR, isac->mocr);
398 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
399 if (isac->monitor)
400 ret = isac->monitor(isac->dch.hw,
475be4d8 401 MONITOR_TX_1, NULL, 0);
cae86d4a
KK		 402 }
403 kfree(isac->mon_tx);
404 isac->mon_tx = NULL;
405 isac->mon_txc = 0;
406 isac->mon_txp = 0;
407 goto AfterMOX1;
408 }
409 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
410 if (isac->monitor)
411 ret = isac->monitor(isac->dch.hw,
475be4d8 412 MONITOR_TX_1, NULL, 0);
cae86d4a
KK		 413 kfree(isac->mon_tx);
414 isac->mon_tx = NULL;
415 isac->mon_txc = 0;
416 isac->mon_txp = 0;
417 goto AfterMOX1;
418 }
419 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
420 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
475be4d8 421 isac->mon_tx[isac->mon_txp - 1]);
cae86d4a
KK		 422 }
423AfterMOX1:
424 val = 0; /* dummy to avoid warning */
425#endif
426}
427
428static void
429isac_cisq_irq(struct isac_hw *isac) {
430 u8 val;
431
432 val = ReadISAC(isac, ISAC_CIR0);
433 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
434 if (val & 2) {
435 pr_debug("%s: ph_state change %x->%x\n", isac->name,
475be4d8 436 isac->state, (val >> 2) & 0xf);
cae86d4a
KK		 437 isac->state = (val >> 2) & 0xf;
438 isac_ph_state_change(isac);
439 }
440 if (val & 1) {
441 val = ReadISAC(isac, ISAC_CIR1);
442 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
443 }
444}
445
446static void
447isacsx_cic_irq(struct isac_hw *isac)
448{
449 u8 val;
450
451 val = ReadISAC(isac, ISACX_CIR0);
452 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
453 if (val & ISACX_CIR0_CIC0) {
454 pr_debug("%s: ph_state change %x->%x\n", isac->name,
475be4d8 455 isac->state, val >> 4);
cae86d4a
KK		 456 isac->state = val >> 4;
457 isac_ph_state_change(isac);
458 }
459}
460
461static void
462isacsx_rme_irq(struct isac_hw *isac)
463{
464 int count;
465 u8 val;
466
467 val = ReadISAC(isac, ISACX_RSTAD);
468 if ((val & (ISACX_RSTAD_VFR |
469 ISACX_RSTAD_RDO |
470 ISACX_RSTAD_CRC |
471 ISACX_RSTAD_RAB))
472 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
473 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
474#ifdef ERROR_STATISTIC
475 if (val & ISACX_RSTAD_CRC)
476 isac->dch.err_rx++;
477 else
478 isac->dch.err_crc++;
479#endif
480 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
481 if (isac->dch.rx_skb)
482 dev_kfree_skb(isac->dch.rx_skb);
483 isac->dch.rx_skb = NULL;
484 } else {
485 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
486 if (count == 0)
487 count = 32;
488 isac_empty_fifo(isac, count);
489 if (isac->dch.rx_skb) {
490 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
491 pr_debug("%s: dchannel received %d\n", isac->name,
475be4d8 492 isac->dch.rx_skb->len);
cae86d4a
KK		 493 recv_Dchannel(&isac->dch);
494 }
495 }
496}
497
498irqreturn_t
499mISDNisac_irq(struct isac_hw *isac, u8 val)
500{
501 if (unlikely(!val))
502 return IRQ_NONE;
503 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
504 if (isac->type & IPAC_TYPE_ISACX) {
505 if (val & ISACX__CIC)
506 isacsx_cic_irq(isac);
507 if (val & ISACX__ICD) {
508 val = ReadISAC(isac, ISACX_ISTAD);
509 pr_debug("%s: ISTAD %02x\n", isac->name, val);
510 if (val & ISACX_D_XDU) {
511 pr_debug("%s: ISAC XDU\n", isac->name);
512#ifdef ERROR_STATISTIC
513 isac->dch.err_tx++;
514#endif
515 isac_retransmit(isac);
516 }
517 if (val & ISACX_D_XMR) {
518 pr_debug("%s: ISAC XMR\n", isac->name);
519#ifdef ERROR_STATISTIC
520 isac->dch.err_tx++;
521#endif
522 isac_retransmit(isac);
523 }
524 if (val & ISACX_D_XPR)
525 isac_xpr_irq(isac);
526 if (val & ISACX_D_RFO) {
527 pr_debug("%s: ISAC RFO\n", isac->name);
528 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
529 }
530 if (val & ISACX_D_RME)
531 isacsx_rme_irq(isac);
532 if (val & ISACX_D_RPF)
533 isac_empty_fifo(isac, 0x20);
534 }
535 } else {
536 if (val & 0x80) /* RME */
537 isac_rme_irq(isac);
538 if (val & 0x40) /* RPF */
539 isac_empty_fifo(isac, 32);
540 if (val & 0x10) /* XPR */
541 isac_xpr_irq(isac);
542 if (val & 0x04) /* CISQ */
543 isac_cisq_irq(isac);
544 if (val & 0x20) /* RSC - never */
545 pr_debug("%s: ISAC RSC interrupt\n", isac->name);
546 if (val & 0x02) /* SIN - never */
547 pr_debug("%s: ISAC SIN interrupt\n", isac->name);
548 if (val & 0x01) { /* EXI */
549 val = ReadISAC(isac, ISAC_EXIR);
550 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
551 if (val & 0x80) /* XMR */
552 pr_debug("%s: ISAC XMR\n", isac->name);
553 if (val & 0x40) { /* XDU */
554 pr_debug("%s: ISAC XDU\n", isac->name);
555#ifdef ERROR_STATISTIC
556 isac->dch.err_tx++;
557#endif
558 isac_retransmit(isac);
559 }
560 if (val & 0x04) /* MOS */
561 isac_mos_irq(isac);
562 }
563 }
564 return IRQ_HANDLED;
565}
566EXPORT_SYMBOL(mISDNisac_irq);
567
568static int
569isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
570{
571 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
572 struct dchannel *dch = container_of(dev, struct dchannel, dev);
573 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
574 int ret = -EINVAL;
575 struct mISDNhead *hh = mISDN_HEAD_P(skb);
576 u32 id;
577 u_long flags;
578
579 switch (hh->prim) {
580 case PH_DATA_REQ:
581 spin_lock_irqsave(isac->hwlock, flags);
582 ret = dchannel_senddata(dch, skb);
583 if (ret > 0) { /* direct TX */
584 id = hh->id; /* skb can be freed */
585 isac_fill_fifo(isac);
586 ret = 0;
587 spin_unlock_irqrestore(isac->hwlock, flags);
588 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
589 } else
590 spin_unlock_irqrestore(isac->hwlock, flags);
591 return ret;
592 case PH_ACTIVATE_REQ:
593 ret = l1_event(dch->l1, hh->prim);
594 break;
595 case PH_DEACTIVATE_REQ:
596 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
597 ret = l1_event(dch->l1, hh->prim);
598 break;
599 }
600
601 if (!ret)
602 dev_kfree_skb(skb);
603 return ret;
604}
605
606static int
c626c127 607isac_ctrl(struct isac_hw *isac, u32 cmd, unsigned long para)
cae86d4a
KK		 608{
609 u8 tl = 0;
c626c127
KK		 610 unsigned long flags;
611 int ret = 0;
cae86d4a
KK		 612
613 switch (cmd) {
614 case HW_TESTLOOP:
615 spin_lock_irqsave(isac->hwlock, flags);
616 if (!(isac->type & IPAC_TYPE_ISACX)) {
617 /* TODO: implement for IPAC_TYPE_ISACX */
618 if (para & 1) /* B1 */
619 tl |= 0x0c;
620 else if (para & 2) /* B2 */
621 tl |= 0x3;
622 /* we only support IOM2 mode */
623 WriteISAC(isac, ISAC_SPCR, tl);
624 if (tl)
625 WriteISAC(isac, ISAC_ADF1, 0x8);
626 else
627 WriteISAC(isac, ISAC_ADF1, 0x0);
628 }
629 spin_unlock_irqrestore(isac->hwlock, flags);
630 break;
c626c127
KK		 631 case HW_TIMER3_VALUE:
632 ret = l1_event(isac->dch.l1, HW_TIMER3_VALUE | (para & 0xff));
633 break;
cae86d4a
KK		 634 default:
635 pr_debug("%s: %s unknown command %x %lx\n", isac->name,
475be4d8 636 __func__, cmd, para);
c626c127 637 ret = -1;
cae86d4a 638 }
c626c127 639 return ret;
cae86d4a
KK		 640}
641
642static int
643isac_l1cmd(struct dchannel *dch, u32 cmd)
644{
645 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
646 u_long flags;
647
648 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
649 switch (cmd) {
650 case INFO3_P8:
651 spin_lock_irqsave(isac->hwlock, flags);
652 ph_command(isac, ISAC_CMD_AR8);
653 spin_unlock_irqrestore(isac->hwlock, flags);
654 break;
655 case INFO3_P10:
656 spin_lock_irqsave(isac->hwlock, flags);
657 ph_command(isac, ISAC_CMD_AR10);
658 spin_unlock_irqrestore(isac->hwlock, flags);
659 break;
660 case HW_RESET_REQ:
661 spin_lock_irqsave(isac->hwlock, flags);
662 if ((isac->state == ISAC_IND_EI) ||
663 (isac->state == ISAC_IND_DR) ||
54fbda50 664 (isac->state == ISAC_IND_DR6) ||
cae86d4a
KK		 665 (isac->state == ISAC_IND_RS))
666 ph_command(isac, ISAC_CMD_TIM);
667 else
668 ph_command(isac, ISAC_CMD_RS);
669 spin_unlock_irqrestore(isac->hwlock, flags);
670 break;
671 case HW_DEACT_REQ:
672 skb_queue_purge(&dch->squeue);
673 if (dch->tx_skb) {
674 dev_kfree_skb(dch->tx_skb);
675 dch->tx_skb = NULL;
676 }
677 dch->tx_idx = 0;
678 if (dch->rx_skb) {
679 dev_kfree_skb(dch->rx_skb);
680 dch->rx_skb = NULL;
681 }
682 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
683 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
684 del_timer(&dch->timer);
685 break;
686 case HW_POWERUP_REQ:
687 spin_lock_irqsave(isac->hwlock, flags);
688 ph_command(isac, ISAC_CMD_TIM);
689 spin_unlock_irqrestore(isac->hwlock, flags);
690 break;
691 case PH_ACTIVATE_IND:
692 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
693 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
475be4d8 694 GFP_ATOMIC);
cae86d4a
KK		 695 break;
696 case PH_DEACTIVATE_IND:
697 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
698 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
475be4d8 699 GFP_ATOMIC);
cae86d4a
KK		 700 break;
701 default:
702 pr_debug("%s: %s unknown command %x\n", isac->name,
475be4d8 703 __func__, cmd);
cae86d4a
KK		 704 return -1;
705 }
706 return 0;
707}
708
709static void
710isac_release(struct isac_hw *isac)
711{
712 if (isac->type & IPAC_TYPE_ISACX)
713 WriteISAC(isac, ISACX_MASK, 0xff);
714 else
715 WriteISAC(isac, ISAC_MASK, 0xff);
716 if (isac->dch.timer.function != NULL) {
717 del_timer(&isac->dch.timer);
718 isac->dch.timer.function = NULL;
719 }
720 kfree(isac->mon_rx);
721 isac->mon_rx = NULL;
722 kfree(isac->mon_tx);
723 isac->mon_tx = NULL;
724 if (isac->dch.l1)
725 l1_event(isac->dch.l1, CLOSE_CHANNEL);
726 mISDN_freedchannel(&isac->dch);
727}
728
729static void
730dbusy_timer_handler(struct isac_hw *isac)
731{
732 int rbch, star;
733 u_long flags;
734
735 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
736 spin_lock_irqsave(isac->hwlock, flags);
737 rbch = ReadISAC(isac, ISAC_RBCH);
738 star = ReadISAC(isac, ISAC_STAR);
739 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
475be4d8 740 isac->name, rbch, star);
cae86d4a
KK		 741 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
742 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
743 else {
744 /* discard frame; reset transceiver */
745 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
746 if (isac->dch.tx_idx)
747 isac->dch.tx_idx = 0;
748 else
749 pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
750 isac->name);
751 /* Transmitter reset */
752 WriteISAC(isac, ISAC_CMDR, 0x01);
753 }
754 spin_unlock_irqrestore(isac->hwlock, flags);
755 }
756}
757
758static int
759open_dchannel(struct isac_hw *isac, struct channel_req *rq)
760{
761 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
475be4d8 762 isac->dch.dev.id, __builtin_return_address(1));
cae86d4a
KK		 763 if (rq->protocol != ISDN_P_TE_S0)
764 return -EINVAL;
765 if (rq->adr.channel == 1)
766 /* E-Channel not supported */
767 return -EINVAL;
768 rq->ch = &isac->dch.dev.D;
769 rq->ch->protocol = rq->protocol;
770 if (isac->dch.state == 7)
771 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
475be4d8 772 0, NULL, GFP_KERNEL);
cae86d4a
KK		 773 return 0;
774}
775
776static const char *ISACVer[] =
777{"2086/2186 V1.1", "2085 B1", "2085 B2",
778 "2085 V2.3"};
779
780static int
781isac_init(struct isac_hw *isac)
782{
783 u8 val;
784 int err = 0;
785
786 if (!isac->dch.l1) {
787 err = create_l1(&isac->dch, isac_l1cmd);
788 if (err)
789 return err;
790 }
791 isac->mon_tx = NULL;
792 isac->mon_rx = NULL;
793 isac->dch.timer.function = (void *) dbusy_timer_handler;
794 isac->dch.timer.data = (long)isac;
795 init_timer(&isac->dch.timer);
796 isac->mocr = 0xaa;
797 if (isac->type & IPAC_TYPE_ISACX) {
798 /* Disable all IRQ */
799 WriteISAC(isac, ISACX_MASK, 0xff);
800 val = ReadISAC(isac, ISACX_STARD);
801 pr_debug("%s: ISACX STARD %x\n", isac->name, val);
802 val = ReadISAC(isac, ISACX_ISTAD);
803 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
804 val = ReadISAC(isac, ISACX_ISTA);
805 pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
806 /* clear LDD */
807 WriteISAC(isac, ISACX_TR_CONF0, 0x00);
808 /* enable transmitter */
809 WriteISAC(isac, ISACX_TR_CONF2, 0x00);
810 /* transparent mode 0, RAC, stop/go */
811 WriteISAC(isac, ISACX_MODED, 0xc9);
812 /* all HDLC IRQ unmasked */
813 val = ReadISAC(isac, ISACX_ID);
814 if (isac->dch.debug & DEBUG_HW)
815 pr_notice("%s: ISACX Design ID %x\n",
475be4d8 816 isac->name, val & 0x3f);
cae86d4a
KK		 817 val = ReadISAC(isac, ISACX_CIR0);
818 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
819 isac->state = val >> 4;
820 isac_ph_state_change(isac);
821 ph_command(isac, ISAC_CMD_RS);
822 WriteISAC(isac, ISACX_MASK, IPACX__ON);
823 WriteISAC(isac, ISACX_MASKD, 0x00);
824 } else { /* old isac */
825 WriteISAC(isac, ISAC_MASK, 0xff);
826 val = ReadISAC(isac, ISAC_STAR);
827 pr_debug("%s: ISAC STAR %x\n", isac->name, val);
828 val = ReadISAC(isac, ISAC_MODE);
829 pr_debug("%s: ISAC MODE %x\n", isac->name, val);
830 val = ReadISAC(isac, ISAC_ADF2);
831 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
832 val = ReadISAC(isac, ISAC_ISTA);
833 pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
834 if (val & 0x01) {
835 val = ReadISAC(isac, ISAC_EXIR);
836 pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
837 }
838 val = ReadISAC(isac, ISAC_RBCH);
839 if (isac->dch.debug & DEBUG_HW)
840 pr_notice("%s: ISAC version (%x): %s\n", isac->name,
475be4d8 841 val, ISACVer[(val >> 5) & 3]);
cae86d4a
KK		 842 isac->type |= ((val >> 5) & 3);
843 if (!isac->adf2)
844 isac->adf2 = 0x80;
845 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
846 pr_info("%s: only support IOM2 mode but adf2=%02x\n",
847 isac->name, isac->adf2);
848 isac_release(isac);
849 return -EINVAL;
850 }
851 WriteISAC(isac, ISAC_ADF2, isac->adf2);
852 WriteISAC(isac, ISAC_SQXR, 0x2f);
853 WriteISAC(isac, ISAC_SPCR, 0x00);
854 WriteISAC(isac, ISAC_STCR, 0x70);
855 WriteISAC(isac, ISAC_MODE, 0xc9);
856 WriteISAC(isac, ISAC_TIMR, 0x00);
857 WriteISAC(isac, ISAC_ADF1, 0x00);
858 val = ReadISAC(isac, ISAC_CIR0);
859 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
860 isac->state = (val >> 2) & 0xf;
861 isac_ph_state_change(isac);
862 ph_command(isac, ISAC_CMD_RS);
863 WriteISAC(isac, ISAC_MASK, 0);
864 }
865 return err;
866}
867
868int
869mISDNisac_init(struct isac_hw *isac, void *hw)
870{
871 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
872 isac->dch.hw = hw;
873 isac->dch.dev.D.send = isac_l1hw;
874 isac->init = isac_init;
875 isac->release = isac_release;
876 isac->ctrl = isac_ctrl;
877 isac->open = open_dchannel;
878 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
879 isac->dch.dev.nrbchan = 2;
880 return 0;
881}
882EXPORT_SYMBOL(mISDNisac_init);
883
884static void
885waitforCEC(struct hscx_hw *hx)
886{
887 u8 starb, to = 50;
888
889 while (to) {
890 starb = ReadHSCX(hx, IPAC_STARB);
891 if (!(starb & 0x04))
892 break;
893 udelay(1);
894 to--;
895 }
896 if (to < 50)
897 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
475be4d8 898 50 - to);
cae86d4a
KK		 899 if (!to)
900 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
901}
902
903
904static void
905waitforXFW(struct hscx_hw *hx)
906{
907 u8 starb, to = 50;
908
909 while (to) {
910 starb = ReadHSCX(hx, IPAC_STARB);
911 if ((starb & 0x44) == 0x40)
912 break;
913 udelay(1);
914 to--;
915 }
916 if (to < 50)
917 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
475be4d8 918 50 - to);
cae86d4a
KK		 919 if (!to)
920 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
921}
922
923static void
924hscx_cmdr(struct hscx_hw *hx, u8 cmd)
925{
926 if (hx->ip->type & IPAC_TYPE_IPACX)
927 WriteHSCX(hx, IPACX_CMDRB, cmd);
928 else {
929 waitforCEC(hx);
930 WriteHSCX(hx, IPAC_CMDRB, cmd);
931 }
932}
933
934static void
935hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
936{
937 u8 *p;
7206e659 938 int maxlen;
cae86d4a
KK		 939
940 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
c27b46e7
KK		 941 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) {
942 hscx->bch.dropcnt += count;
943 hscx_cmdr(hscx, 0x80); /* RMC */
944 return;
945 }
7206e659
KK		 946 maxlen = bchannel_get_rxbuf(&hscx->bch, count);
947 if (maxlen < 0) {
cae86d4a 948 hscx_cmdr(hscx, 0x80); /* RMC */
7206e659
KK		 949 if (hscx->bch.rx_skb)
950 skb_trim(hscx->bch.rx_skb, 0);
951 pr_warning("%s.B%d: No bufferspace for %d bytes\n",
952 hscx->ip->name, hscx->bch.nr, count);
cae86d4a
KK		 953 return;
954 }
955 p = skb_put(hscx->bch.rx_skb, count);
956
957 if (hscx->ip->type & IPAC_TYPE_IPACX)
958 hscx->ip->read_fifo(hscx->ip->hw,
475be4d8 959 hscx->off + IPACX_RFIFOB, p, count);
cae86d4a
KK		 960 else
961 hscx->ip->read_fifo(hscx->ip->hw,
475be4d8 962 hscx->off, p, count);
cae86d4a
KK		 963
964 hscx_cmdr(hscx, 0x80); /* RMC */
965
966 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
967 snprintf(hscx->log, 64, "B%1d-recv %s %d ",
475be4d8 968 hscx->bch.nr, hscx->ip->name, count);
cae86d4a
KK		 969 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
970 }
971}
972
973static void
974hscx_fill_fifo(struct hscx_hw *hscx)
975{
976 int count, more;
977 u8 *p;
978
6d1ee48f
KK		 979 if (!hscx->bch.tx_skb) {
980 if (!test_bit(FLG_TX_EMPTY, &hscx->bch.Flags))
981 return;
cae86d4a
KK		 982 count = hscx->fifo_size;
983 more = 1;
6d1ee48f
KK		 984 p = hscx->log;
985 memset(p, hscx->bch.fill[0], count);
986 } else {
987 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
988 if (count <= 0)
989 return;
990 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
cae86d4a 991
6d1ee48f
KK		 992 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
993 if (count > hscx->fifo_size) {
994 count = hscx->fifo_size;
995 more = 1;
996 }
997 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr,
998 count, hscx->bch.tx_idx, hscx->bch.tx_skb->len);
999 hscx->bch.tx_idx += count;
1000 }
cae86d4a
KK		 1001 if (hscx->ip->type & IPAC_TYPE_IPACX)
1002 hscx->ip->write_fifo(hscx->ip->hw,
475be4d8 1003 hscx->off + IPACX_XFIFOB, p, count);
cae86d4a
KK		 1004 else {
1005 waitforXFW(hscx);
1006 hscx->ip->write_fifo(hscx->ip->hw,
475be4d8 1007 hscx->off, p, count);
cae86d4a
KK		 1008 }
1009 hscx_cmdr(hscx, more ? 0x08 : 0x0a);
1010
6d1ee48f 1011 if (hscx->bch.tx_skb && (hscx->bch.debug & DEBUG_HW_BFIFO)) {
cae86d4a 1012 snprintf(hscx->log, 64, "B%1d-send %s %d ",
475be4d8 1013 hscx->bch.nr, hscx->ip->name, count);
cae86d4a
KK		 1014 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
1015 }
1016}
1017
1018static void
1019hscx_xpr(struct hscx_hw *hx)
1020{
8bfddfbe 1021 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len) {
cae86d4a 1022 hscx_fill_fifo(hx);
8bfddfbe
KK		 1023 } else {
1024 if (hx->bch.tx_skb)
cae86d4a 1025 dev_kfree_skb(hx->bch.tx_skb);
6d1ee48f 1026 if (get_next_bframe(&hx->bch)) {
cae86d4a 1027 hscx_fill_fifo(hx);
6d1ee48f
KK		 1028 test_and_clear_bit(FLG_TX_EMPTY, &hx->bch.Flags);
1029 } else if (test_bit(FLG_TX_EMPTY, &hx->bch.Flags)) {
1030 hscx_fill_fifo(hx);
1031 }
cae86d4a
KK		 1032 }
1033}
1034
1035static void
1036ipac_rme(struct hscx_hw *hx)
1037{
1038 int count;
1039 u8 rstab;
1040
1041 if (hx->ip->type & IPAC_TYPE_IPACX)
1042 rstab = ReadHSCX(hx, IPACX_RSTAB);
1043 else
1044 rstab = ReadHSCX(hx, IPAC_RSTAB);
1045 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
1046 if ((rstab & 0xf0) != 0xa0) {
1047 /* !(VFR && !RDO && CRC && !RAB) */
1048 if (!(rstab & 0x80)) {
1049 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1050 pr_notice("%s: B%1d invalid frame\n",
475be4d8 1051 hx->ip->name, hx->bch.nr);
cae86d4a
KK		 1052 }
1053 if (rstab & 0x40) {
1054 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1055 pr_notice("%s: B%1d RDO proto=%x\n",
475be4d8
JP		 1056 hx->ip->name, hx->bch.nr,
1057 hx->bch.state);
cae86d4a
KK		 1058 }
1059 if (!(rstab & 0x20)) {
1060 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1061 pr_notice("%s: B%1d CRC error\n",
475be4d8 1062 hx->ip->name, hx->bch.nr);
cae86d4a
KK		 1063 }
1064 hscx_cmdr(hx, 0x80); /* Do RMC */
1065 return;
1066 }
1067 if (hx->ip->type & IPAC_TYPE_IPACX)
1068 count = ReadHSCX(hx, IPACX_RBCLB);
1069 else
1070 count = ReadHSCX(hx, IPAC_RBCLB);
1071 count &= (hx->fifo_size - 1);
1072 if (count == 0)
1073 count = hx->fifo_size;
1074 hscx_empty_fifo(hx, count);
1075 if (!hx->bch.rx_skb)
1076 return;
1077 if (hx->bch.rx_skb->len < 2) {
1078 pr_debug("%s: B%1d frame to short %d\n",
475be4d8 1079 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
cae86d4a
KK		 1080 skb_trim(hx->bch.rx_skb, 0);
1081 } else {
1082 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
034005a0 1083 recv_Bchannel(&hx->bch, 0, false);
cae86d4a
KK		 1084 }
1085}
1086
1087static void
1088ipac_irq(struct hscx_hw *hx, u8 ista)
1089{
1090 u8 istab, m, exirb = 0;
1091
1092 if (hx->ip->type & IPAC_TYPE_IPACX)
1093 istab = ReadHSCX(hx, IPACX_ISTAB);
1094 else if (hx->ip->type & IPAC_TYPE_IPAC) {
1095 istab = ReadHSCX(hx, IPAC_ISTAB);
1096 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
1097 if (m & ista) {
1098 exirb = ReadHSCX(hx, IPAC_EXIRB);
1099 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
475be4d8 1100 hx->bch.nr, exirb);
cae86d4a
KK		 1101 }
1102 } else if (hx->bch.nr & 2) { /* HSCX B */
1103 if (ista & (HSCX__EXA | HSCX__ICA))
1104 ipac_irq(&hx->ip->hscx[0], ista);
1105 if (ista & HSCX__EXB) {
1106 exirb = ReadHSCX(hx, IPAC_EXIRB);
1107 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
475be4d8 1108 hx->bch.nr, exirb);
cae86d4a
KK		 1109 }
1110 istab = ista & 0xF8;
1111 } else { /* HSCX A */
1112 istab = ReadHSCX(hx, IPAC_ISTAB);
1113 if (ista & HSCX__EXA) {
1114 exirb = ReadHSCX(hx, IPAC_EXIRB);
1115 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
475be4d8 1116 hx->bch.nr, exirb);
cae86d4a
KK		 1117 }
1118 istab = istab & 0xF8;
1119 }
1120 if (exirb & IPAC_B_XDU)
1121 istab |= IPACX_B_XDU;
1122 if (exirb & IPAC_B_RFO)
1123 istab |= IPACX_B_RFO;
1124 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
1125
1126 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
1127 return;
1128
1129 if (istab & IPACX_B_RME)
1130 ipac_rme(hx);
1131
1132 if (istab & IPACX_B_RPF) {
1133 hscx_empty_fifo(hx, hx->fifo_size);
034005a0
KK		 1134 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
1135 recv_Bchannel(&hx->bch, 0, false);
cae86d4a
KK		 1136 }
1137
1138 if (istab & IPACX_B_RFO) {
1139 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
1140 hscx_cmdr(hx, 0x40); /* RRES */
1141 }
1142
1143 if (istab & IPACX_B_XPR)
1144 hscx_xpr(hx);
1145
1146 if (istab & IPACX_B_XDU) {
1147 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
6d1ee48f
KK		 1148 if (test_bit(FLG_FILLEMPTY, &hx->bch.Flags))
1149 test_and_set_bit(FLG_TX_EMPTY, &hx->bch.Flags);
1150 hscx_xpr(hx);
cae86d4a
KK		 1151 return;
1152 }
1153 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
475be4d8 1154 hx->bch.nr, hx->bch.tx_idx);
cae86d4a
KK		 1155 hx->bch.tx_idx = 0;
1156 hscx_cmdr(hx, 0x01); /* XRES */
1157 }
1158}
1159
1160irqreturn_t
1161mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
1162{
1163 int cnt = maxloop + 1;
1164 u8 ista, istad;
1165 struct isac_hw *isac = &ipac->isac;
1166
1167 if (ipac->type & IPAC_TYPE_IPACX) {
1168 ista = ReadIPAC(ipac, ISACX_ISTA);
1169 while (ista && cnt--) {
1170 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1171 if (ista & IPACX__ICA)
1172 ipac_irq(&ipac->hscx[0], ista);
1173 if (ista & IPACX__ICB)
1174 ipac_irq(&ipac->hscx[1], ista);
1175 if (ista & (ISACX__ICD | ISACX__CIC))
1176 mISDNisac_irq(&ipac->isac, ista);
1177 ista = ReadIPAC(ipac, ISACX_ISTA);
1178 }
1179 } else if (ipac->type & IPAC_TYPE_IPAC) {
1180 ista = ReadIPAC(ipac, IPAC_ISTA);
1181 while (ista && cnt--) {
1182 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1183 if (ista & (IPAC__ICD | IPAC__EXD)) {
1184 istad = ReadISAC(isac, ISAC_ISTA);
1185 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1186 if (istad & IPAC_D_TIN2)
1187 pr_debug("%s TIN2 irq\n", ipac->name);
1188 if (ista & IPAC__EXD)
1189 istad |= 1; /* ISAC EXI */
1190 mISDNisac_irq(isac, istad);
1191 }
1192 if (ista & (IPAC__ICA | IPAC__EXA))
1193 ipac_irq(&ipac->hscx[0], ista);
1194 if (ista & (IPAC__ICB | IPAC__EXB))
1195 ipac_irq(&ipac->hscx[1], ista);
1196 ista = ReadIPAC(ipac, IPAC_ISTA);
1197 }
1198 } else if (ipac->type & IPAC_TYPE_HSCX) {
1199 while (cnt) {
1200 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
1201 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
1202 if (ista)
1203 ipac_irq(&ipac->hscx[1], ista);
1204 istad = ReadISAC(isac, ISAC_ISTA);
1205 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1206 if (istad)
1207 mISDNisac_irq(isac, istad);
1208 if (0 == (ista | istad))
1209 break;
1210 cnt--;
1211 }
1212 }
1213 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
1214 return IRQ_NONE;
1215 if (cnt < maxloop)
1216 pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
475be4d8 1217 maxloop - cnt, smp_processor_id());
cae86d4a
KK		 1218 if (maxloop && !cnt)
1219 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
475be4d8 1220 maxloop, smp_processor_id());
cae86d4a
KK		 1221 return IRQ_HANDLED;
1222}
1223EXPORT_SYMBOL(mISDNipac_irq);
1224
1225static int
1226hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
1227{
1228 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
475be4d8 1229 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
cae86d4a
KK		 1230 if (hscx->ip->type & IPAC_TYPE_IPACX) {
1231 if (hscx->bch.nr & 1) { /* B1 and ICA */
1232 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
1233 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
1234 } else { /* B2 and ICB */
1235 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
1236 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
1237 }
1238 switch (bprotocol) {
1239 case ISDN_P_NONE: /* init */
1240 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
1241 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
1242 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
1243 hscx_cmdr(hscx, 0x41);
1244 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1245 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1246 break;
1247 case ISDN_P_B_RAW:
1248 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
1249 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
1250 hscx_cmdr(hscx, 0x41);
1251 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1252 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1253 break;
1254 case ISDN_P_B_HDLC:
1255 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
1256 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
1257 hscx_cmdr(hscx, 0x41);
1258 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1259 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1260 break;
1261 default:
1262 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1263 bprotocol);
1264 return -ENOPROTOOPT;
1265 }
1266 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
1267 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1268 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1269 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1270 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1271 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1272 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1273 switch (bprotocol) {
1274 case ISDN_P_NONE:
1275 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1276 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1277 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1278 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1279 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1280 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1281 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1282 break;
1283 case ISDN_P_B_RAW:
1284 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1285 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1286 hscx_cmdr(hscx, 0x41);
1287 WriteHSCX(hscx, IPAC_MASKB, 0);
1288 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1289 break;
1290 case ISDN_P_B_HDLC:
1291 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1292 WriteHSCX(hscx, IPAC_CCR1, 0x8a);
1293 hscx_cmdr(hscx, 0x41);
1294 WriteHSCX(hscx, IPAC_MASKB, 0);
1295 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1296 break;
1297 default:
1298 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1299 bprotocol);
1300 return -ENOPROTOOPT;
1301 }
1302 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
1303 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1304 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1305 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1306 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1307 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1308 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1309 switch (bprotocol) {
1310 case ISDN_P_NONE:
1311 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1312 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1313 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1314 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1315 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1316 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1317 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1318 break;
1319 case ISDN_P_B_RAW:
1320 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1321 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1322 hscx_cmdr(hscx, 0x41);
1323 WriteHSCX(hscx, IPAC_MASKB, 0);
1324 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1325 break;
1326 case ISDN_P_B_HDLC:
1327 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1328 WriteHSCX(hscx, IPAC_CCR1, 0x8d);
1329 hscx_cmdr(hscx, 0x41);
1330 WriteHSCX(hscx, IPAC_MASKB, 0);
1331 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1332 break;
1333 default:
1334 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1335 bprotocol);
1336 return -ENOPROTOOPT;
1337 }
1338 } else
1339 return -EINVAL;
1340 hscx->bch.state = bprotocol;
1341 return 0;
1342}
1343
1344static int
1345hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1346{
1347 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1348 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1349 int ret = -EINVAL;
1350 struct mISDNhead *hh = mISDN_HEAD_P(skb);
8bfddfbe 1351 unsigned long flags;
cae86d4a
KK		 1352
1353 switch (hh->prim) {
1354 case PH_DATA_REQ:
1355 spin_lock_irqsave(hx->ip->hwlock, flags);
1356 ret = bchannel_senddata(bch, skb);
1357 if (ret > 0) { /* direct TX */
cae86d4a
KK		 1358 ret = 0;
1359 hscx_fill_fifo(hx);
8bfddfbe
KK		 1360 }
1361 spin_unlock_irqrestore(hx->ip->hwlock, flags);
cae86d4a
KK		 1362 return ret;
1363 case PH_ACTIVATE_REQ:
1364 spin_lock_irqsave(hx->ip->hwlock, flags);
1365 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1366 ret = hscx_mode(hx, ch->protocol);
1367 else
1368 ret = 0;
1369 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1370 if (!ret)
1371 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 1372 NULL, GFP_KERNEL);
cae86d4a
KK		 1373 break;
1374 case PH_DEACTIVATE_REQ:
1375 spin_lock_irqsave(hx->ip->hwlock, flags);
1376 mISDN_clear_bchannel(bch);
1377 hscx_mode(hx, ISDN_P_NONE);
1378 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1379 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 1380 NULL, GFP_KERNEL);
cae86d4a
KK		 1381 ret = 0;
1382 break;
1383 default:
1384 pr_info("%s: %s unknown prim(%x,%x)\n",
1385 hx->ip->name, __func__, hh->prim, hh->id);
1386 ret = -EINVAL;
1387 }
1388 if (!ret)
1389 dev_kfree_skb(skb);
1390 return ret;
1391}
1392
1393static int
1394channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1395{
034005a0 1396 return mISDN_ctrl_bchannel(bch, cq);
cae86d4a
KK		 1397}
1398
1399static int
1400hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1401{
1402 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1403 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1404 int ret = -EINVAL;
1405 u_long flags;
1406
1407 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
1408 switch (cmd) {
1409 case CLOSE_CHANNEL:
1410 test_and_clear_bit(FLG_OPEN, &bch->Flags);
4b921eda 1411 cancel_work_sync(&bch->workq);
1368112c 1412 spin_lock_irqsave(hx->ip->hwlock, flags);
4b921eda 1413 mISDN_clear_bchannel(bch);
1368112c
KK		 1414 hscx_mode(hx, ISDN_P_NONE);
1415 spin_unlock_irqrestore(hx->ip->hwlock, flags);
cae86d4a
KK		 1416 ch->protocol = ISDN_P_NONE;
1417 ch->peer = NULL;
1418 module_put(hx->ip->owner);
1419 ret = 0;
1420 break;
1421 case CONTROL_CHANNEL:
1422 ret = channel_bctrl(bch, arg);
1423 break;
1424 default:
1425 pr_info("%s: %s unknown prim(%x)\n",
1426 hx->ip->name, __func__, cmd);
1427 }
1428 return ret;
1429}
1430
1431static void
1432free_ipac(struct ipac_hw *ipac)
1433{
1434 isac_release(&ipac->isac);
1435}
1436
1437static const char *HSCXVer[] =
1438{"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
1439 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
1440
1441
1442
1443static void
1444hscx_init(struct hscx_hw *hx)
1445{
1446 u8 val;
1447
1448 WriteHSCX(hx, IPAC_RAH2, 0xFF);
1449 WriteHSCX(hx, IPAC_XBCH, 0x00);
1450 WriteHSCX(hx, IPAC_RLCR, 0x00);
1451
1452 if (hx->ip->type & IPAC_TYPE_HSCX) {
1453 WriteHSCX(hx, IPAC_CCR1, 0x85);
1454 val = ReadHSCX(hx, HSCX_VSTR);
1455 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
1456 if (hx->bch.debug & DEBUG_HW)
1457 pr_notice("%s: HSCX version %s\n", hx->ip->name,
475be4d8 1458 HSCXVer[val & 0x0f]);
cae86d4a
KK		 1459 } else
1460 WriteHSCX(hx, IPAC_CCR1, 0x82);
1461 WriteHSCX(hx, IPAC_CCR2, 0x30);
1462 WriteHSCX(hx, IPAC_XCCR, 0x07);
1463 WriteHSCX(hx, IPAC_RCCR, 0x07);
1464}
1465
1466static int
1467ipac_init(struct ipac_hw *ipac)
1468{
1469 u8 val;
1470
1471 if (ipac->type & IPAC_TYPE_HSCX) {
1472 hscx_init(&ipac->hscx[0]);
1473 hscx_init(&ipac->hscx[1]);
1474 val = ReadIPAC(ipac, IPAC_ID);
1475 } else if (ipac->type & IPAC_TYPE_IPAC) {
1476 hscx_init(&ipac->hscx[0]);
1477 hscx_init(&ipac->hscx[1]);
1478 WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
1479 val = ReadIPAC(ipac, IPAC_CONF);
1480 /* conf is default 0, but can be overwritten by card setup */
1481 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
475be4d8 1482 val, ipac->conf);
cae86d4a
KK		 1483 WriteIPAC(ipac, IPAC_CONF, ipac->conf);
1484 val = ReadIPAC(ipac, IPAC_ID);
1485 if (ipac->hscx[0].bch.debug & DEBUG_HW)
1486 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
1487 }
1488 /* nothing special for IPACX to do here */
1489 return isac_init(&ipac->isac);
1490}
1491
1492static int
1493open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
1494{
1495 struct bchannel *bch;
1496
819a1008 1497 if (rq->adr.channel == 0 || rq->adr.channel > 2)
cae86d4a
KK		 1498 return -EINVAL;
1499 if (rq->protocol == ISDN_P_NONE)
1500 return -EINVAL;
1501 bch = &ipac->hscx[rq->adr.channel - 1].bch;
1502 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1503 return -EBUSY; /* b-channel can be only open once */
1504 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1505 bch->ch.protocol = rq->protocol;
1506 rq->ch = &bch->ch;
1507 return 0;
1508}
1509
1510static int
1511channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
1512{
1513 int ret = 0;
1514
1515 switch (cq->op) {
1516 case MISDN_CTRL_GETOP:
c626c127 1517 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
cae86d4a
KK		 1518 break;
1519 case MISDN_CTRL_LOOP:
1520 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
1521 if (cq->channel < 0 || cq->channel > 3) {
1522 ret = -EINVAL;
1523 break;
1524 }
1525 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
1526 break;
c626c127
KK		 1527 case MISDN_CTRL_L1_TIMER3:
1528 ret = ipac->isac.ctrl(&ipac->isac, HW_TIMER3_VALUE, cq->p1);
1529 break;
cae86d4a
KK		 1530 default:
1531 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
1532 ret = -EINVAL;
1533 break;
1534 }
1535 return ret;
1536}
1537
1538static int
1539ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1540{
1541 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1542 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1543 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
1544 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
1545 struct channel_req *rq;
1546 int err = 0;
1547
1548 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
1549 switch (cmd) {
1550 case OPEN_CHANNEL:
1551 rq = arg;
1552 if (rq->protocol == ISDN_P_TE_S0)
1553 err = open_dchannel(isac, rq);
1554 else
1555 err = open_bchannel(ipac, rq);
1556 if (err)
1557 break;
1558 if (!try_module_get(ipac->owner))
1559 pr_info("%s: cannot get module\n", ipac->name);
1560 break;
1561 case CLOSE_CHANNEL:
1562 pr_debug("%s: dev(%d) close from %p\n", ipac->name,
475be4d8 1563 dch->dev.id, __builtin_return_address(0));
cae86d4a
KK		 1564 module_put(ipac->owner);
1565 break;
1566 case CONTROL_CHANNEL:
1567 err = channel_ctrl(ipac, arg);
1568 break;
1569 default:
1570 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
1571 return -EINVAL;
1572 }
1573 return err;
1574}
1575
1576u32
1577mISDNipac_init(struct ipac_hw *ipac, void *hw)
1578{
1579 u32 ret;
1580 u8 i;
1581
1582 ipac->hw = hw;
1583 if (ipac->isac.dch.debug & DEBUG_HW)
1584 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
1585 if (ipac->type & IPAC_TYPE_HSCX) {
1586 ipac->isac.type = IPAC_TYPE_ISAC;
1587 ipac->hscx[0].off = 0;
1588 ipac->hscx[1].off = 0x40;
1589 ipac->hscx[0].fifo_size = 32;
1590 ipac->hscx[1].fifo_size = 32;
1591 } else if (ipac->type & IPAC_TYPE_IPAC) {
1592 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
1593 ipac->hscx[0].off = 0;
1594 ipac->hscx[1].off = 0x40;
1595 ipac->hscx[0].fifo_size = 64;
1596 ipac->hscx[1].fifo_size = 64;
1597 } else if (ipac->type & IPAC_TYPE_IPACX) {
1598 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
1599 ipac->hscx[0].off = IPACX_OFF_ICA;
1600 ipac->hscx[1].off = IPACX_OFF_ICB;
1601 ipac->hscx[0].fifo_size = 64;
1602 ipac->hscx[1].fifo_size = 64;
1603 } else
1604 return 0;
1605
1606 mISDNisac_init(&ipac->isac, hw);
1607
1608 ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
1609
1610 for (i = 0; i < 2; i++) {
1611 ipac->hscx[i].bch.nr = i + 1;
1612 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
1613 list_add(&ipac->hscx[i].bch.ch.list,
475be4d8 1614 &ipac->isac.dch.dev.bchannels);
034005a0
KK		 1615 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM,
1616 ipac->hscx[i].fifo_size);
cae86d4a
KK		 1617 ipac->hscx[i].bch.ch.nr = i + 1;
1618 ipac->hscx[i].bch.ch.send = &hscx_l2l1;
1619 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
1620 ipac->hscx[i].bch.hw = hw;
1621 ipac->hscx[i].ip = ipac;
1622 /* default values for IOM time slots
1623 * can be overwriten by card */
1624 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
1625 }
1626
1627 ipac->init = ipac_init;
1628 ipac->release = free_ipac;
1629
1630 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1631 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1632 return ret;
1633}
1634EXPORT_SYMBOL(mISDNipac_init);
1635
1636static int __init
1637isac_mod_init(void)
1638{
1639 pr_notice("mISDNipac module version %s\n", ISAC_REV);
1640 return 0;
1641}
1642
1643static void __exit
1644isac_mod_cleanup(void)
1645{
1646 pr_notice("mISDNipac module unloaded\n");
1647}
1648module_init(isac_mod_init);
1649module_exit(isac_mod_cleanup);
kernel source for telekom puls (alcatel/mediatek)