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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / irqchip / irq-mt-eic.c
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S		 1#include <linux/kernel.h>
2#include <linux/interrupt.h>
3#include <linux/wakelock.h>
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/delay.h>
7#include <linux/platform_device.h>
8#include <linux/timer.h>
9#include <asm/delay.h>
10#include <linux/rbtree.h>
11#include <linux/irqchip/mt-eic.h>
12#include <mach/sync_write.h>
13#include <linux/irqdomain.h>
14#include <linux/irq.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/sched.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/slab.h>
21
22#define EINT_DEBUG 0
23#if(EINT_DEBUG == 1)
24#define dbgmsg printk
25#else
26#define dbgmsg(...)
27#endif
28
29/* Check if NR_IRQS is enough */
30//#if (EINT_IRQ_BASE + EINT_MAX_CHANNEL) > (NR_IRQS)
31//#error NR_IRQS not enough.
32//#endif
33
34static unsigned int EINT_IRQ_BASE;
35
36//#define EINT_TEST_V2
37
38#define MD_EINT
39#define EINT_TEST
40//#define EINT_TEST_SOFT
41//#define DEINT_SUPPORT
42
43#include <cust_eint.h>
44#ifdef MD_EINT
45#include <mach/md_eint.h>
46
47typedef enum
48{
49 SIM_HOT_PLUG_EINT_NUMBER,
50 SIM_HOT_PLUG_EINT_DEBOUNCETIME,
51 SIM_HOT_PLUG_EINT_POLARITY,
52 SIM_HOT_PLUG_EINT_SENSITIVITY,
53 SIM_HOT_PLUG_EINT_SOCKETTYPE,
54 SIM_HOT_PLUG_EINT_DEDICATEDEN,
55 SIM_HOT_PLUG_EINT_SRCPIN,
56}sim_hot_plug_eint_queryType;
57
58typedef enum
59{
60 ERR_SIM_HOT_PLUG_NULL_POINTER=-13,
61 ERR_SIM_HOT_PLUG_QUERY_TYPE,
62 ERR_SIM_HOT_PLUG_QUERY_STRING,
63}sim_hot_plug_eint_queryErr;
64#endif
65
66typedef void (*eint_funct) (void);
67typedef struct
68{
69 eint_funct *eint_func;
70 unsigned int *eint_auto_umask;
71 /*is_deb_en: 1 means enable, 0 means disable */
72 unsigned int *is_deb_en;
73 unsigned int *deb_time;
74 struct timer_list *eint_sw_deb_timer;
75 unsigned int *count;
76} eint_func;
77
78static eint_func EINT_FUNC;
79
80static unsigned int EINT_MAX_CHANNEL = 0;
81
82static void __iomem *EINT_BASE;
83
84static unsigned int mapping_table_entry = 0;
85
86#define MT_EINT_IRQ_ID 185
87struct wake_lock EINT_suspend_lock;
88#if defined(EINT_TEST_V2)
89static unsigned int cur_eint_num;
90#endif
91static DEFINE_SPINLOCK(eint_lock);
92
93/*
94 * mt_eint_get_mask: To get the eint mask
95 * @eint_num: the EINT number to get
96 */
97static unsigned int mt_eint_get_mask(unsigned int eint_num)
98{
99 unsigned long base;
100 unsigned int st;
101 unsigned int bit = 1 << (eint_num % 32);
102
103 if (eint_num < EINT_MAX_CHANNEL) {
104 base = (eint_num / 32) * 4 + EINT_MASK_BASE;
105 } else {
106 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
107 return 0;
108 }
109
110 st = readl(IOMEM(base));
111 if (st & bit) {
112 st = 1; //masked
113 } else {
114 st = 0; //unmasked
115 }
116
117 return st;
118}
119
120#if 0
121void mt_eint_mask_all(void)
122{
123 unsigned long base;
124 unsigned int val = 0xFFFFFFFF, ap_cnt = (EINT_MAX_CHANNEL / 32), i;
125 if (EINT_MAX_CHANNEL % 32)
126 ap_cnt++;
127 dbgmsg("[EINT] cnt:%d\n", ap_cnt);
128
129 base = EINT_MASK_SET_BASE;
130 for (i = 0; i < ap_cnt; i++) {
131 writel(val, IOMEM(base + (i * 4)));
132 dbgmsg("[EINT] mask addr:%x = %x\n", EINT_MASK_BASE + (i * 4),
133 readl(IOMEM(EINT_MASK_BASE + (i * 4))));
134 }
135}
136
137/*
138 * mt_eint_unmask_all: Mask the specified EINT number.
139 */
140void mt_eint_unmask_all(void)
141{
142 unsigned long base;
143 unsigned int val = 0xFFFFFFFF, ap_cnt = (EINT_MAX_CHANNEL / 32), i;
144 if (EINT_MAX_CHANNEL % 32)
145 ap_cnt++;
146 dbgmsg("[EINT] cnt:%d\n", ap_cnt);
147
148 base = EINT_MASK_CLR_BASE;
149 for (i = 0; i < ap_cnt; i++) {
150 writel(val, IOMEM(base + (i * 4)));
151 dbgmsg("[EINT] unmask addr:%x = %x\n", EINT_MASK_BASE + (i * 4),
152 readl(IOMEM(EINT_MASK_BASE + (i * 4))));
153 }
154}
155
156/*
157 * mt_eint_get_soft: To get the eint mask
158 * @eint_num: the EINT number to get
159 */
160unsigned int mt_eint_get_soft(unsigned int eint_num)
161{
162 unsigned long base;
163 unsigned int st;
164
165 if (eint_num < EINT_MAX_CHANNEL) {
166 base = (eint_num / 32) * 4 + EINT_SOFT_BASE;
167 } else {
168 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
169 return 0;
170 }
171 st = readl(IOMEM(base));
172
173 return st;
174}
175#endif
176
177#if 0
178/*
179 * mt_eint_emu_set: Trigger the specified EINT number.
180 * @eint_num: EINT number to set
181 */
182void mt_eint_emu_set(unsigned int eint_num)
183{
184 unsigned long base = 0;
185 unsigned int bit = 1 << (eint_num % 32);
186 unsigned int value = 0;
187
188 if (eint_num < EINT_MAX_CHANNEL) {
189 base = (eint_num / 32) * 4 + EINT_EMUL_BASE;
190 } else {
191 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
192 return;
193 }
194 value = readl(IOMEM(base));
195 value = bit | value;
196 writel(value, IOMEM(base));
197 value = readl(IOMEM(base));
198
199 dbgmsg("[EINT] emul set addr:%x = %x, bit=%x\n", base, value, bit);
200
201
202}
203
204/*
205 * mt_eint_emu_clr: Trigger the specified EINT number.
206 * @eint_num: EINT number to clr
207 */
208void mt_eint_emu_clr(unsigned int eint_num)
209{
210 unsigned long base = 0;
211 unsigned int bit = 1 << (eint_num % 32);
212 unsigned int value = 0;
213
214 if (eint_num < EINT_MAX_CHANNEL) {
215 base = (eint_num / 32) * 4 + EINT_EMUL_BASE;
216 } else {
217 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
218 return;
219 }
220 value = readl(IOMEM(base));
221 value = (~bit) & value;
222 writel(value, IOMEM(base));
223 value = readl(IOMEM(base));
224
225 dbgmsg("[EINT] emul clr addr:%x = %x, bit=%x\n", base, value, bit);
226
227}
228
229/*
230 * eint_send_pulse: Trigger the specified EINT number.
231 * @eint_num: EINT number to send
232 */
233inline void mt_eint_send_pulse(unsigned int eint_num)
234{
235 unsigned long base_set = (eint_num / 32) * 4 + EINT_SOFT_SET_BASE;
236 unsigned long base_clr = (eint_num / 32) * 4 + EINT_SOFT_CLR_BASE;
237 unsigned int bit = 1 << (eint_num % 32);
238 if (eint_num < EINT_MAX_CHANNEL) {
239 base_set = (eint_num / 32) * 4 + EINT_SOFT_SET_BASE;
240 base_clr = (eint_num / 32) * 4 + EINT_SOFT_CLR_BASE;
241 } else {
242 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
243 return;
244 }
245
246 writel(bit, IOMEM(base_set));
247 writel(bit, IOMEM(base_clr));
248}
249#endif
250
251/*
252 * mt_eint_soft_set: Trigger the specified EINT number.
253 * @eint_num: EINT number to set
254 */
255static void mt_eint_soft_set(unsigned int eint_num)
256{
257
258 unsigned long base;
259 unsigned int bit = 1 << (eint_num % 32);
260
261 if (eint_num < EINT_MAX_CHANNEL) {
262 base = (eint_num / 32) * 4 + EINT_SOFT_SET_BASE;
263 } else {
264 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
265 return;
266 }
267 writel(bit, IOMEM(base));
268
269 dbgmsg("[EINT] soft set addr:%x = %x\n", base, bit);
270
271}
272
273/*
274 * mt_eint_soft_clr: Unmask the specified EINT number.
275 * @eint_num: EINT number to clear
276 */
277static void mt_eint_soft_clr(unsigned int eint_num)
278{
279 unsigned long base;
280 unsigned int bit = 1 << (eint_num % 32);
281
282 if (eint_num < EINT_MAX_CHANNEL) {
283 base = (eint_num / 32) * 4 + EINT_SOFT_CLR_BASE;
284 } else {
285 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
286 return;
287 }
288 writel(bit, IOMEM(base));
289
290 dbgmsg("[EINT] soft clr addr:%x = %x\n", base, bit);
291
292}
293
294/*
295 * mt_eint_mask: Mask the specified EINT number.
296 * @eint_num: EINT number to mask
297 */
298void mt_eint_mask(unsigned int eint_num)
299{
300 unsigned long base;
301 unsigned int bit = 1 << (eint_num % 32);
302
303 if (eint_num < EINT_MAX_CHANNEL) {
304 base = (eint_num / 32) * 4 + EINT_MASK_SET_BASE;
305 } else {
306 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
307 return;
308 }
309 mt_reg_sync_writel(bit, base);
310
311 dbgmsg("[EINT] mask addr:%x = %x\n", base, bit);
312}
313
314/*
315 * mt_eint_unmask: Unmask the specified EINT number.
316 * @eint_num: EINT number to unmask
317 */
318void mt_eint_unmask(unsigned int eint_num)
319{
320 unsigned long base;
321 unsigned int bit = 1 << (eint_num % 32);
322
323 if (eint_num < EINT_MAX_CHANNEL) {
324 base = (eint_num / 32) * 4 + EINT_MASK_CLR_BASE;
325 } else {
326 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
327 return;
328 }
329 mt_reg_sync_writel(bit, base);
330
331 dbgmsg("[EINT] unmask addr:%x = %x\n", base, bit);
332}
333
334/*
335 * mt_eint_set_polarity: Set the polarity for the EINT number.
336 * @eint_num: EINT number to set
337 * @pol: polarity to set
338 */
339void mt_eint_set_polarity(unsigned int eint_num, unsigned int pol)
340{
341 unsigned long base;
342 unsigned int bit = 1 << (eint_num % 32);
343
344 if (pol == MT_EINT_POL_NEG) {
345 if (eint_num < EINT_MAX_CHANNEL) {
346 base = (eint_num / 32) * 4 + EINT_POL_CLR_BASE;
347 } else {
348 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
349 return;
350 }
351 } else {
352 if (eint_num < EINT_MAX_CHANNEL) {
353 base = (eint_num / 32) * 4 + EINT_POL_SET_BASE;
354 } else {
355 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
356 return;
357 }
358 }
359 mt_reg_sync_writel(bit, base);
360 dbgmsg("[EINT] %s :%x, bit: %x\n", __func__, base, bit);
361
362 //for (count = 0; count < 250; count++) ;
363
364 // accodring to Designer's (peter) opinion, the longest latency need is about 250 ns
365 ndelay(300);
366
367 if (eint_num < EINT_MAX_CHANNEL) {
368 base = (eint_num / 32) * 4 + EINT_INTACK_BASE;
369 } else {
370 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
371 return;
372 }
373 mt_reg_sync_writel(bit, base);
374}
375
376/*
377 * mt_eint_get_polarity: Set the polarity for the EINT number.
378 * @eint_num: EINT number to get
379 * Return: polarity type
380 * EINT driver INTERNAL use
381 */
382int mt_eint_get_polarity(unsigned int eint_num)
383{
384 unsigned int val;
385 unsigned long base;
386 unsigned int bit = 1 << (eint_num % 32);
387 unsigned int pol;
388
389 if (eint_num < EINT_MAX_CHANNEL) {
390 base = (eint_num / 32) * 4 + EINT_POL_BASE;
391 } else {
392 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
393 return -1;
394 }
395 val = readl(IOMEM(base));
396
397 dbgmsg("[EINT] %s :%x, bit:%x, val:%x\n", __func__, base, bit, val);
398 if (val & bit) {
399 pol = MT_EINT_POL_POS;
400 } else {
401 pol = MT_EINT_POL_NEG;
402 }
403 return pol;
404}
405
406/* For new EINT SW arch. input is virtual irq */
407int mt_eint_get_polarity_external(unsigned int irq_num)
408{
409 unsigned int val;
410 unsigned long base;
411 unsigned int bit;
412 unsigned int pol;
413 unsigned int eint_num;
414
415 eint_num = irq_num - EINT_IRQ_BASE;
416
417 bit = 1 << (eint_num % 32);
418
419 if (eint_num < EINT_MAX_CHANNEL) {
420 base = (eint_num / 32) * 4 + EINT_POL_BASE;
421 } else {
422 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
423 return -1;
424 }
425 val = readl(IOMEM(base));
426
427 dbgmsg("[EINT] %s :%x, bit:%x, val:%x\n", __func__, base, bit, val);
428 if (val & bit) {
429 pol = MT_EINT_POL_POS;
430 } else {
431 pol = MT_EINT_POL_NEG;
432 }
433 return pol;
434}
435
436void mt_eint_revert_polarity(unsigned int eint_num)
437{
438 unsigned int pol;
439 if(mt_eint_get_polarity(eint_num)) {
440 pol = 0;
441 }
442 else {
443 pol = 1;
444 }
445
446 mt_eint_set_polarity(eint_num, pol);
447}
448
449/*
450 * mt_eint_set_sens: Set the sensitivity for the EINT number.
451 * @eint_num: EINT number to set
452 * @sens: sensitivity to set
453 * Always return 0.
454 */
455unsigned int mt_eint_set_sens(unsigned int eint_num, unsigned int sens)
456{
457 unsigned long base;
458 unsigned int bit = 1 << (eint_num % 32);
459
460 if (sens == MT_EDGE_SENSITIVE) {
461 if (eint_num < EINT_MAX_CHANNEL) {
462 base = (eint_num / 32) * 4 + EINT_SENS_CLR_BASE;
463 } else {
464 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
465 return 0;
466 }
467 } else if (sens == MT_LEVEL_SENSITIVE) {
468 if (eint_num < EINT_MAX_CHANNEL) {
469 base = (eint_num / 32) * 4 + EINT_SENS_SET_BASE;
470 } else {
471 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
472 return 0;
473 }
474 } else {
475 printk("%s invalid sensitivity value\n", __func__);
476 return 0;
477 }
478 mt_reg_sync_writel(bit, base);
479 dbgmsg("[EINT] %s :%x, bit: %x\n", __func__, base, bit);
480 return 0;
481}
482
483/*
484 * mt_eint_get_sens: To get the eint sens
485 * @eint_num: the EINT number to get
486 */
487static int mt_eint_get_sens(unsigned int eint_num)
488{
489 unsigned long base, sens;
490 unsigned int bit = 1 << (eint_num % 32), st;
491
492 if (eint_num < EINT_MAX_CHANNEL) {
493 base = (eint_num / 32) * 4 + EINT_SENS_BASE;
494 } else {
495 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
496 return -1;
497 }
498 st = readl(IOMEM(base));
499 if (st & bit) {
500 sens = MT_LEVEL_SENSITIVE;
501 } else {
502 sens = MT_EDGE_SENSITIVE;
503 }
504 return sens;
505}
506
507/*
508 * mt_eint_ack: To ack the interrupt
509 * @eint_num: the EINT number to set
510 */
511unsigned int mt_eint_ack(unsigned int eint_num)
512{
513 unsigned long base;
514 unsigned int bit = 1 << (eint_num % 32);
515
516 if (eint_num < EINT_MAX_CHANNEL) {
517 base = (eint_num / 32) * 4 + EINT_INTACK_BASE;
518 } else {
519 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
520 return 0;
521 }
522 mt_reg_sync_writel(bit, base);
523
524 dbgmsg("[EINT] %s :%x, bit: %x\n", __func__, base, bit);
525 return 0;
526}
527
528/*
529 * mt_eint_read_status: To read the interrupt status
530 * @eint_num: the EINT number to set
531 */
532static unsigned int mt_eint_read_status(unsigned int eint_num)
533{
534 unsigned long base;
535 unsigned int st;
536 unsigned int bit = 1 << (eint_num % 32);
537
538 if (eint_num < EINT_MAX_CHANNEL) {
539 base = (eint_num / 32) * 4 + EINT_STA_BASE;
540 } else {
541 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
542 return 0;
543 }
544 st = readl(IOMEM(base));
545
546 return (st & bit);
547}
548
549/*
550 * mt_eint_get_status: To get the interrupt status
551 * @eint_num: the EINT number to get
552 */
553static int mt_eint_get_status(unsigned int eint_num)
554{
555 unsigned long base;
556 unsigned int st;
557
558 if (eint_num < EINT_MAX_CHANNEL) {
559 base = (eint_num / 32) * 4 + EINT_STA_BASE;
560 } else {
561 dbgmsg("Error in %s [EINT] num:%d is larger than EINT_MAX_CHANNEL\n", __func__, eint_num);
562 return -1;
563 }
564
565 st = readl(IOMEM(base));
566 return st;
567}
568
569/*
570 * mt_eint_en_hw_debounce: To enable hw debounce
571 * @eint_num: the EINT number to set
572 */
573static void mt_eint_en_hw_debounce(unsigned int eint_num)
574{
575 unsigned long base, bit;
576 base = (eint_num / 4) * 4 + EINT_DBNC_SET_BASE;
577 bit = (EINT_DBNC_SET_EN << EINT_DBNC_SET_EN_BITS) << ((eint_num % 4) * 8);
578 writel(bit, IOMEM(base));
579 EINT_FUNC.is_deb_en[eint_num] = 1;
580}
581
582/*
583 * mt_eint_dis_hw_debounce: To disable hw debounce
584 * @eint_num: the EINT number to set
585 */
586static void mt_eint_dis_hw_debounce(unsigned int eint_num)
587{
588 unsigned long clr_base, bit;
589 clr_base = (eint_num / 4) * 4 + EINT_DBNC_CLR_BASE;
590 bit = (EINT_DBNC_CLR_EN << EINT_DBNC_CLR_EN_BITS) << ((eint_num % 4) * 8);
591 writel(bit, IOMEM(clr_base));
592 EINT_FUNC.is_deb_en[eint_num] = 0;
593}
594
595/*
596 * mt_eint_dis_sw_debounce: To set EINT_FUNC.is_deb_en[eint_num] disable
597 * @eint_num: the EINT number to set
598 */
599static void mt_eint_dis_sw_debounce(unsigned int eint_num)
600{
601 if(eint_num < EINT_MAX_CHANNEL)
602 EINT_FUNC.is_deb_en[eint_num] = 0;
603}
604
605/*
606 * mt_eint_en_sw_debounce: To set EINT_FUNC.is_deb_en[eint_num] enable
607 * @eint_num: the EINT number to set
608 */
609static void mt_eint_en_sw_debounce(unsigned int eint_num)
610{
611 if(eint_num < EINT_MAX_CHANNEL)
612 EINT_FUNC.is_deb_en[eint_num] = 1;
613}
614
615/*
616 * mt_can_en_debounce: Check the EINT number is able to enable debounce or not
617 * @eint_num: the EINT number to set
618 */
619static unsigned int mt_can_en_debounce(unsigned int eint_num)
620{
621 unsigned int sens = mt_eint_get_sens(eint_num);
622 /* debounce: debounce time is not 0 && it is not edge sensitive */
623 if (EINT_FUNC.deb_time[eint_num] != 0 && sens != MT_EDGE_SENSITIVE)
624 return 1;
625 else {
626 dbgmsg
627 ("Can't enable debounce of eint_num:%d, deb_time:%d, sens:%d\n",
628 eint_num, EINT_FUNC.deb_time[eint_num], sens);
629 return 0;
630 }
631}
632
633unsigned int mt_gpio_to_irq(unsigned gpio);
634
635/*
636 * mt_eint_set_hw_debounce: Set the de-bounce time for the specified EINT number.
637 * @gpio_pin: EINT number to acknowledge
638 * @ms: the de-bounce time to set (in miliseconds)
639 */
640void mt_eint_set_hw_debounce(unsigned int gpio_pin, unsigned int ms)
641{
642 unsigned int dbnc, bit, clr_bit, rst, unmask = 0, eint_num;
643 unsigned long base, clr_base;
644
645 eint_num = mt_gpio_to_irq(gpio_pin) - EINT_IRQ_BASE;
646
647 if(eint_num >= EINT_MAX_CHANNEL) {
648 printk("%s: eint_num %d invalid\n", __func__, eint_num);
649 return;
650 }
651
652 base = (eint_num / 4) * 4 + EINT_DBNC_SET_BASE;
653 clr_base = (eint_num / 4) * 4 + EINT_DBNC_CLR_BASE;
654 EINT_FUNC.deb_time[eint_num] = ms;
655
656 /*
657 * Don't enable debounce once debounce time is 0 or
658 * its type is edge sensitive.
659 */
660 if (!mt_can_en_debounce(eint_num)) {
661 dbgmsg("Can't enable debounce of eint_num:%d in %s\n", eint_num,
662 __func__);
663 return;
664 }
665
666 if (ms == 0) {
667 dbnc = 0;
668 dbgmsg("ms should not be 0. eint_num:%d in %s\n", eint_num,
669 __func__);
670 } else if (ms <= 1) {
671 dbnc = 1;
672 } else if (ms <= 16) {
673 dbnc = 2;
674 } else if (ms <= 32) {
675 dbnc = 3;
676 } else if (ms <= 64) {
677 dbnc = 4;
678 } else if (ms <= 128) {
679 dbnc = 5;
680 } else if (ms <= 256) {
681 dbnc = 6;
682 } else {
683 dbnc = 7;
684 }
685
686 /* setp 1: mask the EINT */
687 if(!mt_eint_get_mask(eint_num)) {
688 mt_eint_mask(eint_num);
689 unmask = 1;
690 }
691 /* step 2: Check hw debouce number to decide which type should be used */
692 if (eint_num >= MAX_HW_DEBOUNCE_CNT)
693 mt_eint_en_sw_debounce(eint_num);
694 else {
695 /* step 2.1: set hw debounce flag*/
696 EINT_FUNC.is_deb_en[eint_num] = 1;
697
698 /* step 2.2: disable hw debounce */
699 clr_bit = 0xFF << ((eint_num % 4) * 8);
700 mt_reg_sync_writel(clr_bit, clr_base);
701
702 /* step 2.3: set new debounce value */
703 bit =
704 ((dbnc << EINT_DBNC_SET_DBNC_BITS) |
705 (EINT_DBNC_SET_EN << EINT_DBNC_SET_EN_BITS)) <<
706 ((eint_num % 4) * 8);
707 mt_reg_sync_writel(bit, base);
708
709 /* step 2.4: Delay a while (more than 2T) to wait for hw debounce enable work correctly */
710 udelay(500);
711
712 /* step 2.5: Reset hw debounce counter to avoid unexpected interrupt */
713 rst = (EINT_DBNC_RST_BIT << EINT_DBNC_SET_RST_BITS) <<
714 ((eint_num % 4) * 8);
715 mt_reg_sync_writel(rst, base);
716
717 /* step 2.6: Delay a while (more than 2T) to wait for hw debounce counter reset work correctly */
718 udelay(500);
719 }
720 /* step 3: unmask the EINT */
721 if(unmask == 1)
722 mt_eint_unmask(eint_num);
723}
724
725/*
726 * eint_do_tasklet: EINT tasklet function.
727 * @unused: not use.
728 */
729static void eint_do_tasklet(unsigned long unused)
730{
731 wake_lock_timeout(&EINT_suspend_lock, HZ / 2);
732}
733
734DECLARE_TASKLET(eint_tasklet, eint_do_tasklet, 0);
735
736/*
737 * mt_eint_timer_event_handler: EINT sw debounce handler
738 * @eint_num: the EINT number and use unsigned long to prevent
739 * compile warning of timer usage.
740 */
741static void mt_eint_timer_event_handler(unsigned long eint_num)
742{
743 unsigned int status;
744 unsigned long flags;
745
746 if(eint_num >= EINT_MAX_CHANNEL)
747 return;
748
749 /* disable interrupt for core 0 and it will run on core 0 only */
750 local_irq_save(flags);
751 mt_eint_unmask(eint_num);
752 status = mt_eint_read_status(eint_num);
753 dbgmsg("EINT Module - EINT_STA = 0x%x, in %s\n", status, __func__);
754 if (!EINT_FUNC.eint_func[eint_num])
755 {
756 dbgmsg("EINT Module_IRQ - EINT_STA = 0x%x, in %s\n", status, __func__);
757 if(status) {
758 generic_handle_irq(EINT_IRQ(eint_num));
759 }
760 local_irq_restore(flags);
761 }
762 else
763 {
764 if (status) {
765 mt_eint_mask(eint_num);
766 if (EINT_FUNC.eint_func[eint_num])
767 EINT_FUNC.eint_func[eint_num] ();
768 mt_eint_ack(eint_num);
769 }
770 local_irq_restore(flags);
771 if (EINT_FUNC.eint_auto_umask[eint_num])
772 mt_eint_unmask(eint_num);
773 }
774
775 return;
776}
777
778/*
779 * mt_eint_set_timer_event: To set a timer event for sw debounce.
780 * @eint_num: the EINT number to set
781 */
782static void mt_eint_set_timer_event(unsigned int eint_num)
783{
784 struct timer_list *eint_timer = &EINT_FUNC.eint_sw_deb_timer[eint_num];
785 /* assign this handler to execute on core 0 */
786 int cpu = 0;
787
788 /* register timer for this sw debounce eint */
789 eint_timer->expires =
790 jiffies + msecs_to_jiffies(EINT_FUNC.deb_time[eint_num]);
791 dbgmsg("EINT Module - expires:%llu, jiffies:%llu, deb_in_jiffies:%llu, ", eint_timer->expires, jiffies, msecs_to_jiffies(EINT_FUNC.deb_time[eint_num]));
792 dbgmsg("deb:%d, in %s\n", EINT_FUNC.deb_time[eint_num], __func__);
793 eint_timer->data = eint_num;
794 eint_timer->function = &mt_eint_timer_event_handler;
795 init_timer(eint_timer);
796 add_timer_on(eint_timer, cpu);
797}
798
799/*
800 * mt_eint_isr: EINT interrupt service routine.
801 * @irq: EINT IRQ number
802 * @desc: EINT IRQ descriptor
803 * Return IRQ returned code.
804 */
805static irqreturn_t mt_eint_demux(unsigned irq, struct irq_desc *desc)
806{
807 unsigned int index, rst;
808 unsigned long base;
809 unsigned int status = 0;
810 unsigned int status_check;
811 unsigned int reg_base,offset;
812 unsigned long long t1, t2;
813 int mask_status=0;
814 struct irq_chip *chip = irq_get_chip(irq);
815 chained_irq_enter(chip, desc);
816
817 /*
818 * NoteXXX: Need to get the wake up for 0.5 seconds when an EINT intr tirggers.
819 * This is used to prevent system from suspend such that other drivers
820 * or applications can have enough time to obtain their own wake lock.
821 * (This information is gotten from the power management owner.)
822 */
823
824 tasklet_schedule(&eint_tasklet);
825 dbgmsg("EINT Module - %s ISR Start\n", __func__);
826 //printk("EINT acitve: %s, acitve status: %d\n", mt_irq_is_active(EINT_IRQ) ? "yes" : "no", mt_irq_is_active(EINT_IRQ));
827
828 for (reg_base = 0; reg_base < EINT_MAX_CHANNEL; reg_base+=32) {
829 /* read status register every 32 interrupts */
830 status = mt_eint_get_status(reg_base);
831 if(status){
832 dbgmsg("EINT Module - index:%d,EINT_STA = 0x%x\n",
833 reg_base, status);
834 }
835 else{
836 continue;
837 }
838 for(offset = 0; offset < 32; offset++){
839 index = reg_base + offset;
840 if (index >= EINT_MAX_CHANNEL) break;
841
842 status_check = status & (1 << (index % 32));
843 if (status_check) {
844 dbgmsg("Got eint:%d\n",index);
845
846 EINT_FUNC.count[index]++;
847
848 // deal with EINT from request_irq()
849 if (!EINT_FUNC.eint_func[index])
850 {
851 dbgmsg("EINT %d: go with new mt_eint\n", index);
852 if ((EINT_FUNC.is_deb_en[index] == 1) &&
853 (index >= MAX_HW_DEBOUNCE_CNT)) {
854 /* if its debounce is enable and it is a sw debounce */
855 mt_eint_mask(index);
856 dbgmsg("got sw index %d\n", index);
857 mt_eint_set_timer_event(index);
858 } else {
859 dbgmsg("got hw index %d\n", index);
860 t1 = sched_clock();
861 generic_handle_irq(index + EINT_IRQ_BASE);
862 t2 = sched_clock();
863 if ((EINT_FUNC.is_deb_en[index] == 1) &&
864 (index < MAX_HW_DEBOUNCE_CNT)) {
865
866 if(mt_eint_get_mask(index)==1)
867 {
868 mask_status=1;
869 }
870 else
871 {
872 mask_status=0;
873 }
874 mt_eint_mask(index);
875
876 /* Don't need to use reset ? */
877 /* reset debounce counter */
878 base = (index / 4) * 4 + EINT_DBNC_SET_BASE;
879 rst = (EINT_DBNC_RST_BIT << EINT_DBNC_SET_RST_BITS) <<
880 ((index % 4) * 8);
881 mt_reg_sync_writel(rst, base);
882
883 if(mask_status==0)
884 mt_eint_unmask(index);
885 }
886#if(EINT_DEBUG == 1)
887 dbgmsg("EINT Module - EINT_STA after ack = 0x%x\n", mt_eint_get_status(index));
888#endif
889
890 if ((t2-t1) > EINT_DELAY_WARNING)
891 printk("[EINT]Warn!EINT:%d run too long,s:%llu,e:%llu,total:%llu\n", index, t1, t2, (t2 - t1));
892 }
893 }
894 // deal with EINT from mt_eint_registration()
895 else
896 {
897 mt_eint_mask(index);
898 dbgmsg("EINT %d: go with original mt_eint\n", index);
899 if ((EINT_FUNC.is_deb_en[index] == 1) &&
900 (index >= MAX_HW_DEBOUNCE_CNT)) {
901 /* if its debounce is enable and it is a sw debounce */
902 mt_eint_set_timer_event(index);
903 } else {
904 /* HW debounce or no use debounce */
905 t1 = sched_clock();
906 if (EINT_FUNC.eint_func[index]) {
907 EINT_FUNC.eint_func[index] ();
908 }
909 t2 = sched_clock();
910 mt_eint_ack(index);
911#if 1 /* Don't need to use reset ? */
912 /* reset debounce counter */
913 base = (index / 4) * 4 + EINT_DBNC_SET_BASE;
914 rst =
915 (EINT_DBNC_RST_BIT << EINT_DBNC_SET_RST_BITS) <<
916 ((index % 4) * 8);
917 mt_reg_sync_writel(rst, base);
918#endif
919#if(EINT_DEBUG == 1)
920 status = mt_eint_get_status(index);
921 dbgmsg("EINT Module - EINT_STA after ack = 0x%x\n", status);
922#endif
923 if (EINT_FUNC.eint_auto_umask[index]) {
924 mt_eint_unmask(index);
925 }
926
927 if ((t2-t1) > EINT_DELAY_WARNING)
928 printk("[EINT]Warn!EINT:%d run too long,s:%llu,e:%llu,total:%llu\n", index, t1, t2, (t2 - t1));
929 }
930 }
931 }
932 }
933 }
934
935 dbgmsg("EINT Module - %s ISR END\n", __func__);
936 chained_irq_exit(chip, desc);
937 return IRQ_HANDLED;
938}
939
940static int mt_eint_max_channel(void)
941{
942 return EINT_MAX_CHANNEL;
943}
944
945/*
946 * mt_eint_dis_debounce: To disable debounce.
947 * @eint_num: the EINT number to disable
948 */
949static void mt_eint_dis_debounce(unsigned int eint_num)
950{
951 /* This function is used to disable debounce whether hw or sw */
952 if (eint_num < MAX_HW_DEBOUNCE_CNT)
953 mt_eint_dis_hw_debounce(eint_num);
954 else
955 mt_eint_dis_sw_debounce(eint_num);
956}
957
958/*
959 * mt_eint_registration: register a EINT.
960 * @eint_num: the EINT number to register
961 * @flag: the interrupt line behaviour to select
962 * @EINT_FUNC_PTR: the ISR callback function
963 * @is_auto_unmask: the indication flag of auto unmasking after ISR callback is processed
964 */
965#if 1
966void mt_eint_registration(unsigned int eint_num, unsigned int flag,
967 void (EINT_FUNC_PTR) (void), unsigned int is_auto_umask)
968{
969 if (eint_num < EINT_MAX_CHANNEL) {
970 printk("eint register for %d\n", eint_num);
971 spin_lock(&eint_lock);
972 mt_eint_mask(eint_num);
973
974 if (flag & (EINTF_TRIGGER_RISING | EINTF_TRIGGER_FALLING)) {
975 mt_eint_set_polarity(eint_num, (flag & EINTF_TRIGGER_FALLING) ? MT_EINT_POL_NEG : MT_EINT_POL_POS);
976 mt_eint_set_sens(eint_num, MT_EDGE_SENSITIVE);
977 } else if (flag & (EINTF_TRIGGER_HIGH | EINTF_TRIGGER_LOW)) {
978 mt_eint_set_polarity(eint_num, (flag & EINTF_TRIGGER_LOW) ? MT_EINT_POL_NEG : MT_EINT_POL_POS);
979 mt_eint_set_sens(eint_num, MT_LEVEL_SENSITIVE);
980 } else {
981 printk("[EINT]: Wrong EINT Pol/Sens Setting 0x%x\n", flag);
982 spin_unlock(&eint_lock);
983 return ;
984 }
985
986 EINT_FUNC.eint_func[eint_num] = EINT_FUNC_PTR;
987 spin_unlock(&eint_lock);
988 EINT_FUNC.eint_auto_umask[eint_num] = is_auto_umask;
989 mt_eint_ack(eint_num);
990 mt_eint_unmask(eint_num);
991 } else {
992 printk("[EINT]: Wrong EINT Number %d\n", eint_num);
993 }
994}
995#endif
996
997static unsigned int mt_eint_get_debounce_cnt(unsigned int cur_eint_num)
998{
999 unsigned int dbnc, deb;
1000 unsigned long base;
1001 base = (cur_eint_num / 4) * 4 + EINT_DBNC_BASE;
1002
1003 if(cur_eint_num >= EINT_MAX_CHANNEL)
1004 return 0;
1005
1006 if (cur_eint_num >= MAX_HW_DEBOUNCE_CNT)
1007 deb = EINT_FUNC.deb_time[cur_eint_num];
1008 else {
1009 dbnc = readl(IOMEM(base));
1010 dbnc = ((dbnc >> EINT_DBNC_SET_DBNC_BITS) >> ((cur_eint_num % 4) * 8) & EINT_DBNC);
1011
1012 switch (dbnc) {
1013 case 0:
1014 deb = 0; /* 0.5 actually, but we don't allow user to set. */
1015 dbgmsg(KERN_CRIT"ms should not be 0. eint_num:%d in %s\n",
1016 cur_eint_num, __func__);
1017 break;
1018 case 1:
1019 deb = 1;
1020 break;
1021 case 2:
1022 deb = 16;
1023 break;
1024 case 3:
1025 deb = 32;
1026 break;
1027 case 4:
1028 deb = 64;
1029 break;
1030 case 5:
1031 deb = 128;
1032 break;
1033 case 6:
1034 deb = 256;
1035 break;
1036 case 7:
1037 deb = 512;
1038 break;
1039 default:
1040 deb = 0;
1041 printk("invalid deb time in the EIN_CON register, dbnc:%d, deb:%d\n", dbnc, deb);
1042 break;
1043 }
1044 }
1045
1046 return deb;
1047}
1048
1049static int mt_eint_is_debounce_en(unsigned int cur_eint_num)
1050{
1051 unsigned long base, val, en;
1052 if (cur_eint_num < MAX_HW_DEBOUNCE_CNT) {
1053 base = (cur_eint_num / 4) * 4 + EINT_DBNC_BASE;
1054 val = readl(IOMEM(base));
1055 val = val >> ((cur_eint_num % 4) * 8);
1056 if (val & EINT_DBNC_EN_BIT) {
1057 en = 1;
1058 } else {
1059 en = 0;
1060 }
1061 } else {
1062 en = EINT_FUNC.is_deb_en[cur_eint_num];
1063 }
1064
1065 return en;
1066}
1067
1068static void mt_eint_enable_debounce(unsigned int cur_eint_num)
1069{
1070 mt_eint_mask(cur_eint_num);
1071 if (cur_eint_num < MAX_HW_DEBOUNCE_CNT) {
1072 /* HW debounce */
1073 mt_eint_en_hw_debounce(cur_eint_num);
1074 } else {
1075 /* SW debounce */
1076 mt_eint_en_sw_debounce(cur_eint_num);
1077 }
1078 mt_eint_unmask(cur_eint_num);
1079}
1080
1081static void mt_eint_disable_debounce(unsigned int cur_eint_num)
1082{
1083 mt_eint_mask(cur_eint_num);
1084 if (cur_eint_num < MAX_HW_DEBOUNCE_CNT) {
1085 /* HW debounce */
1086 mt_eint_dis_hw_debounce(cur_eint_num);
1087 } else {
1088 /* SW debounce */
1089 mt_eint_dis_sw_debounce(cur_eint_num);
1090 }
1091 mt_eint_unmask(cur_eint_num);
1092}
1093
1094
1095/*
1096 * mt_eint_setdomain0: set all eint_num to domain 0.
1097 */
1098static void mt_eint_setdomain0(void)
1099{
1100 unsigned long base;
1101 unsigned int val = 0xFFFFFFFF, ap_cnt = (EINT_MAX_CHANNEL / 32), i;
1102 if (EINT_MAX_CHANNEL % 32)
1103 ap_cnt++;
1104 dbgmsg("[EINT] cnt:%d\n", ap_cnt);
1105
1106 base = EINT_D0_EN_BASE;
1107 for (i = 0; i < ap_cnt; i++) {
1108 mt_reg_sync_writel(val, base + (i * 4));
1109 dbgmsg("[EINT] domain addr:%x = %x\n", base, readl(IOMEM(base)));
1110 }
1111}
1112
1113#ifdef MD_EINT
1114typedef struct{
1115 char name[24];
1116 int eint_num;
1117 int eint_deb;
1118 int eint_pol;
1119 int eint_sens;
1120 int socket_type;
1121 int dedicatedEn;
1122 int srcPin;
1123}MD_SIM_HOTPLUG_INFO;
1124
1125#define MD_SIM_MAX 16
1126MD_SIM_HOTPLUG_INFO md_sim_info[MD_SIM_MAX];
1127unsigned int md_sim_counter = 0;
1128
1129int get_eint_attribute(char *name, unsigned int name_len, unsigned int type, char *result, unsigned int *len)
1130{
1131 int i;
1132 int ret = 0;
1133 int *sim_info = (int *)result;
1134 printk("in %s\n",__func__);
1135 //printk("[EINT]CUST_EINT_MD1_CNT:%d,CUST_EINT_MD2_CNT:%d\n",CUST_EINT_MD1_CNT,CUST_EINT_MD2_CNT);
1136 printk("[EINT]CUST_EINT_MD1_CNT:%d",CUST_EINT_MD1_CNT);
1137 printk("query info: name:%s, type:%d, len:%d\n", name,type,name_len);
1138 if (len == NULL || name == NULL || result == NULL)
1139 return ERR_SIM_HOT_PLUG_NULL_POINTER;
1140
1141 for (i = 0; i < md_sim_counter; i++){
1142 printk("compare string:%s\n", md_sim_info[i].name);
1143 if (!strncmp(name, md_sim_info[i].name, name_len))
1144 {
1145 switch(type)
1146 {
1147 case SIM_HOT_PLUG_EINT_NUMBER:
1148 *len = sizeof(md_sim_info[i].eint_num);
1149 memcpy(sim_info, &md_sim_info[i].eint_num, *len);
1150 printk("[EINT]eint_num:%d\n", md_sim_info[i].eint_num);
1151 break;
1152
1153 case SIM_HOT_PLUG_EINT_DEBOUNCETIME:
1154 *len = sizeof(md_sim_info[i].eint_deb);
1155 memcpy(sim_info, &md_sim_info[i].eint_deb, *len);
1156 printk("[EINT]eint_deb:%d\n", md_sim_info[i].eint_deb);
1157 break;
1158
1159 case SIM_HOT_PLUG_EINT_POLARITY:
1160 *len = sizeof(md_sim_info[i].eint_pol);
1161 memcpy(sim_info, &md_sim_info[i].eint_pol, *len);
1162 printk("[EINT]eint_pol:%d\n", md_sim_info[i].eint_pol);
1163 break;
1164
1165 case SIM_HOT_PLUG_EINT_SENSITIVITY:
1166 *len = sizeof(md_sim_info[i].eint_sens);
1167 memcpy(sim_info, &md_sim_info[i].eint_sens, *len);
1168 printk("[EINT]eint_sens:%d\n", md_sim_info[i].eint_sens);
1169 break;
1170
1171 case SIM_HOT_PLUG_EINT_SOCKETTYPE:
1172 *len = sizeof(md_sim_info[i].socket_type);
1173 memcpy(sim_info, &md_sim_info[i].socket_type, *len);
1174 printk("[EINT]socket_type:%d\n", md_sim_info[i].socket_type);
1175 break;
1176
1177 case SIM_HOT_PLUG_EINT_DEDICATEDEN:
1178 *len = sizeof(md_sim_info[i].dedicatedEn);
1179 memcpy(sim_info, &md_sim_info[i].dedicatedEn, *len);
1180 printk("[EINT]dedicatedEn:%d\n", md_sim_info[i].dedicatedEn);
1181 break;
1182
1183 case SIM_HOT_PLUG_EINT_SRCPIN:
1184 *len = sizeof(md_sim_info[i].srcPin);
1185 memcpy(sim_info, &md_sim_info[i].srcPin, *len);
1186 printk("[EINT]srcPin:%d\n", md_sim_info[i].srcPin);
1187 break;
1188
1189 default:
1190 ret = ERR_SIM_HOT_PLUG_QUERY_TYPE;
1191 *len = sizeof(int);
1192 memset(sim_info, 0xff, *len);
1193 break;
1194 }
1195 return ret;
1196 }
1197 }
1198
1199 *len = sizeof(int);
1200 memset(sim_info, 0xff, *len);
1201
1202 return ERR_SIM_HOT_PLUG_QUERY_STRING;
1203}
1204
1205int get_type(char *name)
1206{
1207
1208 int type1 = 0x0;
1209 int type2 = 0x0;
1210#if defined(CONFIG_MTK_SIM1_SOCKET_TYPE) || defined(CONFIG_MTK_SIM2_SOCKET_TYPE)
1211 char *p;
1212#endif
1213
1214#ifdef CONFIG_MTK_SIM1_SOCKET_TYPE
1215 p = (char *)CONFIG_MTK_SIM1_SOCKET_TYPE;
1216 type1 = simple_strtoul(p, &p, 10);
1217#endif
1218#ifdef CONFIG_MTK_SIM2_SOCKET_TYPE
1219 p = (char *)CONFIG_MTK_SIM2_SOCKET_TYPE;
1220 type2 = simple_strtoul(p, &p, 10);
1221#endif
1222 if (!strncmp(name, "MD1_SIM1_HOT_PLUG_EINT", strlen("MD1_SIM1_HOT_PLUG_EINT")))
1223 return type1;
1224 else if (!strncmp(name, "MD1_SIM1_HOT_PLUG_EINT", strlen("MD1_SIM1_HOT_PLUG_EINT")))
1225 return type1;
1226 else if (!strncmp(name, "MD2_SIM2_HOT_PLUG_EINT", strlen("MD2_SIM2_HOT_PLUG_EINT")))
1227 return type2;
1228 else if (!strncmp(name, "MD2_SIM2_HOT_PLUG_EINT", strlen("MD2_SIM2_HOT_PLUG_EINT")))
1229 return type2;
1230 else
1231 return 0;
1232}
1233#endif
1234
1235static void setup_MD_eint(void)
1236{
1237#ifdef MD_EINT
1238 //printk("[EINT]CUST_EINT_MD1_CNT:%d,CUST_EINT_MD2_CNT:%d\n",CUST_EINT_MD1_CNT,CUST_EINT_MD2_CNT);
1239 printk("[EINT]CUST_EINT_MD1_CNT:%d",CUST_EINT_MD1_CNT);
1240
1241#if defined(CUST_EINT_MD1_0_NAME)
1242 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD1_0_NAME);
1243 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD1_0_NUM;
1244 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD1_0_POLARITY;
1245 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD1_0_SENSITIVE;
1246 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1247 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD1_0_DEBOUNCE_CN;
1248 md_sim_info[md_sim_counter].dedicatedEn = CUST_EINT_MD1_0_DEDICATED_EN;
1249 md_sim_info[md_sim_counter].srcPin = CUST_EINT_MD1_0_SRCPIN;
1250 printk("[EINT] MD1 name = %s\n", md_sim_info[md_sim_counter].name);
1251 printk("[EINT] MD1 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1252 md_sim_counter++;
1253#endif
1254#if defined(CUST_EINT_MD1_1_NAME)
1255 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD1_1_NAME);
1256 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD1_1_NUM;
1257 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD1_1_POLARITY;
1258 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD1_1_SENSITIVE;
1259 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1260 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD1_1_DEBOUNCE_CN;
1261 md_sim_info[md_sim_counter].dedicatedEn = CUST_EINT_MD1_1_DEDICATED_EN;
1262 md_sim_info[md_sim_counter].srcPin = CUST_EINT_MD1_1_SRCPIN;
1263 printk("[EINT] MD1 name = %s\n", md_sim_info[md_sim_counter].name);
1264 printk("[EINT] MD1 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1265 md_sim_counter++;
1266#endif
1267#if defined(CUST_EINT_MD1_2_NAME)
1268 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD1_2_NAME);
1269 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD1_2_NUM;
1270 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD1_2_POLARITY;
1271 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD1_2_SENSITIVE;
1272 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1273 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD1_2_DEBOUNCE_CN;
1274 md_sim_info[md_sim_counter].dedicatedEn = CUST_EINT_MD1_2_DEDICATED_EN;
1275 md_sim_info[md_sim_counter].srcPin = CUST_EINT_MD1_2_SRCPIN;
1276 printk("[EINT] MD1 name = %s\n", md_sim_info[md_sim_counter].name);
1277 printk("[EINT] MD1 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1278 md_sim_counter++;
1279#endif
1280#if defined(CUST_EINT_MD1_3_NAME)
1281 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD1_3_NAME);
1282 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD1_3_NUM;
1283 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD1_3_POLARITY;
1284 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD1_3_SENSITIVE;
1285 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1286 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD1_3_DEBOUNCE_CN;
1287 md_sim_info[md_sim_counter].dedicatedEn = CUST_EINT_MD1_3_DEDICATED_EN;
1288 md_sim_info[md_sim_counter].srcPin = CUST_EINT_MD1_3_SRCPIN;
1289 printk("[EINT] MD1 name = %s\n", md_sim_info[md_sim_counter].name);
1290 printk("[EINT] MD1 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1291 md_sim_counter++;
1292#endif
1293#if defined(CUST_EINT_MD1_4_NAME)
1294 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD1_4_NAME);
1295 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD1_4_NUM;
1296 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD1_4_POLARITY;
1297 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD1_4_SENSITIVE;
1298 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1299 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD1_4_DEBOUNCE_CN;
1300 printk("[EINT] MD1 name = %s\n", md_sim_info[md_sim_counter].name);
1301 printk("[EINT] MD1 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1302 md_sim_counter++;
1303#endif
1304
1305#if defined(CUST_EINT_MD2_0_NAME)
1306 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD2_0_NAME);
1307 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD2_0_NUM;
1308 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD2_0_POLARITY;
1309 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD2_0_SENSITIVE;
1310 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1311 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD2_0_DEBOUNCE_CN;
1312 printk("[EINT] MD2 name = %s\n", md_sim_info[md_sim_counter].name);
1313 printk("[EINT] MD2 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1314 md_sim_counter++;
1315#endif
1316#if defined(CUST_EINT_MD2_1_NAME)
1317 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD2_1_NAME);
1318 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD2_1_NUM;
1319 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD2_1_POLARITY;
1320 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD2_1_SENSITIVE;
1321 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1322 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD2_1_DEBOUNCE_CN;
1323 printk("[EINT] MD2 name = %s\n", md_sim_info[md_sim_counter].name);
1324 printk("[EINT] MD2 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1325 md_sim_counter++;
1326#endif
1327#if defined(CUST_EINT_MD2_2_NAME)
1328 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD2_2_NAME);
1329 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD2_2_NUM;
1330 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD2_2_POLARITY;
1331 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD2_2_SENSITIVE;
1332 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1333 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD2_2_DEBOUNCE_CN;
1334 dbgmsg("[EINT] MD2 name = %s\n", md_sim_info[md_sim_counter].name);
1335 dbgmsg("[EINT] MD2 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1336 md_sim_counter++;
1337#endif
1338#if defined(CUST_EINT_MD2_3_NAME)
1339 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD2_3_NAME);
1340 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD2_3_NUM;
1341 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD2_3_POLARITY;
1342 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD2_3_SENSITIVE;
1343 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1344 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD2_3_DEBOUNCE_CN;
1345 printk("[EINT] MD2 name = %s\n", md_sim_info[md_sim_counter].name);
1346 printk("[EINT] MD2 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1347 md_sim_counter++;
1348#endif
1349#if defined(CUST_EINT_MD2_4_NAME)
1350 sprintf(md_sim_info[md_sim_counter].name, CUST_EINT_MD2_4_NAME);
1351 md_sim_info[md_sim_counter].eint_num = CUST_EINT_MD2_4_NUM;
1352 md_sim_info[md_sim_counter].eint_pol= CUST_EINT_MD2_4_POLARITY;
1353 md_sim_info[md_sim_counter].eint_sens = CUST_EINT_MD2_4_SENSITIVE;
1354 md_sim_info[md_sim_counter].socket_type = get_type(md_sim_info[md_sim_counter].name);
1355 md_sim_info[md_sim_counter].eint_deb = CUST_EINT_MD2_4_DEBOUNCE_CN;
1356 printk("[EINT] MD2 name = %s\n", md_sim_info[md_sim_counter].name);
1357 printk("[EINT] MD2 type = %d\n", md_sim_info[md_sim_counter].socket_type);
1358 md_sim_counter++;
1359#endif
1360#endif //MD_EINT
1361}
1362
1363static unsigned int mt_eint_get_count(unsigned int eint_num)
1364{
1365 if(eint_num < EINT_MAX_CHANNEL)
1366 return EINT_FUNC.count[eint_num];
1367
1368 return 0;
1369}
1370
1371#ifdef EINT_TEST_V2
1372unsigned long long hw_debounce_start;
1373unsigned long long hw_debounce_end;
1374volatile int EINT_waiting;
1375static struct platform_driver eint_driver = {
1376 .driver = {
1377 .name = "eint_test",
1378 .bus = &platform_bus_type,
1379 .owner = THIS_MODULE,
1380 }
1381};
1382
1383static void gpio_set_debounce(unsigned gpio, unsigned debounce);
1384
1385static void mt_eint_soft_isr(void)
1386{
1387 dbgmsg("in mt_eint_soft_isr\n");
1388 mt_eint_soft_clr(cur_eint_num);
1389 return;
1390}
1391
1392//static irqreturn_t mt_eint_soft_isr(unsigned irq, struct irq_desc *desc)
1393//{
1394// int eint_num=0;
1395// eint_num=DEMUX_EINT_IRQ(irq);
1396// printk("======EINT_SOFT_ISR======\n");
1397// printk("EINT %d, in %s\n",__func__, eint_num);
1398// mt_eint_soft_clr(eint_num);
1399// printk("======EINT_SOFT_ISR_END======\n");
1400// return IRQ_HANDLED;
1401//}
1402
1403static irqreturn_t mt_eint_soft_revert_isr(unsigned irq, struct irq_desc *desc)
1404{
1405 int eint_num=0;
1406 eint_num=DEMUX_EINT_IRQ(irq);
1407 printk("======EINT_SOFT_REVERT_ISR======\n");
1408 printk("EINT %d, in %s\n", eint_num, __func__);
1409 //mt_eint_soft_clr(eint_num);
1410 mt_eint_revert_polarity(eint_num);
1411 printk("======EINT_SOFT_REVERT_ISR_END======\n");
1412 return IRQ_HANDLED;
1413}
1414
1415volatile unsigned int sw_debounce = 0;
1416
1417static irqreturn_t mt_eint_soft_debounce_isr(unsigned irq, struct irq_desc *desc)
1418{
1419 int eint_num=0;
1420 eint_num=DEMUX_EINT_IRQ(irq);
1421 printk("======EINT_SOFT_DEBOUNCE_ISR======\n");
1422 printk("EINT %d, in %s\n", eint_num, __func__);
1423 //mt_eint_soft_clr(eint_num);
1424 mt_eint_revert_polarity(eint_num);
1425 printk("======EINT_SOFT_DEBOUNCE_ISR_END======\n");
1426 sw_debounce = 1;
1427 return IRQ_HANDLED;
1428}
1429
1430static irqreturn_t mt_eint_soft_nonauto_unmask_isr(unsigned irq, struct irq_desc *desc)
1431{
1432 int eint_num=0;
1433 eint_num=DEMUX_EINT_IRQ(irq);
1434 printk("======EINT_NONAUTO_SOFT_ISR======\n");
1435 printk("EINT %d, in %s\n", eint_num, __func__);
1436 //mt_eint_soft_clr(eint_num);
1437 mt_eint_revert_polarity(eint_num);
1438 disable_irq_nosync(irq);
1439 printk("======EINT_NONAUTO_SOFT_ISR_END======\n");
1440 return IRQ_HANDLED;
1441}
1442
1443#define EINT_IN 0
1444#define EINT_OUT 1
1445// these 2 arrays are for EINT HW debounce test
1446// refer to designer / SA for detail
1447int eint_debounce[] = {30, 31};
1448int gpio_debounce[] = {58, 59};
1449int eint_num=3;
1450
1451static irqreturn_t mt_eint_hw_debounce_isr(unsigned irq, struct irq_desc *desc)
1452{
1453 int eint_num;
1454 eint_num=DEMUX_EINT_IRQ(irq);
1455 hw_debounce_end=sched_clock();
1456 EINT_waiting=0;
1457 printk("======EINT_HW_DEBOUNCE_ISR======\n");
1458 printk("EINT %d, in %s\n", eint_num, __func__);
1459 printk("======EINT_HW_DEBOUNCE_ISR_END======\n");
1460 mt_set_gpio_out(gpio_debounce[EINT_OUT], 0);
1461 return IRQ_HANDLED;
1462}
1463
1464typedef void (*EINT_FUNC_PTR)(void);
1465
1466static void mt_eint_test(void)
1467{
1468 int eint_num = 1;
1469 int is_auto_umask = 0;
1470 int ret = 0;
1471 cur_eint_num = 1;
1472 mt_eint_mask(eint_num);
1473 mt_eint_set_polarity(eint_num, MT_LEVEL_SENSITIVE);
1474 mt_eint_set_sens(eint_num, MT_EINT_POL_POS);
1475 mt_eint_registration(eint_num, IRQF_TRIGGER_HIGH, mt_eint_soft_isr, is_auto_umask);
1476 if(ret>0)
1477 {
1478 printk(KERN_ERR "EINT IRQ LINE NOT AVAILABLE!!\n");
1479 }
1480 mt_eint_unmask(eint_num);
1481 mt_eint_soft_set(eint_num);
1482}
1483
1484void setup_level_trigger_env(unsigned int eint)
1485{
1486 unsigned long base, pol_base, raw_base;
1487 if(eint >= EINT_MAX_CHANNEL) {
1488 printk("%s: eint %d >= %d\n", __func__, eint, EINT_MAX_CHANNEL);
1489 return;
1490 }
1491
1492 base = eint / 32;
1493 raw_base = EINT_RAW_STA_BASE + base * 4;
1494 pol_base = EINT_POL_SET_BASE + base * 4;
1495 //printk("EINT_POL_BASE for eint %d is 0x%x\n", eint, pol_base);
1496 //printk("EINT_RAW_STA_BASE for eint %d is 0x%x\n", eint, raw_base);
1497
1498 mt_eint_mask(eint);
1499 mt_eint_set_sens(eint, MT_LEVEL_SENSITIVE);
1500 mt_eint_set_polarity(eint, MT_EINT_POL_NEG);
1501 writel(readl(IOMEM(raw_base)) & 0xFFFFFFFF, IOMEM(pol_base));
1502}
1503
1504static void mt_eint_autounmask_test(void)
1505{
1506 int ret=0;
1507 struct irq_desc *desc;
1508 printk("%s for EINT %d\n", __func__, eint_num);
1509 setup_level_trigger_env(eint_num);
1510 ret=request_irq(EINT_IRQ(eint_num),(irq_handler_t)mt_eint_soft_revert_isr, mt_eint_get_polarity(eint_num),"EINT-AUTOUNMASK",NULL);
1511 if(ret>0) {
1512 printk(KERN_ERR "EINT IRQ LINE NOT AVAILABLE!!\n");
1513 return;
1514 }
1515 desc=irq_to_desc(EINT_IRQ(eint_num));
1516 printk("EINT %d request_irq done\n",eint_num);
1517 mt_eint_revert_polarity(eint_num);
1518 //mt_eint_soft_set(eint_num);
1519 printk("trigger EINT %d done\n",eint_num);
1520 printk("EINT %d, MASK 0x%d\n",eint_num,mt_eint_get_mask(eint_num));
1521 free_irq(EINT_IRQ(eint_num),NULL);
1522}
1523
1524static int mt_eint_non_autounmask_test(void)
1525{
1526 int ret = 0;
1527 setup_level_trigger_env(eint_num);
1528 EINT_FUNC.eint_func[eint_num]=NULL;
1529 printk("%s for EINT %d\n", __func__, eint_num);
1530 //ret=request_irq(EINT_IRQ(eint_num), (irq_handler_t)mt_eint_soft_nonauto_unmask_isr,IRQF_TRIGGER_LOW ,"EINT-3", NULL);
1531 ret=request_irq(EINT_IRQ(eint_num),(irq_handler_t)mt_eint_soft_nonauto_unmask_isr, mt_eint_get_polarity(eint_num),"EINT-NONAUTOUNMASK",NULL);
1532 if(ret>0) {
1533 printk(KERN_ERR "EINT IRQ LINE NOT AVAILABLE!!\n");
1534 return -1;
1535 }
1536 printk("EINT %d request_irq done\n",eint_num);
1537 //mt_eint_soft_set(eint_num);
1538 mt_eint_revert_polarity(eint_num);
1539 printk("trigger EINT %d done\n",eint_num);
1540 printk("EINT %d, MASK 0x%d\n",eint_num,mt_eint_get_mask(eint_num));
1541 free_irq(EINT_IRQ(eint_num), NULL);
1542 return 1;
1543}
1544
1545void mt_eint_normal_test_based_on_sw_debounce(void)
1546{
1547 int eint_num=36;
1548 int ret=0;
1549 unsigned int debounce_time=30;
1550 setup_level_trigger_env(eint_num);
1551 printk("%s for EINT %d\n", __func__, eint_num);
1552 gpio_set_debounce(EINT_GPIO(eint_num),debounce_time);
1553 printk("EINT %d debounce enable %d\n",eint_num,mt_eint_is_debounce_en(eint_num));
1554 //ret=request_irq(EINT_IRQ(eint_num), (irq_handler_t)mt_eint_soft_debounce_isr,IRQF_TRIGGER_LOW ,"EINT-SWDEBOUNCE",NULL);
1555 ret=request_irq(EINT_IRQ(eint_num),(irq_handler_t)mt_eint_soft_debounce_isr, mt_eint_get_polarity(eint_num),"EINT-SWDEBOUNCE",NULL);
1556 if(ret>0)
1557 printk(KERN_ERR "EINT IRQ LINE NOT AVAILABLE!!\n");
1558 printk("EINT %d request_irq done\n",eint_num);
1559 //mt_eint_soft_set(eint_num);
1560 mt_eint_revert_polarity(eint_num);
1561 printk("trigger EINT %d done\n",eint_num);
1562 printk("start waiting sw_debounce\n");
1563 while(!sw_debounce);
1564 sw_debounce = 0;
1565 // busy wait
1566 printk("EINT %d, MASK 0x%d\n",eint_num,mt_eint_get_mask(eint_num));
1567 free_irq(EINT_IRQ(eint_num),NULL);
1568}
1569
1570void mt_eint_normal_test_based_on_hw_debounce(void)
1571{
1572 int ret=0;
1573 unsigned int debounce_time=16;
1574 unsigned long long delay_start;
1575 printk("%s for EINT %d\n", __func__, eint_debounce[EINT_IN]);
1576 gpio_set_debounce(EINT_GPIO(eint_debounce[EINT_IN]), debounce_time);
1577
1578 /* GPIO setting */
1579 mt_set_gpio_mode(gpio_debounce[EINT_OUT], GPIO_MODE_00);
1580 mt_set_gpio_dir(gpio_debounce[EINT_OUT], GPIO_DIR_OUT);
1581 mt_set_gpio_pull_enable(gpio_debounce[EINT_OUT], 1);
1582 mt_set_gpio_out(gpio_debounce[EINT_OUT], 0);
1583 mt_set_gpio_mode(gpio_debounce[EINT_IN], GPIO_MODE_04);
1584 mt_set_gpio_dir(gpio_debounce[EINT_IN], GPIO_DIR_IN);
1585
1586 printk("before request_irq for EINT %d\n", eint_debounce[EINT_IN]);
1587 EINT_waiting=1;
1588 ret=request_irq(EINT_IRQ(eint_debounce[EINT_IN]), (irq_handler_t)mt_eint_hw_debounce_isr,IRQF_TRIGGER_HIGH ,"EINT-HWDEBOUNCE",NULL);
1589 if(ret>0)
1590 printk(KERN_ERR "EINT IRQ LINE NOT AVAILABLE!!\n");
1591 printk("EINT %d request_irq done\n",eint_debounce[EINT_IN]);
1592 mt_set_gpio_out(gpio_debounce[EINT_OUT], 1);
1593 printk("trigger EINT %d done\n",eint_debounce[EINT_IN]);
1594 hw_debounce_start=delay_start=sched_clock();
1595 printk("waiting for EINT %d\n", eint_debounce[EINT_IN]);
1596
1597 while(EINT_waiting)
1598 {
1599 delay_start=sched_clock();
1600 if(!EINT_waiting)
1601 break;
1602 }
1603 printk("hw_debounce time t1=%llu ,t2=%llu, %llu ns\n",hw_debounce_start,hw_debounce_end,(hw_debounce_end-hw_debounce_start));
1604 printk("duration time t1=%llu ,t2=%llu, %llu ns\n",hw_debounce_start,delay_start,(delay_start-hw_debounce_start));
1605
1606 // divide by 1m => ns to ms
1607 if(!EINT_waiting && (hw_debounce_start - hw_debounce_end) / 1000000 > debounce_time){
1608 printk("...pass\n");
1609 }
1610 else{
1611 printk("...failed\n");
1612 }
1613 printk("EINT %d, MASK 0x%d\n",eint_debounce[EINT_IN],mt_eint_get_mask(eint_debounce[EINT_IN]));
1614 free_irq(EINT_IRQ(eint_debounce[EINT_IN]),NULL);
1615}
1616
1617//static ssize_t test_show(struct device* dev, struct device_attribute* attr, char* buf)
1618static ssize_t test_show(struct device_driver *driver, char *buf)
1619{
1620 return snprintf(buf, PAGE_SIZE, "==EINT test==\n"
1621 "1.EINT original registration test\n"
1622 "2.EINT new design test\n"
1623 "3.EINT new design hw debounce test\n"
1624 "4.EINT new design sw debounce test\n"
1625 "5.EINT new design without auto-unmask\n"
1626 );
1627}
1628
1629//static ssize_t test_store(struct device* dev, struct device_attribute* attr, const char* buf, size_t count)
1630static ssize_t test_store(struct device_driver *driver, const char *buf,size_t count)
1631{
1632 char *p = (char *)buf;
1633 unsigned int num;
1634
1635 num = simple_strtoul(p, &p, 10);
1636 switch(num){
1637 case 1:
1638 mt_eint_test();
1639 break;
1640 case 2:
1641 mt_eint_autounmask_test();
1642 break;
1643 case 3:
1644 mt_eint_normal_test_based_on_hw_debounce();
1645 break;
1646 case 4:
1647 mt_eint_normal_test_based_on_sw_debounce();
1648 break;
1649 case 5:
1650 mt_eint_non_autounmask_test();
1651 break;
1652 default:
1653 break;
1654 }
1655
1656 return count;
1657}
1658
1659DRIVER_ATTR(eint_test_suit, 0644, test_show, test_store);
1660
1661//DEVICE_ATTR(eint_config, 0666, test_show, test_store);
1662
1663//static struct miscdevice mt_eint_dev = {
1664// .minor = MISC_DYNAMIC_MINOR,
1665// .name = "mt_eint",
1666// //.fops = &dev_fops,
1667// .mode = S_IRUGO | S_IWUGO,
1668//};
1669#endif
1670
1671static void gpio_set_debounce(unsigned gpio, unsigned debounce)
1672{
1673 mt_eint_set_hw_debounce(gpio, debounce);
1674}
1675
1676/*
1677 * mt_eint_print_status: Print the EINT status register.
1678 */
1679void mt_eint_print_status(void)
1680{
1681 unsigned int status,index;
1682 unsigned int offset,reg_base,status_check;
1683 printk(KERN_DEBUG"EINT_STA:");
1684 for (reg_base = 0; reg_base < EINT_MAX_CHANNEL; reg_base+=32) {
1685 /* read status register every 32 interrupts */
1686 status = mt_eint_get_status(reg_base);
1687 if(status){
1688 //dbgmsg(KERN_DEBUG"EINT Module - index:%d,EINT_STA = 0x%x\n",
1689 // reg_base, status);
1690 }
1691 else{
1692 continue;
1693 }
1694 for(offset = 0; offset < 32; offset++){
1695 index = reg_base + offset;
1696 if (index >= EINT_MAX_CHANNEL) break;
1697
1698 status_check = status & (1 << offset);
1699 if (status_check)
1700 printk(KERN_DEBUG"EINT %d is pending\n",index);
1701 }
1702 }
1703 printk(KERN_DEBUG"\n");
1704}
1705
1706extern struct irq_chip mt_irq_eint;
1707
1708int get_supported_irq_num(void)
1709{
1710 struct device_node *node;
1711 void __iomem *dist_base;
1712 int ret = 0;
1713
1714 node = of_find_compatible_node(NULL, NULL, "mtk,mt-gic");
1715 if(!node) {
1716 printk("%s can't find node for gic\n", __func__);
1717 return ret;
1718 }
1719
1720 dist_base = of_iomap(node, 0);
1721 #define GIC_DIST_CTR 0x4
1722 ret = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
1723 ret = (ret + 1) * 32;
1724 printk("gic supported max = %d\n", ret);
1725 return ret;
1726}
1727
1728int mt_gpio_set_debounce(unsigned gpio, unsigned debounce)
1729{
1730 if (gpio >= EINT_MAX_CHANNEL)
1731 return -EINVAL;
1732
1733 debounce /= 1000;
1734 mt_eint_set_hw_debounce(gpio,debounce);
1735
1736 return 0;
1737}
1738
1739#define GPIO_MAX 999
1740static struct rb_root root = RB_ROOT;
1741struct pin_node *pins;
1742
1743static struct pin_node* pin_search(u32 gpio)
1744{
1745 struct rb_node *node = root.rb_node;
1746 struct pin_node *pin = NULL;
1747
1748 while(node) {
1749 pin = rb_entry(node, struct pin_node, node);
1750 if(gpio < pin->gpio_pin)
1751 node = node->rb_left;
1752 else if(gpio > pin->gpio_pin)
1753 node = node->rb_right;
1754 else
1755 return pin;
1756 }
1757
1758 return NULL;
1759}
1760
1761static int pin_insert(struct pin_node *pin)
1762{
1763 struct rb_node **new = &(root.rb_node), *parent = NULL;
1764 struct pin_node *node;
1765
1766 while(*new) {
1767 parent = *new;
1768 node = rb_entry(parent, struct pin_node, node);
1769
1770 if(pin->gpio_pin < node->gpio_pin)
1771 new = &(*new)->rb_left;
1772 else if(pin->gpio_pin > node->gpio_pin)
1773 new = &(*new)->rb_right;
1774 else
1775 return 0;
1776 }
1777
1778 rb_link_node(&pin->node, parent, new);
1779 rb_insert_color(&pin->node, &root);
1780 return 1;
1781}
1782
1783static void pin_init(void)
1784{
1785 u32 i;
1786 for(i = 0; i < EINT_MAX_CHANNEL; i++) {
1787 if(pins[i].gpio_pin == GPIO_MAX)
1788 break;
1789 if(!pin_insert(&pins[i])) {
1790 printk("duplicate record? i = %d, gpio = %d, eint = %d\n", i, pins[i].gpio_pin, pins[i].eint_pin);
1791 }
1792 }
1793}
1794
1795static void pin_traverse(void)
1796{
1797 struct pin_node *p;
1798 struct rb_node *r;
1799
1800 for(r = rb_first(&root); r; r = rb_next(r)) {
1801 p = rb_entry(r, struct pin_node, node);
1802 printk("gpio = %d, eint = %d\n", p->gpio_pin, p->eint_pin);
1803 }
1804}
1805
1806unsigned int mt_gpio_to_irq(unsigned int gpio)
1807{
1808 struct pin_node *p;
1809
1810 if (mapping_table_entry > 0) {
1811 p = pin_search(gpio);
1812 if(p == NULL)
1813 return -EINVAL;
1814 else
1815 return p->eint_pin + EINT_IRQ_BASE;
1816 }
1817 else {
1818 return gpio + EINT_IRQ_BASE;
1819 }
1820}
1821
1822/*
1823 * mt_eint_init: initialize EINT driver.
1824 * Always return 0.
1825 */
1826extern int nr_irqs;
1827
1828static void mt_eint_irq_mask(struct irq_data *data)
1829{
1830 mt_eint_mask(data->hwirq);
1831}
1832
1833static void mt_eint_irq_unmask(struct irq_data *data)
1834{
1835 mt_eint_unmask(data->hwirq);
1836}
1837
1838static void mt_eint_irq_ack(struct irq_data *data)
1839{
1840 mt_eint_ack(data->hwirq);
1841}
1842
1843static int mt_eint_irq_set_type(struct irq_data *data, unsigned int type)
1844{
1845 int eint_num = data->hwirq;
1846
1847 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
1848 mt_eint_set_polarity(eint_num, MT_EINT_POL_NEG);
1849 else
1850 mt_eint_set_polarity(eint_num, MT_EINT_POL_POS);
1851 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1852 mt_eint_set_sens(eint_num, MT_EDGE_SENSITIVE);
1853 else
1854 mt_eint_set_sens(eint_num, MT_LEVEL_SENSITIVE);
1855
1856 return IRQ_SET_MASK_OK;
1857}
1858
1859struct irq_chip mt_irq_eint = {
1860 .name = "mt-eint",
1861 .irq_mask = mt_eint_irq_mask,
1862 .irq_unmask = mt_eint_irq_unmask,
1863 .irq_ack = mt_eint_irq_ack,
1864 .irq_set_type = mt_eint_irq_set_type,
1865};
1866
1867int mt_eint_domain_xlate_onetwocell(struct irq_domain *d,
1868 struct device_node *ctrlr,
1869 const u32 *intspec, unsigned int intsize,
1870 unsigned long *out_hwirq, unsigned int *out_type)
1871{
1872 if (WARN_ON(intsize < 1))
1873 return -EINVAL;
1874 *out_hwirq = mt_gpio_to_irq(intspec[0]) - EINT_IRQ_BASE;
1875 *out_type = (intsize > 1) ? intspec[1] : IRQ_TYPE_NONE;
1876 return 0;
1877}
1878
1879const struct irq_domain_ops mt_eint_domain_simple_ops = {
1880 .xlate = mt_eint_domain_xlate_onetwocell,
1881};
1882
1883static int __init mt_eint_init(void)
1884{
1885 unsigned int i, irq;
1886 int irq_base;
1887 struct irq_domain *domain;
1888 struct device_node *node;
1889#if defined(EINT_TEST_V2)
1890 struct pin_node* p;
1891#endif
1892 const __be32 *spec;
1893 u32 len;
1894
1895#if defined(EINT_TEST_V2)
1896 int ret;
1897#endif
1898
1899 /* DTS version */
1900 node = of_find_compatible_node(NULL, NULL, "mtk,mt-eic");
1901 if(node) {
1902 EINT_BASE = of_iomap(node, 0);
1903 printk("get EINT_BASE @ %p\n", EINT_BASE);
1904 }
1905 else {
1906 printk("can't find compatible node\n");
1907 return -1;
1908 }
1909
1910 irq = irq_of_parse_and_map(node, 0);
1911 if(irq <= 0) {
1912 printk("irq # for eint %d\n", irq);
1913 return -1;
1914 }
1915
1916 if (of_property_read_u32(node, "max_eint_num", &EINT_MAX_CHANNEL)) {
1917 return -1;
1918 }
1919 else {
1920 pr_debug("[EIC] max_eint_num = %d\n", EINT_MAX_CHANNEL);
1921
1922 EINT_FUNC.eint_func = (eint_funct *) kmalloc(sizeof(eint_funct)*EINT_MAX_CHANNEL, GFP_KERNEL);
1923 EINT_FUNC.eint_auto_umask = (unsigned int *) kmalloc(sizeof(unsigned int)*EINT_MAX_CHANNEL, GFP_KERNEL);
1924 EINT_FUNC.is_deb_en = (unsigned int *) kmalloc(sizeof(unsigned int)*EINT_MAX_CHANNEL, GFP_KERNEL);
1925 EINT_FUNC.deb_time = (unsigned int *) kmalloc(sizeof(unsigned int)*EINT_MAX_CHANNEL, GFP_KERNEL);
1926 EINT_FUNC.eint_sw_deb_timer = (struct timer_list *) kmalloc(sizeof(struct timer_list)*EINT_MAX_CHANNEL, GFP_KERNEL);
1927 EINT_FUNC.count = (unsigned int *) kmalloc(sizeof(unsigned int)*EINT_MAX_CHANNEL, GFP_KERNEL);
1928
1929 if (of_property_read_u32(node, "mapping_table_entry", &mapping_table_entry)) {
1930 return -1;
1931 }
1932 else {
1933 pr_debug("[EIC] mapping_table_entry = %d\n", mapping_table_entry);
1934
1935 if (mapping_table_entry > 0){
1936 spec = of_get_property(node, "mapping_table", &len);
1937 if (spec == NULL)
1938 return -EINVAL;
1939 len /= sizeof(*spec);
1940
1941 pr_debug("[EIC] mapping_table: spec=%d len=%d\n", be32_to_cpup(spec), len);
1942
1943 pins = (struct pin_node *) kmalloc(sizeof(struct pin_node)*(mapping_table_entry+1), GFP_KERNEL);
1944 for (i = 0; i < mapping_table_entry; i++) {
1945 pr_debug("[EIC] index=%d: gpio_pin=%d, eint_pin=%d\n", i, be32_to_cpup(spec+(i<<1)), be32_to_cpup(spec+(i<<1)+1));
1946 pins[i].gpio_pin = be32_to_cpup(spec+(i<<1));
1947 pins[i].eint_pin = be32_to_cpup(spec+(i<<1)+1);
1948 }
1949 pins[i].gpio_pin = GPIO_MAX;
1950 }
1951 }
1952 }
1953
1954 /* assign to domain 0 for AP */
1955 mt_eint_setdomain0();
1956
1957 wake_lock_init(&EINT_suspend_lock, WAKE_LOCK_SUSPEND, "EINT wakelock");
1958
1959 setup_MD_eint();
1960 for (i = 0; i < EINT_MAX_CHANNEL; i++) {
1961 EINT_FUNC.eint_func[i] = NULL;
1962 EINT_FUNC.is_deb_en[i] = 0;
1963 EINT_FUNC.deb_time[i] = 0;
1964 EINT_FUNC.eint_sw_deb_timer[i].expires = 0;
1965 EINT_FUNC.eint_sw_deb_timer[i].data = 0;
1966 EINT_FUNC.eint_sw_deb_timer[i].function = NULL;
1967 }
1968
1969 /* gpio to eint structure init */
1970 if (mapping_table_entry > 0) {
1971 pin_init();
1972
1973#if defined(EINT_TEST_V2)
1974 pin_traverse();
1975 p = pin_search(31);
1976 if(p)
1977 printk("gpio 31 = eint %d\n", p->eint_pin);
1978
1979 p = pin_search(37);
1980 if(p)
1981 printk("gpio 37 = eint %d\n", p->eint_pin);
1982
1983 p = pin_search(GPIO_MAX);
1984 if(p)
1985 printk("gpio GPIO_MAX = eint %d\n", p->eint_pin);
1986 else
1987 printk("can't find for GPIO %d\n", GPIO_MAX);
1988#endif
1989 }
1990
1991 /* Register Linux IRQ interface */
1992 EINT_IRQ_BASE = get_supported_irq_num();
1993 if(!EINT_IRQ_BASE) {
1994 printk("get_supported_irq_num returns %d\n", EINT_IRQ_BASE);
1995 return -1;
1996 }
1997 printk("EINT_IRQ_BASE = %d, nr_irq = %d\n", EINT_IRQ_BASE, nr_irqs);
1998 printk("gpio 63 = %d\n", mt_gpio_to_irq(63));
1999 irq_base = irq_alloc_descs(EINT_IRQ_BASE, EINT_IRQ_BASE, EINT_MAX_CHANNEL, numa_node_id());
2000 if (irq_base != EINT_IRQ_BASE) {
2001 printk(KERN_ERR "EINT alloc desc error %d\n", irq_base);
2002 return -1;
2003 }
2004
2005 for (i = 0 ; i < EINT_MAX_CHANNEL; i++) {
2006 irq_set_chip_and_handler(i + EINT_IRQ_BASE, &mt_irq_eint,
2007 handle_level_irq);
2008 set_irq_flags(i + EINT_IRQ_BASE, IRQF_VALID);
2009 }
2010
2011 domain = irq_domain_add_legacy(node, EINT_MAX_CHANNEL, EINT_IRQ_BASE, 0,
2012 &mt_eint_domain_simple_ops, NULL);
2013 if (!domain)
2014 printk(KERN_ERR "EINT domain add error\n");
2015
2016 irq_set_chained_handler(irq, (irq_flow_handler_t)mt_eint_demux);
2017
2018#if defined(EINT_TEST_V2)
2019 //int ret;
2020 //ret = misc_register(&mt_eint_dev);
2021
2022 //if(ret < 0) {
2023 // printk("EINT MISC Register fail, ret = %d\n", ret);
2024 // return ret;
2025 //}
2026
2027 //device_create_file(mt_eint_dev.this_device, &dev_attr_eint_config);
2028
2029 //int ret;
2030 ret = platform_driver_register(&eint_driver);
2031 if (ret) {
2032 pr_err("Fail to register eint_driver");
2033 }
2034 ret |= driver_create_file(&eint_driver.driver, &driver_attr_eint_test_suit);
2035 if (ret) {
2036 pr_err("Fail to create eint_driver sysfs files");
2037 }
2038
2039 node = of_find_compatible_node(NULL, NULL, "mediatek, ACCDET-eint");
2040 if(node) {
2041 i = irq_of_parse_and_map(node, 0);
2042 printk("virq for ACCDET = %d\n", i);
2043 }
2044 else {
2045 printk("can't find compatible node for ACCDET\n");
2046 }
2047
2048 node = of_find_compatible_node(NULL, NULL, "mediatek, TOUCH_PANEL-eint");
2049 if(node) {
2050 i = irq_of_parse_and_map(node, 0);
2051 printk("virq for TOUCH = %d\n", i);
2052 }
2053 else {
2054 printk("can't find compatible node for TOUCH\n");
2055 }
2056#endif
2057
2058 return 0;
2059}
2060#if 0
2061void mt_eint_dump_status(unsigned int eint)
2062{
2063 if (eint >= EINT_MAX_CHANNEL)
2064 return;
2065 printk("[EINT] eint:%d,mask:%x,pol:%x,deb:%x,sens:%x\n",eint,mt_eint_get_mask(eint),mt_eint_get_polarity(eint),mt_eint_get_debounce_cnt(eint),mt_eint_get_sens(eint));
2066}
2067#endif
2068
2069arch_initcall(mt_eint_init);
2070
2071EXPORT_SYMBOL(mt_eint_dis_debounce);
2072EXPORT_SYMBOL(mt_eint_registration);
2073EXPORT_SYMBOL(mt_eint_set_hw_debounce);
2074EXPORT_SYMBOL(mt_eint_set_polarity);
2075EXPORT_SYMBOL(mt_eint_set_sens);
2076EXPORT_SYMBOL(mt_eint_mask);
2077EXPORT_SYMBOL(mt_eint_unmask);
2078EXPORT_SYMBOL(mt_eint_print_status);
2079EXPORT_SYMBOL(mt_gpio_set_debounce);
2080EXPORT_SYMBOL(mt_gpio_to_irq);
kernel source for telekom puls (alcatel/mediatek)