Merge tag 'v3.10.65' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / irqchip / irq-gic.c
CommitLineData
f27ecacc
RK
1/*
2 * linux/arch/arm/common/gic.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Interrupt architecture for the GIC:
11 *
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
14 *
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
b3a1bde4
CM
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
f27ecacc
RK
20 *
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
24 */
25#include <linux/init.h>
26#include <linux/kernel.h>
f37a53cc 27#include <linux/err.h>
7e1efcf5 28#include <linux/module.h>
f27ecacc
RK
29#include <linux/list.h>
30#include <linux/smp.h>
c0114709 31#include <linux/cpu.h>
254056f3 32#include <linux/cpu_pm.h>
dcb86e8c 33#include <linux/cpumask.h>
fced80c7 34#include <linux/io.h>
b3f7ed03
RH
35#include <linux/of.h>
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
4294f8ba 38#include <linux/irqdomain.h>
292b293c
MZ
39#include <linux/interrupt.h>
40#include <linux/percpu.h>
41#include <linux/slab.h>
de88cbb7 42#include <linux/irqchip/chained_irq.h>
520f7bd7 43#include <linux/irqchip/arm-gic.h>
f27ecacc 44
4003b69e 45#include <asm/cputype.h>
f27ecacc 46#include <asm/irq.h>
562e0027 47#include <asm/exception.h>
eb50439b 48#include <asm/smp_plat.h>
f27ecacc 49
81243e44 50#include "irqchip.h"
f27ecacc 51
db0d4db2
MZ
52union gic_base {
53 void __iomem *common_base;
54 void __percpu __iomem **percpu_base;
55};
56
57struct gic_chip_data {
db0d4db2
MZ
58 union gic_base dist_base;
59 union gic_base cpu_base;
60#ifdef CONFIG_CPU_PM
61 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
62 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
63 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
64 u32 __percpu *saved_ppi_enable;
65 u32 __percpu *saved_ppi_conf;
66#endif
75294957 67 struct irq_domain *domain;
db0d4db2
MZ
68 unsigned int gic_irqs;
69#ifdef CONFIG_GIC_NON_BANKED
70 void __iomem *(*get_base)(union gic_base *);
71#endif
72};
73
bd31b859 74static DEFINE_RAW_SPINLOCK(irq_controller_lock);
f27ecacc 75
384a2902
NP
76/*
77 * The GIC mapping of CPU interfaces does not necessarily match
78 * the logical CPU numbering. Let's use a mapping as returned
79 * by the GIC itself.
80 */
81#define NR_GIC_CPU_IF 8
82static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
83
d7ed36a4
SS
84/*
85 * Supported arch specific GIC irq extension.
86 * Default make them NULL.
87 */
88struct irq_chip gic_arch_extn = {
1a01753e 89 .irq_eoi = NULL,
d7ed36a4
SS
90 .irq_mask = NULL,
91 .irq_unmask = NULL,
92 .irq_retrigger = NULL,
93 .irq_set_type = NULL,
94 .irq_set_wake = NULL,
95};
96
b3a1bde4
CM
97#ifndef MAX_GIC_NR
98#define MAX_GIC_NR 1
99#endif
100
bef8f9ee 101static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
b3a1bde4 102
db0d4db2
MZ
103#ifdef CONFIG_GIC_NON_BANKED
104static void __iomem *gic_get_percpu_base(union gic_base *base)
105{
106 return *__this_cpu_ptr(base->percpu_base);
107}
108
109static void __iomem *gic_get_common_base(union gic_base *base)
110{
111 return base->common_base;
112}
113
114static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
115{
116 return data->get_base(&data->dist_base);
117}
118
119static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
120{
121 return data->get_base(&data->cpu_base);
122}
123
124static inline void gic_set_base_accessor(struct gic_chip_data *data,
125 void __iomem *(*f)(union gic_base *))
126{
127 data->get_base = f;
128}
129#else
130#define gic_data_dist_base(d) ((d)->dist_base.common_base)
131#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
46f101df 132#define gic_set_base_accessor(d, f)
db0d4db2
MZ
133#endif
134
7d1f4288 135static inline void __iomem *gic_dist_base(struct irq_data *d)
b3a1bde4 136{
7d1f4288 137 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
db0d4db2 138 return gic_data_dist_base(gic_data);
b3a1bde4
CM
139}
140
7d1f4288 141static inline void __iomem *gic_cpu_base(struct irq_data *d)
b3a1bde4 142{
7d1f4288 143 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
db0d4db2 144 return gic_data_cpu_base(gic_data);
b3a1bde4
CM
145}
146
7d1f4288 147static inline unsigned int gic_irq(struct irq_data *d)
b3a1bde4 148{
4294f8ba 149 return d->hwirq;
b3a1bde4
CM
150}
151
f27ecacc
RK
152/*
153 * Routines to acknowledge, disable and enable interrupts
f27ecacc 154 */
7d1f4288 155static void gic_mask_irq(struct irq_data *d)
f27ecacc 156{
4294f8ba 157 u32 mask = 1 << (gic_irq(d) % 32);
c4bfa28a 158
bd31b859 159 raw_spin_lock(&irq_controller_lock);
6ac77e46 160 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
d7ed36a4
SS
161 if (gic_arch_extn.irq_mask)
162 gic_arch_extn.irq_mask(d);
bd31b859 163 raw_spin_unlock(&irq_controller_lock);
f27ecacc
RK
164}
165
7d1f4288 166static void gic_unmask_irq(struct irq_data *d)
f27ecacc 167{
4294f8ba 168 u32 mask = 1 << (gic_irq(d) % 32);
c4bfa28a 169
bd31b859 170 raw_spin_lock(&irq_controller_lock);
d7ed36a4
SS
171 if (gic_arch_extn.irq_unmask)
172 gic_arch_extn.irq_unmask(d);
6ac77e46 173 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
bd31b859 174 raw_spin_unlock(&irq_controller_lock);
f27ecacc
RK
175}
176
1a01753e
WD
177static void gic_eoi_irq(struct irq_data *d)
178{
179 if (gic_arch_extn.irq_eoi) {
bd31b859 180 raw_spin_lock(&irq_controller_lock);
1a01753e 181 gic_arch_extn.irq_eoi(d);
bd31b859 182 raw_spin_unlock(&irq_controller_lock);
1a01753e
WD
183 }
184
6ac77e46 185 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
1a01753e
WD
186}
187
7d1f4288 188static int gic_set_type(struct irq_data *d, unsigned int type)
5c0c1f08 189{
7d1f4288
LB
190 void __iomem *base = gic_dist_base(d);
191 unsigned int gicirq = gic_irq(d);
5c0c1f08
RV
192 u32 enablemask = 1 << (gicirq % 32);
193 u32 enableoff = (gicirq / 32) * 4;
194 u32 confmask = 0x2 << ((gicirq % 16) * 2);
195 u32 confoff = (gicirq / 16) * 4;
196 bool enabled = false;
197 u32 val;
198
199 /* Interrupt configuration for SGIs can't be changed */
200 if (gicirq < 16)
201 return -EINVAL;
202
203 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
204 return -EINVAL;
205
bd31b859 206 raw_spin_lock(&irq_controller_lock);
5c0c1f08 207
d7ed36a4
SS
208 if (gic_arch_extn.irq_set_type)
209 gic_arch_extn.irq_set_type(d, type);
210
6ac77e46 211 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
5c0c1f08
RV
212 if (type == IRQ_TYPE_LEVEL_HIGH)
213 val &= ~confmask;
214 else if (type == IRQ_TYPE_EDGE_RISING)
215 val |= confmask;
216
217 /*
218 * As recommended by the spec, disable the interrupt before changing
219 * the configuration
220 */
6ac77e46
SS
221 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
222 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
5c0c1f08
RV
223 enabled = true;
224 }
225
6ac77e46 226 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
5c0c1f08
RV
227
228 if (enabled)
6ac77e46 229 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
5c0c1f08 230
6fa3eb70 231
bd31b859 232 raw_spin_unlock(&irq_controller_lock);
5c0c1f08
RV
233
234 return 0;
235}
236
d7ed36a4
SS
237static int gic_retrigger(struct irq_data *d)
238{
239 if (gic_arch_extn.irq_retrigger)
240 return gic_arch_extn.irq_retrigger(d);
241
bad9a43a
AD
242 /* the genirq layer expects 0 if we can't retrigger in hardware */
243 return 0;
d7ed36a4
SS
244}
245
a06f5466 246#ifdef CONFIG_SMP
c191789c
RK
247static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
248 bool force)
f27ecacc 249{
7d1f4288 250 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
2e020bb0 251 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
c191789c 252 u32 val, mask, bit;
f27ecacc 253
2e020bb0
TG
254 if (!force)
255 cpu = cpumask_any_and(mask_val, cpu_online_mask);
256 else
257 cpu = cpumask_first(mask_val);
258
384a2902 259 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
87507500 260 return -EINVAL;
c191789c
RK
261
262 mask = 0xff << shift;
384a2902 263 bit = gic_cpu_map[cpu] << shift;
c191789c 264
bd31b859 265 raw_spin_lock(&irq_controller_lock);
6ac77e46
SS
266 val = readl_relaxed(reg) & ~mask;
267 writel_relaxed(val | bit, reg);
bd31b859 268 raw_spin_unlock(&irq_controller_lock);
d5dedd45 269
5dfc54e0 270 return IRQ_SET_MASK_OK;
f27ecacc 271}
a06f5466 272#endif
f27ecacc 273
d7ed36a4
SS
274#ifdef CONFIG_PM
275static int gic_set_wake(struct irq_data *d, unsigned int on)
276{
277 int ret = -ENXIO;
278
279 if (gic_arch_extn.irq_set_wake)
280 ret = gic_arch_extn.irq_set_wake(d, on);
281
282 return ret;
283}
284
285#else
286#define gic_set_wake NULL
287#endif
288
1d5cc604 289static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
562e0027
MZ
290{
291 u32 irqstat, irqnr;
292 struct gic_chip_data *gic = &gic_data[0];
293 void __iomem *cpu_base = gic_data_cpu_base(gic);
294
295 do {
296 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
297 irqnr = irqstat & ~0x1c00;
298
299 if (likely(irqnr > 15 && irqnr < 1021)) {
75294957 300 irqnr = irq_find_mapping(gic->domain, irqnr);
562e0027
MZ
301 handle_IRQ(irqnr, regs);
302 continue;
303 }
304 if (irqnr < 16) {
305 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
306#ifdef CONFIG_SMP
307 handle_IPI(irqnr, regs);
308#endif
309 continue;
310 }
311 break;
312 } while (1);
313}
314
0f347bb9 315static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
b3a1bde4 316{
6845664a
TG
317 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
318 struct irq_chip *chip = irq_get_chip(irq);
0f347bb9 319 unsigned int cascade_irq, gic_irq;
b3a1bde4
CM
320 unsigned long status;
321
1a01753e 322 chained_irq_enter(chip, desc);
b3a1bde4 323
bd31b859 324 raw_spin_lock(&irq_controller_lock);
db0d4db2 325 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
bd31b859 326 raw_spin_unlock(&irq_controller_lock);
b3a1bde4 327
0f347bb9
RK
328 gic_irq = (status & 0x3ff);
329 if (gic_irq == 1023)
b3a1bde4 330 goto out;
b3a1bde4 331
75294957
GL
332 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
333 if (unlikely(gic_irq < 32 || gic_irq > 1020))
aec00956 334 handle_bad_irq(cascade_irq, desc);
0f347bb9
RK
335 else
336 generic_handle_irq(cascade_irq);
b3a1bde4
CM
337
338 out:
1a01753e 339 chained_irq_exit(chip, desc);
b3a1bde4
CM
340}
341
38c677cb 342static struct irq_chip gic_chip = {
7d1f4288 343 .name = "GIC",
7d1f4288
LB
344 .irq_mask = gic_mask_irq,
345 .irq_unmask = gic_unmask_irq,
1a01753e 346 .irq_eoi = gic_eoi_irq,
7d1f4288 347 .irq_set_type = gic_set_type,
d7ed36a4 348 .irq_retrigger = gic_retrigger,
f27ecacc 349#ifdef CONFIG_SMP
c191789c 350 .irq_set_affinity = gic_set_affinity,
f27ecacc 351#endif
d7ed36a4 352 .irq_set_wake = gic_set_wake,
f27ecacc
RK
353};
354
b3a1bde4
CM
355void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
356{
357 if (gic_nr >= MAX_GIC_NR)
358 BUG();
6845664a 359 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
b3a1bde4 360 BUG();
6845664a 361 irq_set_chained_handler(irq, gic_handle_cascade_irq);
b3a1bde4
CM
362}
363
2bb31351
RK
364static u8 gic_get_cpumask(struct gic_chip_data *gic)
365{
366 void __iomem *base = gic_data_dist_base(gic);
367 u32 mask, i;
368
369 for (i = mask = 0; i < 32; i += 4) {
370 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
371 mask |= mask >> 16;
372 mask |= mask >> 8;
373 if (mask)
374 break;
375 }
376
377 if (!mask)
378 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
379
380 return mask;
381}
382
4294f8ba 383static void __init gic_dist_init(struct gic_chip_data *gic)
f27ecacc 384{
75294957 385 unsigned int i;
267840f3 386 u32 cpumask;
4294f8ba 387 unsigned int gic_irqs = gic->gic_irqs;
db0d4db2 388 void __iomem *base = gic_data_dist_base(gic);
f27ecacc 389
6ac77e46 390 writel_relaxed(0, base + GIC_DIST_CTRL);
f27ecacc 391
f27ecacc
RK
392 /*
393 * Set all global interrupts to be level triggered, active low.
394 */
e6afec9b 395 for (i = 32; i < gic_irqs; i += 16)
6ac77e46 396 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
f27ecacc
RK
397
398 /*
399 * Set all global interrupts to this CPU only.
400 */
6fa3eb70
S
401 //cpumask = gic_get_cpumask(gic);
402 /*FIXME*/
403 cpumask = 1 << smp_processor_id();
2bb31351
RK
404 cpumask |= cpumask << 8;
405 cpumask |= cpumask << 16;
e6afec9b 406 for (i = 32; i < gic_irqs; i += 4)
6ac77e46 407 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
f27ecacc
RK
408
409 /*
9395f6ea 410 * Set priority on all global interrupts.
f27ecacc 411 */
e6afec9b 412 for (i = 32; i < gic_irqs; i += 4)
6ac77e46 413 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
f27ecacc
RK
414
415 /*
9395f6ea
RK
416 * Disable all interrupts. Leave the PPI and SGIs alone
417 * as these enables are banked registers.
f27ecacc 418 */
e6afec9b 419 for (i = 32; i < gic_irqs; i += 32)
6ac77e46 420 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
f27ecacc 421
6ac77e46 422 writel_relaxed(1, base + GIC_DIST_CTRL);
f27ecacc
RK
423}
424
bef8f9ee 425static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
f27ecacc 426{
db0d4db2
MZ
427 void __iomem *dist_base = gic_data_dist_base(gic);
428 void __iomem *base = gic_data_cpu_base(gic);
384a2902 429 unsigned int cpu_mask, cpu = smp_processor_id();
9395f6ea
RK
430 int i;
431
384a2902
NP
432 /*
433 * Get what the GIC says our CPU mask is.
434 */
435 BUG_ON(cpu >= NR_GIC_CPU_IF);
6fa3eb70
S
436 //cpu_mask = gic_get_cpumask(gic);
437 //FIXME
438 cpu_mask = 1 << smp_processor_id();
384a2902
NP
439 gic_cpu_map[cpu] = cpu_mask;
440
441 /*
442 * Clear our mask from the other map entries in case they're
443 * still undefined.
444 */
445 for (i = 0; i < NR_GIC_CPU_IF; i++)
446 if (i != cpu)
447 gic_cpu_map[i] &= ~cpu_mask;
448
9395f6ea
RK
449 /*
450 * Deal with the banked PPI and SGI interrupts - disable all
451 * PPI interrupts, ensure all SGI interrupts are enabled.
452 */
6ac77e46
SS
453 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
454 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
9395f6ea
RK
455
456 /*
457 * Set priority on PPI and SGI interrupts
458 */
459 for (i = 0; i < 32; i += 4)
6ac77e46 460 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
9395f6ea 461
6ac77e46
SS
462 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
463 writel_relaxed(1, base + GIC_CPU_CTRL);
f27ecacc
RK
464}
465
254056f3
CC
466#ifdef CONFIG_CPU_PM
467/*
468 * Saves the GIC distributor registers during suspend or idle. Must be called
469 * with interrupts disabled but before powering down the GIC. After calling
470 * this function, no interrupts will be delivered by the GIC, and another
471 * platform-specific wakeup source must be enabled.
472 */
473static void gic_dist_save(unsigned int gic_nr)
474{
475 unsigned int gic_irqs;
476 void __iomem *dist_base;
477 int i;
478
479 if (gic_nr >= MAX_GIC_NR)
480 BUG();
481
482 gic_irqs = gic_data[gic_nr].gic_irqs;
db0d4db2 483 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
254056f3
CC
484
485 if (!dist_base)
486 return;
487
488 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
489 gic_data[gic_nr].saved_spi_conf[i] =
490 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
491
492 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
493 gic_data[gic_nr].saved_spi_target[i] =
494 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
495
496 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
497 gic_data[gic_nr].saved_spi_enable[i] =
498 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
499}
500
501/*
502 * Restores the GIC distributor registers during resume or when coming out of
503 * idle. Must be called before enabling interrupts. If a level interrupt
504 * that occured while the GIC was suspended is still present, it will be
505 * handled normally, but any edge interrupts that occured will not be seen by
506 * the GIC and need to be handled by the platform-specific wakeup source.
507 */
508static void gic_dist_restore(unsigned int gic_nr)
509{
510 unsigned int gic_irqs;
511 unsigned int i;
512 void __iomem *dist_base;
513
514 if (gic_nr >= MAX_GIC_NR)
515 BUG();
516
517 gic_irqs = gic_data[gic_nr].gic_irqs;
db0d4db2 518 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
254056f3
CC
519
520 if (!dist_base)
521 return;
522
523 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
524
525 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
526 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
527 dist_base + GIC_DIST_CONFIG + i * 4);
528
529 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
530 writel_relaxed(0xa0a0a0a0,
531 dist_base + GIC_DIST_PRI + i * 4);
532
533 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
534 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
535 dist_base + GIC_DIST_TARGET + i * 4);
536
537 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
538 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
539 dist_base + GIC_DIST_ENABLE_SET + i * 4);
540
541 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
542}
543
544static void gic_cpu_save(unsigned int gic_nr)
545{
546 int i;
547 u32 *ptr;
548 void __iomem *dist_base;
549 void __iomem *cpu_base;
550
551 if (gic_nr >= MAX_GIC_NR)
552 BUG();
553
db0d4db2
MZ
554 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
555 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
254056f3
CC
556
557 if (!dist_base || !cpu_base)
558 return;
559
560 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
561 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
562 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
563
564 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
565 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
566 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
567
568}
569
570static void gic_cpu_restore(unsigned int gic_nr)
571{
572 int i;
573 u32 *ptr;
574 void __iomem *dist_base;
575 void __iomem *cpu_base;
576
577 if (gic_nr >= MAX_GIC_NR)
578 BUG();
579
db0d4db2
MZ
580 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
581 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
254056f3
CC
582
583 if (!dist_base || !cpu_base)
584 return;
585
586 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
587 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
588 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
589
590 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
591 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
592 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
593
594 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
595 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
596
597 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
598 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
599}
600
601static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
602{
603 int i;
604
605 for (i = 0; i < MAX_GIC_NR; i++) {
db0d4db2
MZ
606#ifdef CONFIG_GIC_NON_BANKED
607 /* Skip over unused GICs */
608 if (!gic_data[i].get_base)
609 continue;
610#endif
254056f3
CC
611 switch (cmd) {
612 case CPU_PM_ENTER:
613 gic_cpu_save(i);
614 break;
615 case CPU_PM_ENTER_FAILED:
616 case CPU_PM_EXIT:
617 gic_cpu_restore(i);
618 break;
619 case CPU_CLUSTER_PM_ENTER:
620 gic_dist_save(i);
621 break;
622 case CPU_CLUSTER_PM_ENTER_FAILED:
623 case CPU_CLUSTER_PM_EXIT:
624 gic_dist_restore(i);
625 break;
626 }
627 }
628
629 return NOTIFY_OK;
630}
631
632static struct notifier_block gic_notifier_block = {
633 .notifier_call = gic_notifier,
634};
635
636static void __init gic_pm_init(struct gic_chip_data *gic)
637{
638 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
639 sizeof(u32));
640 BUG_ON(!gic->saved_ppi_enable);
641
642 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
643 sizeof(u32));
644 BUG_ON(!gic->saved_ppi_conf);
645
abdd7b91
MZ
646 if (gic == &gic_data[0])
647 cpu_pm_register_notifier(&gic_notifier_block);
254056f3
CC
648}
649#else
650static void __init gic_pm_init(struct gic_chip_data *gic)
651{
652}
653#endif
654
b1cffebf
RH
655#ifdef CONFIG_SMP
656void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
657{
658 int cpu;
659 unsigned long map = 0;
660
661 /* Convert our logical CPU mask into a physical one. */
662 for_each_cpu(cpu, mask)
91bdf0d0 663 map |= gic_cpu_map[cpu];
b1cffebf
RH
664
665 /*
666 * Ensure that stores to Normal memory are visible to the
667 * other CPUs before issuing the IPI.
668 */
669 dsb();
670
671 /* this always happens on GIC0 */
672 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
673}
674#endif
675
75294957
GL
676static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
677 irq_hw_number_t hw)
678{
679 if (hw < 32) {
680 irq_set_percpu_devid(irq);
681 irq_set_chip_and_handler(irq, &gic_chip,
682 handle_percpu_devid_irq);
683 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
684 } else {
685 irq_set_chip_and_handler(irq, &gic_chip,
686 handle_fasteoi_irq);
687 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
688 }
689 irq_set_chip_data(irq, d->host_data);
690 return 0;
691}
692
7bb69bad
GL
693static int gic_irq_domain_xlate(struct irq_domain *d,
694 struct device_node *controller,
695 const u32 *intspec, unsigned int intsize,
696 unsigned long *out_hwirq, unsigned int *out_type)
b3f7ed03
RH
697{
698 if (d->of_node != controller)
699 return -EINVAL;
700 if (intsize < 3)
701 return -EINVAL;
702
703 /* Get the interrupt number and add 16 to skip over SGIs */
704 *out_hwirq = intspec[1] + 16;
705
706 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
707 if (!intspec[0])
708 *out_hwirq += 16;
709
710 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
711 return 0;
712}
b3f7ed03 713
6fa3eb70
S
714void gic_register_sgi(unsigned int gic_nr, int irq)
715{
716 struct irq_desc *desc = irq_to_desc(irq);
717 if (desc)
718 desc->irq_data.hwirq = irq;
719 irq_set_chip_and_handler(irq, &gic_chip,
720 handle_fasteoi_irq);
721 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
722 irq_set_chip_data(irq, &gic_data[gic_nr]);
723}
724
c0114709
CM
725#ifdef CONFIG_SMP
726static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
727 unsigned long action, void *hcpu)
728{
8b6fd652 729 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
c0114709
CM
730 gic_cpu_init(&gic_data[0]);
731 return NOTIFY_OK;
732}
733
734/*
735 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
736 * priority because the GIC needs to be up before the ARM generic timers.
737 */
738static struct notifier_block __cpuinitdata gic_cpu_notifier = {
739 .notifier_call = gic_secondary_init,
740 .priority = 100,
741};
742#endif
743
15a25980 744const struct irq_domain_ops gic_irq_domain_ops = {
75294957 745 .map = gic_irq_domain_map,
7bb69bad 746 .xlate = gic_irq_domain_xlate,
4294f8ba
RH
747};
748
db0d4db2
MZ
749void __init gic_init_bases(unsigned int gic_nr, int irq_start,
750 void __iomem *dist_base, void __iomem *cpu_base,
75294957 751 u32 percpu_offset, struct device_node *node)
b580b899 752{
75294957 753 irq_hw_number_t hwirq_base;
bef8f9ee 754 struct gic_chip_data *gic;
384a2902 755 int gic_irqs, irq_base, i;
bef8f9ee
RK
756
757 BUG_ON(gic_nr >= MAX_GIC_NR);
758
759 gic = &gic_data[gic_nr];
db0d4db2
MZ
760#ifdef CONFIG_GIC_NON_BANKED
761 if (percpu_offset) { /* Frankein-GIC without banked registers... */
762 unsigned int cpu;
763
764 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
765 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
766 if (WARN_ON(!gic->dist_base.percpu_base ||
767 !gic->cpu_base.percpu_base)) {
768 free_percpu(gic->dist_base.percpu_base);
769 free_percpu(gic->cpu_base.percpu_base);
770 return;
771 }
772
773 for_each_possible_cpu(cpu) {
4003b69e
TF
774 u32 mpidr = cpu_logical_map(cpu);
775 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
776 unsigned long offset = percpu_offset * core_id;
db0d4db2
MZ
777 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
778 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
779 }
780
781 gic_set_base_accessor(gic, gic_get_percpu_base);
782 } else
783#endif
784 { /* Normal, sane GIC... */
785 WARN(percpu_offset,
786 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
787 percpu_offset);
788 gic->dist_base.common_base = dist_base;
789 gic->cpu_base.common_base = cpu_base;
790 gic_set_base_accessor(gic, gic_get_common_base);
791 }
bef8f9ee 792
384a2902
NP
793 /*
794 * Initialize the CPU interface map to all CPUs.
795 * It will be refined as each CPU probes its ID.
796 */
797 for (i = 0; i < NR_GIC_CPU_IF; i++)
798 gic_cpu_map[i] = 0xff;
799
4294f8ba
RH
800 /*
801 * For primary GICs, skip over SGIs.
802 * For secondary GICs, skip over PPIs, too.
803 */
e0b823e9 804 if (gic_nr == 0 && (irq_start & 31) > 0) {
12679a2d 805 hwirq_base = 16;
e0b823e9
WD
806 if (irq_start != -1)
807 irq_start = (irq_start & ~31) + 16;
808 } else {
12679a2d 809 hwirq_base = 32;
fe41db7b 810 }
4294f8ba
RH
811
812 /*
813 * Find out how many interrupts are supported.
814 * The GIC only supports up to 1020 interrupt sources.
815 */
db0d4db2 816 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
4294f8ba
RH
817 gic_irqs = (gic_irqs + 1) * 32;
818 if (gic_irqs > 1020)
819 gic_irqs = 1020;
820 gic->gic_irqs = gic_irqs;
821
75294957
GL
822 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
823 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
824 if (IS_ERR_VALUE(irq_base)) {
f37a53cc
RH
825 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
826 irq_start);
75294957 827 irq_base = irq_start;
f37a53cc 828 }
75294957
GL
829 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
830 hwirq_base, &gic_irq_domain_ops, gic);
831 if (WARN_ON(!gic->domain))
832 return;
bef8f9ee 833
b1cffebf
RH
834#ifdef CONFIG_SMP
835 set_smp_cross_call(gic_raise_softirq);
c0114709 836 register_cpu_notifier(&gic_cpu_notifier);
b1cffebf 837#endif
cfed7d60
RH
838
839 set_handle_irq(gic_handle_irq);
840
9c12845e 841 gic_chip.flags |= gic_arch_extn.flags;
4294f8ba 842 gic_dist_init(gic);
bef8f9ee 843 gic_cpu_init(gic);
254056f3 844 gic_pm_init(gic);
b580b899
RK
845}
846
b3f7ed03 847#ifdef CONFIG_OF
46f101df 848static int gic_cnt __initdata;
b3f7ed03
RH
849
850int __init gic_of_init(struct device_node *node, struct device_node *parent)
851{
852 void __iomem *cpu_base;
6fa3eb70 853 void __iomem *dist_base;
db0d4db2 854 u32 percpu_offset;
b3f7ed03 855 int irq;
b3f7ed03
RH
856
857 if (WARN_ON(!node))
858 return -ENODEV;
859
860 dist_base = of_iomap(node, 0);
861 WARN(!dist_base, "unable to map gic dist registers\n");
862
863 cpu_base = of_iomap(node, 1);
6fa3eb70 864 WARN(!cpu_base, "unable to map gic cpu registers\n");
b3f7ed03 865
db0d4db2
MZ
866 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
867 percpu_offset = 0;
868
75294957 869 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
b3f7ed03
RH
870
871 if (parent) {
872 irq = irq_of_parse_and_map(node, 0);
873 gic_cascade_irq(gic_cnt, irq);
874 }
875 gic_cnt++;
876 return 0;
877}
81243e44
RH
878IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
879IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
db9e4bf3 880IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
81243e44
RH
881IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
882IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
883
b3f7ed03 884#endif