Commit | Line | Data |
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f27ecacc RK |
1 | /* |
2 | * linux/arch/arm/common/gic.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Interrupt architecture for the GIC: | |
11 | * | |
12 | * o There is one Interrupt Distributor, which receives interrupts | |
13 | * from system devices and sends them to the Interrupt Controllers. | |
14 | * | |
15 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
16 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
17 | * associated CPU. The base address of the CPU interface is usually |
18 | * aliased so that the same address points to different chips depending | |
19 | * on the CPU it is accessed from. | |
f27ecacc RK |
20 | * |
21 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
22 | * As such, the enable set/clear, pending set/clear and active bit | |
23 | * registers are banked per-cpu for these sources. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
f37a53cc | 27 | #include <linux/err.h> |
7e1efcf5 | 28 | #include <linux/module.h> |
f27ecacc RK |
29 | #include <linux/list.h> |
30 | #include <linux/smp.h> | |
c0114709 | 31 | #include <linux/cpu.h> |
254056f3 | 32 | #include <linux/cpu_pm.h> |
dcb86e8c | 33 | #include <linux/cpumask.h> |
fced80c7 | 34 | #include <linux/io.h> |
b3f7ed03 RH |
35 | #include <linux/of.h> |
36 | #include <linux/of_address.h> | |
37 | #include <linux/of_irq.h> | |
4294f8ba | 38 | #include <linux/irqdomain.h> |
292b293c MZ |
39 | #include <linux/interrupt.h> |
40 | #include <linux/percpu.h> | |
41 | #include <linux/slab.h> | |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
4003b69e | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
f27ecacc | 49 | |
81243e44 | 50 | #include "irqchip.h" |
f27ecacc | 51 | |
db0d4db2 MZ |
52 | union gic_base { |
53 | void __iomem *common_base; | |
54 | void __percpu __iomem **percpu_base; | |
55 | }; | |
56 | ||
57 | struct gic_chip_data { | |
db0d4db2 MZ |
58 | union gic_base dist_base; |
59 | union gic_base cpu_base; | |
60 | #ifdef CONFIG_CPU_PM | |
61 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
62 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
63 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
64 | u32 __percpu *saved_ppi_enable; | |
65 | u32 __percpu *saved_ppi_conf; | |
66 | #endif | |
75294957 | 67 | struct irq_domain *domain; |
db0d4db2 MZ |
68 | unsigned int gic_irqs; |
69 | #ifdef CONFIG_GIC_NON_BANKED | |
70 | void __iomem *(*get_base)(union gic_base *); | |
71 | #endif | |
72 | }; | |
73 | ||
bd31b859 | 74 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 75 | |
384a2902 NP |
76 | /* |
77 | * The GIC mapping of CPU interfaces does not necessarily match | |
78 | * the logical CPU numbering. Let's use a mapping as returned | |
79 | * by the GIC itself. | |
80 | */ | |
81 | #define NR_GIC_CPU_IF 8 | |
82 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
83 | ||
d7ed36a4 SS |
84 | /* |
85 | * Supported arch specific GIC irq extension. | |
86 | * Default make them NULL. | |
87 | */ | |
88 | struct irq_chip gic_arch_extn = { | |
1a01753e | 89 | .irq_eoi = NULL, |
d7ed36a4 SS |
90 | .irq_mask = NULL, |
91 | .irq_unmask = NULL, | |
92 | .irq_retrigger = NULL, | |
93 | .irq_set_type = NULL, | |
94 | .irq_set_wake = NULL, | |
95 | }; | |
96 | ||
b3a1bde4 CM |
97 | #ifndef MAX_GIC_NR |
98 | #define MAX_GIC_NR 1 | |
99 | #endif | |
100 | ||
bef8f9ee | 101 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 102 | |
db0d4db2 MZ |
103 | #ifdef CONFIG_GIC_NON_BANKED |
104 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
105 | { | |
106 | return *__this_cpu_ptr(base->percpu_base); | |
107 | } | |
108 | ||
109 | static void __iomem *gic_get_common_base(union gic_base *base) | |
110 | { | |
111 | return base->common_base; | |
112 | } | |
113 | ||
114 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
115 | { | |
116 | return data->get_base(&data->dist_base); | |
117 | } | |
118 | ||
119 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
120 | { | |
121 | return data->get_base(&data->cpu_base); | |
122 | } | |
123 | ||
124 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
125 | void __iomem *(*f)(union gic_base *)) | |
126 | { | |
127 | data->get_base = f; | |
128 | } | |
129 | #else | |
130 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
131 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 132 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
133 | #endif |
134 | ||
7d1f4288 | 135 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 136 | { |
7d1f4288 | 137 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 138 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
139 | } |
140 | ||
7d1f4288 | 141 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 142 | { |
7d1f4288 | 143 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 144 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
145 | } |
146 | ||
7d1f4288 | 147 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 148 | { |
4294f8ba | 149 | return d->hwirq; |
b3a1bde4 CM |
150 | } |
151 | ||
f27ecacc RK |
152 | /* |
153 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 154 | */ |
7d1f4288 | 155 | static void gic_mask_irq(struct irq_data *d) |
f27ecacc | 156 | { |
4294f8ba | 157 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 158 | |
bd31b859 | 159 | raw_spin_lock(&irq_controller_lock); |
6ac77e46 | 160 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
d7ed36a4 SS |
161 | if (gic_arch_extn.irq_mask) |
162 | gic_arch_extn.irq_mask(d); | |
bd31b859 | 163 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
164 | } |
165 | ||
7d1f4288 | 166 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 167 | { |
4294f8ba | 168 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 169 | |
bd31b859 | 170 | raw_spin_lock(&irq_controller_lock); |
d7ed36a4 SS |
171 | if (gic_arch_extn.irq_unmask) |
172 | gic_arch_extn.irq_unmask(d); | |
6ac77e46 | 173 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
bd31b859 | 174 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
175 | } |
176 | ||
1a01753e WD |
177 | static void gic_eoi_irq(struct irq_data *d) |
178 | { | |
179 | if (gic_arch_extn.irq_eoi) { | |
bd31b859 | 180 | raw_spin_lock(&irq_controller_lock); |
1a01753e | 181 | gic_arch_extn.irq_eoi(d); |
bd31b859 | 182 | raw_spin_unlock(&irq_controller_lock); |
1a01753e WD |
183 | } |
184 | ||
6ac77e46 | 185 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
186 | } |
187 | ||
7d1f4288 | 188 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 189 | { |
7d1f4288 LB |
190 | void __iomem *base = gic_dist_base(d); |
191 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
192 | u32 enablemask = 1 << (gicirq % 32); |
193 | u32 enableoff = (gicirq / 32) * 4; | |
194 | u32 confmask = 0x2 << ((gicirq % 16) * 2); | |
195 | u32 confoff = (gicirq / 16) * 4; | |
196 | bool enabled = false; | |
197 | u32 val; | |
198 | ||
199 | /* Interrupt configuration for SGIs can't be changed */ | |
200 | if (gicirq < 16) | |
201 | return -EINVAL; | |
202 | ||
203 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
204 | return -EINVAL; | |
205 | ||
bd31b859 | 206 | raw_spin_lock(&irq_controller_lock); |
5c0c1f08 | 207 | |
d7ed36a4 SS |
208 | if (gic_arch_extn.irq_set_type) |
209 | gic_arch_extn.irq_set_type(d, type); | |
210 | ||
6ac77e46 | 211 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
212 | if (type == IRQ_TYPE_LEVEL_HIGH) |
213 | val &= ~confmask; | |
214 | else if (type == IRQ_TYPE_EDGE_RISING) | |
215 | val |= confmask; | |
216 | ||
217 | /* | |
218 | * As recommended by the spec, disable the interrupt before changing | |
219 | * the configuration | |
220 | */ | |
6ac77e46 SS |
221 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
222 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); | |
5c0c1f08 RV |
223 | enabled = true; |
224 | } | |
225 | ||
6ac77e46 | 226 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
227 | |
228 | if (enabled) | |
6ac77e46 | 229 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
5c0c1f08 | 230 | |
bd31b859 | 231 | raw_spin_unlock(&irq_controller_lock); |
5c0c1f08 RV |
232 | |
233 | return 0; | |
234 | } | |
235 | ||
d7ed36a4 SS |
236 | static int gic_retrigger(struct irq_data *d) |
237 | { | |
238 | if (gic_arch_extn.irq_retrigger) | |
239 | return gic_arch_extn.irq_retrigger(d); | |
240 | ||
bad9a43a AD |
241 | /* the genirq layer expects 0 if we can't retrigger in hardware */ |
242 | return 0; | |
d7ed36a4 SS |
243 | } |
244 | ||
a06f5466 | 245 | #ifdef CONFIG_SMP |
c191789c RK |
246 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
247 | bool force) | |
f27ecacc | 248 | { |
7d1f4288 | 249 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
2e020bb0 | 250 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 251 | u32 val, mask, bit; |
f27ecacc | 252 | |
2e020bb0 TG |
253 | if (!force) |
254 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
255 | else | |
256 | cpu = cpumask_first(mask_val); | |
257 | ||
384a2902 | 258 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 259 | return -EINVAL; |
c191789c RK |
260 | |
261 | mask = 0xff << shift; | |
384a2902 | 262 | bit = gic_cpu_map[cpu] << shift; |
c191789c | 263 | |
bd31b859 | 264 | raw_spin_lock(&irq_controller_lock); |
6ac77e46 SS |
265 | val = readl_relaxed(reg) & ~mask; |
266 | writel_relaxed(val | bit, reg); | |
bd31b859 | 267 | raw_spin_unlock(&irq_controller_lock); |
d5dedd45 | 268 | |
5dfc54e0 | 269 | return IRQ_SET_MASK_OK; |
f27ecacc | 270 | } |
a06f5466 | 271 | #endif |
f27ecacc | 272 | |
d7ed36a4 SS |
273 | #ifdef CONFIG_PM |
274 | static int gic_set_wake(struct irq_data *d, unsigned int on) | |
275 | { | |
276 | int ret = -ENXIO; | |
277 | ||
278 | if (gic_arch_extn.irq_set_wake) | |
279 | ret = gic_arch_extn.irq_set_wake(d, on); | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
284 | #else | |
285 | #define gic_set_wake NULL | |
286 | #endif | |
287 | ||
1d5cc604 | 288 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
289 | { |
290 | u32 irqstat, irqnr; | |
291 | struct gic_chip_data *gic = &gic_data[0]; | |
292 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
293 | ||
294 | do { | |
295 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
296 | irqnr = irqstat & ~0x1c00; | |
297 | ||
298 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
75294957 | 299 | irqnr = irq_find_mapping(gic->domain, irqnr); |
562e0027 MZ |
300 | handle_IRQ(irqnr, regs); |
301 | continue; | |
302 | } | |
303 | if (irqnr < 16) { | |
304 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
305 | #ifdef CONFIG_SMP | |
306 | handle_IPI(irqnr, regs); | |
307 | #endif | |
308 | continue; | |
309 | } | |
310 | break; | |
311 | } while (1); | |
312 | } | |
313 | ||
0f347bb9 | 314 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 | 315 | { |
6845664a TG |
316 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
317 | struct irq_chip *chip = irq_get_chip(irq); | |
0f347bb9 | 318 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
319 | unsigned long status; |
320 | ||
1a01753e | 321 | chained_irq_enter(chip, desc); |
b3a1bde4 | 322 | |
bd31b859 | 323 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 324 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 325 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 326 | |
0f347bb9 RK |
327 | gic_irq = (status & 0x3ff); |
328 | if (gic_irq == 1023) | |
b3a1bde4 | 329 | goto out; |
b3a1bde4 | 330 | |
75294957 GL |
331 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
332 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
aec00956 | 333 | handle_bad_irq(cascade_irq, desc); |
0f347bb9 RK |
334 | else |
335 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
336 | |
337 | out: | |
1a01753e | 338 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
339 | } |
340 | ||
38c677cb | 341 | static struct irq_chip gic_chip = { |
7d1f4288 | 342 | .name = "GIC", |
7d1f4288 LB |
343 | .irq_mask = gic_mask_irq, |
344 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 345 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 346 | .irq_set_type = gic_set_type, |
d7ed36a4 | 347 | .irq_retrigger = gic_retrigger, |
f27ecacc | 348 | #ifdef CONFIG_SMP |
c191789c | 349 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 350 | #endif |
d7ed36a4 | 351 | .irq_set_wake = gic_set_wake, |
f27ecacc RK |
352 | }; |
353 | ||
b3a1bde4 CM |
354 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
355 | { | |
356 | if (gic_nr >= MAX_GIC_NR) | |
357 | BUG(); | |
6845664a | 358 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
b3a1bde4 | 359 | BUG(); |
6845664a | 360 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
b3a1bde4 CM |
361 | } |
362 | ||
2bb31351 RK |
363 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
364 | { | |
365 | void __iomem *base = gic_data_dist_base(gic); | |
366 | u32 mask, i; | |
367 | ||
368 | for (i = mask = 0; i < 32; i += 4) { | |
369 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
370 | mask |= mask >> 16; | |
371 | mask |= mask >> 8; | |
372 | if (mask) | |
373 | break; | |
374 | } | |
375 | ||
376 | if (!mask) | |
377 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); | |
378 | ||
379 | return mask; | |
380 | } | |
381 | ||
4294f8ba | 382 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 383 | { |
75294957 | 384 | unsigned int i; |
267840f3 | 385 | u32 cpumask; |
4294f8ba | 386 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 387 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 388 | |
6ac77e46 | 389 | writel_relaxed(0, base + GIC_DIST_CTRL); |
f27ecacc | 390 | |
f27ecacc RK |
391 | /* |
392 | * Set all global interrupts to be level triggered, active low. | |
393 | */ | |
e6afec9b | 394 | for (i = 32; i < gic_irqs; i += 16) |
6ac77e46 | 395 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
f27ecacc RK |
396 | |
397 | /* | |
398 | * Set all global interrupts to this CPU only. | |
399 | */ | |
2bb31351 RK |
400 | cpumask = gic_get_cpumask(gic); |
401 | cpumask |= cpumask << 8; | |
402 | cpumask |= cpumask << 16; | |
e6afec9b | 403 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 404 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc RK |
405 | |
406 | /* | |
9395f6ea | 407 | * Set priority on all global interrupts. |
f27ecacc | 408 | */ |
e6afec9b | 409 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 410 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
f27ecacc RK |
411 | |
412 | /* | |
9395f6ea RK |
413 | * Disable all interrupts. Leave the PPI and SGIs alone |
414 | * as these enables are banked registers. | |
f27ecacc | 415 | */ |
e6afec9b | 416 | for (i = 32; i < gic_irqs; i += 32) |
6ac77e46 | 417 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
f27ecacc | 418 | |
6ac77e46 | 419 | writel_relaxed(1, base + GIC_DIST_CTRL); |
f27ecacc RK |
420 | } |
421 | ||
bef8f9ee | 422 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 423 | { |
db0d4db2 MZ |
424 | void __iomem *dist_base = gic_data_dist_base(gic); |
425 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 426 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
427 | int i; |
428 | ||
384a2902 NP |
429 | /* |
430 | * Get what the GIC says our CPU mask is. | |
431 | */ | |
432 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
2bb31351 | 433 | cpu_mask = gic_get_cpumask(gic); |
384a2902 NP |
434 | gic_cpu_map[cpu] = cpu_mask; |
435 | ||
436 | /* | |
437 | * Clear our mask from the other map entries in case they're | |
438 | * still undefined. | |
439 | */ | |
440 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
441 | if (i != cpu) | |
442 | gic_cpu_map[i] &= ~cpu_mask; | |
443 | ||
9395f6ea RK |
444 | /* |
445 | * Deal with the banked PPI and SGI interrupts - disable all | |
446 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
447 | */ | |
6ac77e46 SS |
448 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
449 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | |
9395f6ea RK |
450 | |
451 | /* | |
452 | * Set priority on PPI and SGI interrupts | |
453 | */ | |
454 | for (i = 0; i < 32; i += 4) | |
6ac77e46 | 455 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
9395f6ea | 456 | |
6ac77e46 SS |
457 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
458 | writel_relaxed(1, base + GIC_CPU_CTRL); | |
f27ecacc RK |
459 | } |
460 | ||
254056f3 CC |
461 | #ifdef CONFIG_CPU_PM |
462 | /* | |
463 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
464 | * with interrupts disabled but before powering down the GIC. After calling | |
465 | * this function, no interrupts will be delivered by the GIC, and another | |
466 | * platform-specific wakeup source must be enabled. | |
467 | */ | |
468 | static void gic_dist_save(unsigned int gic_nr) | |
469 | { | |
470 | unsigned int gic_irqs; | |
471 | void __iomem *dist_base; | |
472 | int i; | |
473 | ||
474 | if (gic_nr >= MAX_GIC_NR) | |
475 | BUG(); | |
476 | ||
477 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 478 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
479 | |
480 | if (!dist_base) | |
481 | return; | |
482 | ||
483 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
484 | gic_data[gic_nr].saved_spi_conf[i] = | |
485 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
486 | ||
487 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
488 | gic_data[gic_nr].saved_spi_target[i] = | |
489 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
490 | ||
491 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
492 | gic_data[gic_nr].saved_spi_enable[i] = | |
493 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
494 | } | |
495 | ||
496 | /* | |
497 | * Restores the GIC distributor registers during resume or when coming out of | |
498 | * idle. Must be called before enabling interrupts. If a level interrupt | |
499 | * that occured while the GIC was suspended is still present, it will be | |
500 | * handled normally, but any edge interrupts that occured will not be seen by | |
501 | * the GIC and need to be handled by the platform-specific wakeup source. | |
502 | */ | |
503 | static void gic_dist_restore(unsigned int gic_nr) | |
504 | { | |
505 | unsigned int gic_irqs; | |
506 | unsigned int i; | |
507 | void __iomem *dist_base; | |
508 | ||
509 | if (gic_nr >= MAX_GIC_NR) | |
510 | BUG(); | |
511 | ||
512 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 513 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
514 | |
515 | if (!dist_base) | |
516 | return; | |
517 | ||
518 | writel_relaxed(0, dist_base + GIC_DIST_CTRL); | |
519 | ||
520 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
521 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
522 | dist_base + GIC_DIST_CONFIG + i * 4); | |
523 | ||
524 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
525 | writel_relaxed(0xa0a0a0a0, | |
526 | dist_base + GIC_DIST_PRI + i * 4); | |
527 | ||
528 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
529 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
530 | dist_base + GIC_DIST_TARGET + i * 4); | |
531 | ||
532 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
533 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
534 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
535 | ||
536 | writel_relaxed(1, dist_base + GIC_DIST_CTRL); | |
537 | } | |
538 | ||
539 | static void gic_cpu_save(unsigned int gic_nr) | |
540 | { | |
541 | int i; | |
542 | u32 *ptr; | |
543 | void __iomem *dist_base; | |
544 | void __iomem *cpu_base; | |
545 | ||
546 | if (gic_nr >= MAX_GIC_NR) | |
547 | BUG(); | |
548 | ||
db0d4db2 MZ |
549 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
550 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
551 | |
552 | if (!dist_base || !cpu_base) | |
553 | return; | |
554 | ||
555 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
556 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
557 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
558 | ||
559 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
560 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
561 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
562 | ||
563 | } | |
564 | ||
565 | static void gic_cpu_restore(unsigned int gic_nr) | |
566 | { | |
567 | int i; | |
568 | u32 *ptr; | |
569 | void __iomem *dist_base; | |
570 | void __iomem *cpu_base; | |
571 | ||
572 | if (gic_nr >= MAX_GIC_NR) | |
573 | BUG(); | |
574 | ||
db0d4db2 MZ |
575 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
576 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
577 | |
578 | if (!dist_base || !cpu_base) | |
579 | return; | |
580 | ||
581 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
582 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
583 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
584 | ||
585 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
586 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
587 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
588 | ||
589 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
590 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); | |
591 | ||
592 | writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); | |
593 | writel_relaxed(1, cpu_base + GIC_CPU_CTRL); | |
594 | } | |
595 | ||
596 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
597 | { | |
598 | int i; | |
599 | ||
600 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
601 | #ifdef CONFIG_GIC_NON_BANKED |
602 | /* Skip over unused GICs */ | |
603 | if (!gic_data[i].get_base) | |
604 | continue; | |
605 | #endif | |
254056f3 CC |
606 | switch (cmd) { |
607 | case CPU_PM_ENTER: | |
608 | gic_cpu_save(i); | |
609 | break; | |
610 | case CPU_PM_ENTER_FAILED: | |
611 | case CPU_PM_EXIT: | |
612 | gic_cpu_restore(i); | |
613 | break; | |
614 | case CPU_CLUSTER_PM_ENTER: | |
615 | gic_dist_save(i); | |
616 | break; | |
617 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
618 | case CPU_CLUSTER_PM_EXIT: | |
619 | gic_dist_restore(i); | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | return NOTIFY_OK; | |
625 | } | |
626 | ||
627 | static struct notifier_block gic_notifier_block = { | |
628 | .notifier_call = gic_notifier, | |
629 | }; | |
630 | ||
631 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
632 | { | |
633 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
634 | sizeof(u32)); | |
635 | BUG_ON(!gic->saved_ppi_enable); | |
636 | ||
637 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
638 | sizeof(u32)); | |
639 | BUG_ON(!gic->saved_ppi_conf); | |
640 | ||
abdd7b91 MZ |
641 | if (gic == &gic_data[0]) |
642 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
643 | } |
644 | #else | |
645 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
646 | { | |
647 | } | |
648 | #endif | |
649 | ||
b1cffebf RH |
650 | #ifdef CONFIG_SMP |
651 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
652 | { | |
653 | int cpu; | |
654 | unsigned long map = 0; | |
655 | ||
656 | /* Convert our logical CPU mask into a physical one. */ | |
657 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 658 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
659 | |
660 | /* | |
661 | * Ensure that stores to Normal memory are visible to the | |
662 | * other CPUs before issuing the IPI. | |
663 | */ | |
664 | dsb(); | |
665 | ||
666 | /* this always happens on GIC0 */ | |
667 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
668 | } | |
669 | #endif | |
670 | ||
75294957 GL |
671 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
672 | irq_hw_number_t hw) | |
673 | { | |
674 | if (hw < 32) { | |
675 | irq_set_percpu_devid(irq); | |
676 | irq_set_chip_and_handler(irq, &gic_chip, | |
677 | handle_percpu_devid_irq); | |
678 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); | |
679 | } else { | |
680 | irq_set_chip_and_handler(irq, &gic_chip, | |
681 | handle_fasteoi_irq); | |
682 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
683 | } | |
684 | irq_set_chip_data(irq, d->host_data); | |
685 | return 0; | |
686 | } | |
687 | ||
7bb69bad GL |
688 | static int gic_irq_domain_xlate(struct irq_domain *d, |
689 | struct device_node *controller, | |
690 | const u32 *intspec, unsigned int intsize, | |
691 | unsigned long *out_hwirq, unsigned int *out_type) | |
b3f7ed03 RH |
692 | { |
693 | if (d->of_node != controller) | |
694 | return -EINVAL; | |
695 | if (intsize < 3) | |
696 | return -EINVAL; | |
697 | ||
698 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
699 | *out_hwirq = intspec[1] + 16; | |
700 | ||
701 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
702 | if (!intspec[0]) | |
703 | *out_hwirq += 16; | |
704 | ||
705 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
706 | return 0; | |
707 | } | |
b3f7ed03 | 708 | |
c0114709 CM |
709 | #ifdef CONFIG_SMP |
710 | static int __cpuinit gic_secondary_init(struct notifier_block *nfb, | |
711 | unsigned long action, void *hcpu) | |
712 | { | |
8b6fd652 | 713 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
714 | gic_cpu_init(&gic_data[0]); |
715 | return NOTIFY_OK; | |
716 | } | |
717 | ||
718 | /* | |
719 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
720 | * priority because the GIC needs to be up before the ARM generic timers. | |
721 | */ | |
722 | static struct notifier_block __cpuinitdata gic_cpu_notifier = { | |
723 | .notifier_call = gic_secondary_init, | |
724 | .priority = 100, | |
725 | }; | |
726 | #endif | |
727 | ||
15a25980 | 728 | const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 729 | .map = gic_irq_domain_map, |
7bb69bad | 730 | .xlate = gic_irq_domain_xlate, |
4294f8ba RH |
731 | }; |
732 | ||
db0d4db2 MZ |
733 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
734 | void __iomem *dist_base, void __iomem *cpu_base, | |
75294957 | 735 | u32 percpu_offset, struct device_node *node) |
b580b899 | 736 | { |
75294957 | 737 | irq_hw_number_t hwirq_base; |
bef8f9ee | 738 | struct gic_chip_data *gic; |
384a2902 | 739 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
740 | |
741 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
742 | ||
743 | gic = &gic_data[gic_nr]; | |
db0d4db2 MZ |
744 | #ifdef CONFIG_GIC_NON_BANKED |
745 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
746 | unsigned int cpu; | |
747 | ||
748 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
749 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
750 | if (WARN_ON(!gic->dist_base.percpu_base || | |
751 | !gic->cpu_base.percpu_base)) { | |
752 | free_percpu(gic->dist_base.percpu_base); | |
753 | free_percpu(gic->cpu_base.percpu_base); | |
754 | return; | |
755 | } | |
756 | ||
757 | for_each_possible_cpu(cpu) { | |
4003b69e TF |
758 | u32 mpidr = cpu_logical_map(cpu); |
759 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
760 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
761 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
762 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
763 | } | |
764 | ||
765 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
766 | } else | |
767 | #endif | |
768 | { /* Normal, sane GIC... */ | |
769 | WARN(percpu_offset, | |
770 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
771 | percpu_offset); | |
772 | gic->dist_base.common_base = dist_base; | |
773 | gic->cpu_base.common_base = cpu_base; | |
774 | gic_set_base_accessor(gic, gic_get_common_base); | |
775 | } | |
bef8f9ee | 776 | |
384a2902 NP |
777 | /* |
778 | * Initialize the CPU interface map to all CPUs. | |
779 | * It will be refined as each CPU probes its ID. | |
780 | */ | |
781 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
782 | gic_cpu_map[i] = 0xff; | |
783 | ||
4294f8ba RH |
784 | /* |
785 | * For primary GICs, skip over SGIs. | |
786 | * For secondary GICs, skip over PPIs, too. | |
787 | */ | |
e0b823e9 | 788 | if (gic_nr == 0 && (irq_start & 31) > 0) { |
12679a2d | 789 | hwirq_base = 16; |
e0b823e9 WD |
790 | if (irq_start != -1) |
791 | irq_start = (irq_start & ~31) + 16; | |
792 | } else { | |
12679a2d | 793 | hwirq_base = 32; |
fe41db7b | 794 | } |
4294f8ba RH |
795 | |
796 | /* | |
797 | * Find out how many interrupts are supported. | |
798 | * The GIC only supports up to 1020 interrupt sources. | |
799 | */ | |
db0d4db2 | 800 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
801 | gic_irqs = (gic_irqs + 1) * 32; |
802 | if (gic_irqs > 1020) | |
803 | gic_irqs = 1020; | |
804 | gic->gic_irqs = gic_irqs; | |
805 | ||
75294957 GL |
806 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ |
807 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id()); | |
808 | if (IS_ERR_VALUE(irq_base)) { | |
f37a53cc RH |
809 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
810 | irq_start); | |
75294957 | 811 | irq_base = irq_start; |
f37a53cc | 812 | } |
75294957 GL |
813 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, |
814 | hwirq_base, &gic_irq_domain_ops, gic); | |
815 | if (WARN_ON(!gic->domain)) | |
816 | return; | |
bef8f9ee | 817 | |
b1cffebf RH |
818 | #ifdef CONFIG_SMP |
819 | set_smp_cross_call(gic_raise_softirq); | |
c0114709 | 820 | register_cpu_notifier(&gic_cpu_notifier); |
b1cffebf | 821 | #endif |
cfed7d60 RH |
822 | |
823 | set_handle_irq(gic_handle_irq); | |
824 | ||
9c12845e | 825 | gic_chip.flags |= gic_arch_extn.flags; |
4294f8ba | 826 | gic_dist_init(gic); |
bef8f9ee | 827 | gic_cpu_init(gic); |
254056f3 | 828 | gic_pm_init(gic); |
b580b899 RK |
829 | } |
830 | ||
b3f7ed03 | 831 | #ifdef CONFIG_OF |
46f101df | 832 | static int gic_cnt __initdata; |
b3f7ed03 RH |
833 | |
834 | int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
835 | { | |
836 | void __iomem *cpu_base; | |
837 | void __iomem *dist_base; | |
db0d4db2 | 838 | u32 percpu_offset; |
b3f7ed03 | 839 | int irq; |
b3f7ed03 RH |
840 | |
841 | if (WARN_ON(!node)) | |
842 | return -ENODEV; | |
843 | ||
844 | dist_base = of_iomap(node, 0); | |
845 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
846 | ||
847 | cpu_base = of_iomap(node, 1); | |
848 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
849 | ||
db0d4db2 MZ |
850 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
851 | percpu_offset = 0; | |
852 | ||
75294957 | 853 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
b3f7ed03 RH |
854 | |
855 | if (parent) { | |
856 | irq = irq_of_parse_and_map(node, 0); | |
857 | gic_cascade_irq(gic_cnt, irq); | |
858 | } | |
859 | gic_cnt++; | |
860 | return 0; | |
861 | } | |
81243e44 RH |
862 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
863 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
db9e4bf3 | 864 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
865 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
866 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
867 | ||
b3f7ed03 | 868 | #endif |