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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iommu / amd_iommu.c
CommitLineData
b6c02715 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
b6c02715
JR		 3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
72e1dcc4 20#include <linux/ratelimit.h>
b6c02715 21#include <linux/pci.h>
cb41ed85 22#include <linux/pci-ats.h>
a66022c4 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
7f26508b 25#include <linux/debugfs.h>
b6c02715 26#include <linux/scatterlist.h>
51491367 27#include <linux/dma-mapping.h>
b6c02715 28#include <linux/iommu-helper.h>
c156e347 29#include <linux/iommu.h>
815b33fd 30#include <linux/delay.h>
403f81d8 31#include <linux/amd-iommu.h>
72e1dcc4
JR		 32#include <linux/notifier.h>
33#include <linux/export.h>
2b324506
JR		 34#include <linux/irq.h>
35#include <linux/msi.h>
36#include <asm/irq_remapping.h>
37#include <asm/io_apic.h>
38#include <asm/apic.h>
39#include <asm/hw_irq.h>
17f5b569 40#include <asm/msidef.h>
b6c02715 41#include <asm/proto.h>
46a7fa27 42#include <asm/iommu.h>
1d9b16d1 43#include <asm/gart.h>
27c2127a 44#include <asm/dma.h>
403f81d8
JR		 45
46#include "amd_iommu_proto.h"
47#include "amd_iommu_types.h"
6b474b82 48#include "irq_remapping.h"
61e015ac 49#include "pci.h"
b6c02715
JR		 50
51#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
815b33fd 53#define LOOP_TIMEOUT 100000
136f78a1 54
aa3de9c0
OBC		 55/*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
954e3dd8 61 * 512GB Pages are not supported due to a hardware bug
aa3de9c0 62 */
954e3dd8 63#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
aa3de9c0 64
b6c02715
JR		 65static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
bd60b735
JR		 67/* A list of preallocated protection domains */
68static LIST_HEAD(iommu_pd_list);
69static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
8fa5f802
JR		 71/* List of all available dev_data structures */
72static LIST_HEAD(dev_data_list);
73static DEFINE_SPINLOCK(dev_data_list_lock);
74
6efed63b
JR		 75LIST_HEAD(ioapic_map);
76LIST_HEAD(hpet_map);
77
0feae533
JR		 78/*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82static struct protection_domain *pt_domain;
83
26961efe 84static struct iommu_ops amd_iommu_ops;
26961efe 85
72e1dcc4 86static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
52815b75 87int amd_iommu_max_glx_val = -1;
72e1dcc4 88
ac1534a5
JR		 89static struct dma_map_ops amd_iommu_dma_ops;
90
431b2a20
JR		 91/*
92 * general struct to manage commands send to an IOMMU
93 */
d6449536 94struct iommu_cmd {
b6c02715
JR		 95 u32 data[4];
96};
97
05152a04
JR		 98struct kmem_cache *amd_iommu_irq_cache;
99
04bfdd84 100static void update_domain(struct protection_domain *domain);
5abcdba4 101static int __init alloc_passthrough_domain(void);
c1eee67b 102
15898bbc
JR		 103/****************************************************************************
104 *
105 * Helper functions
106 *
107 ****************************************************************************/
108
f62dda66 109static struct iommu_dev_data *alloc_dev_data(u16 devid)
8fa5f802
JR		 110{
111 struct iommu_dev_data *dev_data;
112 unsigned long flags;
113
114 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
115 if (!dev_data)
116 return NULL;
117
f62dda66 118 dev_data->devid = devid;
8fa5f802
JR		 119 atomic_set(&dev_data->bind, 0);
120
121 spin_lock_irqsave(&dev_data_list_lock, flags);
122 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
123 spin_unlock_irqrestore(&dev_data_list_lock, flags);
124
125 return dev_data;
126}
127
128static void free_dev_data(struct iommu_dev_data *dev_data)
129{
130 unsigned long flags;
131
132 spin_lock_irqsave(&dev_data_list_lock, flags);
133 list_del(&dev_data->dev_data_list);
134 spin_unlock_irqrestore(&dev_data_list_lock, flags);
135
78bfa9f3
AW		 136 if (dev_data->group)
137 iommu_group_put(dev_data->group);
138
8fa5f802
JR		 139 kfree(dev_data);
140}
141
3b03bb74
JR		 142static struct iommu_dev_data *search_dev_data(u16 devid)
143{
144 struct iommu_dev_data *dev_data;
145 unsigned long flags;
146
147 spin_lock_irqsave(&dev_data_list_lock, flags);
148 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
149 if (dev_data->devid == devid)
150 goto out_unlock;
151 }
152
153 dev_data = NULL;
154
155out_unlock:
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 return dev_data;
159}
160
161static struct iommu_dev_data *find_dev_data(u16 devid)
162{
163 struct iommu_dev_data *dev_data;
164
165 dev_data = search_dev_data(devid);
166
167 if (dev_data == NULL)
168 dev_data = alloc_dev_data(devid);
169
170 return dev_data;
171}
172
15898bbc
JR		 173static inline u16 get_device_id(struct device *dev)
174{
175 struct pci_dev *pdev = to_pci_dev(dev);
176
6f2729ba 177 return PCI_DEVID(pdev->bus->number, pdev->devfn);
15898bbc
JR		 178}
179
657cbb6b
JR		 180static struct iommu_dev_data *get_dev_data(struct device *dev)
181{
182 return dev->archdata.iommu;
183}
184
5abcdba4
JR		 185static bool pci_iommuv2_capable(struct pci_dev *pdev)
186{
187 static const int caps[] = {
188 PCI_EXT_CAP_ID_ATS,
46277b75
JR		 189 PCI_EXT_CAP_ID_PRI,
190 PCI_EXT_CAP_ID_PASID,
5abcdba4
JR		 191 };
192 int i, pos;
193
194 for (i = 0; i < 3; ++i) {
195 pos = pci_find_ext_capability(pdev, caps[i]);
196 if (pos == 0)
197 return false;
198 }
199
200 return true;
201}
202
6a113ddc
JR		 203static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
204{
205 struct iommu_dev_data *dev_data;
206
207 dev_data = get_dev_data(&pdev->dev);
208
209 return dev_data->errata & (1 << erratum) ? true : false;
210}
211
71c70984
JR		 212/*
213 * In this function the list of preallocated protection domains is traversed to
214 * find the domain for a specific device
215 */
216static struct dma_ops_domain *find_protection_domain(u16 devid)
217{
218 struct dma_ops_domain *entry, *ret = NULL;
219 unsigned long flags;
220 u16 alias = amd_iommu_alias_table[devid];
221
222 if (list_empty(&iommu_pd_list))
223 return NULL;
224
225 spin_lock_irqsave(&iommu_pd_list_lock, flags);
226
227 list_for_each_entry(entry, &iommu_pd_list, list) {
228 if (entry->target_dev == devid ||
229 entry->target_dev == alias) {
230 ret = entry;
231 break;
232 }
233 }
234
235 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
236
237 return ret;
238}
239
98fc5a69
JR		 240/*
241 * This function checks if the driver got a valid device from the caller to
242 * avoid dereferencing invalid pointers.
243 */
244static bool check_device(struct device *dev)
245{
246 u16 devid;
247
248 if (!dev || !dev->dma_mask)
249 return false;
250
251 /* No device or no PCI device */
339d3261 252 if (dev->bus != &pci_bus_type)
98fc5a69
JR		 253 return false;
254
255 devid = get_device_id(dev);
256
257 /* Out of our scope? */
258 if (devid > amd_iommu_last_bdf)
259 return false;
260
261 if (amd_iommu_rlookup_table[devid] == NULL)
262 return false;
263
264 return true;
265}
266
2bff6a50
AW		 267static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
268{
269 while (!bus->self) {
270 if (!pci_is_root_bus(bus))
271 bus = bus->parent;
272 else
273 return ERR_PTR(-ENODEV);
274 }
275
276 return bus;
277}
278
664b6003
AW		 279#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
280
2851db21 281static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
657cbb6b 282{
2851db21 283 struct pci_dev *dma_pdev = pdev;
9dcd6130 284
31fe9435 285 /* Account for quirked devices */
664b6003
AW		 286 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
287
31fe9435
AW		 288 /*
289 * If it's a multifunction device that does not support our
290 * required ACS flags, add to the same group as function 0.
291 */
664b6003
AW		 292 if (dma_pdev->multifunction &&
293 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
294 swap_pci_ref(&dma_pdev,
295 pci_get_slot(dma_pdev->bus,
296 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
297 0)));
298
31fe9435
AW		 299 /*
300 * Devices on the root bus go through the iommu. If that's not us,
301 * find the next upstream device and test ACS up to the root bus.
302 * Finding the next device may require skipping virtual buses.
303 */
664b6003 304 while (!pci_is_root_bus(dma_pdev->bus)) {
2bff6a50
AW		 305 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
306 if (IS_ERR(bus))
307 break;
31fe9435
AW		 308
309 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
664b6003
AW		 310 break;
311
31fe9435 312 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
664b6003
AW		 313 }
314
2851db21
AW		 315 return dma_pdev;
316}
317
ce7ac4ab
AW		 318static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev)
319{
320 struct iommu_group *group = iommu_group_get(&pdev->dev);
321 int ret;
322
323 if (!group) {
324 group = iommu_group_alloc();
325 if (IS_ERR(group))
326 return PTR_ERR(group);
327
328 WARN_ON(&pdev->dev != dev);
329 }
330
331 ret = iommu_group_add_device(group, dev);
332 iommu_group_put(group);
333 return ret;
334}
335
78bfa9f3
AW		 336static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data,
337 struct device *dev)
338{
339 if (!dev_data->group) {
340 struct iommu_group *group = iommu_group_alloc();
341 if (IS_ERR(group))
342 return PTR_ERR(group);
343
344 dev_data->group = group;
345 }
346
347 return iommu_group_add_device(dev_data->group, dev);
348}
349
2851db21
AW		 350static int init_iommu_group(struct device *dev)
351{
352 struct iommu_dev_data *dev_data;
353 struct iommu_group *group;
78bfa9f3 354 struct pci_dev *dma_pdev;
2851db21
AW		 355 int ret;
356
357 group = iommu_group_get(dev);
358 if (group) {
359 iommu_group_put(group);
360 return 0;
361 }
362
363 dev_data = find_dev_data(get_device_id(dev));
364 if (!dev_data)
365 return -ENOMEM;
366
367 if (dev_data->alias_data) {
368 u16 alias;
78bfa9f3
AW		 369 struct pci_bus *bus;
370
371 if (dev_data->alias_data->group)
372 goto use_group;
2851db21 373
78bfa9f3
AW		 374 /*
375 * If the alias device exists, it's effectively just a first
376 * level quirk for finding the DMA source.
377 */
2851db21
AW		 378 alias = amd_iommu_alias_table[dev_data->devid];
379 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
78bfa9f3
AW		 380 if (dma_pdev) {
381 dma_pdev = get_isolation_root(dma_pdev);
382 goto use_pdev;
383 }
2851db21 384
78bfa9f3
AW		 385 /*
386 * If the alias is virtual, try to find a parent device
387 * and test whether the IOMMU group is actualy rooted above
388 * the alias. Be careful to also test the parent device if
389 * we think the alias is the root of the group.
390 */
391 bus = pci_find_bus(0, alias >> 8);
392 if (!bus)
393 goto use_group;
394
395 bus = find_hosted_bus(bus);
396 if (IS_ERR(bus) || !bus->self)
397 goto use_group;
398
399 dma_pdev = get_isolation_root(pci_dev_get(bus->self));
400 if (dma_pdev != bus->self || (dma_pdev->multifunction &&
401 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)))
402 goto use_pdev;
403
404 pci_dev_put(dma_pdev);
405 goto use_group;
406 }
2851db21 407
78bfa9f3
AW		 408 dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev)));
409use_pdev:
ce7ac4ab 410 ret = use_pdev_iommu_group(dma_pdev, dev);
9dcd6130 411 pci_dev_put(dma_pdev);
eb9c9527 412 return ret;
78bfa9f3
AW		 413use_group:
414 return use_dev_data_iommu_group(dev_data->alias_data, dev);
eb9c9527
AW		 415}
416
417static int iommu_init_device(struct device *dev)
418{
419 struct pci_dev *pdev = to_pci_dev(dev);
420 struct iommu_dev_data *dev_data;
421 u16 alias;
422 int ret;
423
424 if (dev->archdata.iommu)
425 return 0;
426
427 dev_data = find_dev_data(get_device_id(dev));
428 if (!dev_data)
429 return -ENOMEM;
430
431 alias = amd_iommu_alias_table[dev_data->devid];
432 if (alias != dev_data->devid) {
433 struct iommu_dev_data *alias_data;
434
435 alias_data = find_dev_data(alias);
436 if (alias_data == NULL) {
437 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
438 dev_name(dev));
439 free_dev_data(dev_data);
440 return -ENOTSUPP;
441 }
442 dev_data->alias_data = alias_data;
443 }
444
445 ret = init_iommu_group(dev);
9dcd6130
AW		 446 if (ret)
447 return ret;
448
5abcdba4
JR		 449 if (pci_iommuv2_capable(pdev)) {
450 struct amd_iommu *iommu;
451
452 iommu = amd_iommu_rlookup_table[dev_data->devid];
453 dev_data->iommu_v2 = iommu->is_iommu_v2;
454 }
455
657cbb6b
JR		 456 dev->archdata.iommu = dev_data;
457
657cbb6b
JR		 458 return 0;
459}
460
26018874
JR		 461static void iommu_ignore_device(struct device *dev)
462{
463 u16 devid, alias;
464
465 devid = get_device_id(dev);
466 alias = amd_iommu_alias_table[devid];
467
468 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
469 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
470
471 amd_iommu_rlookup_table[devid] = NULL;
472 amd_iommu_rlookup_table[alias] = NULL;
473}
474
657cbb6b
JR		 475static void iommu_uninit_device(struct device *dev)
476{
9dcd6130
AW		 477 iommu_group_remove_device(dev);
478
8fa5f802
JR		 479 /*
480 * Nothing to do here - we keep dev_data around for unplugged devices
481 * and reuse it when the device is re-plugged - not doing so would
482 * introduce a ton of races.
483 */
657cbb6b 484}
b7cc9554
JR		 485
486void __init amd_iommu_uninit_devices(void)
487{
8fa5f802 488 struct iommu_dev_data *dev_data, *n;
b7cc9554
JR		 489 struct pci_dev *pdev = NULL;
490
491 for_each_pci_dev(pdev) {
492
493 if (!check_device(&pdev->dev))
494 continue;
495
496 iommu_uninit_device(&pdev->dev);
497 }
8fa5f802
JR		 498
499 /* Free all of our dev_data structures */
500 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
501 free_dev_data(dev_data);
b7cc9554
JR		 502}
503
504int __init amd_iommu_init_devices(void)
505{
506 struct pci_dev *pdev = NULL;
507 int ret = 0;
508
509 for_each_pci_dev(pdev) {
510
511 if (!check_device(&pdev->dev))
512 continue;
513
514 ret = iommu_init_device(&pdev->dev);
26018874
JR		 515 if (ret == -ENOTSUPP)
516 iommu_ignore_device(&pdev->dev);
517 else if (ret)
b7cc9554
JR		 518 goto out_free;
519 }
520
521 return 0;
522
523out_free:
524
525 amd_iommu_uninit_devices();
526
527 return ret;
528}
7f26508b
JR		 529#ifdef CONFIG_AMD_IOMMU_STATS
530
531/*
532 * Initialization code for statistics collection
533 */
534
da49f6df 535DECLARE_STATS_COUNTER(compl_wait);
0f2a86f2 536DECLARE_STATS_COUNTER(cnt_map_single);
146a6917 537DECLARE_STATS_COUNTER(cnt_unmap_single);
d03f067a 538DECLARE_STATS_COUNTER(cnt_map_sg);
55877a6b 539DECLARE_STATS_COUNTER(cnt_unmap_sg);
c8f0fb36 540DECLARE_STATS_COUNTER(cnt_alloc_coherent);
5d31ee7e 541DECLARE_STATS_COUNTER(cnt_free_coherent);
c1858976 542DECLARE_STATS_COUNTER(cross_page);
f57d98ae 543DECLARE_STATS_COUNTER(domain_flush_single);
18811f55 544DECLARE_STATS_COUNTER(domain_flush_all);
5774f7c5 545DECLARE_STATS_COUNTER(alloced_io_mem);
8ecaf8f1 546DECLARE_STATS_COUNTER(total_map_requests);
399be2f5
JR		 547DECLARE_STATS_COUNTER(complete_ppr);
548DECLARE_STATS_COUNTER(invalidate_iotlb);
549DECLARE_STATS_COUNTER(invalidate_iotlb_all);
550DECLARE_STATS_COUNTER(pri_requests);
551
7f26508b 552static struct dentry *stats_dir;
7f26508b
JR		 553static struct dentry *de_fflush;
554
555static void amd_iommu_stats_add(struct __iommu_counter *cnt)
556{
557 if (stats_dir == NULL)
558 return;
559
560 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
561 &cnt->value);
562}
563
564static void amd_iommu_stats_init(void)
565{
566 stats_dir = debugfs_create_dir("amd-iommu", NULL);
567 if (stats_dir == NULL)
568 return;
569
7f26508b 570 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
3775d481 571 &amd_iommu_unmap_flush);
da49f6df
JR		 572
573 amd_iommu_stats_add(&compl_wait);
0f2a86f2 574 amd_iommu_stats_add(&cnt_map_single);
146a6917 575 amd_iommu_stats_add(&cnt_unmap_single);
d03f067a 576 amd_iommu_stats_add(&cnt_map_sg);
55877a6b 577 amd_iommu_stats_add(&cnt_unmap_sg);
c8f0fb36 578 amd_iommu_stats_add(&cnt_alloc_coherent);
5d31ee7e 579 amd_iommu_stats_add(&cnt_free_coherent);
c1858976 580 amd_iommu_stats_add(&cross_page);
f57d98ae 581 amd_iommu_stats_add(&domain_flush_single);
18811f55 582 amd_iommu_stats_add(&domain_flush_all);
5774f7c5 583 amd_iommu_stats_add(&alloced_io_mem);
8ecaf8f1 584 amd_iommu_stats_add(&total_map_requests);
399be2f5
JR		 585 amd_iommu_stats_add(&complete_ppr);
586 amd_iommu_stats_add(&invalidate_iotlb);
587 amd_iommu_stats_add(&invalidate_iotlb_all);
588 amd_iommu_stats_add(&pri_requests);
7f26508b
JR		 589}
590
591#endif
592
a80dc3e0
JR		 593/****************************************************************************
594 *
595 * Interrupt handling functions
596 *
597 ****************************************************************************/
598
e3e59876
JR		 599static void dump_dte_entry(u16 devid)
600{
601 int i;
602
ee6c2868
JR		 603 for (i = 0; i < 4; ++i)
604 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
e3e59876
JR		 605 amd_iommu_dev_table[devid].data[i]);
606}
607
945b4ac4
JR		 608static void dump_command(unsigned long phys_addr)
609{
610 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
611 int i;
612
613 for (i = 0; i < 4; ++i)
614 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
615}
616
a345b23b 617static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
90008ee4 618{
3d06fca8
JR		 619 int type, devid, domid, flags;
620 volatile u32 *event = __evt;
621 int count = 0;
622 u64 address;
623
624retry:
625 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
626 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
627 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
628 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
629 address = (u64)(((u64)event[3]) << 32) | event[2];
630
631 if (type == 0) {
632 /* Did we hit the erratum? */
633 if (++count == LOOP_TIMEOUT) {
634 pr_err("AMD-Vi: No event written to event log\n");
635 return;
636 }
637 udelay(1);
638 goto retry;
639 }
90008ee4 640
4c6f40d4 641 printk(KERN_ERR "AMD-Vi: Event logged [");
90008ee4
JR		 642
643 switch (type) {
644 case EVENT_TYPE_ILL_DEV:
645 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
646 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4 648 address, flags);
e3e59876 649 dump_dte_entry(devid);
90008ee4
JR		 650 break;
651 case EVENT_TYPE_IO_FAULT:
652 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
653 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 654 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 655 domid, address, flags);
656 break;
657 case EVENT_TYPE_DEV_TAB_ERR:
658 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
659 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 660 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 661 address, flags);
662 break;
663 case EVENT_TYPE_PAGE_TAB_ERR:
664 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
665 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
c5081cd7 666 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 667 domid, address, flags);
668 break;
669 case EVENT_TYPE_ILL_CMD:
670 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
945b4ac4 671 dump_command(address);
90008ee4
JR		 672 break;
673 case EVENT_TYPE_CMD_HARD_ERR:
674 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
675 "flags=0x%04x]\n", address, flags);
676 break;
677 case EVENT_TYPE_IOTLB_INV_TO:
678 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
679 "address=0x%016llx]\n",
c5081cd7 680 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 681 address);
682 break;
683 case EVENT_TYPE_INV_DEV_REQ:
684 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
685 "address=0x%016llx flags=0x%04x]\n",
c5081cd7 686 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90008ee4
JR		 687 address, flags);
688 break;
689 default:
690 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
691 }
3d06fca8
JR		 692
693 memset(__evt, 0, 4 * sizeof(u32));
90008ee4
JR		 694}
695
696static void iommu_poll_events(struct amd_iommu *iommu)
697{
698 u32 head, tail;
90008ee4
JR		 699
700 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
701 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
702
703 while (head != tail) {
a345b23b 704 iommu_print_event(iommu, iommu->evt_buf + head);
90008ee4
JR		 705 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
706 }
707
708 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
90008ee4
JR		 709}
710
eee53537 711static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
72e1dcc4
JR		 712{
713 struct amd_iommu_fault fault;
72e1dcc4 714
399be2f5
JR		 715 INC_STATS_COUNTER(pri_requests);
716
72e1dcc4
JR		 717 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
718 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
719 return;
720 }
721
722 fault.address = raw[1];
723 fault.pasid = PPR_PASID(raw[0]);
724 fault.device_id = PPR_DEVID(raw[0]);
725 fault.tag = PPR_TAG(raw[0]);
726 fault.flags = PPR_FLAGS(raw[0]);
727
72e1dcc4
JR		 728 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
729}
730
731static void iommu_poll_ppr_log(struct amd_iommu *iommu)
732{
72e1dcc4
JR		 733 u32 head, tail;
734
735 if (iommu->ppr_log == NULL)
736 return;
737
72e1dcc4
JR		 738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740
741 while (head != tail) {
eee53537
JR		 742 volatile u64 *raw;
743 u64 entry[2];
744 int i;
745
746 raw = (u64 *)(iommu->ppr_log + head);
747
748 /*
749 * Hardware bug: Interrupt may arrive before the entry is
750 * written to memory. If this happens we need to wait for the
751 * entry to arrive.
752 */
753 for (i = 0; i < LOOP_TIMEOUT; ++i) {
754 if (PPR_REQ_TYPE(raw[0]) != 0)
755 break;
756 udelay(1);
757 }
72e1dcc4 758
eee53537
JR		 759 /* Avoid memcpy function-call overhead */
760 entry[0] = raw[0];
761 entry[1] = raw[1];
72e1dcc4 762
eee53537
JR		 763 /*
764 * To detect the hardware bug we need to clear the entry
765 * back to zero.
766 */
767 raw[0] = raw[1] = 0UL;
768
769 /* Update head pointer of hardware ring-buffer */
72e1dcc4
JR		 770 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
771 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
eee53537 772
eee53537
JR		 773 /* Handle PPR entry */
774 iommu_handle_ppr_entry(iommu, entry);
775
eee53537
JR		 776 /* Refresh ring-buffer information */
777 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
72e1dcc4
JR		 778 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
779 }
72e1dcc4
JR		 780}
781
72fe00f0 782irqreturn_t amd_iommu_int_thread(int irq, void *data)
a80dc3e0 783{
3f398bc7
SS		 784 struct amd_iommu *iommu = (struct amd_iommu *) data;
785 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 786
3f398bc7
SS		 787 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
788 /* Enable EVT and PPR interrupts again */
789 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
790 iommu->mmio_base + MMIO_STATUS_OFFSET);
90008ee4 791
3f398bc7
SS		 792 if (status & MMIO_STATUS_EVT_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
794 iommu_poll_events(iommu);
795 }
90008ee4 796
3f398bc7
SS		 797 if (status & MMIO_STATUS_PPR_INT_MASK) {
798 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
799 iommu_poll_ppr_log(iommu);
800 }
90008ee4 801
3f398bc7
SS		 802 /*
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
809 *
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
814 */
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
816 }
90008ee4 817 return IRQ_HANDLED;
a80dc3e0
JR		 818}
819
72fe00f0
JR		 820irqreturn_t amd_iommu_int_handler(int irq, void *data)
821{
822 return IRQ_WAKE_THREAD;
823}
824
431b2a20
JR		 825/****************************************************************************
826 *
827 * IOMMU command queuing functions
828 *
829 ****************************************************************************/
830
ac0ea6e9
JR		 831static int wait_on_sem(volatile u64 *sem)
832{
833 int i = 0;
834
835 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 udelay(1);
837 i += 1;
838 }
839
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 return -EIO;
843 }
844
845 return 0;
846}
847
848static void copy_cmd_to_buffer(struct amd_iommu *iommu,
849 struct iommu_cmd *cmd,
850 u32 tail)
a19ae1ec 851{
a19ae1ec
JR		 852 u8 *target;
853
8a7c5ef3 854 target = iommu->cmd_buf + tail;
ac0ea6e9
JR		 855 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
856
857 /* Copy command to buffer */
858 memcpy(target, cmd, sizeof(*cmd));
859
860 /* Tell the IOMMU about it */
a19ae1ec 861 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
ac0ea6e9 862}
a19ae1ec 863
815b33fd 864static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
ded46737 865{
815b33fd
JR		 866 WARN_ON(address & 0x7ULL);
867
ded46737 868 memset(cmd, 0, sizeof(*cmd));
815b33fd
JR		 869 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
870 cmd->data[1] = upper_32_bits(__pa(address));
871 cmd->data[2] = 1;
ded46737
JR		 872 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
873}
874
94fe79e2
JR		 875static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
876{
877 memset(cmd, 0, sizeof(*cmd));
878 cmd->data[0] = devid;
879 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
880}
881
11b6402c
JR		 882static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
883 size_t size, u16 domid, int pde)
884{
885 u64 pages;
886 int s;
887
888 pages = iommu_num_pages(address, size, PAGE_SIZE);
889 s = 0;
890
891 if (pages > 1) {
892 /*
893 * If we have to flush more than one page, flush all
894 * TLB entries for this domain
895 */
896 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
897 s = 1;
898 }
899
900 address &= PAGE_MASK;
901
902 memset(cmd, 0, sizeof(*cmd));
903 cmd->data[1] |= domid;
904 cmd->data[2] = lower_32_bits(address);
905 cmd->data[3] = upper_32_bits(address);
906 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
907 if (s) /* size bit - we flush more than one 4kb page */
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
df805abb 909 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
11b6402c
JR		 910 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
911}
912
cb41ed85
JR		 913static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
914 u64 address, size_t size)
915{
916 u64 pages;
917 int s;
918
919 pages = iommu_num_pages(address, size, PAGE_SIZE);
920 s = 0;
921
922 if (pages > 1) {
923 /*
924 * If we have to flush more than one page, flush all
925 * TLB entries for this domain
926 */
927 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
928 s = 1;
929 }
930
931 address &= PAGE_MASK;
932
933 memset(cmd, 0, sizeof(*cmd));
934 cmd->data[0] = devid;
935 cmd->data[0] |= (qdep & 0xff) << 24;
936 cmd->data[1] = devid;
937 cmd->data[2] = lower_32_bits(address);
938 cmd->data[3] = upper_32_bits(address);
939 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
940 if (s)
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
942}
943
22e266c7
JR		 944static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
945 u64 address, bool size)
946{
947 memset(cmd, 0, sizeof(*cmd));
948
949 address &= ~(0xfffULL);
950
951 cmd->data[0] = pasid & PASID_MASK;
952 cmd->data[1] = domid;
953 cmd->data[2] = lower_32_bits(address);
954 cmd->data[3] = upper_32_bits(address);
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
957 if (size)
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
959 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
960}
961
962static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
963 int qdep, u64 address, bool size)
964{
965 memset(cmd, 0, sizeof(*cmd));
966
967 address &= ~(0xfffULL);
968
969 cmd->data[0] = devid;
970 cmd->data[0] |= (pasid & 0xff) << 16;
971 cmd->data[0] |= (qdep & 0xff) << 24;
972 cmd->data[1] = devid;
973 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
974 cmd->data[2] = lower_32_bits(address);
975 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
976 cmd->data[3] = upper_32_bits(address);
977 if (size)
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
979 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
980}
981
c99afa25
JR		 982static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
983 int status, int tag, bool gn)
984{
985 memset(cmd, 0, sizeof(*cmd));
986
987 cmd->data[0] = devid;
988 if (gn) {
989 cmd->data[1] = pasid & PASID_MASK;
990 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
991 }
992 cmd->data[3] = tag & 0x1ff;
993 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
994
995 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
996}
997
58fc7f14
JR		 998static void build_inv_all(struct iommu_cmd *cmd)
999{
1000 memset(cmd, 0, sizeof(*cmd));
1001 CMD_SET_TYPE(cmd, CMD_INV_ALL);
a19ae1ec
JR		 1002}
1003
7ef2798d
JR		 1004static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1005{
1006 memset(cmd, 0, sizeof(*cmd));
1007 cmd->data[0] = devid;
1008 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1009}
1010
431b2a20 1011/*
431b2a20 1012 * Writes the command to the IOMMUs command buffer and informs the
ac0ea6e9 1013 * hardware about the new command.
431b2a20 1014 */
f1ca1512
JR		 1015static int iommu_queue_command_sync(struct amd_iommu *iommu,
1016 struct iommu_cmd *cmd,
1017 bool sync)
a19ae1ec 1018{
ac0ea6e9 1019 u32 left, tail, head, next_tail;
a19ae1ec 1020 unsigned long flags;
a19ae1ec 1021
549c90dc 1022 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
ac0ea6e9
JR		 1023
1024again:
a19ae1ec 1025 spin_lock_irqsave(&iommu->lock, flags);
a19ae1ec 1026
ac0ea6e9
JR		 1027 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1028 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1029 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
1030 left = (head - next_tail) % iommu->cmd_buf_size;
a19ae1ec 1031
ac0ea6e9
JR		 1032 if (left <= 2) {
1033 struct iommu_cmd sync_cmd;
1034 volatile u64 sem = 0;
1035 int ret;
8d201968 1036
ac0ea6e9
JR		 1037 build_completion_wait(&sync_cmd, (u64)&sem);
1038 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
da49f6df 1039
ac0ea6e9
JR		 1040 spin_unlock_irqrestore(&iommu->lock, flags);
1041
1042 if ((ret = wait_on_sem(&sem)) != 0)
1043 return ret;
1044
1045 goto again;
8d201968
JR		 1046 }
1047
ac0ea6e9
JR		 1048 copy_cmd_to_buffer(iommu, cmd, tail);
1049
1050 /* We need to sync now to make sure all commands are processed */
f1ca1512 1051 iommu->need_sync = sync;
ac0ea6e9 1052
a19ae1ec 1053 spin_unlock_irqrestore(&iommu->lock, flags);
8d201968 1054
815b33fd 1055 return 0;
8d201968
JR		 1056}
1057
f1ca1512
JR		 1058static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1059{
1060 return iommu_queue_command_sync(iommu, cmd, true);
1061}
1062
8d201968
JR		 1063/*
1064 * This function queues a completion wait command into the command
1065 * buffer of an IOMMU
1066 */
a19ae1ec 1067static int iommu_completion_wait(struct amd_iommu *iommu)
8d201968
JR		 1068{
1069 struct iommu_cmd cmd;
815b33fd 1070 volatile u64 sem = 0;
ac0ea6e9 1071 int ret;
8d201968 1072
09ee17eb 1073 if (!iommu->need_sync)
815b33fd 1074 return 0;
09ee17eb 1075
815b33fd 1076 build_completion_wait(&cmd, (u64)&sem);
a19ae1ec 1077
f1ca1512 1078 ret = iommu_queue_command_sync(iommu, &cmd, false);
a19ae1ec 1079 if (ret)
815b33fd 1080 return ret;
8d201968 1081
ac0ea6e9 1082 return wait_on_sem(&sem);
8d201968
JR		 1083}
1084
d8c13085 1085static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
a19ae1ec 1086{
d8c13085 1087 struct iommu_cmd cmd;
a19ae1ec 1088
d8c13085 1089 build_inv_dte(&cmd, devid);
7e4f88da 1090
d8c13085
JR		 1091 return iommu_queue_command(iommu, &cmd);
1092}
09ee17eb 1093
7d0c5cc5
JR		 1094static void iommu_flush_dte_all(struct amd_iommu *iommu)
1095{
1096 u32 devid;
09ee17eb 1097
7d0c5cc5
JR		 1098 for (devid = 0; devid <= 0xffff; ++devid)
1099 iommu_flush_dte(iommu, devid);
a19ae1ec 1100
7d0c5cc5
JR		 1101 iommu_completion_wait(iommu);
1102}
84df8175 1103
7d0c5cc5
JR		 1104/*
1105 * This function uses heavy locking and may disable irqs for some time. But
1106 * this is no issue because it is only called during resume.
1107 */
1108static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1109{
1110 u32 dom_id;
a19ae1ec 1111
7d0c5cc5
JR		 1112 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1113 struct iommu_cmd cmd;
1114 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1115 dom_id, 1);
1116 iommu_queue_command(iommu, &cmd);
1117 }
8eed9833 1118
7d0c5cc5 1119 iommu_completion_wait(iommu);
a19ae1ec
JR		 1120}
1121
58fc7f14 1122static void iommu_flush_all(struct amd_iommu *iommu)
0518a3a4 1123{
58fc7f14 1124 struct iommu_cmd cmd;
0518a3a4 1125
58fc7f14 1126 build_inv_all(&cmd);
0518a3a4 1127
58fc7f14
JR		 1128 iommu_queue_command(iommu, &cmd);
1129 iommu_completion_wait(iommu);
1130}
1131
7ef2798d
JR		 1132static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1133{
1134 struct iommu_cmd cmd;
1135
1136 build_inv_irt(&cmd, devid);
1137
1138 iommu_queue_command(iommu, &cmd);
1139}
1140
1141static void iommu_flush_irt_all(struct amd_iommu *iommu)
1142{
1143 u32 devid;
1144
1145 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1146 iommu_flush_irt(iommu, devid);
1147
1148 iommu_completion_wait(iommu);
1149}
1150
7d0c5cc5
JR		 1151void iommu_flush_all_caches(struct amd_iommu *iommu)
1152{
58fc7f14
JR		 1153 if (iommu_feature(iommu, FEATURE_IA)) {
1154 iommu_flush_all(iommu);
1155 } else {
1156 iommu_flush_dte_all(iommu);
7ef2798d 1157 iommu_flush_irt_all(iommu);
58fc7f14 1158 iommu_flush_tlb_all(iommu);
0518a3a4
JR		 1159 }
1160}
1161
431b2a20 1162/*
cb41ed85 1163 * Command send function for flushing on-device TLB
431b2a20 1164 */
6c542047
JR		 1165static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1166 u64 address, size_t size)
3fa43655
JR		 1167{
1168 struct amd_iommu *iommu;
b00d3bcf 1169 struct iommu_cmd cmd;
cb41ed85 1170 int qdep;
3fa43655 1171
ea61cddb
JR		 1172 qdep = dev_data->ats.qdep;
1173 iommu = amd_iommu_rlookup_table[dev_data->devid];
3fa43655 1174
ea61cddb 1175 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
b00d3bcf
JR		 1176
1177 return iommu_queue_command(iommu, &cmd);
3fa43655
JR		 1178}
1179
431b2a20 1180/*
431b2a20 1181 * Command send function for invalidating a device table entry
431b2a20 1182 */
6c542047 1183static int device_flush_dte(struct iommu_dev_data *dev_data)
a19ae1ec 1184{
3fa43655 1185 struct amd_iommu *iommu;
ee2fa743 1186 int ret;
a19ae1ec 1187
6c542047 1188 iommu = amd_iommu_rlookup_table[dev_data->devid];
a19ae1ec 1189
f62dda66 1190 ret = iommu_flush_dte(iommu, dev_data->devid);
cb41ed85
JR		 1191 if (ret)
1192 return ret;
1193
ea61cddb 1194 if (dev_data->ats.enabled)
6c542047 1195 ret = device_flush_iotlb(dev_data, 0, ~0UL);
ee2fa743 1196
ee2fa743 1197 return ret;
a19ae1ec
JR		 1198}
1199
431b2a20
JR		 1200/*
1201 * TLB invalidation function which is called from the mapping functions.
1202 * It invalidates a single PTE if the range to flush is within a single
1203 * page. Otherwise it flushes the whole TLB of the IOMMU.
1204 */
17b124bf
JR		 1205static void __domain_flush_pages(struct protection_domain *domain,
1206 u64 address, size_t size, int pde)
a19ae1ec 1207{
cb41ed85 1208 struct iommu_dev_data *dev_data;
11b6402c
JR		 1209 struct iommu_cmd cmd;
1210 int ret = 0, i;
a19ae1ec 1211
11b6402c 1212 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
999ba417 1213
6de8ad9b
JR		 1214 for (i = 0; i < amd_iommus_present; ++i) {
1215 if (!domain->dev_iommu[i])
1216 continue;
1217
1218 /*
1219 * Devices of this domain are behind this IOMMU
1220 * We need a TLB flush
1221 */
11b6402c 1222 ret |= iommu_queue_command(amd_iommus[i], &cmd);
6de8ad9b
JR		 1223 }
1224
cb41ed85 1225 list_for_each_entry(dev_data, &domain->dev_list, list) {
cb41ed85 1226
ea61cddb 1227 if (!dev_data->ats.enabled)
cb41ed85
JR		 1228 continue;
1229
6c542047 1230 ret |= device_flush_iotlb(dev_data, address, size);
cb41ed85
JR		 1231 }
1232
11b6402c 1233 WARN_ON(ret);
6de8ad9b
JR		 1234}
1235
17b124bf
JR		 1236static void domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size)
6de8ad9b 1238{
17b124bf 1239 __domain_flush_pages(domain, address, size, 0);
a19ae1ec 1240}
b6c02715 1241
1c655773 1242/* Flush the whole IO/TLB for a given protection domain */
17b124bf 1243static void domain_flush_tlb(struct protection_domain *domain)
1c655773 1244{
17b124bf 1245 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1c655773
JR		 1246}
1247
42a49f96 1248/* Flush the whole IO/TLB for a given protection domain - including PDE */
17b124bf 1249static void domain_flush_tlb_pde(struct protection_domain *domain)
42a49f96 1250{
17b124bf 1251 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
42a49f96
CW		 1252}
1253
17b124bf 1254static void domain_flush_complete(struct protection_domain *domain)
b00d3bcf 1255{
17b124bf 1256 int i;
18811f55 1257
17b124bf
JR		 1258 for (i = 0; i < amd_iommus_present; ++i) {
1259 if (!domain->dev_iommu[i])
1260 continue;
bfd1be18 1261
17b124bf
JR		 1262 /*
1263 * Devices of this domain are behind this IOMMU
1264 * We need to wait for completion of all commands.
1265 */
1266 iommu_completion_wait(amd_iommus[i]);
bfd1be18 1267 }
e394d72a
JR		 1268}
1269
b00d3bcf 1270
09b42804 1271/*
b00d3bcf 1272 * This function flushes the DTEs for all devices in domain
09b42804 1273 */
17b124bf 1274static void domain_flush_devices(struct protection_domain *domain)
e394d72a 1275{
b00d3bcf 1276 struct iommu_dev_data *dev_data;
b26e81b8 1277
b00d3bcf 1278 list_for_each_entry(dev_data, &domain->dev_list, list)
6c542047 1279 device_flush_dte(dev_data);
a345b23b
JR		 1280}
1281
431b2a20
JR		 1282/****************************************************************************
1283 *
1284 * The functions below are used the create the page table mappings for
1285 * unity mapped regions.
1286 *
1287 ****************************************************************************/
1288
308973d3
JR		 1289/*
1290 * This function is used to add another level to an IO page table. Adding
1291 * another level increases the size of the address space by 9 bits to a size up
1292 * to 64 bits.
1293 */
1294static bool increase_address_space(struct protection_domain *domain,
1295 gfp_t gfp)
1296{
1297 u64 *pte;
1298
1299 if (domain->mode == PAGE_MODE_6_LEVEL)
1300 /* address space already 64 bit large */
1301 return false;
1302
1303 pte = (void *)get_zeroed_page(gfp);
1304 if (!pte)
1305 return false;
1306
1307 *pte = PM_LEVEL_PDE(domain->mode,
1308 virt_to_phys(domain->pt_root));
1309 domain->pt_root = pte;
1310 domain->mode += 1;
1311 domain->updated = true;
1312
1313 return true;
1314}
1315
1316static u64 *alloc_pte(struct protection_domain *domain,
1317 unsigned long address,
cbb9d729 1318 unsigned long page_size,
308973d3
JR		 1319 u64 **pte_page,
1320 gfp_t gfp)
1321{
cbb9d729 1322 int level, end_lvl;
308973d3 1323 u64 *pte, *page;
cbb9d729
JR		 1324
1325 BUG_ON(!is_power_of_2(page_size));
308973d3
JR		 1326
1327 while (address > PM_LEVEL_SIZE(domain->mode))
1328 increase_address_space(domain, gfp);
1329
cbb9d729
JR		 1330 level = domain->mode - 1;
1331 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1332 address = PAGE_SIZE_ALIGN(address, page_size);
1333 end_lvl = PAGE_SIZE_LEVEL(page_size);
308973d3
JR		 1334
1335 while (level > end_lvl) {
1336 if (!IOMMU_PTE_PRESENT(*pte)) {
1337 page = (u64 *)get_zeroed_page(gfp);
1338 if (!page)
1339 return NULL;
1340 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1341 }
1342
cbb9d729
JR		 1343 /* No level skipping support yet */
1344 if (PM_PTE_LEVEL(*pte) != level)
1345 return NULL;
1346
308973d3
JR		 1347 level -= 1;
1348
1349 pte = IOMMU_PTE_PAGE(*pte);
1350
1351 if (pte_page && level == end_lvl)
1352 *pte_page = pte;
1353
1354 pte = &pte[PM_LEVEL_INDEX(level, address)];
1355 }
1356
1357 return pte;
1358}
1359
1360/*
1361 * This function checks if there is a PTE for a given dma address. If
1362 * there is one, it returns the pointer to it.
1363 */
24cd7723 1364static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
308973d3
JR		 1365{
1366 int level;
1367 u64 *pte;
1368
24cd7723
JR		 1369 if (address > PM_LEVEL_SIZE(domain->mode))
1370 return NULL;
1371
1372 level = domain->mode - 1;
1373 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
308973d3 1374
24cd7723
JR		 1375 while (level > 0) {
1376
1377 /* Not Present */
308973d3
JR		 1378 if (!IOMMU_PTE_PRESENT(*pte))
1379 return NULL;
1380
24cd7723
JR		 1381 /* Large PTE */
1382 if (PM_PTE_LEVEL(*pte) == 0x07) {
1383 unsigned long pte_mask, __pte;
1384
1385 /*
1386 * If we have a series of large PTEs, make
1387 * sure to return a pointer to the first one.
1388 */
1389 pte_mask = PTE_PAGE_SIZE(*pte);
1390 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1391 __pte = ((unsigned long)pte) & pte_mask;
1392
1393 return (u64 *)__pte;
1394 }
1395
1396 /* No level skipping support yet */
1397 if (PM_PTE_LEVEL(*pte) != level)
1398 return NULL;
1399
308973d3
JR		 1400 level -= 1;
1401
24cd7723 1402 /* Walk to the next level */
308973d3
JR		 1403 pte = IOMMU_PTE_PAGE(*pte);
1404 pte = &pte[PM_LEVEL_INDEX(level, address)];
308973d3
JR		 1405 }
1406
1407 return pte;
1408}
1409
431b2a20
JR		 1410/*
1411 * Generic mapping functions. It maps a physical address into a DMA
1412 * address space. It allocates the page table pages if necessary.
1413 * In the future it can be extended to a generic mapping function
1414 * supporting all features of AMD IOMMU page tables like level skipping
1415 * and full 64 bit address spaces.
1416 */
38e817fe
JR		 1417static int iommu_map_page(struct protection_domain *dom,
1418 unsigned long bus_addr,
1419 unsigned long phys_addr,
abdc5eb3 1420 int prot,
cbb9d729 1421 unsigned long page_size)
bd0e5211 1422{
8bda3092 1423 u64 __pte, *pte;
cbb9d729 1424 int i, count;
abdc5eb3 1425
bad1cac2 1426 if (!(prot & IOMMU_PROT_MASK))
bd0e5211
JR		 1427 return -EINVAL;
1428
cbb9d729
JR		 1429 bus_addr = PAGE_ALIGN(bus_addr);
1430 phys_addr = PAGE_ALIGN(phys_addr);
1431 count = PAGE_SIZE_PTE_COUNT(page_size);
1432 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1433
1434 for (i = 0; i < count; ++i)
1435 if (IOMMU_PTE_PRESENT(pte[i]))
1436 return -EBUSY;
bd0e5211 1437
cbb9d729
JR		 1438 if (page_size > PAGE_SIZE) {
1439 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1440 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1441 } else
1442 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
bd0e5211 1443
bd0e5211
JR		 1444 if (prot & IOMMU_PROT_IR)
1445 __pte |= IOMMU_PTE_IR;
1446 if (prot & IOMMU_PROT_IW)
1447 __pte |= IOMMU_PTE_IW;
1448
cbb9d729
JR		 1449 for (i = 0; i < count; ++i)
1450 pte[i] = __pte;
bd0e5211 1451
04bfdd84
JR		 1452 update_domain(dom);
1453
bd0e5211
JR		 1454 return 0;
1455}
1456
24cd7723
JR		 1457static unsigned long iommu_unmap_page(struct protection_domain *dom,
1458 unsigned long bus_addr,
1459 unsigned long page_size)
eb74ff6c 1460{
24cd7723
JR		 1461 unsigned long long unmap_size, unmapped;
1462 u64 *pte;
1463
1464 BUG_ON(!is_power_of_2(page_size));
1465
1466 unmapped = 0;
eb74ff6c 1467
24cd7723
JR		 1468 while (unmapped < page_size) {
1469
1470 pte = fetch_pte(dom, bus_addr);
1471
1472 if (!pte) {
1473 /*
1474 * No PTE for this address
1475 * move forward in 4kb steps
1476 */
1477 unmap_size = PAGE_SIZE;
1478 } else if (PM_PTE_LEVEL(*pte) == 0) {
1479 /* 4kb PTE found for this address */
1480 unmap_size = PAGE_SIZE;
1481 *pte = 0ULL;
1482 } else {
1483 int count, i;
1484
1485 /* Large PTE found which maps this address */
1486 unmap_size = PTE_PAGE_SIZE(*pte);
ed2f0795
AW		 1487
1488 /* Only unmap from the first pte in the page */
1489 if ((unmap_size - 1) & bus_addr)
1490 break;
24cd7723
JR		 1491 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1492 for (i = 0; i < count; i++)
1493 pte[i] = 0ULL;
1494 }
1495
1496 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1497 unmapped += unmap_size;
1498 }
1499
ed2f0795 1500 BUG_ON(unmapped && !is_power_of_2(unmapped));
eb74ff6c 1501
24cd7723 1502 return unmapped;
eb74ff6c 1503}
eb74ff6c 1504
431b2a20
JR		 1505/*
1506 * This function checks if a specific unity mapping entry is needed for
1507 * this specific IOMMU.
1508 */
bd0e5211
JR		 1509static int iommu_for_unity_map(struct amd_iommu *iommu,
1510 struct unity_map_entry *entry)
1511{
1512 u16 bdf, i;
1513
1514 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1515 bdf = amd_iommu_alias_table[i];
1516 if (amd_iommu_rlookup_table[bdf] == iommu)
1517 return 1;
1518 }
1519
1520 return 0;
1521}
1522
431b2a20
JR		 1523/*
1524 * This function actually applies the mapping to the page table of the
1525 * dma_ops domain.
1526 */
bd0e5211
JR		 1527static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1528 struct unity_map_entry *e)
1529{
1530 u64 addr;
1531 int ret;
1532
1533 for (addr = e->address_start; addr < e->address_end;
1534 addr += PAGE_SIZE) {
abdc5eb3 1535 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
cbb9d729 1536 PAGE_SIZE);
bd0e5211
JR		 1537 if (ret)
1538 return ret;
1539 /*
1540 * if unity mapping is in aperture range mark the page
1541 * as allocated in the aperture
1542 */
1543 if (addr < dma_dom->aperture_size)
c3239567 1544 __set_bit(addr >> PAGE_SHIFT,
384de729 1545 dma_dom->aperture[0]->bitmap);
bd0e5211
JR		 1546 }
1547
1548 return 0;
1549}
1550
171e7b37
JR		 1551/*
1552 * Init the unity mappings for a specific IOMMU in the system
1553 *
1554 * Basically iterates over all unity mapping entries and applies them to
1555 * the default domain DMA of that IOMMU if necessary.
1556 */
1557static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1558{
1559 struct unity_map_entry *entry;
1560 int ret;
1561
1562 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1563 if (!iommu_for_unity_map(iommu, entry))
1564 continue;
1565 ret = dma_ops_unity_map(iommu->default_dom, entry);
1566 if (ret)
1567 return ret;
1568 }
1569
1570 return 0;
1571}
1572
431b2a20
JR		 1573/*
1574 * Inits the unity mappings required for a specific device
1575 */
bd0e5211
JR		 1576static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1577 u16 devid)
1578{
1579 struct unity_map_entry *e;
1580 int ret;
1581
1582 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1583 if (!(devid >= e->devid_start && devid <= e->devid_end))
1584 continue;
1585 ret = dma_ops_unity_map(dma_dom, e);
1586 if (ret)
1587 return ret;
1588 }
1589
1590 return 0;
1591}
1592
431b2a20
JR		 1593/****************************************************************************
1594 *
1595 * The next functions belong to the address allocator for the dma_ops
1596 * interface functions. They work like the allocators in the other IOMMU
1597 * drivers. Its basically a bitmap which marks the allocated pages in
1598 * the aperture. Maybe it could be enhanced in the future to a more
1599 * efficient allocator.
1600 *
1601 ****************************************************************************/
d3086444 1602
431b2a20 1603/*
384de729 1604 * The address allocator core functions.
431b2a20
JR		 1605 *
1606 * called with domain->lock held
1607 */
384de729 1608
171e7b37
JR		 1609/*
1610 * Used to reserve address ranges in the aperture (e.g. for exclusion
1611 * ranges.
1612 */
1613static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1614 unsigned long start_page,
1615 unsigned int pages)
1616{
1617 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1618
1619 if (start_page + pages > last_page)
1620 pages = last_page - start_page;
1621
1622 for (i = start_page; i < start_page + pages; ++i) {
1623 int index = i / APERTURE_RANGE_PAGES;
1624 int page = i % APERTURE_RANGE_PAGES;
1625 __set_bit(page, dom->aperture[index]->bitmap);
1626 }
1627}
1628
9cabe89b
JR		 1629/*
1630 * This function is used to add a new aperture range to an existing
1631 * aperture in case of dma_ops domain allocation or address allocation
1632 * failure.
1633 */
576175c2 1634static int alloc_new_range(struct dma_ops_domain *dma_dom,
9cabe89b
JR		 1635 bool populate, gfp_t gfp)
1636{
1637 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
576175c2 1638 struct amd_iommu *iommu;
17f5b569 1639 unsigned long i, old_size;
9cabe89b 1640
f5e9705c
JR		 1641#ifdef CONFIG_IOMMU_STRESS
1642 populate = false;
1643#endif
1644
9cabe89b
JR		 1645 if (index >= APERTURE_MAX_RANGES)
1646 return -ENOMEM;
1647
1648 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1649 if (!dma_dom->aperture[index])
1650 return -ENOMEM;
1651
1652 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1653 if (!dma_dom->aperture[index]->bitmap)
1654 goto out_free;
1655
1656 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1657
1658 if (populate) {
1659 unsigned long address = dma_dom->aperture_size;
1660 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1661 u64 *pte, *pte_page;
1662
1663 for (i = 0; i < num_ptes; ++i) {
cbb9d729 1664 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
9cabe89b
JR		 1665 &pte_page, gfp);
1666 if (!pte)
1667 goto out_free;
1668
1669 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1670
1671 address += APERTURE_RANGE_SIZE / 64;
1672 }
1673 }
1674
17f5b569 1675 old_size = dma_dom->aperture_size;
9cabe89b
JR		 1676 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1677
17f5b569
JR		 1678 /* Reserve address range used for MSI messages */
1679 if (old_size < MSI_ADDR_BASE_LO &&
1680 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1681 unsigned long spage;
1682 int pages;
1683
1684 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1685 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1686
1687 dma_ops_reserve_addresses(dma_dom, spage, pages);
1688 }
1689
b595076a 1690 /* Initialize the exclusion range if necessary */
576175c2
JR		 1691 for_each_iommu(iommu) {
1692 if (iommu->exclusion_start &&
1693 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1694 && iommu->exclusion_start < dma_dom->aperture_size) {
1695 unsigned long startpage;
1696 int pages = iommu_num_pages(iommu->exclusion_start,
1697 iommu->exclusion_length,
1698 PAGE_SIZE);
1699 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1700 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1701 }
00cd122a
JR		 1702 }
1703
1704 /*
1705 * Check for areas already mapped as present in the new aperture
1706 * range and mark those pages as reserved in the allocator. Such
1707 * mappings may already exist as a result of requested unity
1708 * mappings for devices.
1709 */
1710 for (i = dma_dom->aperture[index]->offset;
1711 i < dma_dom->aperture_size;
1712 i += PAGE_SIZE) {
24cd7723 1713 u64 *pte = fetch_pte(&dma_dom->domain, i);
00cd122a
JR		 1714 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1715 continue;
1716
fcd0861d 1717 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
00cd122a
JR		 1718 }
1719
04bfdd84
JR		 1720 update_domain(&dma_dom->domain);
1721
9cabe89b
JR		 1722 return 0;
1723
1724out_free:
04bfdd84
JR		 1725 update_domain(&dma_dom->domain);
1726
9cabe89b
JR		 1727 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1728
1729 kfree(dma_dom->aperture[index]);
1730 dma_dom->aperture[index] = NULL;
1731
1732 return -ENOMEM;
1733}
1734
384de729
JR		 1735static unsigned long dma_ops_area_alloc(struct device *dev,
1736 struct dma_ops_domain *dom,
1737 unsigned int pages,
1738 unsigned long align_mask,
1739 u64 dma_mask,
1740 unsigned long start)
1741{
803b8cb4 1742 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
384de729
JR		 1743 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1744 int i = start >> APERTURE_RANGE_SHIFT;
1745 unsigned long boundary_size;
1746 unsigned long address = -1;
1747 unsigned long limit;
1748
803b8cb4
JR		 1749 next_bit >>= PAGE_SHIFT;
1750
384de729
JR		 1751 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1752 PAGE_SIZE) >> PAGE_SHIFT;
1753
1754 for (;i < max_index; ++i) {
1755 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1756
1757 if (dom->aperture[i]->offset >= dma_mask)
1758 break;
1759
1760 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1761 dma_mask >> PAGE_SHIFT);
1762
1763 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1764 limit, next_bit, pages, 0,
1765 boundary_size, align_mask);
1766 if (address != -1) {
1767 address = dom->aperture[i]->offset +
1768 (address << PAGE_SHIFT);
803b8cb4 1769 dom->next_address = address + (pages << PAGE_SHIFT);
384de729
JR		 1770 break;
1771 }
1772
1773 next_bit = 0;
1774 }
1775
1776 return address;
1777}
1778
d3086444
JR		 1779static unsigned long dma_ops_alloc_addresses(struct device *dev,
1780 struct dma_ops_domain *dom,
6d4f343f 1781 unsigned int pages,
832a90c3
JR		 1782 unsigned long align_mask,
1783 u64 dma_mask)
d3086444 1784{
d3086444 1785 unsigned long address;
d3086444 1786
fe16f088
JR		 1787#ifdef CONFIG_IOMMU_STRESS
1788 dom->next_address = 0;
1789 dom->need_flush = true;
1790#endif
d3086444 1791
384de729 1792 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
803b8cb4 1793 dma_mask, dom->next_address);
d3086444 1794
1c655773 1795 if (address == -1) {
803b8cb4 1796 dom->next_address = 0;
384de729
JR		 1797 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1798 dma_mask, 0);
1c655773
JR		 1799 dom->need_flush = true;
1800 }
d3086444 1801
384de729 1802 if (unlikely(address == -1))
8fd524b3 1803 address = DMA_ERROR_CODE;
d3086444
JR		 1804
1805 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1806
1807 return address;
1808}
1809
431b2a20
JR		 1810/*
1811 * The address free function.
1812 *
1813 * called with domain->lock held
1814 */
d3086444
JR		 1815static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1816 unsigned long address,
1817 unsigned int pages)
1818{
384de729
JR		 1819 unsigned i = address >> APERTURE_RANGE_SHIFT;
1820 struct aperture_range *range = dom->aperture[i];
80be308d 1821
384de729
JR		 1822 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1823
47bccd6b
JR		 1824#ifdef CONFIG_IOMMU_STRESS
1825 if (i < 4)
1826 return;
1827#endif
80be308d 1828
803b8cb4 1829 if (address >= dom->next_address)
80be308d 1830 dom->need_flush = true;
384de729
JR		 1831
1832 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
803b8cb4 1833
a66022c4 1834 bitmap_clear(range->bitmap, address, pages);
384de729 1835
d3086444
JR		 1836}
1837
431b2a20
JR		 1838/****************************************************************************
1839 *
1840 * The next functions belong to the domain allocation. A domain is
1841 * allocated for every IOMMU as the default domain. If device isolation
1842 * is enabled, every device get its own domain. The most important thing
1843 * about domains is the page table mapping the DMA address space they
1844 * contain.
1845 *
1846 ****************************************************************************/
1847
aeb26f55
JR		 1848/*
1849 * This function adds a protection domain to the global protection domain list
1850 */
1851static void add_domain_to_list(struct protection_domain *domain)
1852{
1853 unsigned long flags;
1854
1855 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1856 list_add(&domain->list, &amd_iommu_pd_list);
1857 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1858}
1859
1860/*
1861 * This function removes a protection domain to the global
1862 * protection domain list
1863 */
1864static void del_domain_from_list(struct protection_domain *domain)
1865{
1866 unsigned long flags;
1867
1868 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1869 list_del(&domain->list);
1870 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1871}
1872
ec487d1a
JR		 1873static u16 domain_id_alloc(void)
1874{
1875 unsigned long flags;
1876 int id;
1877
1878 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1879 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1880 BUG_ON(id == 0);
1881 if (id > 0 && id < MAX_DOMAIN_ID)
1882 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1883 else
1884 id = 0;
1885 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1886
1887 return id;
1888}
1889
a2acfb75
JR		 1890static void domain_id_free(int id)
1891{
1892 unsigned long flags;
1893
1894 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1895 if (id > 0 && id < MAX_DOMAIN_ID)
1896 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1897 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1898}
a2acfb75 1899
86db2e5d 1900static void free_pagetable(struct protection_domain *domain)
ec487d1a
JR		 1901{
1902 int i, j;
1903 u64 *p1, *p2, *p3;
1904
86db2e5d 1905 p1 = domain->pt_root;
ec487d1a
JR		 1906
1907 if (!p1)
1908 return;
1909
1910 for (i = 0; i < 512; ++i) {
1911 if (!IOMMU_PTE_PRESENT(p1[i]))
1912 continue;
1913
1914 p2 = IOMMU_PTE_PAGE(p1[i]);
3cc3d84b 1915 for (j = 0; j < 512; ++j) {
ec487d1a
JR		 1916 if (!IOMMU_PTE_PRESENT(p2[j]))
1917 continue;
1918 p3 = IOMMU_PTE_PAGE(p2[j]);
1919 free_page((unsigned long)p3);
1920 }
1921
1922 free_page((unsigned long)p2);
1923 }
1924
1925 free_page((unsigned long)p1);
86db2e5d
JR		 1926
1927 domain->pt_root = NULL;
ec487d1a
JR		 1928}
1929
b16137b1
JR		 1930static void free_gcr3_tbl_level1(u64 *tbl)
1931{
1932 u64 *ptr;
1933 int i;
1934
1935 for (i = 0; i < 512; ++i) {
1936 if (!(tbl[i] & GCR3_VALID))
1937 continue;
1938
1939 ptr = __va(tbl[i] & PAGE_MASK);
1940
1941 free_page((unsigned long)ptr);
1942 }
1943}
1944
1945static void free_gcr3_tbl_level2(u64 *tbl)
1946{
1947 u64 *ptr;
1948 int i;
1949
1950 for (i = 0; i < 512; ++i) {
1951 if (!(tbl[i] & GCR3_VALID))
1952 continue;
1953
1954 ptr = __va(tbl[i] & PAGE_MASK);
1955
1956 free_gcr3_tbl_level1(ptr);
1957 }
1958}
1959
52815b75
JR		 1960static void free_gcr3_table(struct protection_domain *domain)
1961{
b16137b1
JR		 1962 if (domain->glx == 2)
1963 free_gcr3_tbl_level2(domain->gcr3_tbl);
1964 else if (domain->glx == 1)
1965 free_gcr3_tbl_level1(domain->gcr3_tbl);
1966 else if (domain->glx != 0)
1967 BUG();
1968
52815b75
JR		 1969 free_page((unsigned long)domain->gcr3_tbl);
1970}
1971
431b2a20
JR		 1972/*
1973 * Free a domain, only used if something went wrong in the
1974 * allocation path and we need to free an already allocated page table
1975 */
ec487d1a
JR		 1976static void dma_ops_domain_free(struct dma_ops_domain *dom)
1977{
384de729
JR		 1978 int i;
1979
ec487d1a
JR		 1980 if (!dom)
1981 return;
1982
aeb26f55
JR		 1983 del_domain_from_list(&dom->domain);
1984
86db2e5d 1985 free_pagetable(&dom->domain);
ec487d1a 1986
384de729
JR		 1987 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1988 if (!dom->aperture[i])
1989 continue;
1990 free_page((unsigned long)dom->aperture[i]->bitmap);
1991 kfree(dom->aperture[i]);
1992 }
ec487d1a
JR		 1993
1994 kfree(dom);
1995}
1996
431b2a20
JR		 1997/*
1998 * Allocates a new protection domain usable for the dma_ops functions.
b595076a 1999 * It also initializes the page table and the address allocator data
431b2a20
JR		 2000 * structures required for the dma_ops interface
2001 */
87a64d52 2002static struct dma_ops_domain *dma_ops_domain_alloc(void)
ec487d1a
JR		 2003{
2004 struct dma_ops_domain *dma_dom;
ec487d1a
JR		 2005
2006 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2007 if (!dma_dom)
2008 return NULL;
2009
2010 spin_lock_init(&dma_dom->domain.lock);
2011
2012 dma_dom->domain.id = domain_id_alloc();
2013 if (dma_dom->domain.id == 0)
2014 goto free_dma_dom;
7c392cbe 2015 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
8f7a017c 2016 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
ec487d1a 2017 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
9fdb19d6 2018 dma_dom->domain.flags = PD_DMA_OPS_MASK;
ec487d1a
JR		 2019 dma_dom->domain.priv = dma_dom;
2020 if (!dma_dom->domain.pt_root)
2021 goto free_dma_dom;
ec487d1a 2022
1c655773 2023 dma_dom->need_flush = false;
bd60b735 2024 dma_dom->target_dev = 0xffff;
1c655773 2025
aeb26f55
JR		 2026 add_domain_to_list(&dma_dom->domain);
2027
576175c2 2028 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
ec487d1a 2029 goto free_dma_dom;
ec487d1a 2030
431b2a20 2031 /*
ec487d1a
JR		 2032 * mark the first page as allocated so we never return 0 as
2033 * a valid dma-address. So we can use 0 as error value
431b2a20 2034 */
384de729 2035 dma_dom->aperture[0]->bitmap[0] = 1;
803b8cb4 2036 dma_dom->next_address = 0;
ec487d1a 2037
ec487d1a
JR		 2038
2039 return dma_dom;
2040
2041free_dma_dom:
2042 dma_ops_domain_free(dma_dom);
2043
2044 return NULL;
2045}
2046
5b28df6f
JR		 2047/*
2048 * little helper function to check whether a given protection domain is a
2049 * dma_ops domain
2050 */
2051static bool dma_ops_domain(struct protection_domain *domain)
2052{
2053 return domain->flags & PD_DMA_OPS_MASK;
2054}
2055
fd7b5535 2056static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
b20ac0d4 2057{
132bd68f 2058 u64 pte_root = 0;
ee6c2868 2059 u64 flags = 0;
863c74eb 2060
132bd68f
JR		 2061 if (domain->mode != PAGE_MODE_NONE)
2062 pte_root = virt_to_phys(domain->pt_root);
2063
38ddf41b
JR		 2064 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2065 << DEV_ENTRY_MODE_SHIFT;
2066 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
b20ac0d4 2067
ee6c2868
JR		 2068 flags = amd_iommu_dev_table[devid].data[1];
2069
fd7b5535
JR		 2070 if (ats)
2071 flags |= DTE_FLAG_IOTLB;
2072
52815b75
JR		 2073 if (domain->flags & PD_IOMMUV2_MASK) {
2074 u64 gcr3 = __pa(domain->gcr3_tbl);
2075 u64 glx = domain->glx;
2076 u64 tmp;
2077
2078 pte_root |= DTE_FLAG_GV;
2079 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2080
2081 /* First mask out possible old values for GCR3 table */
2082 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2083 flags &= ~tmp;
2084
2085 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2086 flags &= ~tmp;
2087
2088 /* Encode GCR3 table into DTE */
2089 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2090 pte_root |= tmp;
2091
2092 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2093 flags |= tmp;
2094
2095 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2096 flags |= tmp;
2097 }
2098
ee6c2868
JR		 2099 flags &= ~(0xffffUL);
2100 flags |= domain->id;
2101
2102 amd_iommu_dev_table[devid].data[1] = flags;
2103 amd_iommu_dev_table[devid].data[0] = pte_root;
15898bbc
JR		 2104}
2105
2106static void clear_dte_entry(u16 devid)
2107{
15898bbc
JR		 2108 /* remove entry from the device table seen by the hardware */
2109 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2110 amd_iommu_dev_table[devid].data[1] = 0;
15898bbc
JR		 2111
2112 amd_iommu_apply_erratum_63(devid);
7f760ddd
JR		 2113}
2114
ec9e79ef
JR		 2115static void do_attach(struct iommu_dev_data *dev_data,
2116 struct protection_domain *domain)
7f760ddd 2117{
7f760ddd 2118 struct amd_iommu *iommu;
ec9e79ef 2119 bool ats;
fd7b5535 2120
ec9e79ef
JR		 2121 iommu = amd_iommu_rlookup_table[dev_data->devid];
2122 ats = dev_data->ats.enabled;
7f760ddd
JR		 2123
2124 /* Update data structures */
2125 dev_data->domain = domain;
2126 list_add(&dev_data->list, &domain->dev_list);
f62dda66 2127 set_dte_entry(dev_data->devid, domain, ats);
7f760ddd
JR		 2128
2129 /* Do reference counting */
2130 domain->dev_iommu[iommu->index] += 1;
2131 domain->dev_cnt += 1;
2132
2133 /* Flush the DTE entry */
6c542047 2134 device_flush_dte(dev_data);
7f760ddd
JR		 2135}
2136
ec9e79ef 2137static void do_detach(struct iommu_dev_data *dev_data)
7f760ddd 2138{
7f760ddd 2139 struct amd_iommu *iommu;
7f760ddd 2140
ec9e79ef 2141 iommu = amd_iommu_rlookup_table[dev_data->devid];
15898bbc
JR		 2142
2143 /* decrease reference counters */
7f760ddd
JR		 2144 dev_data->domain->dev_iommu[iommu->index] -= 1;
2145 dev_data->domain->dev_cnt -= 1;
2146
2147 /* Update data structures */
2148 dev_data->domain = NULL;
2149 list_del(&dev_data->list);
f62dda66 2150 clear_dte_entry(dev_data->devid);
15898bbc 2151
7f760ddd 2152 /* Flush the DTE entry */
6c542047 2153 device_flush_dte(dev_data);
2b681faf
JR		 2154}
2155
2156/*
2157 * If a device is not yet associated with a domain, this function does
2158 * assigns it visible for the hardware
2159 */
ec9e79ef 2160static int __attach_device(struct iommu_dev_data *dev_data,
15898bbc 2161 struct protection_domain *domain)
2b681faf 2162{
84fe6c19 2163 int ret;
657cbb6b 2164
2b681faf
JR		 2165 /* lock domain */
2166 spin_lock(&domain->lock);
2167
71f77580
JR		 2168 if (dev_data->alias_data != NULL) {
2169 struct iommu_dev_data *alias_data = dev_data->alias_data;
15898bbc 2170
2b02b091
JR		 2171 /* Some sanity checks */
2172 ret = -EBUSY;
2173 if (alias_data->domain != NULL &&
2174 alias_data->domain != domain)
2175 goto out_unlock;
eba6ac60 2176
2b02b091
JR		 2177 if (dev_data->domain != NULL &&
2178 dev_data->domain != domain)
2179 goto out_unlock;
15898bbc 2180
2b02b091 2181 /* Do real assignment */
7f760ddd 2182 if (alias_data->domain == NULL)
ec9e79ef 2183 do_attach(alias_data, domain);
24100055
JR		 2184
2185 atomic_inc(&alias_data->bind);
657cbb6b 2186 }
15898bbc 2187
7f760ddd 2188 if (dev_data->domain == NULL)
ec9e79ef 2189 do_attach(dev_data, domain);
eba6ac60 2190
24100055
JR		 2191 atomic_inc(&dev_data->bind);
2192
84fe6c19
JL		 2193 ret = 0;
2194
2195out_unlock:
2196
eba6ac60
JR		 2197 /* ready */
2198 spin_unlock(&domain->lock);
15898bbc 2199
84fe6c19 2200 return ret;
0feae533 2201}
b20ac0d4 2202
52815b75
JR		 2203
2204static void pdev_iommuv2_disable(struct pci_dev *pdev)
2205{
2206 pci_disable_ats(pdev);
2207 pci_disable_pri(pdev);
2208 pci_disable_pasid(pdev);
2209}
2210
6a113ddc
JR		 2211/* FIXME: Change generic reset-function to do the same */
2212static int pri_reset_while_enabled(struct pci_dev *pdev)
2213{
2214 u16 control;
2215 int pos;
2216
46277b75 2217 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
6a113ddc
JR		 2218 if (!pos)
2219 return -EINVAL;
2220
46277b75
JR		 2221 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2222 control |= PCI_PRI_CTRL_RESET;
2223 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
6a113ddc
JR		 2224
2225 return 0;
2226}
2227
52815b75
JR		 2228static int pdev_iommuv2_enable(struct pci_dev *pdev)
2229{
6a113ddc
JR		 2230 bool reset_enable;
2231 int reqs, ret;
2232
2233 /* FIXME: Hardcode number of outstanding requests for now */
2234 reqs = 32;
2235 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2236 reqs = 1;
2237 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
52815b75
JR		 2238
2239 /* Only allow access to user-accessible pages */
2240 ret = pci_enable_pasid(pdev, 0);
2241 if (ret)
2242 goto out_err;
2243
2244 /* First reset the PRI state of the device */
2245 ret = pci_reset_pri(pdev);
2246 if (ret)
2247 goto out_err;
2248
6a113ddc
JR		 2249 /* Enable PRI */
2250 ret = pci_enable_pri(pdev, reqs);
52815b75
JR		 2251 if (ret)
2252 goto out_err;
2253
6a113ddc
JR		 2254 if (reset_enable) {
2255 ret = pri_reset_while_enabled(pdev);
2256 if (ret)
2257 goto out_err;
2258 }
2259
52815b75
JR		 2260 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2261 if (ret)
2262 goto out_err;
2263
2264 return 0;
2265
2266out_err:
2267 pci_disable_pri(pdev);
2268 pci_disable_pasid(pdev);
2269
2270 return ret;
2271}
2272
c99afa25 2273/* FIXME: Move this to PCI code */
a3b93121 2274#define PCI_PRI_TLP_OFF (1 << 15)
c99afa25 2275
98f1ad25 2276static bool pci_pri_tlp_required(struct pci_dev *pdev)
c99afa25 2277{
a3b93121 2278 u16 status;
c99afa25
JR		 2279 int pos;
2280
46277b75 2281 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c99afa25
JR		 2282 if (!pos)
2283 return false;
2284
a3b93121 2285 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
c99afa25 2286
a3b93121 2287 return (status & PCI_PRI_TLP_OFF) ? true : false;
c99afa25
JR		 2288}
2289
407d733e 2290/*
df805abb 2291 * If a device is not yet associated with a domain, this function
407d733e
JR		 2292 * assigns it visible for the hardware
2293 */
15898bbc
JR		 2294static int attach_device(struct device *dev,
2295 struct protection_domain *domain)
0feae533 2296{
fd7b5535 2297 struct pci_dev *pdev = to_pci_dev(dev);
ea61cddb 2298 struct iommu_dev_data *dev_data;
eba6ac60 2299 unsigned long flags;
15898bbc 2300 int ret;
eba6ac60 2301
ea61cddb
JR		 2302 dev_data = get_dev_data(dev);
2303
52815b75
JR		 2304 if (domain->flags & PD_IOMMUV2_MASK) {
2305 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2306 return -EINVAL;
2307
2308 if (pdev_iommuv2_enable(pdev) != 0)
2309 return -EINVAL;
2310
2311 dev_data->ats.enabled = true;
2312 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
c99afa25 2313 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
52815b75
JR		 2314 } else if (amd_iommu_iotlb_sup &&
2315 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
ea61cddb
JR		 2316 dev_data->ats.enabled = true;
2317 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2318 }
fd7b5535 2319
eba6ac60 2320 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2321 ret = __attach_device(dev_data, domain);
b20ac0d4
JR		 2322 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2323
0feae533
JR		 2324 /*
2325 * We might boot into a crash-kernel here. The crashed kernel
2326 * left the caches in the IOMMU dirty. So we have to flush
2327 * here to evict all dirty stuff.
2328 */
17b124bf 2329 domain_flush_tlb_pde(domain);
15898bbc
JR		 2330
2331 return ret;
b20ac0d4
JR		 2332}
2333
355bf553
JR		 2334/*
2335 * Removes a device from a protection domain (unlocked)
2336 */
ec9e79ef 2337static void __detach_device(struct iommu_dev_data *dev_data)
355bf553 2338{
2ca76279 2339 struct protection_domain *domain;
7c392cbe 2340 unsigned long flags;
c4596114 2341
7f760ddd 2342 BUG_ON(!dev_data->domain);
355bf553 2343
2ca76279
JR		 2344 domain = dev_data->domain;
2345
2346 spin_lock_irqsave(&domain->lock, flags);
24100055 2347
71f77580
JR		 2348 if (dev_data->alias_data != NULL) {
2349 struct iommu_dev_data *alias_data = dev_data->alias_data;
2350
7f760ddd 2351 if (atomic_dec_and_test(&alias_data->bind))
ec9e79ef 2352 do_detach(alias_data);
24100055
JR		 2353 }
2354
7f760ddd 2355 if (atomic_dec_and_test(&dev_data->bind))
ec9e79ef 2356 do_detach(dev_data);
7f760ddd 2357
2ca76279 2358 spin_unlock_irqrestore(&domain->lock, flags);
21129f78
JR		 2359
2360 /*
2361 * If we run in passthrough mode the device must be assigned to the
d3ad9373
JR		 2362 * passthrough domain if it is detached from any other domain.
2363 * Make sure we can deassign from the pt_domain itself.
21129f78 2364 */
5abcdba4 2365 if (dev_data->passthrough &&
d3ad9373 2366 (dev_data->domain == NULL && domain != pt_domain))
ec9e79ef 2367 __attach_device(dev_data, pt_domain);
355bf553
JR		 2368}
2369
2370/*
2371 * Removes a device from a protection domain (with devtable_lock held)
2372 */
15898bbc 2373static void detach_device(struct device *dev)
355bf553 2374{
52815b75 2375 struct protection_domain *domain;
ea61cddb 2376 struct iommu_dev_data *dev_data;
355bf553
JR		 2377 unsigned long flags;
2378
ec9e79ef 2379 dev_data = get_dev_data(dev);
52815b75 2380 domain = dev_data->domain;
ec9e79ef 2381
355bf553
JR		 2382 /* lock device table */
2383 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
ec9e79ef 2384 __detach_device(dev_data);
355bf553 2385 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
fd7b5535 2386
52815b75
JR		 2387 if (domain->flags & PD_IOMMUV2_MASK)
2388 pdev_iommuv2_disable(to_pci_dev(dev));
2389 else if (dev_data->ats.enabled)
ea61cddb 2390 pci_disable_ats(to_pci_dev(dev));
52815b75
JR		 2391
2392 dev_data->ats.enabled = false;
355bf553 2393}
e275a2a0 2394
15898bbc
JR		 2395/*
2396 * Find out the protection domain structure for a given PCI device. This
2397 * will give us the pointer to the page table root for example.
2398 */
2399static struct protection_domain *domain_for_device(struct device *dev)
2400{
71f77580 2401 struct iommu_dev_data *dev_data;
2b02b091 2402 struct protection_domain *dom = NULL;
15898bbc 2403 unsigned long flags;
15898bbc 2404
657cbb6b 2405 dev_data = get_dev_data(dev);
15898bbc 2406
2b02b091
JR		 2407 if (dev_data->domain)
2408 return dev_data->domain;
15898bbc 2409
71f77580
JR		 2410 if (dev_data->alias_data != NULL) {
2411 struct iommu_dev_data *alias_data = dev_data->alias_data;
2b02b091
JR		 2412
2413 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2414 if (alias_data->domain != NULL) {
2415 __attach_device(dev_data, alias_data->domain);
2416 dom = alias_data->domain;
2417 }
2418 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2419 }
15898bbc
JR		 2420
2421 return dom;
2422}
2423
e275a2a0
JR		 2424static int device_change_notifier(struct notifier_block *nb,
2425 unsigned long action, void *data)
2426{
e275a2a0 2427 struct dma_ops_domain *dma_domain;
5abcdba4
JR		 2428 struct protection_domain *domain;
2429 struct iommu_dev_data *dev_data;
2430 struct device *dev = data;
e275a2a0 2431 struct amd_iommu *iommu;
1ac4cbbc 2432 unsigned long flags;
5abcdba4 2433 u16 devid;
e275a2a0 2434
98fc5a69
JR		 2435 if (!check_device(dev))
2436 return 0;
e275a2a0 2437
5abcdba4
JR		 2438 devid = get_device_id(dev);
2439 iommu = amd_iommu_rlookup_table[devid];
2440 dev_data = get_dev_data(dev);
e275a2a0
JR		 2441
2442 switch (action) {
c1eee67b 2443 case BUS_NOTIFY_UNBOUND_DRIVER:
657cbb6b
JR		 2444
2445 domain = domain_for_device(dev);
2446
e275a2a0
JR		 2447 if (!domain)
2448 goto out;
5abcdba4 2449 if (dev_data->passthrough)
a1ca331c 2450 break;
15898bbc 2451 detach_device(dev);
1ac4cbbc
JR		 2452 break;
2453 case BUS_NOTIFY_ADD_DEVICE:
657cbb6b
JR		 2454
2455 iommu_init_device(dev);
2456
2c9195e9
JR		 2457 /*
2458 * dev_data is still NULL and
2459 * got initialized in iommu_init_device
2460 */
2461 dev_data = get_dev_data(dev);
2462
2463 if (iommu_pass_through || dev_data->iommu_v2) {
2464 dev_data->passthrough = true;
2465 attach_device(dev, pt_domain);
2466 break;
2467 }
2468
657cbb6b
JR		 2469 domain = domain_for_device(dev);
2470
1ac4cbbc
JR		 2471 /* allocate a protection domain if a device is added */
2472 dma_domain = find_protection_domain(devid);
c2a2876e
JR		 2473 if (!dma_domain) {
2474 dma_domain = dma_ops_domain_alloc();
2475 if (!dma_domain)
2476 goto out;
2477 dma_domain->target_dev = devid;
2478
2479 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2480 list_add_tail(&dma_domain->list, &iommu_pd_list);
2481 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2482 }
ac1534a5 2483
2c9195e9 2484 dev->archdata.dma_ops = &amd_iommu_dma_ops;
ac1534a5 2485
e275a2a0 2486 break;
657cbb6b
JR		 2487 case BUS_NOTIFY_DEL_DEVICE:
2488
2489 iommu_uninit_device(dev);
2490
e275a2a0
JR		 2491 default:
2492 goto out;
2493 }
2494
e275a2a0
JR		 2495 iommu_completion_wait(iommu);
2496
2497out:
2498 return 0;
2499}
2500
b25ae679 2501static struct notifier_block device_nb = {
e275a2a0
JR		 2502 .notifier_call = device_change_notifier,
2503};
355bf553 2504
8638c491
JR		 2505void amd_iommu_init_notifier(void)
2506{
2507 bus_register_notifier(&pci_bus_type, &device_nb);
2508}
2509
431b2a20
JR		 2510/*****************************************************************************
2511 *
2512 * The next functions belong to the dma_ops mapping/unmapping code.
2513 *
2514 *****************************************************************************/
2515
2516/*
2517 * In the dma_ops path we only have the struct device. This function
2518 * finds the corresponding IOMMU, the protection domain and the
2519 * requestor id for a given device.
2520 * If the device is not yet associated with a domain this is also done
2521 * in this function.
2522 */
94f6d190 2523static struct protection_domain *get_domain(struct device *dev)
b20ac0d4 2524{
94f6d190 2525 struct protection_domain *domain;
b20ac0d4 2526 struct dma_ops_domain *dma_dom;
94f6d190 2527 u16 devid = get_device_id(dev);
b20ac0d4 2528
f99c0f1c 2529 if (!check_device(dev))
94f6d190 2530 return ERR_PTR(-EINVAL);
b20ac0d4 2531
94f6d190
JR		 2532 domain = domain_for_device(dev);
2533 if (domain != NULL && !dma_ops_domain(domain))
2534 return ERR_PTR(-EBUSY);
f99c0f1c 2535
94f6d190
JR		 2536 if (domain != NULL)
2537 return domain;
b20ac0d4 2538
df805abb 2539 /* Device not bound yet - bind it */
94f6d190 2540 dma_dom = find_protection_domain(devid);
15898bbc 2541 if (!dma_dom)
94f6d190
JR		 2542 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2543 attach_device(dev, &dma_dom->domain);
15898bbc 2544 DUMP_printk("Using protection domain %d for device %s\n",
94f6d190 2545 dma_dom->domain.id, dev_name(dev));
f91ba190 2546
94f6d190 2547 return &dma_dom->domain;
b20ac0d4
JR		 2548}
2549
04bfdd84
JR		 2550static void update_device_table(struct protection_domain *domain)
2551{
492667da 2552 struct iommu_dev_data *dev_data;
04bfdd84 2553
ea61cddb
JR		 2554 list_for_each_entry(dev_data, &domain->dev_list, list)
2555 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
04bfdd84
JR		 2556}
2557
2558static void update_domain(struct protection_domain *domain)
2559{
2560 if (!domain->updated)
2561 return;
2562
2563 update_device_table(domain);
17b124bf
JR		 2564
2565 domain_flush_devices(domain);
2566 domain_flush_tlb_pde(domain);
04bfdd84
JR		 2567
2568 domain->updated = false;
2569}
2570
8bda3092
JR		 2571/*
2572 * This function fetches the PTE for a given address in the aperture
2573 */
2574static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2575 unsigned long address)
2576{
384de729 2577 struct aperture_range *aperture;
8bda3092
JR		 2578 u64 *pte, *pte_page;
2579
384de729
JR		 2580 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2581 if (!aperture)
2582 return NULL;
2583
2584 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
8bda3092 2585 if (!pte) {
cbb9d729 2586 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
abdc5eb3 2587 GFP_ATOMIC);
384de729
JR		 2588 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2589 } else
8c8c143c 2590 pte += PM_LEVEL_INDEX(0, address);
8bda3092 2591
04bfdd84 2592 update_domain(&dom->domain);
8bda3092
JR		 2593
2594 return pte;
2595}
2596
431b2a20
JR		 2597/*
2598 * This is the generic map function. It maps one 4kb page at paddr to
2599 * the given address in the DMA address space for the domain.
2600 */
680525e0 2601static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
cb76c322
JR		 2602 unsigned long address,
2603 phys_addr_t paddr,
2604 int direction)
2605{
2606 u64 *pte, __pte;
2607
2608 WARN_ON(address > dom->aperture_size);
2609
2610 paddr &= PAGE_MASK;
2611
8bda3092 2612 pte = dma_ops_get_pte(dom, address);
53812c11 2613 if (!pte)
8fd524b3 2614 return DMA_ERROR_CODE;
cb76c322
JR		 2615
2616 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2617
2618 if (direction == DMA_TO_DEVICE)
2619 __pte |= IOMMU_PTE_IR;
2620 else if (direction == DMA_FROM_DEVICE)
2621 __pte |= IOMMU_PTE_IW;
2622 else if (direction == DMA_BIDIRECTIONAL)
2623 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2624
2625 WARN_ON(*pte);
2626
2627 *pte = __pte;
2628
2629 return (dma_addr_t)address;
2630}
2631
431b2a20
JR		 2632/*
2633 * The generic unmapping function for on page in the DMA address space.
2634 */
680525e0 2635static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
cb76c322
JR		 2636 unsigned long address)
2637{
384de729 2638 struct aperture_range *aperture;
cb76c322
JR		 2639 u64 *pte;
2640
2641 if (address >= dom->aperture_size)
2642 return;
2643
384de729
JR		 2644 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2645 if (!aperture)
2646 return;
2647
2648 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2649 if (!pte)
2650 return;
cb76c322 2651
8c8c143c 2652 pte += PM_LEVEL_INDEX(0, address);
cb76c322
JR		 2653
2654 WARN_ON(!*pte);
2655
2656 *pte = 0ULL;
2657}
2658
431b2a20
JR		 2659/*
2660 * This function contains common code for mapping of a physically
24f81160
JR		 2661 * contiguous memory region into DMA address space. It is used by all
2662 * mapping functions provided with this IOMMU driver.
431b2a20
JR		 2663 * Must be called with the domain lock held.
2664 */
cb76c322 2665static dma_addr_t __map_single(struct device *dev,
cb76c322
JR		 2666 struct dma_ops_domain *dma_dom,
2667 phys_addr_t paddr,
2668 size_t size,
6d4f343f 2669 int dir,
832a90c3
JR		 2670 bool align,
2671 u64 dma_mask)
cb76c322
JR		 2672{
2673 dma_addr_t offset = paddr & ~PAGE_MASK;
53812c11 2674 dma_addr_t address, start, ret;
cb76c322 2675 unsigned int pages;
6d4f343f 2676 unsigned long align_mask = 0;
cb76c322
JR		 2677 int i;
2678
e3c449f5 2679 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
cb76c322
JR		 2680 paddr &= PAGE_MASK;
2681
8ecaf8f1
JR		 2682 INC_STATS_COUNTER(total_map_requests);
2683
c1858976
JR		 2684 if (pages > 1)
2685 INC_STATS_COUNTER(cross_page);
2686
6d4f343f
JR		 2687 if (align)
2688 align_mask = (1UL << get_order(size)) - 1;
2689
11b83888 2690retry:
832a90c3
JR		 2691 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2692 dma_mask);
8fd524b3 2693 if (unlikely(address == DMA_ERROR_CODE)) {
11b83888
JR		 2694 /*
2695 * setting next_address here will let the address
2696 * allocator only scan the new allocated range in the
2697 * first run. This is a small optimization.
2698 */
2699 dma_dom->next_address = dma_dom->aperture_size;
2700
576175c2 2701 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
11b83888
JR		 2702 goto out;
2703
2704 /*
af901ca1 2705 * aperture was successfully enlarged by 128 MB, try
11b83888
JR		 2706 * allocation again
2707 */
2708 goto retry;
2709 }
cb76c322
JR		 2710
2711 start = address;
2712 for (i = 0; i < pages; ++i) {
680525e0 2713 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
8fd524b3 2714 if (ret == DMA_ERROR_CODE)
53812c11
JR		 2715 goto out_unmap;
2716
cb76c322
JR		 2717 paddr += PAGE_SIZE;
2718 start += PAGE_SIZE;
2719 }
2720 address += offset;
2721
5774f7c5
JR		 2722 ADD_STATS_COUNTER(alloced_io_mem, size);
2723
afa9fdc2 2724 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
17b124bf 2725 domain_flush_tlb(&dma_dom->domain);
1c655773 2726 dma_dom->need_flush = false;
318afd41 2727 } else if (unlikely(amd_iommu_np_cache))
17b124bf 2728 domain_flush_pages(&dma_dom->domain, address, size);
270cab24 2729
cb76c322
JR		 2730out:
2731 return address;
53812c11
JR		 2732
2733out_unmap:
2734
2735 for (--i; i >= 0; --i) {
2736 start -= PAGE_SIZE;
680525e0 2737 dma_ops_domain_unmap(dma_dom, start);
53812c11
JR		 2738 }
2739
2740 dma_ops_free_addresses(dma_dom, address, pages);
2741
8fd524b3 2742 return DMA_ERROR_CODE;
cb76c322
JR		 2743}
2744
431b2a20
JR		 2745/*
2746 * Does the reverse of the __map_single function. Must be called with
2747 * the domain lock held too
2748 */
cd8c82e8 2749static void __unmap_single(struct dma_ops_domain *dma_dom,
cb76c322
JR		 2750 dma_addr_t dma_addr,
2751 size_t size,
2752 int dir)
2753{
04e0463e 2754 dma_addr_t flush_addr;
cb76c322
JR		 2755 dma_addr_t i, start;
2756 unsigned int pages;
2757
8fd524b3 2758 if ((dma_addr == DMA_ERROR_CODE) ||
b8d9905d 2759 (dma_addr + size > dma_dom->aperture_size))
cb76c322
JR		 2760 return;
2761
04e0463e 2762 flush_addr = dma_addr;
e3c449f5 2763 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
cb76c322
JR		 2764 dma_addr &= PAGE_MASK;
2765 start = dma_addr;
2766
2767 for (i = 0; i < pages; ++i) {
680525e0 2768 dma_ops_domain_unmap(dma_dom, start);
cb76c322
JR		 2769 start += PAGE_SIZE;
2770 }
2771
5774f7c5
JR		 2772 SUB_STATS_COUNTER(alloced_io_mem, size);
2773
cb76c322 2774 dma_ops_free_addresses(dma_dom, dma_addr, pages);
270cab24 2775
80be308d 2776 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
17b124bf 2777 domain_flush_pages(&dma_dom->domain, flush_addr, size);
80be308d
JR		 2778 dma_dom->need_flush = false;
2779 }
cb76c322
JR		 2780}
2781
431b2a20
JR		 2782/*
2783 * The exported map_single function for dma_ops.
2784 */
51491367
FT		 2785static dma_addr_t map_page(struct device *dev, struct page *page,
2786 unsigned long offset, size_t size,
2787 enum dma_data_direction dir,
2788 struct dma_attrs *attrs)
4da70b9e
JR		 2789{
2790 unsigned long flags;
4da70b9e 2791 struct protection_domain *domain;
4da70b9e 2792 dma_addr_t addr;
832a90c3 2793 u64 dma_mask;
51491367 2794 phys_addr_t paddr = page_to_phys(page) + offset;
4da70b9e 2795
0f2a86f2
JR		 2796 INC_STATS_COUNTER(cnt_map_single);
2797
94f6d190
JR		 2798 domain = get_domain(dev);
2799 if (PTR_ERR(domain) == -EINVAL)
4da70b9e 2800 return (dma_addr_t)paddr;
94f6d190
JR		 2801 else if (IS_ERR(domain))
2802 return DMA_ERROR_CODE;
4da70b9e 2803
f99c0f1c
JR		 2804 dma_mask = *dev->dma_mask;
2805
4da70b9e 2806 spin_lock_irqsave(&domain->lock, flags);
94f6d190 2807
cd8c82e8 2808 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
832a90c3 2809 dma_mask);
8fd524b3 2810 if (addr == DMA_ERROR_CODE)
4da70b9e
JR		 2811 goto out;
2812
17b124bf 2813 domain_flush_complete(domain);
4da70b9e
JR		 2814
2815out:
2816 spin_unlock_irqrestore(&domain->lock, flags);
2817
2818 return addr;
2819}
2820
431b2a20
JR		 2821/*
2822 * The exported unmap_single function for dma_ops.
2823 */
51491367
FT		 2824static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2825 enum dma_data_direction dir, struct dma_attrs *attrs)
4da70b9e
JR		 2826{
2827 unsigned long flags;
4da70b9e 2828 struct protection_domain *domain;
4da70b9e 2829
146a6917
JR		 2830 INC_STATS_COUNTER(cnt_unmap_single);
2831
94f6d190
JR		 2832 domain = get_domain(dev);
2833 if (IS_ERR(domain))
5b28df6f
JR		 2834 return;
2835
4da70b9e
JR		 2836 spin_lock_irqsave(&domain->lock, flags);
2837
cd8c82e8 2838 __unmap_single(domain->priv, dma_addr, size, dir);
4da70b9e 2839
17b124bf 2840 domain_flush_complete(domain);
4da70b9e
JR		 2841
2842 spin_unlock_irqrestore(&domain->lock, flags);
2843}
2844
431b2a20
JR		 2845/*
2846 * The exported map_sg function for dma_ops (handles scatter-gather
2847 * lists).
2848 */
65b050ad 2849static int map_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2850 int nelems, enum dma_data_direction dir,
2851 struct dma_attrs *attrs)
65b050ad
JR		 2852{
2853 unsigned long flags;
65b050ad 2854 struct protection_domain *domain;
65b050ad
JR		 2855 int i;
2856 struct scatterlist *s;
2857 phys_addr_t paddr;
2858 int mapped_elems = 0;
832a90c3 2859 u64 dma_mask;
65b050ad 2860
d03f067a
JR		 2861 INC_STATS_COUNTER(cnt_map_sg);
2862
94f6d190 2863 domain = get_domain(dev);
a0e191b2 2864 if (IS_ERR(domain))
94f6d190 2865 return 0;
dbcc112e 2866
832a90c3 2867 dma_mask = *dev->dma_mask;
65b050ad 2868
65b050ad
JR		 2869 spin_lock_irqsave(&domain->lock, flags);
2870
2871 for_each_sg(sglist, s, nelems, i) {
2872 paddr = sg_phys(s);
2873
cd8c82e8 2874 s->dma_address = __map_single(dev, domain->priv,
832a90c3
JR		 2875 paddr, s->length, dir, false,
2876 dma_mask);
65b050ad
JR		 2877
2878 if (s->dma_address) {
2879 s->dma_length = s->length;
2880 mapped_elems++;
2881 } else
2882 goto unmap;
65b050ad
JR		 2883 }
2884
17b124bf 2885 domain_flush_complete(domain);
65b050ad
JR		 2886
2887out:
2888 spin_unlock_irqrestore(&domain->lock, flags);
2889
2890 return mapped_elems;
2891unmap:
2892 for_each_sg(sglist, s, mapped_elems, i) {
2893 if (s->dma_address)
cd8c82e8 2894 __unmap_single(domain->priv, s->dma_address,
65b050ad
JR		 2895 s->dma_length, dir);
2896 s->dma_address = s->dma_length = 0;
2897 }
2898
2899 mapped_elems = 0;
2900
2901 goto out;
2902}
2903
431b2a20
JR		 2904/*
2905 * The exported map_sg function for dma_ops (handles scatter-gather
2906 * lists).
2907 */
65b050ad 2908static void unmap_sg(struct device *dev, struct scatterlist *sglist,
160c1d8e
FT		 2909 int nelems, enum dma_data_direction dir,
2910 struct dma_attrs *attrs)
65b050ad
JR		 2911{
2912 unsigned long flags;
65b050ad
JR		 2913 struct protection_domain *domain;
2914 struct scatterlist *s;
65b050ad
JR		 2915 int i;
2916
55877a6b
JR		 2917 INC_STATS_COUNTER(cnt_unmap_sg);
2918
94f6d190
JR		 2919 domain = get_domain(dev);
2920 if (IS_ERR(domain))
5b28df6f
JR		 2921 return;
2922
65b050ad
JR		 2923 spin_lock_irqsave(&domain->lock, flags);
2924
2925 for_each_sg(sglist, s, nelems, i) {
cd8c82e8 2926 __unmap_single(domain->priv, s->dma_address,
65b050ad 2927 s->dma_length, dir);
65b050ad
JR		 2928 s->dma_address = s->dma_length = 0;
2929 }
2930
17b124bf 2931 domain_flush_complete(domain);
65b050ad
JR		 2932
2933 spin_unlock_irqrestore(&domain->lock, flags);
2934}
2935
431b2a20
JR		 2936/*
2937 * The exported alloc_coherent function for dma_ops.
2938 */
5d8b53cf 2939static void *alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 2940 dma_addr_t *dma_addr, gfp_t flag,
2941 struct dma_attrs *attrs)
5d8b53cf
JR		 2942{
2943 unsigned long flags;
2944 void *virt_addr;
5d8b53cf 2945 struct protection_domain *domain;
5d8b53cf 2946 phys_addr_t paddr;
832a90c3 2947 u64 dma_mask = dev->coherent_dma_mask;
5d8b53cf 2948
c8f0fb36
JR		 2949 INC_STATS_COUNTER(cnt_alloc_coherent);
2950
94f6d190
JR		 2951 domain = get_domain(dev);
2952 if (PTR_ERR(domain) == -EINVAL) {
f99c0f1c
JR		 2953 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2954 *dma_addr = __pa(virt_addr);
2955 return virt_addr;
94f6d190
JR		 2956 } else if (IS_ERR(domain))
2957 return NULL;
5d8b53cf 2958
f99c0f1c
JR		 2959 dma_mask = dev->coherent_dma_mask;
2960 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2961 flag |= __GFP_ZERO;
5d8b53cf
JR		 2962
2963 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2964 if (!virt_addr)
b25ae679 2965 return NULL;
5d8b53cf 2966
5d8b53cf
JR		 2967 paddr = virt_to_phys(virt_addr);
2968
832a90c3
JR		 2969 if (!dma_mask)
2970 dma_mask = *dev->dma_mask;
2971
5d8b53cf
JR		 2972 spin_lock_irqsave(&domain->lock, flags);
2973
cd8c82e8 2974 *dma_addr = __map_single(dev, domain->priv, paddr,
832a90c3 2975 size, DMA_BIDIRECTIONAL, true, dma_mask);
5d8b53cf 2976
8fd524b3 2977 if (*dma_addr == DMA_ERROR_CODE) {
367d04c4 2978 spin_unlock_irqrestore(&domain->lock, flags);
5b28df6f 2979 goto out_free;
367d04c4 2980 }
5d8b53cf 2981
17b124bf 2982 domain_flush_complete(domain);
5d8b53cf 2983
5d8b53cf
JR		 2984 spin_unlock_irqrestore(&domain->lock, flags);
2985
2986 return virt_addr;
5b28df6f
JR		 2987
2988out_free:
2989
2990 free_pages((unsigned long)virt_addr, get_order(size));
2991
2992 return NULL;
5d8b53cf
JR		 2993}
2994
431b2a20
JR		 2995/*
2996 * The exported free_coherent function for dma_ops.
431b2a20 2997 */
5d8b53cf 2998static void free_coherent(struct device *dev, size_t size,
baa676fc
AP		 2999 void *virt_addr, dma_addr_t dma_addr,
3000 struct dma_attrs *attrs)
5d8b53cf
JR		 3001{
3002 unsigned long flags;
5d8b53cf 3003 struct protection_domain *domain;
5d8b53cf 3004
5d31ee7e
JR		 3005 INC_STATS_COUNTER(cnt_free_coherent);
3006
94f6d190
JR		 3007 domain = get_domain(dev);
3008 if (IS_ERR(domain))
5b28df6f
JR		 3009 goto free_mem;
3010
5d8b53cf
JR		 3011 spin_lock_irqsave(&domain->lock, flags);
3012
cd8c82e8 3013 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
5d8b53cf 3014
17b124bf 3015 domain_flush_complete(domain);
5d8b53cf
JR		 3016
3017 spin_unlock_irqrestore(&domain->lock, flags);
3018
3019free_mem:
3020 free_pages((unsigned long)virt_addr, get_order(size));
3021}
3022
b39ba6ad
JR		 3023/*
3024 * This function is called by the DMA layer to find out if we can handle a
3025 * particular device. It is part of the dma_ops.
3026 */
3027static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3028{
420aef8a 3029 return check_device(dev);
b39ba6ad
JR		 3030}
3031
c432f3df 3032/*
431b2a20
JR		 3033 * The function for pre-allocating protection domains.
3034 *
c432f3df
JR		 3035 * If the driver core informs the DMA layer if a driver grabs a device
3036 * we don't need to preallocate the protection domains anymore.
3037 * For now we have to.
3038 */
943bc7e1 3039static void __init prealloc_protection_domains(void)
c432f3df 3040{
5abcdba4 3041 struct iommu_dev_data *dev_data;
c432f3df 3042 struct dma_ops_domain *dma_dom;
5abcdba4 3043 struct pci_dev *dev = NULL;
98fc5a69 3044 u16 devid;
c432f3df 3045
d18c69d3 3046 for_each_pci_dev(dev) {
98fc5a69
JR		 3047
3048 /* Do we handle this device? */
3049 if (!check_device(&dev->dev))
c432f3df 3050 continue;
98fc5a69 3051
5abcdba4
JR		 3052 dev_data = get_dev_data(&dev->dev);
3053 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3054 /* Make sure passthrough domain is allocated */
3055 alloc_passthrough_domain();
3056 dev_data->passthrough = true;
3057 attach_device(&dev->dev, pt_domain);
df805abb 3058 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
5abcdba4
JR		 3059 dev_name(&dev->dev));
3060 }
3061
98fc5a69 3062 /* Is there already any domain for it? */
15898bbc 3063 if (domain_for_device(&dev->dev))
c432f3df 3064 continue;
98fc5a69
JR		 3065
3066 devid = get_device_id(&dev->dev);
3067
87a64d52 3068 dma_dom = dma_ops_domain_alloc();
c432f3df
JR		 3069 if (!dma_dom)
3070 continue;
3071 init_unity_mappings_for_device(dma_dom, devid);
bd60b735
JR		 3072 dma_dom->target_dev = devid;
3073
15898bbc 3074 attach_device(&dev->dev, &dma_dom->domain);
be831297 3075
bd60b735 3076 list_add_tail(&dma_dom->list, &iommu_pd_list);
c432f3df
JR		 3077 }
3078}
3079
160c1d8e 3080static struct dma_map_ops amd_iommu_dma_ops = {
baa676fc
AP		 3081 .alloc = alloc_coherent,
3082 .free = free_coherent,
51491367
FT		 3083 .map_page = map_page,
3084 .unmap_page = unmap_page,
6631ee9d
JR		 3085 .map_sg = map_sg,
3086 .unmap_sg = unmap_sg,
b39ba6ad 3087 .dma_supported = amd_iommu_dma_supported,
6631ee9d
JR		 3088};
3089
27c2127a
JR		 3090static unsigned device_dma_ops_init(void)
3091{
5abcdba4 3092 struct iommu_dev_data *dev_data;
27c2127a
JR		 3093 struct pci_dev *pdev = NULL;
3094 unsigned unhandled = 0;
3095
3096 for_each_pci_dev(pdev) {
3097 if (!check_device(&pdev->dev)) {
af1be049
JR		 3098
3099 iommu_ignore_device(&pdev->dev);
3100
27c2127a
JR		 3101 unhandled += 1;
3102 continue;
3103 }
3104
5abcdba4
JR		 3105 dev_data = get_dev_data(&pdev->dev);
3106
3107 if (!dev_data->passthrough)
3108 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3109 else
3110 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
27c2127a
JR		 3111 }
3112
3113 return unhandled;
3114}
3115
431b2a20
JR		 3116/*
3117 * The function which clues the AMD IOMMU driver into dma_ops.
3118 */
f5325094
JR		 3119
3120void __init amd_iommu_init_api(void)
3121{
2cc21c42 3122 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
f5325094
JR		 3123}
3124
6631ee9d
JR		 3125int __init amd_iommu_init_dma_ops(void)
3126{
3127 struct amd_iommu *iommu;
27c2127a 3128 int ret, unhandled;
6631ee9d 3129
431b2a20
JR		 3130 /*
3131 * first allocate a default protection domain for every IOMMU we
3132 * found in the system. Devices not assigned to any other
3133 * protection domain will be assigned to the default one.
3134 */
3bd22172 3135 for_each_iommu(iommu) {
87a64d52 3136 iommu->default_dom = dma_ops_domain_alloc();
6631ee9d
JR		 3137 if (iommu->default_dom == NULL)
3138 return -ENOMEM;
e2dc14a2 3139 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
6631ee9d
JR		 3140 ret = iommu_init_unity_mappings(iommu);
3141 if (ret)
3142 goto free_domains;
3143 }
3144
431b2a20 3145 /*
8793abeb 3146 * Pre-allocate the protection domains for each device.
431b2a20 3147 */
8793abeb 3148 prealloc_protection_domains();
6631ee9d
JR		 3149
3150 iommu_detected = 1;
75f1cdf1 3151 swiotlb = 0;
6631ee9d 3152
431b2a20 3153 /* Make the driver finally visible to the drivers */
27c2127a
JR		 3154 unhandled = device_dma_ops_init();
3155 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3156 /* There are unhandled devices - initialize swiotlb for them */
3157 swiotlb = 1;
3158 }
6631ee9d 3159
7f26508b
JR		 3160 amd_iommu_stats_init();
3161
62410eeb
JR		 3162 if (amd_iommu_unmap_flush)
3163 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3164 else
3165 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3166
6631ee9d
JR		 3167 return 0;
3168
3169free_domains:
3170
3bd22172 3171 for_each_iommu(iommu) {
91457df7 3172 dma_ops_domain_free(iommu->default_dom);
6631ee9d
JR		 3173 }
3174
3175 return ret;
3176}
6d98cd80
JR		 3177
3178/*****************************************************************************
3179 *
3180 * The following functions belong to the exported interface of AMD IOMMU
3181 *
3182 * This interface allows access to lower level functions of the IOMMU
3183 * like protection domain handling and assignement of devices to domains
3184 * which is not possible with the dma_ops interface.
3185 *
3186 *****************************************************************************/
3187
6d98cd80
JR		 3188static void cleanup_domain(struct protection_domain *domain)
3189{
b15dba93 3190 struct iommu_dev_data *entry;
6d98cd80 3191 unsigned long flags;
6d98cd80
JR		 3192
3193 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3194
b15dba93
JR		 3195 while (!list_empty(&domain->dev_list)) {
3196 entry = list_first_entry(&domain->dev_list,
3197 struct iommu_dev_data, list);
3198 __detach_device(entry);
3199 atomic_set(&entry->bind, 0);
492667da 3200 }
6d98cd80
JR		 3201
3202 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3203}
3204
2650815f
JR		 3205static void protection_domain_free(struct protection_domain *domain)
3206{
3207 if (!domain)
3208 return;
3209
aeb26f55
JR		 3210 del_domain_from_list(domain);
3211
2650815f
JR		 3212 if (domain->id)
3213 domain_id_free(domain->id);
3214
3215 kfree(domain);
3216}
3217
3218static struct protection_domain *protection_domain_alloc(void)
c156e347
JR		 3219{
3220 struct protection_domain *domain;
3221
3222 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3223 if (!domain)
2650815f 3224 return NULL;
c156e347
JR		 3225
3226 spin_lock_init(&domain->lock);
5d214fe6 3227 mutex_init(&domain->api_lock);
c156e347
JR		 3228 domain->id = domain_id_alloc();
3229 if (!domain->id)
2650815f 3230 goto out_err;
7c392cbe 3231 INIT_LIST_HEAD(&domain->dev_list);
2650815f 3232
aeb26f55
JR		 3233 add_domain_to_list(domain);
3234
2650815f
JR		 3235 return domain;
3236
3237out_err:
3238 kfree(domain);
3239
3240 return NULL;
3241}
3242
5abcdba4
JR		 3243static int __init alloc_passthrough_domain(void)
3244{
3245 if (pt_domain != NULL)
3246 return 0;
3247
3248 /* allocate passthrough domain */
3249 pt_domain = protection_domain_alloc();
3250 if (!pt_domain)
3251 return -ENOMEM;
3252
3253 pt_domain->mode = PAGE_MODE_NONE;
3254
3255 return 0;
3256}
2650815f
JR		 3257static int amd_iommu_domain_init(struct iommu_domain *dom)
3258{
3259 struct protection_domain *domain;
3260
3261 domain = protection_domain_alloc();
3262 if (!domain)
c156e347 3263 goto out_free;
2650815f
JR		 3264
3265 domain->mode = PAGE_MODE_3_LEVEL;
c156e347
JR		 3266 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3267 if (!domain->pt_root)
3268 goto out_free;
3269
f3572db8
JR		 3270 domain->iommu_domain = dom;
3271
c156e347
JR		 3272 dom->priv = domain;
3273
0ff64f80
JR		 3274 dom->geometry.aperture_start = 0;
3275 dom->geometry.aperture_end = ~0ULL;
3276 dom->geometry.force_aperture = true;
3277
c156e347
JR		 3278 return 0;
3279
3280out_free:
2650815f 3281 protection_domain_free(domain);
c156e347
JR		 3282
3283 return -ENOMEM;
3284}
3285
98383fc3
JR		 3286static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3287{
3288 struct protection_domain *domain = dom->priv;
3289
3290 if (!domain)
3291 return;
3292
3293 if (domain->dev_cnt > 0)
3294 cleanup_domain(domain);
3295
3296 BUG_ON(domain->dev_cnt != 0);
3297
132bd68f
JR		 3298 if (domain->mode != PAGE_MODE_NONE)
3299 free_pagetable(domain);
98383fc3 3300
52815b75
JR		 3301 if (domain->flags & PD_IOMMUV2_MASK)
3302 free_gcr3_table(domain);
3303
8b408fe4 3304 protection_domain_free(domain);
98383fc3
JR		 3305
3306 dom->priv = NULL;
3307}
3308
684f2888
JR		 3309static void amd_iommu_detach_device(struct iommu_domain *dom,
3310 struct device *dev)
3311{
657cbb6b 3312 struct iommu_dev_data *dev_data = dev->archdata.iommu;
684f2888 3313 struct amd_iommu *iommu;
684f2888
JR		 3314 u16 devid;
3315
98fc5a69 3316 if (!check_device(dev))
684f2888
JR		 3317 return;
3318
98fc5a69 3319 devid = get_device_id(dev);
684f2888 3320
657cbb6b 3321 if (dev_data->domain != NULL)
15898bbc 3322 detach_device(dev);
684f2888
JR		 3323
3324 iommu = amd_iommu_rlookup_table[devid];
3325 if (!iommu)
3326 return;
3327
684f2888
JR		 3328 iommu_completion_wait(iommu);
3329}
3330
01106066
JR		 3331static int amd_iommu_attach_device(struct iommu_domain *dom,
3332 struct device *dev)
3333{
3334 struct protection_domain *domain = dom->priv;
657cbb6b 3335 struct iommu_dev_data *dev_data;
01106066 3336 struct amd_iommu *iommu;
15898bbc 3337 int ret;
01106066 3338
98fc5a69 3339 if (!check_device(dev))
01106066
JR		 3340 return -EINVAL;
3341
657cbb6b
JR		 3342 dev_data = dev->archdata.iommu;
3343
f62dda66 3344 iommu = amd_iommu_rlookup_table[dev_data->devid];
01106066
JR		 3345 if (!iommu)
3346 return -EINVAL;
3347
657cbb6b 3348 if (dev_data->domain)
15898bbc 3349 detach_device(dev);
01106066 3350
15898bbc 3351 ret = attach_device(dev, domain);
01106066
JR		 3352
3353 iommu_completion_wait(iommu);
3354
15898bbc 3355 return ret;
01106066
JR		 3356}
3357
468e2366 3358static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
5009065d 3359 phys_addr_t paddr, size_t page_size, int iommu_prot)
c6229ca6
JR		 3360{
3361 struct protection_domain *domain = dom->priv;
c6229ca6
JR		 3362 int prot = 0;
3363 int ret;
3364
132bd68f
JR		 3365 if (domain->mode == PAGE_MODE_NONE)
3366 return -EINVAL;
3367
c6229ca6
JR		 3368 if (iommu_prot & IOMMU_READ)
3369 prot |= IOMMU_PROT_IR;
3370 if (iommu_prot & IOMMU_WRITE)
3371 prot |= IOMMU_PROT_IW;
3372
5d214fe6 3373 mutex_lock(&domain->api_lock);
795e74f7 3374 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
5d214fe6
JR		 3375 mutex_unlock(&domain->api_lock);
3376
795e74f7 3377 return ret;
c6229ca6
JR		 3378}
3379
5009065d
OBC		 3380static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3381 size_t page_size)
eb74ff6c 3382{
eb74ff6c 3383 struct protection_domain *domain = dom->priv;
5009065d 3384 size_t unmap_size;
eb74ff6c 3385
132bd68f
JR		 3386 if (domain->mode == PAGE_MODE_NONE)
3387 return -EINVAL;
3388
5d214fe6 3389 mutex_lock(&domain->api_lock);
468e2366 3390 unmap_size = iommu_unmap_page(domain, iova, page_size);
795e74f7 3391 mutex_unlock(&domain->api_lock);
eb74ff6c 3392
17b124bf 3393 domain_flush_tlb_pde(domain);
5d214fe6 3394
5009065d 3395 return unmap_size;
eb74ff6c
JR		 3396}
3397
645c4c8d 3398static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
bb5547ac 3399 dma_addr_t iova)
645c4c8d
JR		 3400{
3401 struct protection_domain *domain = dom->priv;
f03152bb 3402 unsigned long offset_mask;
645c4c8d 3403 phys_addr_t paddr;
f03152bb 3404 u64 *pte, __pte;
645c4c8d 3405
132bd68f
JR		 3406 if (domain->mode == PAGE_MODE_NONE)
3407 return iova;
3408
24cd7723 3409 pte = fetch_pte(domain, iova);
645c4c8d 3410
a6d41a40 3411 if (!pte || !IOMMU_PTE_PRESENT(*pte))
645c4c8d
JR		 3412 return 0;
3413
f03152bb
JR		 3414 if (PM_PTE_LEVEL(*pte) == 0)
3415 offset_mask = PAGE_SIZE - 1;
3416 else
3417 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3418
3419 __pte = *pte & PM_ADDR_MASK;
3420 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
645c4c8d
JR		 3421
3422 return paddr;
3423}
3424
dbb9fd86
SY		 3425static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3426 unsigned long cap)
3427{
80a506b8
JR		 3428 switch (cap) {
3429 case IOMMU_CAP_CACHE_COHERENCY:
3430 return 1;
bdddadcb
JR		 3431 case IOMMU_CAP_INTR_REMAP:
3432 return irq_remapping_enabled;
80a506b8
JR		 3433 }
3434
dbb9fd86
SY		 3435 return 0;
3436}
3437
26961efe
JR		 3438static struct iommu_ops amd_iommu_ops = {
3439 .domain_init = amd_iommu_domain_init,
3440 .domain_destroy = amd_iommu_domain_destroy,
3441 .attach_dev = amd_iommu_attach_device,
3442 .detach_dev = amd_iommu_detach_device,
468e2366
JR		 3443 .map = amd_iommu_map,
3444 .unmap = amd_iommu_unmap,
26961efe 3445 .iova_to_phys = amd_iommu_iova_to_phys,
dbb9fd86 3446 .domain_has_cap = amd_iommu_domain_has_cap,
aa3de9c0 3447 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
26961efe
JR		 3448};
3449
0feae533
JR		 3450/*****************************************************************************
3451 *
3452 * The next functions do a basic initialization of IOMMU for pass through
3453 * mode
3454 *
3455 * In passthrough mode the IOMMU is initialized and enabled but not used for
3456 * DMA-API translation.
3457 *
3458 *****************************************************************************/
3459
3460int __init amd_iommu_init_passthrough(void)
3461{
5abcdba4 3462 struct iommu_dev_data *dev_data;
0feae533 3463 struct pci_dev *dev = NULL;
5abcdba4 3464 struct amd_iommu *iommu;
15898bbc 3465 u16 devid;
5abcdba4 3466 int ret;
0feae533 3467
5abcdba4
JR		 3468 ret = alloc_passthrough_domain();
3469 if (ret)
3470 return ret;
0feae533 3471
6c54aabd 3472 for_each_pci_dev(dev) {
98fc5a69 3473 if (!check_device(&dev->dev))
0feae533
JR		 3474 continue;
3475
5abcdba4
JR		 3476 dev_data = get_dev_data(&dev->dev);
3477 dev_data->passthrough = true;
3478
98fc5a69
JR		 3479 devid = get_device_id(&dev->dev);
3480
15898bbc 3481 iommu = amd_iommu_rlookup_table[devid];
0feae533
JR		 3482 if (!iommu)
3483 continue;
3484
15898bbc 3485 attach_device(&dev->dev, pt_domain);
0feae533
JR		 3486 }
3487
2655d7a2
JR		 3488 amd_iommu_stats_init();
3489
0feae533
JR		 3490 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3491
3492 return 0;
3493}
72e1dcc4
JR		 3494
3495/* IOMMUv2 specific functions */
3496int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3497{
3498 return atomic_notifier_chain_register(&ppr_notifier, nb);
3499}
3500EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3501
3502int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3503{
3504 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3505}
3506EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
132bd68f
JR		 3507
3508void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3509{
3510 struct protection_domain *domain = dom->priv;
3511 unsigned long flags;
3512
3513 spin_lock_irqsave(&domain->lock, flags);
3514
3515 /* Update data structure */
3516 domain->mode = PAGE_MODE_NONE;
3517 domain->updated = true;
3518
3519 /* Make changes visible to IOMMUs */
3520 update_domain(domain);
3521
3522 /* Page-table is not visible to IOMMU anymore, so free it */
3523 free_pagetable(domain);
3524
3525 spin_unlock_irqrestore(&domain->lock, flags);
3526}
3527EXPORT_SYMBOL(amd_iommu_domain_direct_map);
52815b75
JR		 3528
3529int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3530{
3531 struct protection_domain *domain = dom->priv;
3532 unsigned long flags;
3533 int levels, ret;
3534
3535 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3536 return -EINVAL;
3537
3538 /* Number of GCR3 table levels required */
3539 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3540 levels += 1;
3541
3542 if (levels > amd_iommu_max_glx_val)
3543 return -EINVAL;
3544
3545 spin_lock_irqsave(&domain->lock, flags);
3546
3547 /*
3548 * Save us all sanity checks whether devices already in the
3549 * domain support IOMMUv2. Just force that the domain has no
3550 * devices attached when it is switched into IOMMUv2 mode.
3551 */
3552 ret = -EBUSY;
3553 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3554 goto out;
3555
3556 ret = -ENOMEM;
3557 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3558 if (domain->gcr3_tbl == NULL)
3559 goto out;
3560
3561 domain->glx = levels;
3562 domain->flags |= PD_IOMMUV2_MASK;
3563 domain->updated = true;
3564
3565 update_domain(domain);
3566
3567 ret = 0;
3568
3569out:
3570 spin_unlock_irqrestore(&domain->lock, flags);
3571
3572 return ret;
3573}
3574EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
22e266c7
JR		 3575
3576static int __flush_pasid(struct protection_domain *domain, int pasid,
3577 u64 address, bool size)
3578{
3579 struct iommu_dev_data *dev_data;
3580 struct iommu_cmd cmd;
3581 int i, ret;
3582
3583 if (!(domain->flags & PD_IOMMUV2_MASK))
3584 return -EINVAL;
3585
3586 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3587
3588 /*
3589 * IOMMU TLB needs to be flushed before Device TLB to
3590 * prevent device TLB refill from IOMMU TLB
3591 */
3592 for (i = 0; i < amd_iommus_present; ++i) {
3593 if (domain->dev_iommu[i] == 0)
3594 continue;
3595
3596 ret = iommu_queue_command(amd_iommus[i], &cmd);
3597 if (ret != 0)
3598 goto out;
3599 }
3600
3601 /* Wait until IOMMU TLB flushes are complete */
3602 domain_flush_complete(domain);
3603
3604 /* Now flush device TLBs */
3605 list_for_each_entry(dev_data, &domain->dev_list, list) {
3606 struct amd_iommu *iommu;
3607 int qdep;
3608
3609 BUG_ON(!dev_data->ats.enabled);
3610
3611 qdep = dev_data->ats.qdep;
3612 iommu = amd_iommu_rlookup_table[dev_data->devid];
3613
3614 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3615 qdep, address, size);
3616
3617 ret = iommu_queue_command(iommu, &cmd);
3618 if (ret != 0)
3619 goto out;
3620 }
3621
3622 /* Wait until all device TLBs are flushed */
3623 domain_flush_complete(domain);
3624
3625 ret = 0;
3626
3627out:
3628
3629 return ret;
3630}
3631
3632static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3633 u64 address)
3634{
399be2f5
JR		 3635 INC_STATS_COUNTER(invalidate_iotlb);
3636
22e266c7
JR		 3637 return __flush_pasid(domain, pasid, address, false);
3638}
3639
3640int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3641 u64 address)
3642{
3643 struct protection_domain *domain = dom->priv;
3644 unsigned long flags;
3645 int ret;
3646
3647 spin_lock_irqsave(&domain->lock, flags);
3648 ret = __amd_iommu_flush_page(domain, pasid, address);
3649 spin_unlock_irqrestore(&domain->lock, flags);
3650
3651 return ret;
3652}
3653EXPORT_SYMBOL(amd_iommu_flush_page);
3654
3655static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3656{
399be2f5
JR		 3657 INC_STATS_COUNTER(invalidate_iotlb_all);
3658
22e266c7
JR		 3659 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3660 true);
3661}
3662
3663int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3664{
3665 struct protection_domain *domain = dom->priv;
3666 unsigned long flags;
3667 int ret;
3668
3669 spin_lock_irqsave(&domain->lock, flags);
3670 ret = __amd_iommu_flush_tlb(domain, pasid);
3671 spin_unlock_irqrestore(&domain->lock, flags);
3672
3673 return ret;
3674}
3675EXPORT_SYMBOL(amd_iommu_flush_tlb);
3676
b16137b1
JR		 3677static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3678{
3679 int index;
3680 u64 *pte;
3681
3682 while (true) {
3683
3684 index = (pasid >> (9 * level)) & 0x1ff;
3685 pte = &root[index];
3686
3687 if (level == 0)
3688 break;
3689
3690 if (!(*pte & GCR3_VALID)) {
3691 if (!alloc)
3692 return NULL;
3693
3694 root = (void *)get_zeroed_page(GFP_ATOMIC);
3695 if (root == NULL)
3696 return NULL;
3697
3698 *pte = __pa(root) | GCR3_VALID;
3699 }
3700
3701 root = __va(*pte & PAGE_MASK);
3702
3703 level -= 1;
3704 }
3705
3706 return pte;
3707}
3708
3709static int __set_gcr3(struct protection_domain *domain, int pasid,
3710 unsigned long cr3)
3711{
3712 u64 *pte;
3713
3714 if (domain->mode != PAGE_MODE_NONE)
3715 return -EINVAL;
3716
3717 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3718 if (pte == NULL)
3719 return -ENOMEM;
3720
3721 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3722
3723 return __amd_iommu_flush_tlb(domain, pasid);
3724}
3725
3726static int __clear_gcr3(struct protection_domain *domain, int pasid)
3727{
3728 u64 *pte;
3729
3730 if (domain->mode != PAGE_MODE_NONE)
3731 return -EINVAL;
3732
3733 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3734 if (pte == NULL)
3735 return 0;
3736
3737 *pte = 0;
3738
3739 return __amd_iommu_flush_tlb(domain, pasid);
3740}
3741
3742int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3743 unsigned long cr3)
3744{
3745 struct protection_domain *domain = dom->priv;
3746 unsigned long flags;
3747 int ret;
3748
3749 spin_lock_irqsave(&domain->lock, flags);
3750 ret = __set_gcr3(domain, pasid, cr3);
3751 spin_unlock_irqrestore(&domain->lock, flags);
3752
3753 return ret;
3754}
3755EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3756
3757int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3758{
3759 struct protection_domain *domain = dom->priv;
3760 unsigned long flags;
3761 int ret;
3762
3763 spin_lock_irqsave(&domain->lock, flags);
3764 ret = __clear_gcr3(domain, pasid);
3765 spin_unlock_irqrestore(&domain->lock, flags);
3766
3767 return ret;
3768}
3769EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
c99afa25
JR		 3770
3771int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3772 int status, int tag)
3773{
3774 struct iommu_dev_data *dev_data;
3775 struct amd_iommu *iommu;
3776 struct iommu_cmd cmd;
3777
399be2f5
JR		 3778 INC_STATS_COUNTER(complete_ppr);
3779
c99afa25
JR		 3780 dev_data = get_dev_data(&pdev->dev);
3781 iommu = amd_iommu_rlookup_table[dev_data->devid];
3782
3783 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3784 tag, dev_data->pri_tlp);
3785
3786 return iommu_queue_command(iommu, &cmd);
3787}
3788EXPORT_SYMBOL(amd_iommu_complete_ppr);
f3572db8
JR		 3789
3790struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3791{
3792 struct protection_domain *domain;
3793
3794 domain = get_domain(&pdev->dev);
3795 if (IS_ERR(domain))
3796 return NULL;
3797
3798 /* Only return IOMMUv2 domains */
3799 if (!(domain->flags & PD_IOMMUV2_MASK))
3800 return NULL;
3801
3802 return domain->iommu_domain;
3803}
3804EXPORT_SYMBOL(amd_iommu_get_v2_domain);
6a113ddc
JR		 3805
3806void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3807{
3808 struct iommu_dev_data *dev_data;
3809
3810 if (!amd_iommu_v2_supported())
3811 return;
3812
3813 dev_data = get_dev_data(&pdev->dev);
3814 dev_data->errata |= (1 << erratum);
3815}
3816EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
52efdb89
JR		 3817
3818int amd_iommu_device_info(struct pci_dev *pdev,
3819 struct amd_iommu_device_info *info)
3820{
3821 int max_pasids;
3822 int pos;
3823
3824 if (pdev == NULL || info == NULL)
3825 return -EINVAL;
3826
3827 if (!amd_iommu_v2_supported())
3828 return -EINVAL;
3829
3830 memset(info, 0, sizeof(*info));
3831
3832 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3833 if (pos)
3834 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3835
3836 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3837 if (pos)
3838 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3839
3840 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3841 if (pos) {
3842 int features;
3843
3844 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3845 max_pasids = min(max_pasids, (1 << 20));
3846
3847 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3848 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3849
3850 features = pci_pasid_features(pdev);
3851 if (features & PCI_PASID_CAP_EXEC)
3852 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3853 if (features & PCI_PASID_CAP_PRIV)
3854 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3855 }
3856
3857 return 0;
3858}
3859EXPORT_SYMBOL(amd_iommu_device_info);
2b324506
JR		 3860
3861#ifdef CONFIG_IRQ_REMAP
3862
3863/*****************************************************************************
3864 *
3865 * Interrupt Remapping Implementation
3866 *
3867 *****************************************************************************/
3868
3869union irte {
3870 u32 val;
3871 struct {
3872 u32 valid : 1,
3873 no_fault : 1,
3874 int_type : 3,
3875 rq_eoi : 1,
3876 dm : 1,
3877 rsvd_1 : 1,
3878 destination : 8,
3879 vector : 8,
3880 rsvd_2 : 8;
3881 } fields;
3882};
3883
3884#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3885#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3886#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3887#define DTE_IRQ_REMAP_ENABLE 1ULL
3888
3889static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3890{
3891 u64 dte;
3892
3893 dte = amd_iommu_dev_table[devid].data[2];
3894 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3895 dte |= virt_to_phys(table->table);
3896 dte |= DTE_IRQ_REMAP_INTCTL;
3897 dte |= DTE_IRQ_TABLE_LEN;
3898 dte |= DTE_IRQ_REMAP_ENABLE;
3899
3900 amd_iommu_dev_table[devid].data[2] = dte;
3901}
3902
3903#define IRTE_ALLOCATED (~1U)
3904
3905static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3906{
3907 struct irq_remap_table *table = NULL;
3908 struct amd_iommu *iommu;
3909 unsigned long flags;
3910 u16 alias;
3911
3912 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3913
3914 iommu = amd_iommu_rlookup_table[devid];
3915 if (!iommu)
3916 goto out_unlock;
3917
3918 table = irq_lookup_table[devid];
3919 if (table)
3920 goto out;
3921
3922 alias = amd_iommu_alias_table[devid];
3923 table = irq_lookup_table[alias];
3924 if (table) {
3925 irq_lookup_table[devid] = table;
3926 set_dte_irq_entry(devid, table);
3927 iommu_flush_dte(iommu, devid);
3928 goto out;
3929 }
3930
3931 /* Nothing there yet, allocate new irq remapping table */
3932 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3933 if (!table)
3934 goto out;
3935
197887f0
JR		 3936 /* Initialize table spin-lock */
3937 spin_lock_init(&table->lock);
3938
2b324506
JR		 3939 if (ioapic)
3940 /* Keep the first 32 indexes free for IOAPIC interrupts */
3941 table->min_index = 32;
3942
3943 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3944 if (!table->table) {
3945 kfree(table);
821f0f68 3946 table = NULL;
2b324506
JR		 3947 goto out;
3948 }
3949
3950 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3951
3952 if (ioapic) {
3953 int i;
3954
3955 for (i = 0; i < 32; ++i)
3956 table->table[i] = IRTE_ALLOCATED;
3957 }
3958
3959 irq_lookup_table[devid] = table;
3960 set_dte_irq_entry(devid, table);
3961 iommu_flush_dte(iommu, devid);
3962 if (devid != alias) {
3963 irq_lookup_table[alias] = table;
0a4e3565 3964 set_dte_irq_entry(alias, table);
2b324506
JR		 3965 iommu_flush_dte(iommu, alias);
3966 }
3967
3968out:
3969 iommu_completion_wait(iommu);
3970
3971out_unlock:
3972 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3973
3974 return table;
3975}
3976
3977static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3978{
3979 struct irq_remap_table *table;
3980 unsigned long flags;
3981 int index, c;
3982
3983 table = get_irq_table(devid, false);
3984 if (!table)
3985 return -ENODEV;
3986
3987 spin_lock_irqsave(&table->lock, flags);
3988
3989 /* Scan table for free entries */
3990 for (c = 0, index = table->min_index;
3991 index < MAX_IRQS_PER_TABLE;
3992 ++index) {
3993 if (table->table[index] == 0)
3994 c += 1;
3995 else
3996 c = 0;
3997
3998 if (c == count) {
0dfedd61 3999 struct irq_2_irte *irte_info;
2b324506
JR		 4000
4001 for (; c != 0; --c)
4002 table->table[index - c + 1] = IRTE_ALLOCATED;
4003
4004 index -= count - 1;
4005
9b1b0e42 4006 cfg->remapped = 1;
0dfedd61
JR		 4007 irte_info = &cfg->irq_2_irte;
4008 irte_info->devid = devid;
4009 irte_info->index = index;
2b324506
JR		 4010
4011 goto out;
4012 }
4013 }
4014
4015 index = -ENOSPC;
4016
4017out:
4018 spin_unlock_irqrestore(&table->lock, flags);
4019
4020 return index;
4021}
4022
4023static int get_irte(u16 devid, int index, union irte *irte)
4024{
4025 struct irq_remap_table *table;
4026 unsigned long flags;
4027
4028 table = get_irq_table(devid, false);
4029 if (!table)
4030 return -ENOMEM;
4031
4032 spin_lock_irqsave(&table->lock, flags);
4033 irte->val = table->table[index];
4034 spin_unlock_irqrestore(&table->lock, flags);
4035
4036 return 0;
4037}
4038
4039static int modify_irte(u16 devid, int index, union irte irte)
4040{
4041 struct irq_remap_table *table;
4042 struct amd_iommu *iommu;
4043 unsigned long flags;
4044
4045 iommu = amd_iommu_rlookup_table[devid];
4046 if (iommu == NULL)
4047 return -EINVAL;
4048
4049 table = get_irq_table(devid, false);
4050 if (!table)
4051 return -ENOMEM;
4052
4053 spin_lock_irqsave(&table->lock, flags);
4054 table->table[index] = irte.val;
4055 spin_unlock_irqrestore(&table->lock, flags);
4056
4057 iommu_flush_irt(iommu, devid);
4058 iommu_completion_wait(iommu);
4059
4060 return 0;
4061}
4062
4063static void free_irte(u16 devid, int index)
4064{
4065 struct irq_remap_table *table;
4066 struct amd_iommu *iommu;
4067 unsigned long flags;
4068
4069 iommu = amd_iommu_rlookup_table[devid];
4070 if (iommu == NULL)
4071 return;
4072
4073 table = get_irq_table(devid, false);
4074 if (!table)
4075 return;
4076
4077 spin_lock_irqsave(&table->lock, flags);
4078 table->table[index] = 0;
4079 spin_unlock_irqrestore(&table->lock, flags);
4080
4081 iommu_flush_irt(iommu, devid);
4082 iommu_completion_wait(iommu);
4083}
4084
5527de74
JR		 4085static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4086 unsigned int destination, int vector,
4087 struct io_apic_irq_attr *attr)
4088{
4089 struct irq_remap_table *table;
0dfedd61 4090 struct irq_2_irte *irte_info;
5527de74
JR		 4091 struct irq_cfg *cfg;
4092 union irte irte;
4093 int ioapic_id;
4094 int index;
4095 int devid;
4096 int ret;
4097
4098 cfg = irq_get_chip_data(irq);
4099 if (!cfg)
4100 return -EINVAL;
4101
0dfedd61 4102 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4103 ioapic_id = mpc_ioapic_id(attr->ioapic);
4104 devid = get_ioapic_devid(ioapic_id);
4105
4106 if (devid < 0)
4107 return devid;
4108
4109 table = get_irq_table(devid, true);
4110 if (table == NULL)
4111 return -ENOMEM;
4112
4113 index = attr->ioapic_pin;
4114
4115 /* Setup IRQ remapping info */
9b1b0e42 4116 cfg->remapped = 1;
0dfedd61
JR		 4117 irte_info->devid = devid;
4118 irte_info->index = index;
5527de74
JR		 4119
4120 /* Setup IRTE for IOMMU */
4121 irte.val = 0;
4122 irte.fields.vector = vector;
4123 irte.fields.int_type = apic->irq_delivery_mode;
4124 irte.fields.destination = destination;
4125 irte.fields.dm = apic->irq_dest_mode;
4126 irte.fields.valid = 1;
4127
4128 ret = modify_irte(devid, index, irte);
4129 if (ret)
4130 return ret;
4131
4132 /* Setup IOAPIC entry */
4133 memset(entry, 0, sizeof(*entry));
4134
4135 entry->vector = index;
4136 entry->mask = 0;
4137 entry->trigger = attr->trigger;
4138 entry->polarity = attr->polarity;
4139
4140 /*
4141 * Mask level triggered irqs.
5527de74
JR		 4142 */
4143 if (attr->trigger)
4144 entry->mask = 1;
4145
4146 return 0;
4147}
4148
4149static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4150 bool force)
4151{
0dfedd61 4152 struct irq_2_irte *irte_info;
5527de74
JR		 4153 unsigned int dest, irq;
4154 struct irq_cfg *cfg;
4155 union irte irte;
4156 int err;
4157
4158 if (!config_enabled(CONFIG_SMP))
4159 return -1;
4160
4161 cfg = data->chip_data;
4162 irq = data->irq;
0dfedd61 4163 irte_info = &cfg->irq_2_irte;
5527de74
JR		 4164
4165 if (!cpumask_intersects(mask, cpu_online_mask))
4166 return -EINVAL;
4167
0dfedd61 4168 if (get_irte(irte_info->devid, irte_info->index, &irte))
5527de74
JR		 4169 return -EBUSY;
4170
4171 if (assign_irq_vector(irq, cfg, mask))
4172 return -EBUSY;
4173
4174 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4175 if (err) {
4176 if (assign_irq_vector(irq, cfg, data->affinity))
4177 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4178 return err;
4179 }
4180
4181 irte.fields.vector = cfg->vector;
4182 irte.fields.destination = dest;
4183
0dfedd61 4184 modify_irte(irte_info->devid, irte_info->index, irte);
5527de74
JR		 4185
4186 if (cfg->move_in_progress)
4187 send_cleanup_vector(cfg);
4188
4189 cpumask_copy(data->affinity, mask);
4190
4191 return 0;
4192}
4193
4194static int free_irq(int irq)
4195{
0dfedd61 4196 struct irq_2_irte *irte_info;
5527de74
JR		 4197 struct irq_cfg *cfg;
4198
4199 cfg = irq_get_chip_data(irq);
4200 if (!cfg)
4201 return -EINVAL;
4202
0dfedd61 4203 irte_info = &cfg->irq_2_irte;
5527de74 4204
0dfedd61 4205 free_irte(irte_info->devid, irte_info->index);
5527de74
JR		 4206
4207 return 0;
4208}
4209
0b4d48cb
JR		 4210static void compose_msi_msg(struct pci_dev *pdev,
4211 unsigned int irq, unsigned int dest,
4212 struct msi_msg *msg, u8 hpet_id)
4213{
0dfedd61 4214 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4215 struct irq_cfg *cfg;
4216 union irte irte;
4217
4218 cfg = irq_get_chip_data(irq);
4219 if (!cfg)
4220 return;
4221
0dfedd61 4222 irte_info = &cfg->irq_2_irte;
0b4d48cb
JR		 4223
4224 irte.val = 0;
4225 irte.fields.vector = cfg->vector;
4226 irte.fields.int_type = apic->irq_delivery_mode;
4227 irte.fields.destination = dest;
4228 irte.fields.dm = apic->irq_dest_mode;
4229 irte.fields.valid = 1;
4230
0dfedd61 4231 modify_irte(irte_info->devid, irte_info->index, irte);
0b4d48cb
JR		 4232
4233 msg->address_hi = MSI_ADDR_BASE_HI;
4234 msg->address_lo = MSI_ADDR_BASE_LO;
0dfedd61 4235 msg->data = irte_info->index;
0b4d48cb
JR		 4236}
4237
4238static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4239{
4240 struct irq_cfg *cfg;
4241 int index;
4242 u16 devid;
4243
4244 if (!pdev)
4245 return -EINVAL;
4246
4247 cfg = irq_get_chip_data(irq);
4248 if (!cfg)
4249 return -EINVAL;
4250
4251 devid = get_device_id(&pdev->dev);
4252 index = alloc_irq_index(cfg, devid, nvec);
4253
4254 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4255}
4256
4257static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4258 int index, int offset)
4259{
0dfedd61 4260 struct irq_2_irte *irte_info;
0b4d48cb
JR		 4261 struct irq_cfg *cfg;
4262 u16 devid;
4263
4264 if (!pdev)
4265 return -EINVAL;
4266
4267 cfg = irq_get_chip_data(irq);
4268 if (!cfg)
4269 return -EINVAL;
4270
4271 if (index >= MAX_IRQS_PER_TABLE)
4272 return 0;
4273
4274 devid = get_device_id(&pdev->dev);
0dfedd61 4275 irte_info = &cfg->irq_2_irte;
0b4d48cb 4276
9b1b0e42 4277 cfg->remapped = 1;
0dfedd61
JR		 4278 irte_info->devid = devid;
4279 irte_info->index = index + offset;
0b4d48cb
JR		 4280
4281 return 0;
4282}
4283
d976195c
JR		 4284static int setup_hpet_msi(unsigned int irq, unsigned int id)
4285{
0dfedd61 4286 struct irq_2_irte *irte_info;
d976195c
JR		 4287 struct irq_cfg *cfg;
4288 int index, devid;
4289
4290 cfg = irq_get_chip_data(irq);
4291 if (!cfg)
4292 return -EINVAL;
4293
0dfedd61 4294 irte_info = &cfg->irq_2_irte;
d976195c
JR		 4295 devid = get_hpet_devid(id);
4296 if (devid < 0)
4297 return devid;
4298
4299 index = alloc_irq_index(cfg, devid, 1);
4300 if (index < 0)
4301 return index;
4302
9b1b0e42 4303 cfg->remapped = 1;
0dfedd61
JR		 4304 irte_info->devid = devid;
4305 irte_info->index = index;
d976195c
JR		 4306
4307 return 0;
4308}
4309
6b474b82
JR		 4310struct irq_remap_ops amd_iommu_irq_ops = {
4311 .supported = amd_iommu_supported,
4312 .prepare = amd_iommu_prepare,
4313 .enable = amd_iommu_enable,
4314 .disable = amd_iommu_disable,
4315 .reenable = amd_iommu_reenable,
4316 .enable_faulting = amd_iommu_enable_faulting,
4317 .setup_ioapic_entry = setup_ioapic_entry,
4318 .set_affinity = set_affinity,
4319 .free_irq = free_irq,
4320 .compose_msi_msg = compose_msi_msg,
4321 .msi_alloc_irq = msi_alloc_irq,
4322 .msi_setup_irq = msi_setup_irq,
4323 .setup_hpet_msi = setup_hpet_msi,
4324};
2b324506 4325#endif
kernel source for telekom puls (alcatel/mediatek)