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Merge tag 'v3.10.108' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / qib / qib_verbs.c
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f931551b 1/*
e2eed58b 2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
1fb9fed6 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
f931551b
RC		 4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <rdma/ib_mad.h>
36#include <rdma/ib_user_verbs.h>
37#include <linux/io.h>
e4dd23d7 38#include <linux/module.h>
f931551b
RC		 39#include <linux/utsname.h>
40#include <linux/rculist.h>
41#include <linux/mm.h>
af061a64 42#include <linux/random.h>
ef5844a0 43#include <linux/vmalloc.h>
f931551b
RC		 44
45#include "qib.h"
46#include "qib_common.h"
47
af061a64 48static unsigned int ib_qib_qp_table_size = 256;
f931551b
RC		 49module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
50MODULE_PARM_DESC(qp_table_size, "QP table size");
51
52unsigned int ib_qib_lkey_table_size = 16;
53module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
54 S_IRUGO);
55MODULE_PARM_DESC(lkey_table_size,
56 "LKEY table size in bits (2^n, 1 <= n <= 23)");
57
58static unsigned int ib_qib_max_pds = 0xFFFF;
59module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
60MODULE_PARM_DESC(max_pds,
61 "Maximum number of protection domains to support");
62
63static unsigned int ib_qib_max_ahs = 0xFFFF;
64module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
65MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
66
67unsigned int ib_qib_max_cqes = 0x2FFFF;
68module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
69MODULE_PARM_DESC(max_cqes,
70 "Maximum number of completion queue entries to support");
71
72unsigned int ib_qib_max_cqs = 0x1FFFF;
73module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
74MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
75
76unsigned int ib_qib_max_qp_wrs = 0x3FFF;
77module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
78MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
79
80unsigned int ib_qib_max_qps = 16384;
81module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
82MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
83
84unsigned int ib_qib_max_sges = 0x60;
85module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
86MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
87
88unsigned int ib_qib_max_mcast_grps = 16384;
89module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
90MODULE_PARM_DESC(max_mcast_grps,
91 "Maximum number of multicast groups to support");
92
93unsigned int ib_qib_max_mcast_qp_attached = 16;
94module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
95 uint, S_IRUGO);
96MODULE_PARM_DESC(max_mcast_qp_attached,
97 "Maximum number of attached QPs to support");
98
99unsigned int ib_qib_max_srqs = 1024;
100module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
101MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
102
103unsigned int ib_qib_max_srq_sges = 128;
104module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
105MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
106
107unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
108module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
109MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
110
111static unsigned int ib_qib_disable_sma;
112module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
113MODULE_PARM_DESC(disable_sma, "Disable the SMA");
114
115/*
116 * Note that it is OK to post send work requests in the SQE and ERR
117 * states; qib_do_send() will process them and generate error
118 * completions as per IB 1.2 C10-96.
119 */
120const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
121 [IB_QPS_RESET] = 0,
122 [IB_QPS_INIT] = QIB_POST_RECV_OK,
123 [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
124 [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
125 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
126 QIB_PROCESS_NEXT_SEND_OK,
127 [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
128 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
129 [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
130 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
131 [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
132 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
133};
134
135struct qib_ucontext {
136 struct ib_ucontext ibucontext;
137};
138
139static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
140 *ibucontext)
141{
142 return container_of(ibucontext, struct qib_ucontext, ibucontext);
143}
144
145/*
146 * Translate ib_wr_opcode into ib_wc_opcode.
147 */
148const enum ib_wc_opcode ib_qib_wc_opcode[] = {
149 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
150 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
151 [IB_WR_SEND] = IB_WC_SEND,
152 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
153 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
154 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
155 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
156};
157
158/*
159 * System image GUID.
160 */
161__be64 ib_qib_sys_image_guid;
162
163/**
164 * qib_copy_sge - copy data to SGE memory
165 * @ss: the SGE state
166 * @data: the data to copy
167 * @length: the length of the data
168 */
169void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
170{
171 struct qib_sge *sge = &ss->sge;
172
173 while (length) {
174 u32 len = sge->length;
175
176 if (len > length)
177 len = length;
178 if (len > sge->sge_length)
179 len = sge->sge_length;
180 BUG_ON(len == 0);
181 memcpy(sge->vaddr, data, len);
182 sge->vaddr += len;
183 sge->length -= len;
184 sge->sge_length -= len;
185 if (sge->sge_length == 0) {
186 if (release)
6a82649f 187 qib_put_mr(sge->mr);
f931551b
RC		 188 if (--ss->num_sge)
189 *sge = *ss->sg_list++;
190 } else if (sge->length == 0 && sge->mr->lkey) {
191 if (++sge->n >= QIB_SEGSZ) {
192 if (++sge->m >= sge->mr->mapsz)
193 break;
194 sge->n = 0;
195 }
196 sge->vaddr =
197 sge->mr->map[sge->m]->segs[sge->n].vaddr;
198 sge->length =
199 sge->mr->map[sge->m]->segs[sge->n].length;
200 }
201 data += len;
202 length -= len;
203 }
204}
205
206/**
207 * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
208 * @ss: the SGE state
209 * @length: the number of bytes to skip
210 */
211void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
212{
213 struct qib_sge *sge = &ss->sge;
214
215 while (length) {
216 u32 len = sge->length;
217
218 if (len > length)
219 len = length;
220 if (len > sge->sge_length)
221 len = sge->sge_length;
222 BUG_ON(len == 0);
223 sge->vaddr += len;
224 sge->length -= len;
225 sge->sge_length -= len;
226 if (sge->sge_length == 0) {
227 if (release)
6a82649f 228 qib_put_mr(sge->mr);
f931551b
RC		 229 if (--ss->num_sge)
230 *sge = *ss->sg_list++;
231 } else if (sge->length == 0 && sge->mr->lkey) {
232 if (++sge->n >= QIB_SEGSZ) {
233 if (++sge->m >= sge->mr->mapsz)
234 break;
235 sge->n = 0;
236 }
237 sge->vaddr =
238 sge->mr->map[sge->m]->segs[sge->n].vaddr;
239 sge->length =
240 sge->mr->map[sge->m]->segs[sge->n].length;
241 }
242 length -= len;
243 }
244}
245
246/*
247 * Count the number of DMA descriptors needed to send length bytes of data.
248 * Don't modify the qib_sge_state to get the count.
249 * Return zero if any of the segments is not aligned.
250 */
251static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
252{
253 struct qib_sge *sg_list = ss->sg_list;
254 struct qib_sge sge = ss->sge;
255 u8 num_sge = ss->num_sge;
256 u32 ndesc = 1; /* count the header */
257
258 while (length) {
259 u32 len = sge.length;
260
261 if (len > length)
262 len = length;
263 if (len > sge.sge_length)
264 len = sge.sge_length;
265 BUG_ON(len == 0);
266 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
267 (len != length && (len & (sizeof(u32) - 1)))) {
268 ndesc = 0;
269 break;
270 }
271 ndesc++;
272 sge.vaddr += len;
273 sge.length -= len;
274 sge.sge_length -= len;
275 if (sge.sge_length == 0) {
276 if (--num_sge)
277 sge = *sg_list++;
278 } else if (sge.length == 0 && sge.mr->lkey) {
279 if (++sge.n >= QIB_SEGSZ) {
280 if (++sge.m >= sge.mr->mapsz)
281 break;
282 sge.n = 0;
283 }
284 sge.vaddr =
285 sge.mr->map[sge.m]->segs[sge.n].vaddr;
286 sge.length =
287 sge.mr->map[sge.m]->segs[sge.n].length;
288 }
289 length -= len;
290 }
291 return ndesc;
292}
293
294/*
295 * Copy from the SGEs to the data buffer.
296 */
297static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
298{
299 struct qib_sge *sge = &ss->sge;
300
301 while (length) {
302 u32 len = sge->length;
303
304 if (len > length)
305 len = length;
306 if (len > sge->sge_length)
307 len = sge->sge_length;
308 BUG_ON(len == 0);
309 memcpy(data, sge->vaddr, len);
310 sge->vaddr += len;
311 sge->length -= len;
312 sge->sge_length -= len;
313 if (sge->sge_length == 0) {
314 if (--ss->num_sge)
315 *sge = *ss->sg_list++;
316 } else if (sge->length == 0 && sge->mr->lkey) {
317 if (++sge->n >= QIB_SEGSZ) {
318 if (++sge->m >= sge->mr->mapsz)
319 break;
320 sge->n = 0;
321 }
322 sge->vaddr =
323 sge->mr->map[sge->m]->segs[sge->n].vaddr;
324 sge->length =
325 sge->mr->map[sge->m]->segs[sge->n].length;
326 }
327 data += len;
328 length -= len;
329 }
330}
331
332/**
333 * qib_post_one_send - post one RC, UC, or UD send work request
334 * @qp: the QP to post on
335 * @wr: the work request to send
336 */
551ace12
MM		 337static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr,
338 int *scheduled)
f931551b
RC		 339{
340 struct qib_swqe *wqe;
341 u32 next;
342 int i;
343 int j;
344 int acc;
345 int ret;
346 unsigned long flags;
347 struct qib_lkey_table *rkt;
348 struct qib_pd *pd;
349
350 spin_lock_irqsave(&qp->s_lock, flags);
351
352 /* Check that state is OK to post send. */
353 if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
354 goto bail_inval;
355
356 /* IB spec says that num_sge == 0 is OK. */
357 if (wr->num_sge > qp->s_max_sge)
358 goto bail_inval;
359
360 /*
361 * Don't allow RDMA reads or atomic operations on UC or
362 * undefined operations.
363 * Make sure buffer is large enough to hold the result for atomics.
364 */
365 if (wr->opcode == IB_WR_FAST_REG_MR) {
366 if (qib_fast_reg_mr(qp, wr))
367 goto bail_inval;
368 } else if (qp->ibqp.qp_type == IB_QPT_UC) {
369 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
370 goto bail_inval;
371 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
372 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
373 if (wr->opcode != IB_WR_SEND &&
374 wr->opcode != IB_WR_SEND_WITH_IMM)
375 goto bail_inval;
376 /* Check UD destination address PD */
377 if (qp->ibqp.pd != wr->wr.ud.ah->pd)
378 goto bail_inval;
379 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
380 goto bail_inval;
381 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
382 (wr->num_sge == 0 ||
383 wr->sg_list[0].length < sizeof(u64) ||
384 wr->sg_list[0].addr & (sizeof(u64) - 1)))
385 goto bail_inval;
386 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
387 goto bail_inval;
388
389 next = qp->s_head + 1;
390 if (next >= qp->s_size)
391 next = 0;
392 if (next == qp->s_last) {
393 ret = -ENOMEM;
394 goto bail;
395 }
396
397 rkt = &to_idev(qp->ibqp.device)->lk_table;
398 pd = to_ipd(qp->ibqp.pd);
399 wqe = get_swqe_ptr(qp, qp->s_head);
400 wqe->wr = *wr;
401 wqe->length = 0;
402 j = 0;
403 if (wr->num_sge) {
404 acc = wr->opcode >= IB_WR_RDMA_READ ?
405 IB_ACCESS_LOCAL_WRITE : 0;
406 for (i = 0; i < wr->num_sge; i++) {
407 u32 length = wr->sg_list[i].length;
408 int ok;
409
410 if (length == 0)
411 continue;
412 ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
413 &wr->sg_list[i], acc);
414 if (!ok)
415 goto bail_inval_free;
416 wqe->length += length;
417 j++;
418 }
419 wqe->wr.num_sge = j;
420 }
421 if (qp->ibqp.qp_type == IB_QPT_UC ||
422 qp->ibqp.qp_type == IB_QPT_RC) {
423 if (wqe->length > 0x80000000U)
424 goto bail_inval_free;
425 } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
426 qp->port_num - 1)->ibmtu)
427 goto bail_inval_free;
428 else
429 atomic_inc(&to_iah(wr->wr.ud.ah)->refcount);
430 wqe->ssn = qp->s_ssn++;
431 qp->s_head = next;
432
433 ret = 0;
434 goto bail;
435
436bail_inval_free:
437 while (j) {
438 struct qib_sge *sge = &wqe->sg_list[--j];
439
6a82649f 440 qib_put_mr(sge->mr);
f931551b
RC		 441 }
442bail_inval:
443 ret = -EINVAL;
444bail:
551ace12
MM		 445 if (!ret && !wr->next &&
446 !qib_sdma_empty(
447 dd_from_ibdev(qp->ibqp.device)->pport + qp->port_num - 1)) {
448 qib_schedule_send(qp);
449 *scheduled = 1;
450 }
f931551b
RC		 451 spin_unlock_irqrestore(&qp->s_lock, flags);
452 return ret;
453}
454
455/**
456 * qib_post_send - post a send on a QP
457 * @ibqp: the QP to post the send on
458 * @wr: the list of work requests to post
459 * @bad_wr: the first bad WR is put here
460 *
461 * This may be called from interrupt context.
462 */
463static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
464 struct ib_send_wr **bad_wr)
465{
466 struct qib_qp *qp = to_iqp(ibqp);
467 int err = 0;
551ace12 468 int scheduled = 0;
f931551b
RC		 469
470 for (; wr; wr = wr->next) {
551ace12 471 err = qib_post_one_send(qp, wr, &scheduled);
f931551b
RC		 472 if (err) {
473 *bad_wr = wr;
474 goto bail;
475 }
476 }
477
478 /* Try to do the send work in the caller's context. */
551ace12
MM		 479 if (!scheduled)
480 qib_do_send(&qp->s_work);
f931551b
RC		 481
482bail:
483 return err;
484}
485
486/**
487 * qib_post_receive - post a receive on a QP
488 * @ibqp: the QP to post the receive on
489 * @wr: the WR to post
490 * @bad_wr: the first bad WR is put here
491 *
492 * This may be called from interrupt context.
493 */
494static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
495 struct ib_recv_wr **bad_wr)
496{
497 struct qib_qp *qp = to_iqp(ibqp);
498 struct qib_rwq *wq = qp->r_rq.wq;
499 unsigned long flags;
500 int ret;
501
502 /* Check that state is OK to post receive. */
503 if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
504 *bad_wr = wr;
505 ret = -EINVAL;
506 goto bail;
507 }
508
509 for (; wr; wr = wr->next) {
510 struct qib_rwqe *wqe;
511 u32 next;
512 int i;
513
514 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
515 *bad_wr = wr;
516 ret = -EINVAL;
517 goto bail;
518 }
519
520 spin_lock_irqsave(&qp->r_rq.lock, flags);
521 next = wq->head + 1;
522 if (next >= qp->r_rq.size)
523 next = 0;
524 if (next == wq->tail) {
525 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
526 *bad_wr = wr;
527 ret = -ENOMEM;
528 goto bail;
529 }
530
531 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
532 wqe->wr_id = wr->wr_id;
533 wqe->num_sge = wr->num_sge;
534 for (i = 0; i < wr->num_sge; i++)
535 wqe->sg_list[i] = wr->sg_list[i];
536 /* Make sure queue entry is written before the head index. */
537 smp_wmb();
538 wq->head = next;
539 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
540 }
541 ret = 0;
542
543bail:
544 return ret;
545}
546
547/**
548 * qib_qp_rcv - processing an incoming packet on a QP
549 * @rcd: the context pointer
550 * @hdr: the packet header
551 * @has_grh: true if the packet has a GRH
552 * @data: the packet data
553 * @tlen: the packet length
554 * @qp: the QP the packet came on
555 *
556 * This is called from qib_ib_rcv() to process an incoming packet
557 * for the given QP.
558 * Called at interrupt level.
559 */
560static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
561 int has_grh, void *data, u32 tlen, struct qib_qp *qp)
562{
563 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
564
a5210c12
RC		 565 spin_lock(&qp->r_lock);
566
f931551b
RC		 567 /* Check for valid receive state. */
568 if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
569 ibp->n_pkt_drops++;
a5210c12 570 goto unlock;
f931551b
RC		 571 }
572
573 switch (qp->ibqp.qp_type) {
574 case IB_QPT_SMI:
575 case IB_QPT_GSI:
576 if (ib_qib_disable_sma)
577 break;
578 /* FALLTHROUGH */
579 case IB_QPT_UD:
580 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
581 break;
582
583 case IB_QPT_RC:
584 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
585 break;
586
587 case IB_QPT_UC:
588 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
589 break;
590
591 default:
592 break;
593 }
a5210c12
RC		 594
595unlock:
596 spin_unlock(&qp->r_lock);
f931551b
RC		 597}
598
599/**
600 * qib_ib_rcv - process an incoming packet
601 * @rcd: the context pointer
602 * @rhdr: the header of the packet
603 * @data: the packet payload
604 * @tlen: the packet length
605 *
606 * This is called from qib_kreceive() to process an incoming packet at
607 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
608 */
609void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
610{
611 struct qib_pportdata *ppd = rcd->ppd;
612 struct qib_ibport *ibp = &ppd->ibport_data;
613 struct qib_ib_header *hdr = rhdr;
614 struct qib_other_headers *ohdr;
615 struct qib_qp *qp;
616 u32 qp_num;
617 int lnh;
618 u8 opcode;
619 u16 lid;
620
621 /* 24 == LRH+BTH+CRC */
622 if (unlikely(tlen < 24))
623 goto drop;
624
625 /* Check for a valid destination LID (see ch. 7.11.1). */
626 lid = be16_to_cpu(hdr->lrh[1]);
627 if (lid < QIB_MULTICAST_LID_BASE) {
628 lid &= ~((1 << ppd->lmc) - 1);
629 if (unlikely(lid != ppd->lid))
630 goto drop;
631 }
632
633 /* Check for GRH */
634 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
635 if (lnh == QIB_LRH_BTH)
636 ohdr = &hdr->u.oth;
637 else if (lnh == QIB_LRH_GRH) {
638 u32 vtf;
639
640 ohdr = &hdr->u.l.oth;
641 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
642 goto drop;
643 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
644 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
645 goto drop;
646 } else
647 goto drop;
648
649 opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
650 ibp->opstats[opcode & 0x7f].n_bytes += tlen;
651 ibp->opstats[opcode & 0x7f].n_packets++;
652
653 /* Get the destination QP number. */
654 qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
655 if (qp_num == QIB_MULTICAST_QPN) {
656 struct qib_mcast *mcast;
657 struct qib_mcast_qp *p;
658
659 if (lnh != QIB_LRH_GRH)
660 goto drop;
661 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
662 if (mcast == NULL)
663 goto drop;
664 ibp->n_multicast_rcv++;
665 list_for_each_entry_rcu(p, &mcast->qp_list, list)
666 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
667 /*
668 * Notify qib_multicast_detach() if it is waiting for us
669 * to finish.
670 */
671 if (atomic_dec_return(&mcast->refcount) <= 1)
672 wake_up(&mcast->wait);
673 } else {
af061a64
MM		 674 if (rcd->lookaside_qp) {
675 if (rcd->lookaside_qpn != qp_num) {
676 if (atomic_dec_and_test(
677 &rcd->lookaside_qp->refcount))
678 wake_up(
679 &rcd->lookaside_qp->wait);
680 rcd->lookaside_qp = NULL;
681 }
682 }
683 if (!rcd->lookaside_qp) {
684 qp = qib_lookup_qpn(ibp, qp_num);
685 if (!qp)
686 goto drop;
687 rcd->lookaside_qp = qp;
688 rcd->lookaside_qpn = qp_num;
689 } else
690 qp = rcd->lookaside_qp;
f931551b
RC		 691 ibp->n_unicast_rcv++;
692 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
f931551b
RC		 693 }
694 return;
695
696drop:
697 ibp->n_pkt_drops++;
698}
699
700/*
701 * This is called from a timer to check for QPs
702 * which need kernel memory in order to send a packet.
703 */
704static void mem_timer(unsigned long data)
705{
706 struct qib_ibdev *dev = (struct qib_ibdev *) data;
707 struct list_head *list = &dev->memwait;
708 struct qib_qp *qp = NULL;
709 unsigned long flags;
710
711 spin_lock_irqsave(&dev->pending_lock, flags);
712 if (!list_empty(list)) {
713 qp = list_entry(list->next, struct qib_qp, iowait);
714 list_del_init(&qp->iowait);
715 atomic_inc(&qp->refcount);
716 if (!list_empty(list))
717 mod_timer(&dev->mem_timer, jiffies + 1);
718 }
719 spin_unlock_irqrestore(&dev->pending_lock, flags);
720
721 if (qp) {
722 spin_lock_irqsave(&qp->s_lock, flags);
723 if (qp->s_flags & QIB_S_WAIT_KMEM) {
724 qp->s_flags &= ~QIB_S_WAIT_KMEM;
725 qib_schedule_send(qp);
726 }
727 spin_unlock_irqrestore(&qp->s_lock, flags);
728 if (atomic_dec_and_test(&qp->refcount))
729 wake_up(&qp->wait);
730 }
731}
732
733static void update_sge(struct qib_sge_state *ss, u32 length)
734{
735 struct qib_sge *sge = &ss->sge;
736
737 sge->vaddr += length;
738 sge->length -= length;
739 sge->sge_length -= length;
740 if (sge->sge_length == 0) {
741 if (--ss->num_sge)
742 *sge = *ss->sg_list++;
743 } else if (sge->length == 0 && sge->mr->lkey) {
744 if (++sge->n >= QIB_SEGSZ) {
745 if (++sge->m >= sge->mr->mapsz)
746 return;
747 sge->n = 0;
748 }
749 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
750 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
751 }
752}
753
754#ifdef __LITTLE_ENDIAN
755static inline u32 get_upper_bits(u32 data, u32 shift)
756{
757 return data >> shift;
758}
759
760static inline u32 set_upper_bits(u32 data, u32 shift)
761{
762 return data << shift;
763}
764
765static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
766{
767 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
768 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
769 return data;
770}
771#else
772static inline u32 get_upper_bits(u32 data, u32 shift)
773{
774 return data << shift;
775}
776
777static inline u32 set_upper_bits(u32 data, u32 shift)
778{
779 return data >> shift;
780}
781
782static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
783{
784 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
785 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
786 return data;
787}
788#endif
789
790static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
791 u32 length, unsigned flush_wc)
792{
793 u32 extra = 0;
794 u32 data = 0;
795 u32 last;
796
797 while (1) {
798 u32 len = ss->sge.length;
799 u32 off;
800
801 if (len > length)
802 len = length;
803 if (len > ss->sge.sge_length)
804 len = ss->sge.sge_length;
805 BUG_ON(len == 0);
806 /* If the source address is not aligned, try to align it. */
807 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
808 if (off) {
809 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
810 ~(sizeof(u32) - 1));
811 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
812 u32 y;
813
814 y = sizeof(u32) - off;
815 if (len > y)
816 len = y;
817 if (len + extra >= sizeof(u32)) {
818 data |= set_upper_bits(v, extra *
819 BITS_PER_BYTE);
820 len = sizeof(u32) - extra;
821 if (len == length) {
822 last = data;
823 break;
824 }
825 __raw_writel(data, piobuf);
826 piobuf++;
827 extra = 0;
828 data = 0;
829 } else {
830 /* Clear unused upper bytes */
831 data |= clear_upper_bytes(v, len, extra);
832 if (len == length) {
833 last = data;
834 break;
835 }
836 extra += len;
837 }
838 } else if (extra) {
839 /* Source address is aligned. */
840 u32 *addr = (u32 *) ss->sge.vaddr;
841 int shift = extra * BITS_PER_BYTE;
842 int ushift = 32 - shift;
843 u32 l = len;
844
845 while (l >= sizeof(u32)) {
846 u32 v = *addr;
847
848 data |= set_upper_bits(v, shift);
849 __raw_writel(data, piobuf);
850 data = get_upper_bits(v, ushift);
851 piobuf++;
852 addr++;
853 l -= sizeof(u32);
854 }
855 /*
856 * We still have 'extra' number of bytes leftover.
857 */
858 if (l) {
859 u32 v = *addr;
860
861 if (l + extra >= sizeof(u32)) {
862 data |= set_upper_bits(v, shift);
863 len -= l + extra - sizeof(u32);
864 if (len == length) {
865 last = data;
866 break;
867 }
868 __raw_writel(data, piobuf);
869 piobuf++;
870 extra = 0;
871 data = 0;
872 } else {
873 /* Clear unused upper bytes */
874 data |= clear_upper_bytes(v, l, extra);
875 if (len == length) {
876 last = data;
877 break;
878 }
879 extra += l;
880 }
881 } else if (len == length) {
882 last = data;
883 break;
884 }
885 } else if (len == length) {
886 u32 w;
887
888 /*
889 * Need to round up for the last dword in the
890 * packet.
891 */
892 w = (len + 3) >> 2;
893 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
894 piobuf += w - 1;
895 last = ((u32 *) ss->sge.vaddr)[w - 1];
896 break;
897 } else {
898 u32 w = len >> 2;
899
900 qib_pio_copy(piobuf, ss->sge.vaddr, w);
901 piobuf += w;
902
903 extra = len & (sizeof(u32) - 1);
904 if (extra) {
905 u32 v = ((u32 *) ss->sge.vaddr)[w];
906
907 /* Clear unused upper bytes */
908 data = clear_upper_bytes(v, extra, 0);
909 }
910 }
911 update_sge(ss, len);
912 length -= len;
913 }
914 /* Update address before sending packet. */
915 update_sge(ss, length);
916 if (flush_wc) {
917 /* must flush early everything before trigger word */
918 qib_flush_wc();
919 __raw_writel(last, piobuf);
920 /* be sure trigger word is written */
921 qib_flush_wc();
922 } else
923 __raw_writel(last, piobuf);
924}
925
48947109
MM		 926static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
927 struct qib_qp *qp)
f931551b
RC		 928{
929 struct qib_verbs_txreq *tx;
930 unsigned long flags;
931
932 spin_lock_irqsave(&qp->s_lock, flags);
933 spin_lock(&dev->pending_lock);
934
935 if (!list_empty(&dev->txreq_free)) {
936 struct list_head *l = dev->txreq_free.next;
937
938 list_del(l);
48947109
MM		 939 spin_unlock(&dev->pending_lock);
940 spin_unlock_irqrestore(&qp->s_lock, flags);
f931551b 941 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
f931551b
RC		 942 } else {
943 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
944 list_empty(&qp->iowait)) {
945 dev->n_txwait++;
946 qp->s_flags |= QIB_S_WAIT_TX;
947 list_add_tail(&qp->iowait, &dev->txwait);
948 }
f931551b 949 qp->s_flags &= ~QIB_S_BUSY;
48947109
MM		 950 spin_unlock(&dev->pending_lock);
951 spin_unlock_irqrestore(&qp->s_lock, flags);
952 tx = ERR_PTR(-EBUSY);
f931551b 953 }
48947109
MM		 954 return tx;
955}
f931551b 956
48947109
MM		 957static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
958 struct qib_qp *qp)
959{
960 struct qib_verbs_txreq *tx;
961 unsigned long flags;
f931551b 962
48947109
MM		 963 spin_lock_irqsave(&dev->pending_lock, flags);
964 /* assume the list non empty */
965 if (likely(!list_empty(&dev->txreq_free))) {
966 struct list_head *l = dev->txreq_free.next;
967
968 list_del(l);
969 spin_unlock_irqrestore(&dev->pending_lock, flags);
970 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
971 } else {
972 /* call slow path to get the extra lock */
973 spin_unlock_irqrestore(&dev->pending_lock, flags);
974 tx = __get_txreq(dev, qp);
975 }
f931551b
RC		 976 return tx;
977}
978
979void qib_put_txreq(struct qib_verbs_txreq *tx)
980{
981 struct qib_ibdev *dev;
982 struct qib_qp *qp;
983 unsigned long flags;
984
985 qp = tx->qp;
986 dev = to_idev(qp->ibqp.device);
987
988 if (atomic_dec_and_test(&qp->refcount))
989 wake_up(&qp->wait);
990 if (tx->mr) {
6a82649f 991 qib_put_mr(tx->mr);
f931551b
RC		 992 tx->mr = NULL;
993 }
994 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
995 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
996 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
997 tx->txreq.addr, tx->hdr_dwords << 2,
998 DMA_TO_DEVICE);
999 kfree(tx->align_buf);
1000 }
1001
1002 spin_lock_irqsave(&dev->pending_lock, flags);
1003
1004 /* Put struct back on free list */
1005 list_add(&tx->txreq.list, &dev->txreq_free);
1006
1007 if (!list_empty(&dev->txwait)) {
1008 /* Wake up first QP wanting a free struct */
1009 qp = list_entry(dev->txwait.next, struct qib_qp, iowait);
1010 list_del_init(&qp->iowait);
1011 atomic_inc(&qp->refcount);
1012 spin_unlock_irqrestore(&dev->pending_lock, flags);
1013
1014 spin_lock_irqsave(&qp->s_lock, flags);
1015 if (qp->s_flags & QIB_S_WAIT_TX) {
1016 qp->s_flags &= ~QIB_S_WAIT_TX;
1017 qib_schedule_send(qp);
1018 }
1019 spin_unlock_irqrestore(&qp->s_lock, flags);
1020
1021 if (atomic_dec_and_test(&qp->refcount))
1022 wake_up(&qp->wait);
1023 } else
1024 spin_unlock_irqrestore(&dev->pending_lock, flags);
1025}
1026
1027/*
1028 * This is called when there are send DMA descriptors that might be
1029 * available.
1030 *
1031 * This is called with ppd->sdma_lock held.
1032 */
1033void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
1034{
1035 struct qib_qp *qp, *nqp;
1036 struct qib_qp *qps[20];
1037 struct qib_ibdev *dev;
1038 unsigned i, n;
1039
1040 n = 0;
1041 dev = &ppd->dd->verbs_dev;
1042 spin_lock(&dev->pending_lock);
1043
1044 /* Search wait list for first QP wanting DMA descriptors. */
1045 list_for_each_entry_safe(qp, nqp, &dev->dmawait, iowait) {
1046 if (qp->port_num != ppd->port)
1047 continue;
1048 if (n == ARRAY_SIZE(qps))
1049 break;
1050 if (qp->s_tx->txreq.sg_count > avail)
1051 break;
1052 avail -= qp->s_tx->txreq.sg_count;
1053 list_del_init(&qp->iowait);
1054 atomic_inc(&qp->refcount);
1055 qps[n++] = qp;
1056 }
1057
1058 spin_unlock(&dev->pending_lock);
1059
1060 for (i = 0; i < n; i++) {
1061 qp = qps[i];
1062 spin_lock(&qp->s_lock);
1063 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1064 qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1065 qib_schedule_send(qp);
1066 }
1067 spin_unlock(&qp->s_lock);
1068 if (atomic_dec_and_test(&qp->refcount))
1069 wake_up(&qp->wait);
1070 }
1071}
1072
1073/*
1074 * This is called with ppd->sdma_lock held.
1075 */
1076static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1077{
1078 struct qib_verbs_txreq *tx =
1079 container_of(cookie, struct qib_verbs_txreq, txreq);
1080 struct qib_qp *qp = tx->qp;
1081
1082 spin_lock(&qp->s_lock);
1083 if (tx->wqe)
1084 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1085 else if (qp->ibqp.qp_type == IB_QPT_RC) {
1086 struct qib_ib_header *hdr;
1087
1088 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1089 hdr = &tx->align_buf->hdr;
1090 else {
1091 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1092
1093 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1094 }
1095 qib_rc_send_complete(qp, hdr);
1096 }
1097 if (atomic_dec_and_test(&qp->s_dma_busy)) {
1098 if (qp->state == IB_QPS_RESET)
1099 wake_up(&qp->wait_dma);
1100 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1101 qp->s_flags &= ~QIB_S_WAIT_DMA;
1102 qib_schedule_send(qp);
1103 }
1104 }
1105 spin_unlock(&qp->s_lock);
1106
1107 qib_put_txreq(tx);
1108}
1109
1110static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1111{
1112 unsigned long flags;
1113 int ret = 0;
1114
1115 spin_lock_irqsave(&qp->s_lock, flags);
1116 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1117 spin_lock(&dev->pending_lock);
1118 if (list_empty(&qp->iowait)) {
1119 if (list_empty(&dev->memwait))
1120 mod_timer(&dev->mem_timer, jiffies + 1);
1121 qp->s_flags |= QIB_S_WAIT_KMEM;
1122 list_add_tail(&qp->iowait, &dev->memwait);
1123 }
1124 spin_unlock(&dev->pending_lock);
1125 qp->s_flags &= ~QIB_S_BUSY;
1126 ret = -EBUSY;
1127 }
1128 spin_unlock_irqrestore(&qp->s_lock, flags);
1129
1130 return ret;
1131}
1132
1133static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1134 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1135 u32 plen, u32 dwords)
1136{
1137 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1138 struct qib_devdata *dd = dd_from_dev(dev);
1139 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1140 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1141 struct qib_verbs_txreq *tx;
1142 struct qib_pio_header *phdr;
1143 u32 control;
1144 u32 ndesc;
1145 int ret;
1146
1147 tx = qp->s_tx;
1148 if (tx) {
1149 qp->s_tx = NULL;
1150 /* resend previously constructed packet */
1151 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1152 goto bail;
1153 }
1154
48947109
MM		 1155 tx = get_txreq(dev, qp);
1156 if (IS_ERR(tx))
1157 goto bail_tx;
f931551b
RC		 1158
1159 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1160 be16_to_cpu(hdr->lrh[0]) >> 12);
1161 tx->qp = qp;
1162 atomic_inc(&qp->refcount);
1163 tx->wqe = qp->s_wqe;
1164 tx->mr = qp->s_rdma_mr;
1165 if (qp->s_rdma_mr)
1166 qp->s_rdma_mr = NULL;
1167 tx->txreq.callback = sdma_complete;
1168 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1169 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1170 else
1171 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1172 if (plen + 1 > dd->piosize2kmax_dwords)
1173 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1174
1175 if (len) {
1176 /*
1177 * Don't try to DMA if it takes more descriptors than
1178 * the queue holds.
1179 */
1180 ndesc = qib_count_sge(ss, len);
1181 if (ndesc >= ppd->sdma_descq_cnt)
1182 ndesc = 0;
1183 } else
1184 ndesc = 1;
1185 if (ndesc) {
1186 phdr = &dev->pio_hdrs[tx->hdr_inx];
1187 phdr->pbc[0] = cpu_to_le32(plen);
1188 phdr->pbc[1] = cpu_to_le32(control);
1189 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1190 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1191 tx->txreq.sg_count = ndesc;
1192 tx->txreq.addr = dev->pio_hdrs_phys +
1193 tx->hdr_inx * sizeof(struct qib_pio_header);
1194 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1195 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1196 goto bail;
1197 }
1198
1199 /* Allocate a buffer and copy the header and payload to it. */
1200 tx->hdr_dwords = plen + 1;
1201 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1202 if (!phdr)
1203 goto err_tx;
1204 phdr->pbc[0] = cpu_to_le32(plen);
1205 phdr->pbc[1] = cpu_to_le32(control);
1206 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1207 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1208
1209 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1210 tx->hdr_dwords << 2, DMA_TO_DEVICE);
1211 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1212 goto map_err;
1213 tx->align_buf = phdr;
1214 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1215 tx->txreq.sg_count = 1;
1216 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1217 goto unaligned;
1218
1219map_err:
1220 kfree(phdr);
1221err_tx:
1222 qib_put_txreq(tx);
1223 ret = wait_kmem(dev, qp);
1224unaligned:
1225 ibp->n_unaligned++;
1226bail:
1227 return ret;
48947109
MM		 1228bail_tx:
1229 ret = PTR_ERR(tx);
1230 goto bail;
f931551b
RC		 1231}
1232
1233/*
1234 * If we are now in the error state, return zero to flush the
1235 * send work request.
1236 */
1237static int no_bufs_available(struct qib_qp *qp)
1238{
1239 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1240 struct qib_devdata *dd;
1241 unsigned long flags;
1242 int ret = 0;
1243
1244 /*
1245 * Note that as soon as want_buffer() is called and
1246 * possibly before it returns, qib_ib_piobufavail()
1247 * could be called. Therefore, put QP on the I/O wait list before
1248 * enabling the PIO avail interrupt.
1249 */
1250 spin_lock_irqsave(&qp->s_lock, flags);
1251 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1252 spin_lock(&dev->pending_lock);
1253 if (list_empty(&qp->iowait)) {
1254 dev->n_piowait++;
1255 qp->s_flags |= QIB_S_WAIT_PIO;
1256 list_add_tail(&qp->iowait, &dev->piowait);
1257 dd = dd_from_dev(dev);
1258 dd->f_wantpiobuf_intr(dd, 1);
1259 }
1260 spin_unlock(&dev->pending_lock);
1261 qp->s_flags &= ~QIB_S_BUSY;
1262 ret = -EBUSY;
1263 }
1264 spin_unlock_irqrestore(&qp->s_lock, flags);
1265 return ret;
1266}
1267
1268static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1269 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1270 u32 plen, u32 dwords)
1271{
1272 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1273 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1274 u32 *hdr = (u32 *) ibhdr;
1275 u32 __iomem *piobuf_orig;
1276 u32 __iomem *piobuf;
1277 u64 pbc;
1278 unsigned long flags;
1279 unsigned flush_wc;
1280 u32 control;
1281 u32 pbufn;
1282
1283 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1284 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1285 pbc = ((u64) control << 32) | plen;
1286 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1287 if (unlikely(piobuf == NULL))
1288 return no_bufs_available(qp);
1289
1290 /*
1291 * Write the pbc.
1292 * We have to flush after the PBC for correctness on some cpus
1293 * or WC buffer can be written out of order.
1294 */
1295 writeq(pbc, piobuf);
1296 piobuf_orig = piobuf;
1297 piobuf += 2;
1298
1299 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1300 if (len == 0) {
1301 /*
1302 * If there is just the header portion, must flush before
1303 * writing last word of header for correctness, and after
1304 * the last header word (trigger word).
1305 */
1306 if (flush_wc) {
1307 qib_flush_wc();
1308 qib_pio_copy(piobuf, hdr, hdrwords - 1);
1309 qib_flush_wc();
1310 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1311 qib_flush_wc();
1312 } else
1313 qib_pio_copy(piobuf, hdr, hdrwords);
1314 goto done;
1315 }
1316
1317 if (flush_wc)
1318 qib_flush_wc();
1319 qib_pio_copy(piobuf, hdr, hdrwords);
1320 piobuf += hdrwords;
1321
1322 /* The common case is aligned and contained in one segment. */
1323 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1324 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1325 u32 *addr = (u32 *) ss->sge.vaddr;
1326
1327 /* Update address before sending packet. */
1328 update_sge(ss, len);
1329 if (flush_wc) {
1330 qib_pio_copy(piobuf, addr, dwords - 1);
1331 /* must flush early everything before trigger word */
1332 qib_flush_wc();
1333 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1334 /* be sure trigger word is written */
1335 qib_flush_wc();
1336 } else
1337 qib_pio_copy(piobuf, addr, dwords);
1338 goto done;
1339 }
1340 copy_io(piobuf, ss, len, flush_wc);
1341done:
1342 if (dd->flags & QIB_USE_SPCL_TRIG) {
1343 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1344 qib_flush_wc();
1345 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1346 }
1347 qib_sendbuf_done(dd, pbufn);
1348 if (qp->s_rdma_mr) {
6a82649f 1349 qib_put_mr(qp->s_rdma_mr);
f931551b
RC		 1350 qp->s_rdma_mr = NULL;
1351 }
1352 if (qp->s_wqe) {
1353 spin_lock_irqsave(&qp->s_lock, flags);
1354 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1355 spin_unlock_irqrestore(&qp->s_lock, flags);
1356 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1357 spin_lock_irqsave(&qp->s_lock, flags);
1358 qib_rc_send_complete(qp, ibhdr);
1359 spin_unlock_irqrestore(&qp->s_lock, flags);
1360 }
1361 return 0;
1362}
1363
1364/**
1365 * qib_verbs_send - send a packet
1366 * @qp: the QP to send on
1367 * @hdr: the packet header
1368 * @hdrwords: the number of 32-bit words in the header
1369 * @ss: the SGE to send
1370 * @len: the length of the packet in bytes
1371 *
1372 * Return zero if packet is sent or queued OK.
1373 * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1374 */
1375int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1376 u32 hdrwords, struct qib_sge_state *ss, u32 len)
1377{
1378 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1379 u32 plen;
1380 int ret;
1381 u32 dwords = (len + 3) >> 2;
1382
1383 /*
1384 * Calculate the send buffer trigger address.
1385 * The +1 counts for the pbc control dword following the pbc length.
1386 */
1387 plen = hdrwords + dwords + 1;
1388
1389 /*
1390 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1391 * can defer SDMA restart until link goes ACTIVE without
1392 * worrying about just how we got there.
1393 */
1394 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1395 !(dd->flags & QIB_HAS_SEND_DMA))
1396 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1397 plen, dwords);
1398 else
1399 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1400 plen, dwords);
1401
1402 return ret;
1403}
1404
1405int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1406 u64 *rwords, u64 *spkts, u64 *rpkts,
1407 u64 *xmit_wait)
1408{
1409 int ret;
1410 struct qib_devdata *dd = ppd->dd;
1411
1412 if (!(dd->flags & QIB_PRESENT)) {
1413 /* no hardware, freeze, etc. */
1414 ret = -EINVAL;
1415 goto bail;
1416 }
1417 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1418 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1419 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1420 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1421 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1422
1423 ret = 0;
1424
1425bail:
1426 return ret;
1427}
1428
1429/**
1430 * qib_get_counters - get various chip counters
1431 * @dd: the qlogic_ib device
1432 * @cntrs: counters are placed here
1433 *
1434 * Return the counters needed by recv_pma_get_portcounters().
1435 */
1436int qib_get_counters(struct qib_pportdata *ppd,
1437 struct qib_verbs_counters *cntrs)
1438{
1439 int ret;
1440
1441 if (!(ppd->dd->flags & QIB_PRESENT)) {
1442 /* no hardware, freeze, etc. */
1443 ret = -EINVAL;
1444 goto bail;
1445 }
1446 cntrs->symbol_error_counter =
1447 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1448 cntrs->link_error_recovery_counter =
1449 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1450 /*
1451 * The link downed counter counts when the other side downs the
1452 * connection. We add in the number of times we downed the link
1453 * due to local link integrity errors to compensate.
1454 */
1455 cntrs->link_downed_counter =
1456 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1457 cntrs->port_rcv_errors =
1458 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1459 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1460 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1461 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1462 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1463 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1464 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1465 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1466 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1467 cntrs->port_rcv_errors +=
1468 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1469 cntrs->port_rcv_errors +=
1470 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1471 cntrs->port_rcv_remphys_errors =
1472 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1473 cntrs->port_xmit_discards =
1474 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1475 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1476 QIBPORTCNTR_WORDSEND);
1477 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1478 QIBPORTCNTR_WORDRCV);
1479 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1480 QIBPORTCNTR_PKTSEND);
1481 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1482 QIBPORTCNTR_PKTRCV);
1483 cntrs->local_link_integrity_errors =
1484 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1485 cntrs->excessive_buffer_overrun_errors =
1486 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1487 cntrs->vl15_dropped =
1488 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1489
1490 ret = 0;
1491
1492bail:
1493 return ret;
1494}
1495
1496/**
1497 * qib_ib_piobufavail - callback when a PIO buffer is available
1498 * @dd: the device pointer
1499 *
1500 * This is called from qib_intr() at interrupt level when a PIO buffer is
1501 * available after qib_verbs_send() returned an error that no buffers were
1502 * available. Disable the interrupt if there are no more QPs waiting.
1503 */
1504void qib_ib_piobufavail(struct qib_devdata *dd)
1505{
1506 struct qib_ibdev *dev = &dd->verbs_dev;
1507 struct list_head *list;
1508 struct qib_qp *qps[5];
1509 struct qib_qp *qp;
1510 unsigned long flags;
1511 unsigned i, n;
1512
1513 list = &dev->piowait;
1514 n = 0;
1515
1516 /*
1517 * Note: checking that the piowait list is empty and clearing
1518 * the buffer available interrupt needs to be atomic or we
1519 * could end up with QPs on the wait list with the interrupt
1520 * disabled.
1521 */
1522 spin_lock_irqsave(&dev->pending_lock, flags);
1523 while (!list_empty(list)) {
1524 if (n == ARRAY_SIZE(qps))
1525 goto full;
1526 qp = list_entry(list->next, struct qib_qp, iowait);
1527 list_del_init(&qp->iowait);
1528 atomic_inc(&qp->refcount);
1529 qps[n++] = qp;
1530 }
1531 dd->f_wantpiobuf_intr(dd, 0);
1532full:
1533 spin_unlock_irqrestore(&dev->pending_lock, flags);
1534
1535 for (i = 0; i < n; i++) {
1536 qp = qps[i];
1537
1538 spin_lock_irqsave(&qp->s_lock, flags);
1539 if (qp->s_flags & QIB_S_WAIT_PIO) {
1540 qp->s_flags &= ~QIB_S_WAIT_PIO;
1541 qib_schedule_send(qp);
1542 }
1543 spin_unlock_irqrestore(&qp->s_lock, flags);
1544
1545 /* Notify qib_destroy_qp() if it is waiting. */
1546 if (atomic_dec_and_test(&qp->refcount))
1547 wake_up(&qp->wait);
1548 }
1549}
1550
1551static int qib_query_device(struct ib_device *ibdev,
1552 struct ib_device_attr *props)
1553{
1554 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1555 struct qib_ibdev *dev = to_idev(ibdev);
1556
1557 memset(props, 0, sizeof(*props));
1558
1559 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1560 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1561 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1562 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1563 props->page_size_cap = PAGE_SIZE;
1564 props->vendor_id =
1565 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1566 props->vendor_part_id = dd->deviceid;
1567 props->hw_ver = dd->minrev;
1568 props->sys_image_guid = ib_qib_sys_image_guid;
1569 props->max_mr_size = ~0ULL;
1570 props->max_qp = ib_qib_max_qps;
1571 props->max_qp_wr = ib_qib_max_qp_wrs;
1572 props->max_sge = ib_qib_max_sges;
1573 props->max_cq = ib_qib_max_cqs;
1574 props->max_ah = ib_qib_max_ahs;
1575 props->max_cqe = ib_qib_max_cqes;
1576 props->max_mr = dev->lk_table.max;
1577 props->max_fmr = dev->lk_table.max;
1578 props->max_map_per_fmr = 32767;
1579 props->max_pd = ib_qib_max_pds;
1580 props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1581 props->max_qp_init_rd_atom = 255;
1582 /* props->max_res_rd_atom */
1583 props->max_srq = ib_qib_max_srqs;
1584 props->max_srq_wr = ib_qib_max_srq_wrs;
1585 props->max_srq_sge = ib_qib_max_srq_sges;
1586 /* props->local_ca_ack_delay */
1587 props->atomic_cap = IB_ATOMIC_GLOB;
1588 props->max_pkeys = qib_get_npkeys(dd);
1589 props->max_mcast_grp = ib_qib_max_mcast_grps;
1590 props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1591 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1592 props->max_mcast_grp;
1593
1594 return 0;
1595}
1596
1597static int qib_query_port(struct ib_device *ibdev, u8 port,
1598 struct ib_port_attr *props)
1599{
1600 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1601 struct qib_ibport *ibp = to_iport(ibdev, port);
1602 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1603 enum ib_mtu mtu;
1604 u16 lid = ppd->lid;
1605
1606 memset(props, 0, sizeof(*props));
1607 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1608 props->lmc = ppd->lmc;
1609 props->sm_lid = ibp->sm_lid;
1610 props->sm_sl = ibp->sm_sl;
1611 props->state = dd->f_iblink_state(ppd->lastibcstat);
1612 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1613 props->port_cap_flags = ibp->port_cap_flags;
1614 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1615 props->max_msg_sz = 0x80000000;
1616 props->pkey_tbl_len = qib_get_npkeys(dd);
1617 props->bad_pkey_cntr = ibp->pkey_violations;
1618 props->qkey_viol_cntr = ibp->qkey_violations;
1619 props->active_width = ppd->link_width_active;
1620 /* See rate_show() */
1621 props->active_speed = ppd->link_speed_active;
1622 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1623 props->init_type_reply = 0;
1624
1625 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1626 switch (ppd->ibmtu) {
1627 case 4096:
1628 mtu = IB_MTU_4096;
1629 break;
1630 case 2048:
1631 mtu = IB_MTU_2048;
1632 break;
1633 case 1024:
1634 mtu = IB_MTU_1024;
1635 break;
1636 case 512:
1637 mtu = IB_MTU_512;
1638 break;
1639 case 256:
1640 mtu = IB_MTU_256;
1641 break;
1642 default:
1643 mtu = IB_MTU_2048;
1644 }
1645 props->active_mtu = mtu;
1646 props->subnet_timeout = ibp->subnet_timeout;
1647
1648 return 0;
1649}
1650
1651static int qib_modify_device(struct ib_device *device,
1652 int device_modify_mask,
1653 struct ib_device_modify *device_modify)
1654{
1655 struct qib_devdata *dd = dd_from_ibdev(device);
1656 unsigned i;
1657 int ret;
1658
1659 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1660 IB_DEVICE_MODIFY_NODE_DESC)) {
1661 ret = -EOPNOTSUPP;
1662 goto bail;
1663 }
1664
1665 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1666 memcpy(device->node_desc, device_modify->node_desc, 64);
1667 for (i = 0; i < dd->num_pports; i++) {
1668 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1669
1670 qib_node_desc_chg(ibp);
1671 }
1672 }
1673
1674 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1675 ib_qib_sys_image_guid =
1676 cpu_to_be64(device_modify->sys_image_guid);
1677 for (i = 0; i < dd->num_pports; i++) {
1678 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1679
1680 qib_sys_guid_chg(ibp);
1681 }
1682 }
1683
1684 ret = 0;
1685
1686bail:
1687 return ret;
1688}
1689
1690static int qib_modify_port(struct ib_device *ibdev, u8 port,
1691 int port_modify_mask, struct ib_port_modify *props)
1692{
1693 struct qib_ibport *ibp = to_iport(ibdev, port);
1694 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1695
1696 ibp->port_cap_flags |= props->set_port_cap_mask;
1697 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1698 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1699 qib_cap_mask_chg(ibp);
1700 if (port_modify_mask & IB_PORT_SHUTDOWN)
1701 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1702 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1703 ibp->qkey_violations = 0;
1704 return 0;
1705}
1706
1707static int qib_query_gid(struct ib_device *ibdev, u8 port,
1708 int index, union ib_gid *gid)
1709{
1710 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1711 int ret = 0;
1712
1713 if (!port || port > dd->num_pports)
1714 ret = -EINVAL;
1715 else {
1716 struct qib_ibport *ibp = to_iport(ibdev, port);
1717 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1718
1719 gid->global.subnet_prefix = ibp->gid_prefix;
1720 if (index == 0)
1721 gid->global.interface_id = ppd->guid;
1722 else if (index < QIB_GUIDS_PER_PORT)
1723 gid->global.interface_id = ibp->guids[index - 1];
1724 else
1725 ret = -EINVAL;
1726 }
1727
1728 return ret;
1729}
1730
1731static struct ib_pd *qib_alloc_pd(struct ib_device *ibdev,
1732 struct ib_ucontext *context,
1733 struct ib_udata *udata)
1734{
1735 struct qib_ibdev *dev = to_idev(ibdev);
1736 struct qib_pd *pd;
1737 struct ib_pd *ret;
1738
1739 /*
1740 * This is actually totally arbitrary. Some correctness tests
1741 * assume there's a maximum number of PDs that can be allocated.
1742 * We don't actually have this limit, but we fail the test if
1743 * we allow allocations of more than we report for this value.
1744 */
1745
1746 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1747 if (!pd) {
1748 ret = ERR_PTR(-ENOMEM);
1749 goto bail;
1750 }
1751
1752 spin_lock(&dev->n_pds_lock);
1753 if (dev->n_pds_allocated == ib_qib_max_pds) {
1754 spin_unlock(&dev->n_pds_lock);
1755 kfree(pd);
1756 ret = ERR_PTR(-ENOMEM);
1757 goto bail;
1758 }
1759
1760 dev->n_pds_allocated++;
1761 spin_unlock(&dev->n_pds_lock);
1762
1763 /* ib_alloc_pd() will initialize pd->ibpd. */
1764 pd->user = udata != NULL;
1765
1766 ret = &pd->ibpd;
1767
1768bail:
1769 return ret;
1770}
1771
1772static int qib_dealloc_pd(struct ib_pd *ibpd)
1773{
1774 struct qib_pd *pd = to_ipd(ibpd);
1775 struct qib_ibdev *dev = to_idev(ibpd->device);
1776
1777 spin_lock(&dev->n_pds_lock);
1778 dev->n_pds_allocated--;
1779 spin_unlock(&dev->n_pds_lock);
1780
1781 kfree(pd);
1782
1783 return 0;
1784}
1785
1786int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1787{
1788 /* A multicast address requires a GRH (see ch. 8.4.1). */
1789 if (ah_attr->dlid >= QIB_MULTICAST_LID_BASE &&
1790 ah_attr->dlid != QIB_PERMISSIVE_LID &&
1791 !(ah_attr->ah_flags & IB_AH_GRH))
1792 goto bail;
1793 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1794 ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1795 goto bail;
1796 if (ah_attr->dlid == 0)
1797 goto bail;
1798 if (ah_attr->port_num < 1 ||
1799 ah_attr->port_num > ibdev->phys_port_cnt)
1800 goto bail;
1801 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1802 ib_rate_to_mult(ah_attr->static_rate) < 0)
1803 goto bail;
1804 if (ah_attr->sl > 15)
1805 goto bail;
1806 return 0;
1807bail:
1808 return -EINVAL;
1809}
1810
1811/**
1812 * qib_create_ah - create an address handle
1813 * @pd: the protection domain
1814 * @ah_attr: the attributes of the AH
1815 *
1816 * This may be called from interrupt context.
1817 */
1818static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1819 struct ib_ah_attr *ah_attr)
1820{
1821 struct qib_ah *ah;
1822 struct ib_ah *ret;
1823 struct qib_ibdev *dev = to_idev(pd->device);
1824 unsigned long flags;
1825
1826 if (qib_check_ah(pd->device, ah_attr)) {
1827 ret = ERR_PTR(-EINVAL);
1828 goto bail;
1829 }
1830
1831 ah = kmalloc(sizeof *ah, GFP_ATOMIC);
1832 if (!ah) {
1833 ret = ERR_PTR(-ENOMEM);
1834 goto bail;
1835 }
1836
1837 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1838 if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1839 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1840 kfree(ah);
1841 ret = ERR_PTR(-ENOMEM);
1842 goto bail;
1843 }
1844
1845 dev->n_ahs_allocated++;
1846 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1847
1848 /* ib_create_ah() will initialize ah->ibah. */
1849 ah->attr = *ah_attr;
1850 atomic_set(&ah->refcount, 0);
1851
1852 ret = &ah->ibah;
1853
1854bail:
1855 return ret;
1856}
1857
1fb9fed6
MM		 1858struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1859{
1860 struct ib_ah_attr attr;
1861 struct ib_ah *ah = ERR_PTR(-EINVAL);
1862 struct qib_qp *qp0;
1863
1864 memset(&attr, 0, sizeof attr);
1865 attr.dlid = dlid;
1866 attr.port_num = ppd_from_ibp(ibp)->port;
1867 rcu_read_lock();
1868 qp0 = rcu_dereference(ibp->qp0);
1869 if (qp0)
1870 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1871 rcu_read_unlock();
1872 return ah;
1873}
1874
f931551b
RC		 1875/**
1876 * qib_destroy_ah - destroy an address handle
1877 * @ibah: the AH to destroy
1878 *
1879 * This may be called from interrupt context.
1880 */
1881static int qib_destroy_ah(struct ib_ah *ibah)
1882{
1883 struct qib_ibdev *dev = to_idev(ibah->device);
1884 struct qib_ah *ah = to_iah(ibah);
1885 unsigned long flags;
1886
1887 if (atomic_read(&ah->refcount) != 0)
1888 return -EBUSY;
1889
1890 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1891 dev->n_ahs_allocated--;
1892 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1893
1894 kfree(ah);
1895
1896 return 0;
1897}
1898
1899static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1900{
1901 struct qib_ah *ah = to_iah(ibah);
1902
1903 if (qib_check_ah(ibah->device, ah_attr))
1904 return -EINVAL;
1905
1906 ah->attr = *ah_attr;
1907
1908 return 0;
1909}
1910
1911static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1912{
1913 struct qib_ah *ah = to_iah(ibah);
1914
1915 *ah_attr = ah->attr;
1916
1917 return 0;
1918}
1919
1920/**
1921 * qib_get_npkeys - return the size of the PKEY table for context 0
1922 * @dd: the qlogic_ib device
1923 */
1924unsigned qib_get_npkeys(struct qib_devdata *dd)
1925{
1926 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1927}
1928
1929/*
1930 * Return the indexed PKEY from the port PKEY table.
1931 * No need to validate rcd[ctxt]; the port is setup if we are here.
1932 */
1933unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1934{
1935 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1936 struct qib_devdata *dd = ppd->dd;
1937 unsigned ctxt = ppd->hw_pidx;
1938 unsigned ret;
1939
1940 /* dd->rcd null if mini_init or some init failures */
1941 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1942 ret = 0;
1943 else
1944 ret = dd->rcd[ctxt]->pkeys[index];
1945
1946 return ret;
1947}
1948
1949static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1950 u16 *pkey)
1951{
1952 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1953 int ret;
1954
1955 if (index >= qib_get_npkeys(dd)) {
1956 ret = -EINVAL;
1957 goto bail;
1958 }
1959
1960 *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1961 ret = 0;
1962
1963bail:
1964 return ret;
1965}
1966
1967/**
1968 * qib_alloc_ucontext - allocate a ucontest
1969 * @ibdev: the infiniband device
1970 * @udata: not used by the QLogic_IB driver
1971 */
1972
1973static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
1974 struct ib_udata *udata)
1975{
1976 struct qib_ucontext *context;
1977 struct ib_ucontext *ret;
1978
1979 context = kmalloc(sizeof *context, GFP_KERNEL);
1980 if (!context) {
1981 ret = ERR_PTR(-ENOMEM);
1982 goto bail;
1983 }
1984
1985 ret = &context->ibucontext;
1986
1987bail:
1988 return ret;
1989}
1990
1991static int qib_dealloc_ucontext(struct ib_ucontext *context)
1992{
1993 kfree(to_iucontext(context));
1994 return 0;
1995}
1996
1997static void init_ibport(struct qib_pportdata *ppd)
1998{
1999 struct qib_verbs_counters cntrs;
2000 struct qib_ibport *ibp = &ppd->ibport_data;
2001
2002 spin_lock_init(&ibp->lock);
2003 /* Set the prefix to the default value (see ch. 4.1.1) */
2004 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
2005 ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
2006 ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
2007 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
2008 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
2009 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
2010 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
2011 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
2012 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
2013 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
2014 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
2015 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
2016 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
2017 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
2018
2019 /* Snapshot current HW counters to "clear" them. */
2020 qib_get_counters(ppd, &cntrs);
2021 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
2022 ibp->z_link_error_recovery_counter =
2023 cntrs.link_error_recovery_counter;
2024 ibp->z_link_downed_counter = cntrs.link_downed_counter;
2025 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
2026 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
2027 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
2028 ibp->z_port_xmit_data = cntrs.port_xmit_data;
2029 ibp->z_port_rcv_data = cntrs.port_rcv_data;
2030 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
2031 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
2032 ibp->z_local_link_integrity_errors =
2033 cntrs.local_link_integrity_errors;
2034 ibp->z_excessive_buffer_overrun_errors =
2035 cntrs.excessive_buffer_overrun_errors;
2036 ibp->z_vl15_dropped = cntrs.vl15_dropped;
af061a64
MM		 2037 RCU_INIT_POINTER(ibp->qp0, NULL);
2038 RCU_INIT_POINTER(ibp->qp1, NULL);
f931551b
RC		 2039}
2040
2041/**
2042 * qib_register_ib_device - register our device with the infiniband core
2043 * @dd: the device data structure
2044 * Return the allocated qib_ibdev pointer or NULL on error.
2045 */
2046int qib_register_ib_device(struct qib_devdata *dd)
2047{
2048 struct qib_ibdev *dev = &dd->verbs_dev;
2049 struct ib_device *ibdev = &dev->ibdev;
2050 struct qib_pportdata *ppd = dd->pport;
2051 unsigned i, lk_tab_size;
2052 int ret;
2053
2054 dev->qp_table_size = ib_qib_qp_table_size;
af061a64
MM		 2055 get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
2056 dev->qp_table = kmalloc(dev->qp_table_size * sizeof *dev->qp_table,
f931551b
RC		 2057 GFP_KERNEL);
2058 if (!dev->qp_table) {
2059 ret = -ENOMEM;
2060 goto err_qpt;
2061 }
af061a64
MM		 2062 for (i = 0; i < dev->qp_table_size; i++)
2063 RCU_INIT_POINTER(dev->qp_table[i], NULL);
f931551b
RC		 2064
2065 for (i = 0; i < dd->num_pports; i++)
2066 init_ibport(ppd + i);
2067
2068 /* Only need to initialize non-zero fields. */
2069 spin_lock_init(&dev->qpt_lock);
2070 spin_lock_init(&dev->n_pds_lock);
2071 spin_lock_init(&dev->n_ahs_lock);
2072 spin_lock_init(&dev->n_cqs_lock);
2073 spin_lock_init(&dev->n_qps_lock);
2074 spin_lock_init(&dev->n_srqs_lock);
2075 spin_lock_init(&dev->n_mcast_grps_lock);
2076 init_timer(&dev->mem_timer);
2077 dev->mem_timer.function = mem_timer;
2078 dev->mem_timer.data = (unsigned long) dev;
2079
2080 qib_init_qpn_table(dd, &dev->qpn_table);
2081
2082 /*
2083 * The top ib_qib_lkey_table_size bits are used to index the
2084 * table. The lower 8 bits can be owned by the user (copied from
2085 * the LKEY). The remaining bits act as a generation number or tag.
2086 */
2087 spin_lock_init(&dev->lk_table.lock);
ef5844a0
MM		 2088 /* insure generation is at least 4 bits see keys.c */
2089 if (ib_qib_lkey_table_size > MAX_LKEY_TABLE_BITS) {
2090 qib_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
2091 ib_qib_lkey_table_size, MAX_LKEY_TABLE_BITS);
2092 ib_qib_lkey_table_size = MAX_LKEY_TABLE_BITS;
2093 }
f931551b
RC		 2094 dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2095 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1fb9fed6 2096 dev->lk_table.table = (struct qib_mregion __rcu **)
ef5844a0 2097 vmalloc(lk_tab_size);
f931551b
RC		 2098 if (dev->lk_table.table == NULL) {
2099 ret = -ENOMEM;
2100 goto err_lk;
2101 }
8aac4cc3
MM		 2102 RCU_INIT_POINTER(dev->dma_mr, NULL);
2103 for (i = 0; i < dev->lk_table.max; i++)
2104 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
f931551b
RC		 2105 INIT_LIST_HEAD(&dev->pending_mmaps);
2106 spin_lock_init(&dev->pending_lock);
2107 dev->mmap_offset = PAGE_SIZE;
2108 spin_lock_init(&dev->mmap_offset_lock);
2109 INIT_LIST_HEAD(&dev->piowait);
2110 INIT_LIST_HEAD(&dev->dmawait);
2111 INIT_LIST_HEAD(&dev->txwait);
2112 INIT_LIST_HEAD(&dev->memwait);
2113 INIT_LIST_HEAD(&dev->txreq_free);
2114
2115 if (ppd->sdma_descq_cnt) {
2116 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2117 ppd->sdma_descq_cnt *
2118 sizeof(struct qib_pio_header),
2119 &dev->pio_hdrs_phys,
2120 GFP_KERNEL);
2121 if (!dev->pio_hdrs) {
2122 ret = -ENOMEM;
2123 goto err_hdrs;
2124 }
2125 }
2126
2127 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2128 struct qib_verbs_txreq *tx;
2129
2130 tx = kzalloc(sizeof *tx, GFP_KERNEL);
2131 if (!tx) {
2132 ret = -ENOMEM;
2133 goto err_tx;
2134 }
2135 tx->hdr_inx = i;
2136 list_add(&tx->txreq.list, &dev->txreq_free);
2137 }
2138
2139 /*
2140 * The system image GUID is supposed to be the same for all
2141 * IB HCAs in a single system but since there can be other
2142 * device types in the system, we can't be sure this is unique.
2143 */
2144 if (!ib_qib_sys_image_guid)
2145 ib_qib_sys_image_guid = ppd->guid;
2146
2147 strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2148 ibdev->owner = THIS_MODULE;
2149 ibdev->node_guid = ppd->guid;
2150 ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2151 ibdev->uverbs_cmd_mask =
2152 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2153 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2154 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2155 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2156 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2157 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2158 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
2159 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
2160 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2161 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2162 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2163 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2164 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2165 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2166 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2167 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2168 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2169 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2170 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2171 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2172 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2173 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2174 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2175 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2176 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2177 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2178 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2179 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2180 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2181 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2182 ibdev->node_type = RDMA_NODE_IB_CA;
2183 ibdev->phys_port_cnt = dd->num_pports;
2184 ibdev->num_comp_vectors = 1;
2185 ibdev->dma_device = &dd->pcidev->dev;
2186 ibdev->query_device = qib_query_device;
2187 ibdev->modify_device = qib_modify_device;
2188 ibdev->query_port = qib_query_port;
2189 ibdev->modify_port = qib_modify_port;
2190 ibdev->query_pkey = qib_query_pkey;
2191 ibdev->query_gid = qib_query_gid;
2192 ibdev->alloc_ucontext = qib_alloc_ucontext;
2193 ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2194 ibdev->alloc_pd = qib_alloc_pd;
2195 ibdev->dealloc_pd = qib_dealloc_pd;
2196 ibdev->create_ah = qib_create_ah;
2197 ibdev->destroy_ah = qib_destroy_ah;
2198 ibdev->modify_ah = qib_modify_ah;
2199 ibdev->query_ah = qib_query_ah;
2200 ibdev->create_srq = qib_create_srq;
2201 ibdev->modify_srq = qib_modify_srq;
2202 ibdev->query_srq = qib_query_srq;
2203 ibdev->destroy_srq = qib_destroy_srq;
2204 ibdev->create_qp = qib_create_qp;
2205 ibdev->modify_qp = qib_modify_qp;
2206 ibdev->query_qp = qib_query_qp;
2207 ibdev->destroy_qp = qib_destroy_qp;
2208 ibdev->post_send = qib_post_send;
2209 ibdev->post_recv = qib_post_receive;
2210 ibdev->post_srq_recv = qib_post_srq_receive;
2211 ibdev->create_cq = qib_create_cq;
2212 ibdev->destroy_cq = qib_destroy_cq;
2213 ibdev->resize_cq = qib_resize_cq;
2214 ibdev->poll_cq = qib_poll_cq;
2215 ibdev->req_notify_cq = qib_req_notify_cq;
2216 ibdev->get_dma_mr = qib_get_dma_mr;
2217 ibdev->reg_phys_mr = qib_reg_phys_mr;
2218 ibdev->reg_user_mr = qib_reg_user_mr;
2219 ibdev->dereg_mr = qib_dereg_mr;
2220 ibdev->alloc_fast_reg_mr = qib_alloc_fast_reg_mr;
2221 ibdev->alloc_fast_reg_page_list = qib_alloc_fast_reg_page_list;
2222 ibdev->free_fast_reg_page_list = qib_free_fast_reg_page_list;
2223 ibdev->alloc_fmr = qib_alloc_fmr;
2224 ibdev->map_phys_fmr = qib_map_phys_fmr;
2225 ibdev->unmap_fmr = qib_unmap_fmr;
2226 ibdev->dealloc_fmr = qib_dealloc_fmr;
2227 ibdev->attach_mcast = qib_multicast_attach;
2228 ibdev->detach_mcast = qib_multicast_detach;
2229 ibdev->process_mad = qib_process_mad;
2230 ibdev->mmap = qib_mmap;
2231 ibdev->dma_ops = &qib_dma_mapping_ops;
2232
2233 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
e2eed58b 2234 "Intel Infiniband HCA %s", init_utsname()->nodename);
f931551b
RC		 2235
2236 ret = ib_register_device(ibdev, qib_create_port_files);
2237 if (ret)
2238 goto err_reg;
2239
2240 ret = qib_create_agents(dev);
2241 if (ret)
2242 goto err_agents;
2243
c9bdad3c
MM		 2244 ret = qib_verbs_register_sysfs(dd);
2245 if (ret)
f931551b
RC		 2246 goto err_class;
2247
2248 goto bail;
2249
2250err_class:
2251 qib_free_agents(dev);
2252err_agents:
2253 ib_unregister_device(ibdev);
2254err_reg:
2255err_tx:
2256 while (!list_empty(&dev->txreq_free)) {
2257 struct list_head *l = dev->txreq_free.next;
2258 struct qib_verbs_txreq *tx;
2259
2260 list_del(l);
2261 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2262 kfree(tx);
2263 }
2264 if (ppd->sdma_descq_cnt)
2265 dma_free_coherent(&dd->pcidev->dev,
2266 ppd->sdma_descq_cnt *
2267 sizeof(struct qib_pio_header),
2268 dev->pio_hdrs, dev->pio_hdrs_phys);
2269err_hdrs:
ef5844a0 2270 vfree(dev->lk_table.table);
f931551b
RC		 2271err_lk:
2272 kfree(dev->qp_table);
2273err_qpt:
2274 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2275bail:
2276 return ret;
2277}
2278
2279void qib_unregister_ib_device(struct qib_devdata *dd)
2280{
2281 struct qib_ibdev *dev = &dd->verbs_dev;
2282 struct ib_device *ibdev = &dev->ibdev;
2283 u32 qps_inuse;
2284 unsigned lk_tab_size;
2285
2286 qib_verbs_unregister_sysfs(dd);
2287
2288 qib_free_agents(dev);
2289
2290 ib_unregister_device(ibdev);
2291
2292 if (!list_empty(&dev->piowait))
2293 qib_dev_err(dd, "piowait list not empty!\n");
2294 if (!list_empty(&dev->dmawait))
2295 qib_dev_err(dd, "dmawait list not empty!\n");
2296 if (!list_empty(&dev->txwait))
2297 qib_dev_err(dd, "txwait list not empty!\n");
2298 if (!list_empty(&dev->memwait))
2299 qib_dev_err(dd, "memwait list not empty!\n");
2300 if (dev->dma_mr)
2301 qib_dev_err(dd, "DMA MR not NULL!\n");
2302
2303 qps_inuse = qib_free_all_qps(dd);
2304 if (qps_inuse)
2305 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2306 qps_inuse);
2307
2308 del_timer_sync(&dev->mem_timer);
2309 qib_free_qpn_table(&dev->qpn_table);
2310 while (!list_empty(&dev->txreq_free)) {
2311 struct list_head *l = dev->txreq_free.next;
2312 struct qib_verbs_txreq *tx;
2313
2314 list_del(l);
2315 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2316 kfree(tx);
2317 }
2318 if (dd->pport->sdma_descq_cnt)
2319 dma_free_coherent(&dd->pcidev->dev,
2320 dd->pport->sdma_descq_cnt *
2321 sizeof(struct qib_pio_header),
2322 dev->pio_hdrs, dev->pio_hdrs_phys);
2323 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
ef5844a0 2324 vfree(dev->lk_table.table);
f931551b
RC		 2325 kfree(dev->qp_table);
2326}
551ace12
MM		 2327
2328/*
2329 * This must be called with s_lock held.
2330 */
2331void qib_schedule_send(struct qib_qp *qp)
2332{
2333 if (qib_send_ok(qp)) {
2334 struct qib_ibport *ibp =
2335 to_iport(qp->ibqp.device, qp->port_num);
2336 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
2337
2338 queue_work(ppd->qib_wq, &qp->s_work);
2339 }
2340}
kernel source for telekom puls (alcatel/mediatek)