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Merge branches 'pxa-ian' and 'pxa-xm270' into pxa
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / ipath / ipath_kernel.h
CommitLineData
d41d3aeb
BS		 1#ifndef _IPATH_KERNEL_H
2#define _IPATH_KERNEL_H
3/*
e7eacd36 4 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
d41d3aeb
BS		 5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36/*
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
39 */
40
41#include <linux/interrupt.h>
1fd3b40f
BS		 42#include <linux/pci.h>
43#include <linux/dma-mapping.h>
2c45688f 44#include <linux/mutex.h>
afce688b
RC		 45#include <linux/list.h>
46#include <linux/scatterlist.h>
d41d3aeb 47#include <asm/io.h>
49739b3e 48#include <rdma/ib_verbs.h>
d41d3aeb
BS		 49
50#include "ipath_common.h"
51#include "ipath_debug.h"
52#include "ipath_registers.h"
53
54/* only s/w major version of InfiniPath we can handle */
55#define IPATH_CHIP_VERS_MAJ 2U
56
57/* don't care about this except printing */
58#define IPATH_CHIP_VERS_MIN 0U
59
60/* temporary, maybe always */
61extern struct infinipath_stats ipath_stats;
62
63#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
aecd3b5a
MA		 64/*
65 * First-cut critierion for "device is active" is
66 * two thousand dwords combined Tx, Rx traffic per
67 * 5-second interval. SMA packets are 64 dwords,
68 * and occur "a few per second", presumably each way.
69 */
70#define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000)
71/*
72 * Struct used to indicate which errors are logged in each of the
73 * error-counters that are logged to EEPROM. A counter is incremented
74 * _once_ (saturating at 255) for each event with any bits set in
75 * the error or hwerror register masks below.
76 */
77#define IPATH_EEP_LOG_CNT (4)
78struct ipath_eep_log_mask {
79 u64 errs_to_log;
80 u64 hwerrs_to_log;
81};
d41d3aeb
BS		 82
83struct ipath_portdata {
84 void **port_rcvegrbuf;
85 dma_addr_t *port_rcvegrbuf_phys;
86 /* rcvhdrq base, needs mmap before useful */
87 void *port_rcvhdrq;
88 /* kernel virtual address where hdrqtail is updated */
1fd3b40f 89 void *port_rcvhdrtail_kvaddr;
d41d3aeb
BS		 90 /*
91 * temp buffer for expected send setup, allocated at open, instead
92 * of each setup call
93 */
94 void *port_tid_pg_list;
95 /* when waiting for rcv or pioavail */
96 wait_queue_head_t port_wait;
97 /*
98 * rcvegr bufs base, physical, must fit
99 * in 44 bits so 32 bit programs mmap64 44 bit works)
100 */
101 dma_addr_t port_rcvegr_phys;
102 /* mmap of hdrq, must fit in 44 bits */
103 dma_addr_t port_rcvhdrq_phys;
f37bda92 104 dma_addr_t port_rcvhdrqtailaddr_phys;
d41d3aeb 105 /*
9929b0fb
BS		 106 * number of opens (including slave subports) on this instance
107 * (ignoring forks, dup, etc. for now)
d41d3aeb
BS		 108 */
109 int port_cnt;
110 /*
111 * how much space to leave at start of eager TID entries for
112 * protocol use, on each TID
113 */
114 /* instead of calculating it */
115 unsigned port_port;
9929b0fb
BS		 116 /* non-zero if port is being shared. */
117 u16 port_subport_cnt;
118 /* non-zero if port is being shared. */
119 u16 port_subport_id;
e2ab41ca
DO		 120 /* number of pio bufs for this port (all procs, if shared) */
121 u32 port_piocnt;
122 /* first pio buffer for this port */
123 u32 port_pio_base;
d41d3aeb
BS		 124 /* chip offset of PIO buffers for this port */
125 u32 port_piobufs;
126 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
127 u32 port_rcvegrbuf_chunks;
128 /* how many egrbufs per chunk */
129 u32 port_rcvegrbufs_perchunk;
130 /* order for port_rcvegrbuf_pages */
131 size_t port_rcvegrbuf_size;
132 /* rcvhdrq size (for freeing) */
133 size_t port_rcvhdrq_size;
134 /* next expected TID to check when looking for free */
135 u32 port_tidcursor;
136 /* next expected TID to check */
137 unsigned long port_flag;
f2d04231
RW		 138 /* what happened */
139 unsigned long int_flag;
d41d3aeb
BS		 140 /* WAIT_RCV that timed out, no interrupt */
141 u32 port_rcvwait_to;
142 /* WAIT_PIO that timed out, no interrupt */
143 u32 port_piowait_to;
144 /* WAIT_RCV already happened, no wait */
145 u32 port_rcvnowait;
146 /* WAIT_PIO already happened, no wait */
147 u32 port_pionowait;
148 /* total number of rcvhdrqfull errors */
149 u32 port_hdrqfull;
755807a2
DO		 150 /*
151 * Used to suppress multiple instances of same
152 * port staying stuck at same point.
153 */
154 u32 port_lastrcvhdrqtail;
70c51da2
AJ		 155 /* saved total number of rcvhdrqfull errors for poll edge trigger */
156 u32 port_hdrqfull_poll;
157 /* total number of polled urgent packets */
158 u32 port_urgent;
159 /* saved total number of polled urgent packets for poll edge trigger */
160 u32 port_urgent_poll;
d41d3aeb 161 /* pid of process using this port */
40d97692
PE		 162 struct pid *port_pid;
163 struct pid *port_subpid[INFINIPATH_MAX_SUBPORT];
d41d3aeb
BS		 164 /* same size as task_struct .comm[] */
165 char port_comm[16];
166 /* pkeys set by this use of this port */
167 u16 port_pkeys[4];
168 /* so file ops can get at unit */
169 struct ipath_devdata *port_dd;
9929b0fb
BS		 170 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
171 void *subport_uregbase;
172 /* An array of pages for the eager receive buffers * N */
173 void *subport_rcvegrbuf;
174 /* An array of pages for the eager header queue entries * N */
175 void *subport_rcvhdr_base;
176 /* The version of the library which opened this port */
177 u32 userversion;
178 /* Bitmask of active slaves */
179 u32 active_slaves;
f2d04231
RW		 180 /* Type of packets or conditions we want to poll for */
181 u16 poll_type;
c59a80ac
RC		 182 /* port rcvhdrq head offset */
183 u32 port_head;
9355fb6a
RC		 184 /* receive packet sequence counter */
185 u32 port_seq_cnt;
d41d3aeb
BS		 186};
187
188struct sk_buff;
afce688b
RC		 189struct ipath_sge_state;
190struct ipath_verbs_txreq;
d41d3aeb
BS		 191
192/*
193 * control information for layered drivers
194 */
195struct _ipath_layer {
196 void *l_arg;
197};
198
1fd3b40f
BS		 199struct ipath_skbinfo {
200 struct sk_buff *skb;
201 dma_addr_t phys;
202};
203
afce688b
RC		 204struct ipath_sdma_txreq {
205 int flags;
206 int sg_count;
207 union {
208 struct scatterlist *sg;
209 void *map_addr;
210 };
211 void (*callback)(void *, int);
212 void *callback_cookie;
213 int callback_status;
214 u16 start_idx; /* sdma private */
215 u16 next_descq_idx; /* sdma private */
216 struct list_head list; /* sdma private */
217};
218
219struct ipath_sdma_desc {
220 __le64 qw[2];
221};
222
223#define IPATH_SDMA_TXREQ_F_USELARGEBUF 0x1
224#define IPATH_SDMA_TXREQ_F_HEADTOHOST 0x2
225#define IPATH_SDMA_TXREQ_F_INTREQ 0x4
226#define IPATH_SDMA_TXREQ_F_FREEBUF 0x8
227#define IPATH_SDMA_TXREQ_F_FREEDESC 0x10
228#define IPATH_SDMA_TXREQ_F_VL15 0x20
229
230#define IPATH_SDMA_TXREQ_S_OK 0
231#define IPATH_SDMA_TXREQ_S_SENDERROR 1
232#define IPATH_SDMA_TXREQ_S_ABORTED 2
233#define IPATH_SDMA_TXREQ_S_SHUTDOWN 3
234
e8ffef73
RD		 235#define IPATH_SDMA_STATUS_SCORE_BOARD_DRAIN_IN_PROG (1ull << 63)
236#define IPATH_SDMA_STATUS_ABORT_IN_PROG (1ull << 62)
237#define IPATH_SDMA_STATUS_INTERNAL_SDMA_ENABLE (1ull << 61)
238#define IPATH_SDMA_STATUS_SCB_EMPTY (1ull << 30)
239
c4b4d16e
RC		 240/* max dwords in small buffer packet */
241#define IPATH_SMALLBUF_DWORDS (dd->ipath_piosize2k >> 2)
242
c4bce803
DO		 243/*
244 * Possible IB config parameters for ipath_f_get/set_ib_cfg()
245 */
246#define IPATH_IB_CFG_LIDLMC 0 /* Get/set LID (LS16b) and Mask (MS16b) */
247#define IPATH_IB_CFG_HRTBT 1 /* Get/set Heartbeat off/enable/auto */
248#define IPATH_IB_HRTBT_ON 3 /* Heartbeat enabled, sent every 100msec */
249#define IPATH_IB_HRTBT_OFF 0 /* Heartbeat off */
250#define IPATH_IB_CFG_LWID_ENB 2 /* Get/set allowed Link-width */
251#define IPATH_IB_CFG_LWID 3 /* Get currently active Link-width */
252#define IPATH_IB_CFG_SPD_ENB 4 /* Get/set allowed Link speeds */
253#define IPATH_IB_CFG_SPD 5 /* Get current Link spd */
254#define IPATH_IB_CFG_RXPOL_ENB 6 /* Get/set Auto-RX-polarity enable */
255#define IPATH_IB_CFG_LREV_ENB 7 /* Get/set Auto-Lane-reversal enable */
256#define IPATH_IB_CFG_LINKLATENCY 8 /* Get Auto-Lane-reversal enable */
257
258
d41d3aeb
BS		 259struct ipath_devdata {
260 struct list_head ipath_list;
261
262 struct ipath_kregs const *ipath_kregs;
263 struct ipath_cregs const *ipath_cregs;
264
265 /* mem-mapped pointer to base of chip regs */
266 u64 __iomem *ipath_kregbase;
267 /* end of mem-mapped chip space; range checking */
268 u64 __iomem *ipath_kregend;
269 /* physical address of chip for io_remap, etc. */
270 unsigned long ipath_physaddr;
271 /* base of memory alloced for ipath_kregbase, for free */
272 u64 *ipath_kregalloc;
d41d3aeb
BS		 273 /* ipath_cfgports pointers */
274 struct ipath_portdata **ipath_pd;
275 /* sk_buffs used by port 0 eager receive queue */
1fd3b40f 276 struct ipath_skbinfo *ipath_port0_skbinfo;
d41d3aeb
BS		 277 /* kvirt address of 1st 2k pio buffer */
278 void __iomem *ipath_pio2kbase;
279 /* kvirt address of 1st 4k pio buffer */
280 void __iomem *ipath_pio4kbase;
281 /*
282 * points to area where PIOavail registers will be DMA'ed.
283 * Has to be on a page of it's own, because the page will be
284 * mapped into user program space. This copy is *ONLY* ever
285 * written by DMA, not by the driver! Need a copy per device
286 * when we get to multiple devices
287 */
288 volatile __le64 *ipath_pioavailregs_dma;
289 /* physical address where updates occur */
290 dma_addr_t ipath_pioavailregs_phys;
291 struct _ipath_layer ipath_layer;
292 /* setup intr */
293 int (*ipath_f_intrsetup)(struct ipath_devdata *);
c4bce803
DO		 294 /* fallback to alternate interrupt type if possible */
295 int (*ipath_f_intr_fallback)(struct ipath_devdata *);
d41d3aeb
BS		 296 /* setup on-chip bus config */
297 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
298 /* hard reset chip */
299 int (*ipath_f_reset)(struct ipath_devdata *);
300 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
301 size_t);
302 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
303 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
304 size_t);
305 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
306 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
307 int (*ipath_f_early_init)(struct ipath_devdata *);
308 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
309 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
310 u32, unsigned long);
311 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
312 void (*ipath_f_cleanup)(struct ipath_devdata *);
313 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
314 /* fill out chip-specific fields */
315 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
51f65ebc
BS		 316 /* free irq */
317 void (*ipath_f_free_irq)(struct ipath_devdata *);
c4bce803
DO		 318 struct ipath_message_header *(*ipath_f_get_msgheader)
319 (struct ipath_devdata *, __le32 *);
60948a41 320 void (*ipath_f_config_ports)(struct ipath_devdata *, ushort);
c4bce803
DO		 321 int (*ipath_f_get_ib_cfg)(struct ipath_devdata *, int);
322 int (*ipath_f_set_ib_cfg)(struct ipath_devdata *, int, u32);
323 void (*ipath_f_config_jint)(struct ipath_devdata *, u16 , u16);
3029fcc3 324 void (*ipath_f_read_counters)(struct ipath_devdata *,
c4bce803
DO		 325 struct infinipath_counters *);
326 void (*ipath_f_xgxs_reset)(struct ipath_devdata *);
327 /* per chip actions needed for IB Link up/down changes */
328 int (*ipath_f_ib_updown)(struct ipath_devdata *, int, u64);
329
9355fb6a 330 unsigned ipath_lastegr_idx;
b1c1b6a3
BS		 331 struct ipath_ibdev *verbs_dev;
332 struct timer_list verbs_timer;
d41d3aeb
BS		 333 /* total dwords sent (summed from counter) */
334 u64 ipath_sword;
335 /* total dwords rcvd (summed from counter) */
336 u64 ipath_rword;
337 /* total packets sent (summed from counter) */
338 u64 ipath_spkts;
339 /* total packets rcvd (summed from counter) */
340 u64 ipath_rpkts;
341 /* ipath_statusp initially points to this. */
342 u64 _ipath_status;
343 /* GUID for this interface, in network order */
344 __be64 ipath_guid;
345 /*
346 * aggregrate of error bits reported since last cleared, for
347 * limiting of error reporting
348 */
349 ipath_err_t ipath_lasterror;
350 /*
351 * aggregrate of error bits reported since last cleared, for
352 * limiting of hwerror reporting
353 */
354 ipath_err_t ipath_lasthwerror;
78d1e02f 355 /* errors masked because they occur too fast */
d41d3aeb 356 ipath_err_t ipath_maskederrs;
72708a0a 357 u64 ipath_lastlinkrecov; /* link recoveries at last ACTIVE */
d41d3aeb
BS		 358 /* time in jiffies at which to re-enable maskederrs */
359 unsigned long ipath_unmasktime;
d41d3aeb
BS		 360 /* count of egrfull errors, combined for all ports */
361 u64 ipath_last_tidfull;
362 /* for ipath_qcheck() */
363 u64 ipath_lastport0rcv_cnt;
364 /* template for writing TIDs */
365 u64 ipath_tidtemplate;
366 /* value to write to free TIDs */
367 u64 ipath_tidinvalid;
525d0ca1 368 /* IBA6120 rcv interrupt setup */
d41d3aeb
BS		 369 u64 ipath_rhdrhead_intr_off;
370
371 /* size of memory at ipath_kregbase */
372 u32 ipath_kregsize;
373 /* number of registers used for pioavail */
374 u32 ipath_pioavregs;
375 /* IPATH_POLL, etc. */
376 u32 ipath_flags;
0fd41363
BS		 377 /* ipath_flags driver is waiting for */
378 u32 ipath_state_wanted;
d41d3aeb
BS		 379 /* last buffer for user use, first buf for kernel use is this
380 * index. */
381 u32 ipath_lastport_piobuf;
382 /* is a stats timer active */
383 u32 ipath_stats_timer_active;
3588423f
AJ		 384 /* number of interrupts for this device -- saturates... */
385 u32 ipath_int_counter;
d41d3aeb
BS		 386 /* dwords sent read from counter */
387 u32 ipath_lastsword;
388 /* dwords received read from counter */
389 u32 ipath_lastrword;
390 /* sent packets read from counter */
391 u32 ipath_lastspkts;
392 /* received packets read from counter */
393 u32 ipath_lastrpkts;
394 /* pio bufs allocated per port */
395 u32 ipath_pbufsport;
e2ab41ca
DO		 396 /* if remainder on bufs/port, ports < extrabuf get 1 extra */
397 u32 ipath_ports_extrabuf;
1d7c2e52 398 u32 ipath_pioupd_thresh; /* update threshold, some chips */
d41d3aeb
BS		 399 /*
400 * number of ports configured as max; zero is set to number chip
401 * supports, less gives more pio bufs/port, etc.
402 */
403 u32 ipath_cfgports;
d41d3aeb
BS		 404 /* count of port 0 hdrqfull errors */
405 u32 ipath_p0_hdrqfull;
60948a41
RC		 406 /* port 0 number of receive eager buffers */
407 u32 ipath_p0_rcvegrcnt;
d41d3aeb 408
d41d3aeb
BS		 409 /*
410 * index of last piobuffer we used. Speeds up searching, by
411 * starting at this point. Doesn't matter if multiple cpu's use and
412 * update, last updater is only write that matters. Whenever it
413 * wraps, we update shadow copies. Need a copy per device when we
414 * get to multiple devices
415 */
416 u32 ipath_lastpioindex;
c4b4d16e 417 u32 ipath_lastpioindexl;
d41d3aeb
BS		 418 /* max length of freezemsg */
419 u32 ipath_freezelen;
420 /*
421 * consecutive times we wanted a PIO buffer but were unable to
422 * get one
423 */
424 u32 ipath_consec_nopiobuf;
425 /*
426 * hint that we should update ipath_pioavailshadow before
427 * looking for a PIO buffer
428 */
429 u32 ipath_upd_pio_shadow;
430 /* so we can rewrite it after a chip reset */
431 u32 ipath_pcibar0;
432 /* so we can rewrite it after a chip reset */
433 u32 ipath_pcibar1;
afce688b
RC		 434 u32 ipath_x1_fix_tries;
435 u32 ipath_autoneg_tries;
436 u32 serdes_first_init_done;
437
438 struct ipath_relock {
439 atomic_t ipath_relock_timer_active;
440 struct timer_list ipath_relock_timer;
441 unsigned int ipath_relock_interval; /* in jiffies */
442 } ipath_relock_singleton;
d41d3aeb 443
51f65ebc
BS		 444 /* interrupt number */
445 int ipath_irq;
d41d3aeb
BS		 446 /* HT/PCI Vendor ID (here for NodeInfo) */
447 u16 ipath_vendorid;
448 /* HT/PCI Device ID (here for NodeInfo) */
449 u16 ipath_deviceid;
450 /* offset in HT config space of slave/primary interface block */
451 u8 ipath_ht_slave_off;
452 /* for write combining settings */
453 unsigned long ipath_wc_cookie;
957670a5
BS		 454 unsigned long ipath_wc_base;
455 unsigned long ipath_wc_len;
d41d3aeb
BS		 456 /* ref count for each pkey */
457 atomic_t ipath_pkeyrefs[4];
d41d3aeb
BS		 458 /* shadow copy of struct page *'s for exp tid pages */
459 struct page **ipath_pageshadow;
1fd3b40f
BS		 460 /* shadow copy of dma handles for exp tid pages */
461 dma_addr_t *ipath_physshadow;
c4bce803 462 u64 __iomem *ipath_egrtidbase;
ddb70c83
DO		 463 /* lock to workaround chip bug 9437 and others */
464 spinlock_t ipath_kernel_tid_lock;
6bb68835 465 spinlock_t ipath_user_tid_lock;
e342c119 466 spinlock_t ipath_sendctrl_lock;
d41d3aeb
BS		 467
468 /*
469 * IPATH_STATUS_*,
470 * this address is mapped readonly into user processes so they can
471 * get status cheaply, whenever they want.
472 */
473 u64 *ipath_statusp;
474 /* freeze msg if hw error put chip in freeze */
475 char *ipath_freezemsg;
476 /* pci access data structure */
477 struct pci_dev *pcidev;
a2acb2ff
BS		 478 struct cdev *user_cdev;
479 struct cdev *diag_cdev;
f4e91eb4
TJ		 480 struct device *user_dev;
481 struct device *diag_dev;
d41d3aeb
BS		 482 /* timer used to prevent stats overflow, error throttling, etc. */
483 struct timer_list ipath_stats_timer;
9b436eb4
DO		 484 /* timer to verify interrupts work, and fallback if possible */
485 struct timer_list ipath_intrchk_timer;
35783ec0
BS		 486 void *ipath_dummy_hdrq; /* used after port close */
487 dma_addr_t ipath_dummy_hdrq_phys;
d41d3aeb 488
afce688b
RC		 489 /* SendDMA related entries */
490 spinlock_t ipath_sdma_lock;
f018c7e1 491 unsigned long ipath_sdma_status;
afce688b
RC		 492 unsigned long ipath_sdma_abort_jiffies;
493 unsigned long ipath_sdma_abort_intr_timeout;
494 unsigned long ipath_sdma_buf_jiffies;
495 struct ipath_sdma_desc *ipath_sdma_descq;
496 u64 ipath_sdma_descq_added;
497 u64 ipath_sdma_descq_removed;
498 int ipath_sdma_desc_nreserved;
499 u16 ipath_sdma_descq_cnt;
500 u16 ipath_sdma_descq_tail;
501 u16 ipath_sdma_descq_head;
502 u16 ipath_sdma_next_intr;
503 u16 ipath_sdma_reset_wait;
504 u8 ipath_sdma_generation;
505 struct tasklet_struct ipath_sdma_abort_task;
506 struct tasklet_struct ipath_sdma_notify_task;
507 struct list_head ipath_sdma_activelist;
508 struct list_head ipath_sdma_notifylist;
509 atomic_t ipath_sdma_vl15_count;
510 struct timer_list ipath_sdma_vl15_timer;
511
512 dma_addr_t ipath_sdma_descq_phys;
513 volatile __le64 *ipath_sdma_head_dma;
514 dma_addr_t ipath_sdma_head_phys;
515
a18e26ae
RC		 516 unsigned long ipath_ureg_align; /* user register alignment */
517
afce688b
RC		 518 struct delayed_work ipath_autoneg_work;
519 wait_queue_head_t ipath_autoneg_wait;
520
58411d1c
JG		 521 /* HoL blocking / user app forward-progress state */
522 unsigned ipath_hol_state;
523 unsigned ipath_hol_next;
524 struct timer_list ipath_hol_timer;
525
d41d3aeb
BS		 526 /*
527 * Shadow copies of registers; size indicates read access size.
528 * Most of them are readonly, but some are write-only register,
529 * where we manipulate the bits in the shadow copy, and then write
530 * the shadow copy to infinipath.
531 *
532 * We deliberately make most of these 32 bits, since they have
533 * restricted range. For any that we read, we won't to generate 32
534 * bit accesses, since Opteron will generate 2 separate 32 bit HT
535 * transactions for a 64 bit read, and we want to avoid unnecessary
536 * HT transactions.
537 */
538
539 /* This is the 64 bit group */
540
541 /*
542 * shadow of pioavail, check to be sure it's large enough at
543 * init time.
544 */
545 unsigned long ipath_pioavailshadow[8];
c4b4d16e
RC		 546 /* bitmap of send buffers available for the kernel to use with PIO. */
547 unsigned long ipath_pioavailkernel[8];
d41d3aeb
BS		 548 /* shadow of kr_gpio_out, for rmw ops */
549 u64 ipath_gpio_out;
8f140b40
AJ		 550 /* shadow the gpio mask register */
551 u64 ipath_gpio_mask;
17b2eb9f
MA		 552 /* shadow the gpio output enable, etc... */
553 u64 ipath_extctrl;
d41d3aeb
BS		 554 /* kr_revision shadow */
555 u64 ipath_revision;
556 /*
557 * shadow of ibcctrl, for interrupt handling of link changes,
558 * etc.
559 */
560 u64 ipath_ibcctrl;
561 /*
562 * last ibcstatus, to suppress "duplicate" status change messages,
563 * mostly from 2 to 3
564 */
565 u64 ipath_lastibcstat;
566 /* hwerrmask shadow */
567 ipath_err_t ipath_hwerrmask;
78d1e02f 568 ipath_err_t ipath_errormask; /* errormask shadow */
d41d3aeb
BS		 569 /* interrupt config reg shadow */
570 u64 ipath_intconfig;
571 /* kr_sendpiobufbase value */
572 u64 ipath_piobufbase;
afce688b
RC		 573 /* kr_ibcddrctrl shadow */
574 u64 ipath_ibcddrctrl;
d41d3aeb
BS		 575
576 /* these are the "32 bit" regs */
577
578 /*
579 * number of GUIDs in the flash for this interface; may need some
580 * rethinking for setting on other ifaces
581 */
582 u32 ipath_nguid;
583 /*
584 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
585 * all expect bit fields to be "unsigned long"
586 */
587 /* shadow kr_rcvctrl */
588 unsigned long ipath_rcvctrl;
589 /* shadow kr_sendctrl */
590 unsigned long ipath_sendctrl;
afce688b
RC		 591 /* to not count armlaunch after cancel */
592 unsigned long ipath_lastcancel;
593 /* count cases where special trigger was needed (double write) */
594 unsigned long ipath_spectriggerhit;
d41d3aeb
BS		 595
596 /* value we put in kr_rcvhdrcnt */
597 u32 ipath_rcvhdrcnt;
598 /* value we put in kr_rcvhdrsize */
599 u32 ipath_rcvhdrsize;
600 /* value we put in kr_rcvhdrentsize */
601 u32 ipath_rcvhdrentsize;
602 /* offset of last entry in rcvhdrq */
603 u32 ipath_hdrqlast;
604 /* kr_portcnt value */
605 u32 ipath_portcnt;
606 /* kr_pagealign value */
607 u32 ipath_palign;
608 /* number of "2KB" PIO buffers */
609 u32 ipath_piobcnt2k;
610 /* size in bytes of "2KB" PIO buffers */
611 u32 ipath_piosize2k;
612 /* number of "4KB" PIO buffers */
613 u32 ipath_piobcnt4k;
614 /* size in bytes of "4KB" PIO buffers */
615 u32 ipath_piosize4k;
afce688b 616 u32 ipath_pioreserved; /* reserved special-inkernel; */
d41d3aeb
BS		 617 /* kr_rcvegrbase value */
618 u32 ipath_rcvegrbase;
619 /* kr_rcvegrcnt value */
620 u32 ipath_rcvegrcnt;
621 /* kr_rcvtidbase value */
622 u32 ipath_rcvtidbase;
623 /* kr_rcvtidcnt value */
624 u32 ipath_rcvtidcnt;
625 /* kr_sendregbase */
626 u32 ipath_sregbase;
627 /* kr_userregbase */
628 u32 ipath_uregbase;
629 /* kr_counterregbase */
630 u32 ipath_cregbase;
631 /* shadow the control register contents */
632 u32 ipath_control;
d41d3aeb
BS		 633 /* PCI revision register (HTC rev on FPGA) */
634 u32 ipath_pcirev;
635
636 /* chip address space used by 4k pio buffers */
637 u32 ipath_4kalign;
638 /* The MTU programmed for this unit */
639 u32 ipath_ibmtu;
640 /*
641 * The max size IB packet, included IB headers that we can send.
642 * Starts same as ipath_piosize, but is affected when ibmtu is
643 * changed, or by size of eager buffers
644 */
645 u32 ipath_ibmaxlen;
646 /*
647 * ibmaxlen at init time, limited by chip and by receive buffer
648 * size. Not changed after init.
649 */
650 u32 ipath_init_ibmaxlen;
651 /* size of each rcvegrbuffer */
652 u32 ipath_rcvegrbufsize;
6ca2abf4
AJ		 653 /* localbus width (1, 2,4,8,16,32) from config space */
654 u32 ipath_lbus_width;
655 /* localbus speed (HT: 200,400,800,1000; PCIe 2500) */
656 u32 ipath_lbus_speed;
d41d3aeb
BS		 657 /*
658 * number of sequential ibcstatus change for polling active/quiet
659 * (i.e., link not coming up).
660 */
661 u32 ipath_ibpollcnt;
662 /* low and high portions of MSI capability/vector */
663 u32 ipath_msi_lo;
664 /* saved after PCIe init for restore after reset */
665 u32 ipath_msi_hi;
666 /* MSI data (vector) saved for restore */
667 u16 ipath_msi_data;
668 /* MLID programmed for this instance */
669 u16 ipath_mlid;
670 /* LID programmed for this instance */
671 u16 ipath_lid;
672 /* list of pkeys programmed; 0 if not set */
673 u16 ipath_pkeys[4];
8307c28e
BS		 674 /*
675 * ASCII serial number, from flash, large enough for original
676 * all digit strings, and longer QLogic serial number format
677 */
678 u8 ipath_serial[16];
d41d3aeb 679 /* human readable board version */
afce688b 680 u8 ipath_boardversion[96];
6ca2abf4 681 u8 ipath_lbus_info[32]; /* human readable localbus info */
d41d3aeb
BS		 682 /* chip major rev, from ipath_revision */
683 u8 ipath_majrev;
684 /* chip minor rev, from ipath_revision */
685 u8 ipath_minrev;
686 /* board rev, from ipath_revision */
687 u8 ipath_boardrev;
d41d3aeb
BS		 688 /* saved for restore after reset */
689 u8 ipath_pci_cacheline;
690 /* LID mask control */
691 u8 ipath_lmc;
c4bce803
DO		 692 /* link width supported */
693 u8 ipath_link_width_supported;
694 /* link speed supported */
695 u8 ipath_link_speed_supported;
696 u8 ipath_link_width_enabled;
697 u8 ipath_link_speed_enabled;
698 u8 ipath_link_width_active;
699 u8 ipath_link_speed_active;
30fc5c31
BS		 700 /* Rx Polarity inversion (compensate for ~tx on partner) */
701 u8 ipath_rx_pol_inv;
fba75200 702
9355fb6a
RC		 703 u8 ipath_r_portenable_shift;
704 u8 ipath_r_intravail_shift;
705 u8 ipath_r_tailupd_shift;
706 u8 ipath_r_portcfg_shift;
707
708 /* unit # of this chip, if present */
709 int ipath_unit;
710
fba75200
BS		 711 /* local link integrity counter */
712 u32 ipath_lli_counter;
713 /* local link integrity errors */
714 u32 ipath_lli_errors;
2c9446a1
BS		 715 /*
716 * Above counts only cases where _successive_ LocalLinkIntegrity
717 * errors were seen in the receive headers of kern-packets.
718 * Below are the three (monotonically increasing) counters
719 * maintained via GPIO interrupts on iba6120-rev2.
720 */
721 u32 ipath_rxfc_unsupvl_errs;
722 u32 ipath_overrun_thresh_errs;
723 u32 ipath_lli_errs;
f62fe77a
BS		 724
725 /*
726 * Not all devices managed by a driver instance are the same
727 * type, so these fields must be per-device.
728 */
729 u64 ipath_i_bitsextant;
730 ipath_err_t ipath_e_bitsextant;
731 ipath_err_t ipath_hwe_bitsextant;
732
733 /*
734 * Below should be computable from number of ports,
735 * since they are never modified.
736 */
9355fb6a
RC		 737 u64 ipath_i_rcvavail_mask;
738 u64 ipath_i_rcvurg_mask;
c4bce803
DO		 739 u16 ipath_i_rcvurg_shift;
740 u16 ipath_i_rcvavail_shift;
f62fe77a
BS		 741
742 /*
743 * Register bits for selecting i2c direction and values, used for
744 * I2C serial flash.
745 */
d84e0b28
MA		 746 u8 ipath_gpio_sda_num;
747 u8 ipath_gpio_scl_num;
748 u8 ipath_i2c_chain_type;
f62fe77a
BS		 749 u64 ipath_gpio_sda;
750 u64 ipath_gpio_scl;
82466f00 751
17b2eb9f
MA		 752 /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */
753 spinlock_t ipath_gpio_lock;
754
c4bce803
DO		 755 /*
756 * IB link and linktraining states and masks that vary per chip in
757 * some way. Set at init, to avoid each IB status change interrupt
758 */
759 u8 ibcs_ls_shift;
760 u8 ibcs_lts_mask;
761 u32 ibcs_mask;
762 u32 ib_init;
763 u32 ib_arm;
764 u32 ib_active;
765
766 u16 ipath_rhf_offset; /* offset of RHF within receive header entry */
767
768 /*
769 * shift/mask for linkcmd, linkinitcmd, maxpktlen in ibccontol
770 * reg. Changes for IBA7220
771 */
772 u8 ibcc_lic_mask; /* LinkInitCmd */
773 u8 ibcc_lc_shift; /* LinkCmd */
774 u8 ibcc_mpl_shift; /* Maxpktlen */
775
776 u8 delay_mult;
777
82466f00
MA		 778 /* used to override LED behavior */
779 u8 ipath_led_override; /* Substituted for normal value, if non-zero */
780 u16 ipath_led_override_timeoff; /* delta to next timer event */
781 u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */
782 u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */
783 atomic_t ipath_led_override_timer_active;
784 /* Used to flash LEDs in override mode */
785 struct timer_list ipath_led_override_timer;
786
aecd3b5a
MA		 787 /* Support (including locks) for EEPROM logging of errors and time */
788 /* control access to actual counters, timer */
789 spinlock_t ipath_eep_st_lock;
790 /* control high-level access to EEPROM */
2c45688f 791 struct mutex ipath_eep_lock;
aecd3b5a
MA		 792 /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */
793 uint64_t ipath_traffic_wds;
794 /* active time is kept in seconds, but logged in hours */
795 atomic_t ipath_active_time;
796 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
797 uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT];
798 uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT];
799 uint16_t ipath_eep_hrs;
800 /*
801 * masks for which bits of errs, hwerrs that cause
802 * each of the counters to increment.
803 */
804 struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT];
c4bce803
DO		 805
806 /* interrupt mitigation reload register info */
807 u16 ipath_jint_idle_ticks; /* idle clock ticks */
808 u16 ipath_jint_max_packets; /* max packets across all ports */
afce688b
RC		 809
810 /*
811 * lock for access to SerDes, and flags to sequence preset
812 * versus steady-state. 7220-only at the moment.
813 */
814 spinlock_t ipath_sdepb_lock;
815 u8 ipath_presets_needed; /* Set if presets to be restored next DOWN */
d41d3aeb
BS		 816};
817
58411d1c
JG		 818/* ipath_hol_state values (stopping/starting user proc, send flushing) */
819#define IPATH_HOL_UP 0
820#define IPATH_HOL_DOWN 1
821/* ipath_hol_next toggle values, used when hol_state IPATH_HOL_DOWN */
822#define IPATH_HOL_DOWNSTOP 0
823#define IPATH_HOL_DOWNCONT 1
824
afce688b
RC		 825/* bit positions for sdma_status */
826#define IPATH_SDMA_ABORTING 0
827#define IPATH_SDMA_DISARMED 1
828#define IPATH_SDMA_DISABLED 2
829#define IPATH_SDMA_LAYERBUF 3
f018c7e1
RD		 830#define IPATH_SDMA_RUNNING 30
831#define IPATH_SDMA_SHUTDOWN 31
afce688b
RC		 832
833/* bit combinations that correspond to abort states */
834#define IPATH_SDMA_ABORT_NONE 0
835#define IPATH_SDMA_ABORT_ABORTING (1UL << IPATH_SDMA_ABORTING)
836#define IPATH_SDMA_ABORT_DISARMED ((1UL << IPATH_SDMA_ABORTING) | \
837 (1UL << IPATH_SDMA_DISARMED))
838#define IPATH_SDMA_ABORT_DISABLED ((1UL << IPATH_SDMA_ABORTING) | \
839 (1UL << IPATH_SDMA_DISABLED))
840#define IPATH_SDMA_ABORT_ABORTED ((1UL << IPATH_SDMA_ABORTING) | \
841 (1UL << IPATH_SDMA_DISARMED) | (1UL << IPATH_SDMA_DISABLED))
842#define IPATH_SDMA_ABORT_MASK ((1UL<<IPATH_SDMA_ABORTING) | \
843 (1UL << IPATH_SDMA_DISARMED) | (1UL << IPATH_SDMA_DISABLED))
844
845#define IPATH_SDMA_BUF_NONE 0
846#define IPATH_SDMA_BUF_MASK (1UL<<IPATH_SDMA_LAYERBUF)
847
9929b0fb
BS		 848/* Private data for file operations */
849struct ipath_filedata {
850 struct ipath_portdata *pd;
851 unsigned subport;
852 unsigned tidcursor;
afce688b 853 struct ipath_user_sdma_queue *pq;
9929b0fb 854};
d41d3aeb
BS		 855extern struct list_head ipath_dev_list;
856extern spinlock_t ipath_devs_lock;
857extern struct ipath_devdata *ipath_lookup(int unit);
858
d41d3aeb
BS		 859int ipath_init_chip(struct ipath_devdata *, int);
860int ipath_enable_wc(struct ipath_devdata *dd);
861void ipath_disable_wc(struct ipath_devdata *dd);
6ef6aee2 862int ipath_count_units(int *npresentp, int *nupp, int *maxportsp);
d41d3aeb 863void ipath_shutdown_device(struct ipath_devdata *);
0f4fc5eb 864void ipath_clear_freeze(struct ipath_devdata *);
d41d3aeb
BS		 865
866struct file_operations;
2b8693c0 867int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
f4e91eb4 868 struct cdev **cdevp, struct device **devp);
d41d3aeb 869void ipath_cdev_cleanup(struct cdev **cdevp,
f4e91eb4 870 struct device **devp);
d41d3aeb 871
a2acb2ff
BS		 872int ipath_diag_add(struct ipath_devdata *);
873void ipath_diag_remove(struct ipath_devdata *);
d41d3aeb 874
0fd41363 875extern wait_queue_head_t ipath_state_wait;
d41d3aeb
BS		 876
877int ipath_user_add(struct ipath_devdata *dd);
a2acb2ff 878void ipath_user_remove(struct ipath_devdata *dd);
d41d3aeb
BS		 879
880struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
881
882extern int ipath_diag_inuse;
883
7d12e780 884irqreturn_t ipath_intr(int irq, void *devid);
124b4dcb
DO		 885int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
886 ipath_err_t err);
d41d3aeb
BS		 887#if __IPATH_INFO || __IPATH_DBG
888extern const char *ipath_ibcstatus_str[];
889#endif
890
891/* clean up any per-chip chip-specific stuff */
892void ipath_chip_cleanup(struct ipath_devdata *);
893/* clean up any chip type-specific stuff */
894void ipath_chip_done(void);
895
896/* check to see if we have to force ordering for write combining */
897int ipath_unordered_wc(void);
898
899void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
900 unsigned cnt);
3810f2a8 901void ipath_cancel_sends(struct ipath_devdata *, int);
d41d3aeb
BS		 902
903int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
f37bda92 904void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
d41d3aeb
BS		 905
906int ipath_parse_ushort(const char *str, unsigned short *valp);
907
c59a80ac 908void ipath_kreceive(struct ipath_portdata *);
d41d3aeb
BS		 909int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
910int ipath_reset_device(int);
911void ipath_get_faststats(unsigned long);
140277e9 912int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
34b2aafe
BS		 913int ipath_set_linkstate(struct ipath_devdata *, u8);
914int ipath_set_mtu(struct ipath_devdata *, u16);
915int ipath_set_lid(struct ipath_devdata *, u32, u8);
30fc5c31 916int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv);
6ac50727
DO		 917void ipath_enable_armlaunch(struct ipath_devdata *);
918void ipath_disable_armlaunch(struct ipath_devdata *);
58411d1c
JG		 919void ipath_hol_down(struct ipath_devdata *);
920void ipath_hol_up(struct ipath_devdata *);
921void ipath_hol_event(unsigned long);
afce688b
RC		 922void ipath_toggle_rclkrls(struct ipath_devdata *);
923void ipath_sd7220_clr_ibpar(struct ipath_devdata *);
924void ipath_set_relock_poll(struct ipath_devdata *, int);
925void ipath_shutdown_relock_poll(struct ipath_devdata *);
d41d3aeb
BS		 926
927/* for use in system calls, where we want to know device type, etc. */
9929b0fb
BS		 928#define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd
929#define subport_fp(fp) \
930 ((struct ipath_filedata *)(fp)->private_data)->subport
931#define tidcursor_fp(fp) \
932 ((struct ipath_filedata *)(fp)->private_data)->tidcursor
afce688b
RC		 933#define user_sdma_queue_fp(fp) \
934 ((struct ipath_filedata *)(fp)->private_data)->pq
d41d3aeb
BS		 935
936/*
937 * values for ipath_flags
938 */
a51a2513
RC		 939 /* chip can report link latency (IB 1.2) */
940#define IPATH_HAS_LINK_LATENCY 0x1
2ba3f56e 941 /* The chip is up and initted */
d41d3aeb
BS		 942#define IPATH_INITTED 0x2
943 /* set if any user code has set kr_rcvhdrsize */
944#define IPATH_RCVHDRSZ_SET 0x4
945 /* The chip is present and valid for accesses */
946#define IPATH_PRESENT 0x8
947 /* HT link0 is only 8 bits wide, ignore upper byte crc
948 * errors, etc. */
949#define IPATH_8BIT_IN_HT0 0x10
950 /* HT link1 is only 8 bits wide, ignore upper byte crc
951 * errors, etc. */
952#define IPATH_8BIT_IN_HT1 0x20
953 /* The link is down */
954#define IPATH_LINKDOWN 0x40
955 /* The link level is up (0x11) */
956#define IPATH_LINKINIT 0x80
957 /* The link is in the armed (0x21) state */
958#define IPATH_LINKARMED 0x100
959 /* The link is in the active (0x31) state */
960#define IPATH_LINKACTIVE 0x200
961 /* link current state is unknown */
962#define IPATH_LINKUNK 0x400
210d6ca3
RC		 963 /* Write combining flush needed for PIO */
964#define IPATH_PIO_FLUSH_WC 0x1000
9355fb6a
RC		 965 /* DMA Receive tail pointer */
966#define IPATH_NODMA_RTAIL 0x2000
d41d3aeb
BS		 967 /* no IB cable, or no device on IB cable */
968#define IPATH_NOCABLE 0x4000
969 /* Supports port zero per packet receive interrupts via
970 * GPIO */
971#define IPATH_GPIO_INTR 0x8000
972 /* uses the coded 4byte TID, not 8 byte */
973#define IPATH_4BYTE_TID 0x10000
974 /* packet/word counters are 32 bit, else those 4 counters
975 * are 64bit */
976#define IPATH_32BITCOUNTERS 0x20000
7da0498e
AJ		 977 /* Interrupt register is 64 bits */
978#define IPATH_INTREG_64 0x40000
9355fb6a 979 /* can miss port0 rx interrupts */
d41d3aeb 980#define IPATH_DISABLED 0x80000 /* administratively disabled */
2c9446a1
BS		 981 /* Use GPIO interrupts for new counters */
982#define IPATH_GPIO_ERRINTRS 0x100000
4ea61b54 983#define IPATH_SWAP_PIOBUFS 0x200000
afce688b
RC		 984 /* Supports Send DMA */
985#define IPATH_HAS_SEND_DMA 0x400000
986 /* Supports Send Count (not just word count) in PBC */
987#define IPATH_HAS_PBC_CNT 0x800000
359193ef
MA		 988 /* Suppress heartbeat, even if turning off loopback */
989#define IPATH_NO_HRTBT 0x1000000
afce688b 990#define IPATH_HAS_THRESH_UPDATE 0x4000000
359193ef 991#define IPATH_HAS_MULT_IB_SPEED 0x8000000
afce688b
RC		 992#define IPATH_IB_AUTONEG_INPROG 0x10000000
993#define IPATH_IB_AUTONEG_FAILED 0x20000000
4330e4da
MA		 994 /* Linkdown-disable intentionally, Do not attempt to bring up */
995#define IPATH_IB_LINK_DISABLED 0x40000000
58411d1c 996#define IPATH_IB_FORCE_NOTIFY 0x80000000 /* force notify on next ib change */
2c9446a1
BS		 997
998/* Bits in GPIO for the added interrupts */
999#define IPATH_GPIO_PORT0_BIT 2
1000#define IPATH_GPIO_RXUVL_BIT 3
1001#define IPATH_GPIO_OVRUN_BIT 4
1002#define IPATH_GPIO_LLI_BIT 5
1003#define IPATH_GPIO_ERRINTR_MASK 0x38
d41d3aeb
BS		 1004
1005/* portdata flag bit offsets */
1006 /* waiting for a packet to arrive */
1007#define IPATH_PORT_WAITING_RCV 2
947d7617
RC		 1008 /* master has not finished initializing */
1009#define IPATH_PORT_MASTER_UNINIT 4
f2d04231
RW		 1010 /* waiting for an urgent packet to arrive */
1011#define IPATH_PORT_WAITING_URG 5
d41d3aeb
BS		 1012
1013/* free up any allocated data at closes */
1014void ipath_free_data(struct ipath_portdata *dd);
c4b4d16e
RC		 1015u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *);
1016void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1017 unsigned len, int avail);
afce688b 1018void ipath_init_iba7220_funcs(struct ipath_devdata *);
525d0ca1
BS		 1019void ipath_init_iba6120_funcs(struct ipath_devdata *);
1020void ipath_init_iba6110_funcs(struct ipath_devdata *);
f2080fa3 1021void ipath_get_eeprom_info(struct ipath_devdata *);
aecd3b5a
MA		 1022int ipath_update_eeprom_log(struct ipath_devdata *dd);
1023void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr);
d41d3aeb 1024u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
e2ab41ca 1025void ipath_disarm_senderrbufs(struct ipath_devdata *);
c4b4d16e 1026void ipath_force_pio_avail_update(struct ipath_devdata *);
49739b3e 1027void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev);
d41d3aeb 1028
82466f00
MA		 1029/*
1030 * Set LED override, only the two LSBs have "public" meaning, but
1031 * any non-zero value substitutes them for the Link and LinkTrain
1032 * LED states.
1033 */
1034#define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1035#define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */
1036void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val);
1037
afce688b
RC		 1038/* send dma routines */
1039int setup_sdma(struct ipath_devdata *);
1040void teardown_sdma(struct ipath_devdata *);
124b4dcb 1041void ipath_restart_sdma(struct ipath_devdata *);
afce688b
RC		 1042void ipath_sdma_intr(struct ipath_devdata *);
1043int ipath_sdma_verbs_send(struct ipath_devdata *, struct ipath_sge_state *,
1044 u32, struct ipath_verbs_txreq *);
1045/* ipath_sdma_lock should be locked before calling this. */
1046int ipath_sdma_make_progress(struct ipath_devdata *dd);
1047
1048/* must be called under ipath_sdma_lock */
1049static inline u16 ipath_sdma_descq_freecnt(const struct ipath_devdata *dd)
1050{
1051 return dd->ipath_sdma_descq_cnt -
1052 (dd->ipath_sdma_descq_added - dd->ipath_sdma_descq_removed) -
1053 1 - dd->ipath_sdma_desc_nreserved;
1054}
1055
1056static inline void ipath_sdma_desc_reserve(struct ipath_devdata *dd, u16 cnt)
1057{
1058 dd->ipath_sdma_desc_nreserved += cnt;
1059}
1060
1061static inline void ipath_sdma_desc_unreserve(struct ipath_devdata *dd, u16 cnt)
1062{
1063 dd->ipath_sdma_desc_nreserved -= cnt;
1064}
1065
d41d3aeb
BS		 1066/*
1067 * number of words used for protocol header if not set by ipath_userinit();
1068 */
1069#define IPATH_DFLT_RCVHDRSIZE 9
1070
d41d3aeb 1071int ipath_get_user_pages(unsigned long, size_t, struct page **);
d41d3aeb
BS		 1072void ipath_release_user_pages(struct page **, size_t);
1073void ipath_release_user_pages_on_close(struct page **, size_t);
1074int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
1075int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
d84e0b28
MA		 1076int ipath_tempsense_read(struct ipath_devdata *, u8 regnum);
1077int ipath_tempsense_write(struct ipath_devdata *, u8 regnum, u8 data);
d41d3aeb
BS		 1078
1079/* these are used for the registers that vary with port */
1080void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
1081 unsigned, u64);
d41d3aeb
BS		 1082
1083/*
1084 * We could have a single register get/put routine, that takes a group type,
1085 * but this is somewhat clearer and cleaner. It also gives us some error
1086 * checking. 64 bit register reads should always work, but are inefficient
1087 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
1088 * so we use kreg32 wherever possible. User register and counter register
1089 * reads are always 32 bit reads, so only one form of those routines.
1090 */
1091
1092/*
1093 * At the moment, none of the s-registers are writable, so no
afce688b 1094 * ipath_write_sreg().
d41d3aeb
BS		 1095 */
1096
1097/**
1098 * ipath_read_ureg32 - read 32-bit virtualized per-port register
1099 * @dd: device
1100 * @regno: register number
1101 * @port: port number
1102 *
1103 * Return the contents of a register that is virtualized to be per port.
685f97e8
BS		 1104 * Returns -1 on errors (not distinguishable from valid contents at
1105 * runtime; we may add a separate error variable at some point).
d41d3aeb
BS		 1106 */
1107static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
1108 ipath_ureg regno, int port)
1109{
c71c30dc 1110 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 1111 return 0;
1112
1113 return readl(regno + (u64 __iomem *)
1114 (dd->ipath_uregbase +
1115 (char __iomem *)dd->ipath_kregbase +
a18e26ae 1116 dd->ipath_ureg_align * port));
d41d3aeb
BS		 1117}
1118
1119/**
1120 * ipath_write_ureg - write 32-bit virtualized per-port register
1121 * @dd: device
1122 * @regno: register number
1123 * @value: value
1124 * @port: port
1125 *
1126 * Write the contents of a register that is virtualized to be per port.
1127 */
1128static inline void ipath_write_ureg(const struct ipath_devdata *dd,
1129 ipath_ureg regno, u64 value, int port)
1130{
1131 u64 __iomem *ubase = (u64 __iomem *)
1132 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
a18e26ae 1133 dd->ipath_ureg_align * port);
d41d3aeb
BS		 1134 if (dd->ipath_kregbase)
1135 writeq(value, &ubase[regno]);
1136}
1137
1138static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
1139 ipath_kreg regno)
1140{
c71c30dc 1141 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 1142 return -1;
1143 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
1144}
1145
1146static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
1147 ipath_kreg regno)
1148{
c71c30dc 1149 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 1150 return -1;
1151
1152 return readq(&dd->ipath_kregbase[regno]);
1153}
1154
1155static inline void ipath_write_kreg(const struct ipath_devdata *dd,
1156 ipath_kreg regno, u64 value)
1157{
1158 if (dd->ipath_kregbase)
1159 writeq(value, &dd->ipath_kregbase[regno]);
1160}
1161
1162static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
1163 ipath_sreg regno)
1164{
c71c30dc 1165 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 1166 return 0;
1167
1168 return readq(regno + (u64 __iomem *)
1169 (dd->ipath_cregbase +
1170 (char __iomem *)dd->ipath_kregbase));
1171}
1172
1173static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
1174 ipath_sreg regno)
1175{
c71c30dc 1176 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
d41d3aeb
BS		 1177 return 0;
1178 return readl(regno + (u64 __iomem *)
1179 (dd->ipath_cregbase +
1180 (char __iomem *)dd->ipath_kregbase));
1181}
1182
6c719cae
RC		 1183static inline void ipath_write_creg(const struct ipath_devdata *dd,
1184 ipath_creg regno, u64 value)
1185{
1186 if (dd->ipath_kregbase)
1187 writeq(value, regno + (u64 __iomem *)
1188 (dd->ipath_cregbase +
1189 (char __iomem *)dd->ipath_kregbase));
1190}
1191
c59a80ac
RC		 1192static inline void ipath_clear_rcvhdrtail(const struct ipath_portdata *pd)
1193{
1194 *((u64 *) pd->port_rcvhdrtail_kvaddr) = 0ULL;
1195}
1196
1197static inline u32 ipath_get_rcvhdrtail(const struct ipath_portdata *pd)
1198{
1199 return (u32) le64_to_cpu(*((volatile __le64 *)
1200 pd->port_rcvhdrtail_kvaddr));
1201}
1202
9355fb6a
RC		 1203static inline u32 ipath_get_hdrqtail(const struct ipath_portdata *pd)
1204{
1205 const struct ipath_devdata *dd = pd->port_dd;
1206 u32 hdrqtail;
1207
1208 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1209 __le32 *rhf_addr;
1210 u32 seq;
1211
1212 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1213 pd->port_head + dd->ipath_rhf_offset;
1214 seq = ipath_hdrget_seq(rhf_addr);
1215 hdrqtail = pd->port_head;
1216 if (seq == pd->port_seq_cnt)
1217 hdrqtail++;
1218 } else
1219 hdrqtail = ipath_get_rcvhdrtail(pd);
1220
1221 return hdrqtail;
1222}
1223
7da0498e
AJ		 1224static inline u64 ipath_read_ireg(const struct ipath_devdata *dd, ipath_kreg r)
1225{
1226 return (dd->ipath_flags & IPATH_INTREG_64) ?
1227 ipath_read_kreg64(dd, r) : ipath_read_kreg32(dd, r);
1228}
1229
c4bce803
DO		 1230/*
1231 * from contents of IBCStatus (or a saved copy), return linkstate
1232 * Report ACTIVE_DEFER as ACTIVE, because we treat them the same
1233 * everywhere, anyway (and should be, for almost all purposes).
1234 */
1235static inline u32 ipath_ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
1236{
1237 u32 state = (u32)(ibcs >> dd->ibcs_ls_shift) &
1238 INFINIPATH_IBCS_LINKSTATE_MASK;
1239 if (state == INFINIPATH_IBCS_L_STATE_ACT_DEFER)
1240 state = INFINIPATH_IBCS_L_STATE_ACTIVE;
1241 return state;
1242}
1243
1244/* from contents of IBCStatus (or a saved copy), return linktrainingstate */
1245static inline u32 ipath_ib_linktrstate(struct ipath_devdata *dd, u64 ibcs)
1246{
1247 return (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1248 dd->ibcs_lts_mask;
1249}
1250
58411d1c
JG		 1251/*
1252 * from contents of IBCStatus (or a saved copy), return logical link state
1253 * combination of link state and linktraining state (down, active, init,
1254 * arm, etc.
1255 */
1256static inline u32 ipath_ib_state(struct ipath_devdata *dd, u64 ibcs)
1257{
1258 u32 ibs;
1259 ibs = (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
1260 dd->ibcs_lts_mask;
1261 ibs |= (u32)(ibcs &
1262 (INFINIPATH_IBCS_LINKSTATE_MASK << dd->ibcs_ls_shift));
1263 return ibs;
1264}
1265
d41d3aeb
BS		 1266/*
1267 * sysfs interface.
1268 */
1269
1270struct device_driver;
1271
b55f4f06 1272extern const char ib_ipath_version[];
d41d3aeb 1273
23b9c1ab 1274extern struct attribute_group *ipath_driver_attr_groups[];
d41d3aeb
BS		 1275
1276int ipath_device_create_group(struct device *, struct ipath_devdata *);
1277void ipath_device_remove_group(struct device *, struct ipath_devdata *);
1278int ipath_expose_reset(struct device *);
1279
1280int ipath_init_ipathfs(void);
1281void ipath_exit_ipathfs(void);
1282int ipathfs_add_device(struct ipath_devdata *);
1283int ipathfs_remove_device(struct ipath_devdata *);
1284
1fd3b40f
BS		 1285/*
1286 * dma_addr wrappers - all 0's invalid for hw
1287 */
1288dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long,
1289 size_t, int);
1290dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int);
afce688b 1291const char *ipath_get_unit_name(int unit);
1fd3b40f 1292
d41d3aeb
BS		 1293/*
1294 * Flush write combining store buffers (if present) and perform a write
1295 * barrier.
1296 */
1297#if defined(CONFIG_X86_64)
1298#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
1299#else
1300#define ipath_flush_wc() wmb()
1301#endif
1302
1303extern unsigned ipath_debug; /* debugging bit mask */
72708a0a 1304extern unsigned ipath_linkrecovery;
826d8010 1305extern unsigned ipath_mtu4096;
d41d3aeb
BS		 1306extern struct mutex ipath_mutex;
1307
b55f4f06 1308#define IPATH_DRV_NAME "ib_ipath"
d41d3aeb 1309#define IPATH_MAJOR 233
a2acb2ff 1310#define IPATH_USER_MINOR_BASE 0
98341f26 1311#define IPATH_DIAGPKT_MINOR 127
a2acb2ff
BS		 1312#define IPATH_DIAG_MINOR_BASE 129
1313#define IPATH_NMINORS 255
d41d3aeb
BS		 1314
1315#define ipath_dev_err(dd,fmt,...) \
1316 do { \
1317 const struct ipath_devdata *__dd = (dd); \
1318 if (__dd->pcidev) \
1319 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
1320 ipath_get_unit_name(__dd->ipath_unit), \
1321 ##__VA_ARGS__); \
1322 else \
1323 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
1324 ipath_get_unit_name(__dd->ipath_unit), \
1325 ##__VA_ARGS__); \
1326 } while (0)
1327
1328#if _IPATH_DEBUGGING
1329
1330# define __IPATH_DBG_WHICH(which,fmt,...) \
1331 do { \
2ba3f56e 1332 if (unlikely(ipath_debug & (which))) \
d41d3aeb
BS		 1333 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
1334 __func__,##__VA_ARGS__); \
1335 } while(0)
1336
1337# define ipath_dbg(fmt,...) \
1338 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
1339# define ipath_cdbg(which,fmt,...) \
1340 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
1341
1342#else /* ! _IPATH_DEBUGGING */
1343
1344# define ipath_dbg(fmt,...)
1345# define ipath_cdbg(which,fmt,...)
1346
1347#endif /* _IPATH_DEBUGGING */
1348
8d588f8b
BS		 1349/*
1350 * this is used for formatting hw error messages...
1351 */
1352struct ipath_hwerror_msgs {
1353 u64 mask;
1354 const char *msg;
1355};
1356
1357#define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
1358
1359/* in ipath_intr.c... */
1360void ipath_format_hwerrors(u64 hwerrs,
1361 const struct ipath_hwerror_msgs *hwerrmsgs,
1362 size_t nhwerrmsgs,
1363 char *msg, size_t lmsg);
1364
d41d3aeb 1365#endif /* _IPATH_KERNEL_H */
kernel source for telekom puls (alcatel/mediatek)