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timers: add mod_timer_pending()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / infiniband / hw / ipath / ipath_driver.c
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7bb206e3 1/*
e7eacd36 2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
7bb206e3
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/spinlock.h>
35#include <linux/idr.h>
36#include <linux/pci.h>
9bec3992 37#include <linux/io.h>
7bb206e3
BS		 38#include <linux/delay.h>
39#include <linux/netdevice.h>
40#include <linux/vmalloc.h>
41
42#include "ipath_kernel.h"
b1c1b6a3 43#include "ipath_verbs.h"
7bb206e3
BS		 44
45static void ipath_update_pio_bufs(struct ipath_devdata *);
46
47const char *ipath_get_unit_name(int unit)
48{
49 static char iname[16];
50 snprintf(iname, sizeof iname, "infinipath%u", unit);
51 return iname;
52}
53
759d5768 54#define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
7bb206e3
BS		 55#define PFX IPATH_DRV_NAME ": "
56
57/*
58 * The size has to be longer than this string, so we can append
59 * board/chip information to it in the init code.
60 */
b55f4f06 61const char ib_ipath_version[] = IPATH_IDSTR "\n";
7bb206e3
BS		 62
63static struct idr unit_table;
64DEFINE_SPINLOCK(ipath_devs_lock);
65LIST_HEAD(ipath_dev_list);
66
0fd41363 67wait_queue_head_t ipath_state_wait;
7bb206e3
BS		 68
69unsigned ipath_debug = __IPATH_INFO;
70
71module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72MODULE_PARM_DESC(debug, "mask for debug prints");
73EXPORT_SYMBOL_GPL(ipath_debug);
74
826d8010
DO		 75unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
76module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
77MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
78
58411d1c
JG		 79static unsigned ipath_hol_timeout_ms = 13000;
80module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
81MODULE_PARM_DESC(hol_timeout_ms,
82 "duration of user app suspension after link failure");
83
72708a0a
DO		 84unsigned ipath_linkrecovery = 1;
85module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
86MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
87
7bb206e3 88MODULE_LICENSE("GPL");
928e3e4b 89MODULE_AUTHOR("QLogic <support@qlogic.com>");
759d5768 90MODULE_DESCRIPTION("QLogic InfiniPath driver");
7bb206e3 91
bb917144
AJ		 92/*
93 * Table to translate the LINKTRAININGSTATE portion of
94 * IBCStatus to a human-readable form.
95 */
7bb206e3
BS		 96const char *ipath_ibcstatus_str[] = {
97 "Disabled",
98 "LinkUp",
99 "PollActive",
100 "PollQuiet",
101 "SleepDelay",
102 "SleepQuiet",
103 "LState6", /* unused */
104 "LState7", /* unused */
105 "CfgDebounce",
106 "CfgRcvfCfg",
107 "CfgWaitRmt",
108 "CfgIdle",
109 "RecovRetrain",
bb917144 110 "CfgTxRevLane", /* unused before IBA7220 */
7bb206e3
BS		 111 "RecovWaitRmt",
112 "RecovIdle",
bb917144
AJ		 113 /* below were added for IBA7220 */
114 "CfgEnhanced",
115 "CfgTest",
116 "CfgWaitRmtTest",
117 "CfgWaitCfgEnhanced",
118 "SendTS_T",
119 "SendTstIdles",
120 "RcvTS_T",
121 "SendTst_TS1s",
122 "LTState18", "LTState19", "LTState1A", "LTState1B",
123 "LTState1C", "LTState1D", "LTState1E", "LTState1F"
7bb206e3
BS		 124};
125
7bb206e3
BS		 126static void __devexit ipath_remove_one(struct pci_dev *);
127static int __devinit ipath_init_one(struct pci_dev *,
128 const struct pci_device_id *);
129
130/* Only needed for registration, nothing else needs this info */
131#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
124b4dcb 132#define PCI_VENDOR_ID_QLOGIC 0x1077
7bb206e3
BS		 133#define PCI_DEVICE_ID_INFINIPATH_HT 0xd
134#define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
124b4dcb 135#define PCI_DEVICE_ID_INFINIPATH_7220 0x7220
7bb206e3 136
3588423f
AJ		 137/* Number of seconds before our card status check... */
138#define STATUS_TIMEOUT 60
139
7bb206e3 140static const struct pci_device_id ipath_pci_tbl[] = {
6f4bb3d8
RD		 141 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
142 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
124b4dcb 143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_INFINIPATH_7220) },
6f4bb3d8 144 { 0, }
7bb206e3
BS		 145};
146
147MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
148
149static struct pci_driver ipath_driver = {
150 .name = IPATH_DRV_NAME,
151 .probe = ipath_init_one,
152 .remove = __devexit_p(ipath_remove_one),
153 .id_table = ipath_pci_tbl,
23b9c1ab
GKH		 154 .driver = {
155 .groups = ipath_driver_attr_groups,
156 },
7bb206e3
BS		 157};
158
7bb206e3
BS		 159static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
160 u32 *bar0, u32 *bar1)
161{
162 int ret;
163
164 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
165 if (ret)
166 ipath_dev_err(dd, "failed to read bar0 before enable: "
167 "error %d\n", -ret);
168
169 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
170 if (ret)
171 ipath_dev_err(dd, "failed to read bar1 before enable: "
172 "error %d\n", -ret);
173
174 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
175}
176
177static void ipath_free_devdata(struct pci_dev *pdev,
178 struct ipath_devdata *dd)
179{
180 unsigned long flags;
181
182 pci_set_drvdata(pdev, NULL);
183
184 if (dd->ipath_unit != -1) {
185 spin_lock_irqsave(&ipath_devs_lock, flags);
186 idr_remove(&unit_table, dd->ipath_unit);
187 list_del(&dd->ipath_list);
188 spin_unlock_irqrestore(&ipath_devs_lock, flags);
189 }
06993ca6 190 vfree(dd);
7bb206e3
BS		 191}
192
193static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
194{
195 unsigned long flags;
196 struct ipath_devdata *dd;
7bb206e3
BS		 197 int ret;
198
199 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
200 dd = ERR_PTR(-ENOMEM);
201 goto bail;
202 }
203
06993ca6 204 dd = vmalloc(sizeof(*dd));
7bb206e3
BS		 205 if (!dd) {
206 dd = ERR_PTR(-ENOMEM);
207 goto bail;
208 }
06993ca6 209 memset(dd, 0, sizeof(*dd));
7bb206e3
BS		 210 dd->ipath_unit = -1;
211
212 spin_lock_irqsave(&ipath_devs_lock, flags);
213
214 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
215 if (ret < 0) {
216 printk(KERN_ERR IPATH_DRV_NAME
217 ": Could not allocate unit ID: error %d\n", -ret);
218 ipath_free_devdata(pdev, dd);
219 dd = ERR_PTR(ret);
220 goto bail_unlock;
221 }
222
223 dd->pcidev = pdev;
224 pci_set_drvdata(pdev, dd);
225
226 list_add(&dd->ipath_list, &ipath_dev_list);
227
228bail_unlock:
229 spin_unlock_irqrestore(&ipath_devs_lock, flags);
230
231bail:
232 return dd;
233}
234
235static inline struct ipath_devdata *__ipath_lookup(int unit)
236{
237 return idr_find(&unit_table, unit);
238}
239
240struct ipath_devdata *ipath_lookup(int unit)
241{
242 struct ipath_devdata *dd;
243 unsigned long flags;
244
245 spin_lock_irqsave(&ipath_devs_lock, flags);
246 dd = __ipath_lookup(unit);
247 spin_unlock_irqrestore(&ipath_devs_lock, flags);
248
249 return dd;
250}
251
6ef6aee2 252int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
7bb206e3
BS		 253{
254 int nunits, npresent, nup;
255 struct ipath_devdata *dd;
256 unsigned long flags;
6ef6aee2 257 int maxports;
7bb206e3
BS		 258
259 nunits = npresent = nup = maxports = 0;
260
261 spin_lock_irqsave(&ipath_devs_lock, flags);
262
263 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
264 nunits++;
265 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
266 npresent++;
267 if (dd->ipath_lid &&
268 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
269 | IPATH_LINKUNK)))
270 nup++;
271 if (dd->ipath_cfgports > maxports)
272 maxports = dd->ipath_cfgports;
273 }
274
275 spin_unlock_irqrestore(&ipath_devs_lock, flags);
276
277 if (npresentp)
278 *npresentp = npresent;
279 if (nupp)
280 *nupp = nup;
281 if (maxportsp)
282 *maxportsp = maxports;
283
284 return nunits;
285}
286
7bb206e3
BS		 287/*
288 * These next two routines are placeholders in case we don't have per-arch
289 * code for controlling write combining. If explicit control of write
290 * combining is not available, performance will probably be awful.
291 */
292
293int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
294{
295 return -EOPNOTSUPP;
296}
297
298void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
299{
300}
301
9bec3992
DO		 302/*
303 * Perform a PIO buffer bandwidth write test, to verify proper system
304 * configuration. Even when all the setup calls work, occasionally
305 * BIOS or other issues can prevent write combining from working, or
306 * can cause other bandwidth problems to the chip.
307 *
308 * This test simply writes the same buffer over and over again, and
309 * measures close to the peak bandwidth to the chip (not testing
310 * data bandwidth to the wire). On chips that use an address-based
311 * trigger to send packets to the wire, this is easy. On chips that
312 * use a count to trigger, we want to make sure that the packet doesn't
313 * go out on the wire, or trigger flow control checks.
314 */
315static void ipath_verify_pioperf(struct ipath_devdata *dd)
316{
317 u32 pbnum, cnt, lcnt;
318 u32 __iomem *piobuf;
319 u32 *addr;
320 u64 msecs, emsecs;
321
c4b4d16e 322 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
9bec3992
DO		 323 if (!piobuf) {
324 dev_info(&dd->pcidev->dev,
325 "No PIObufs for checking perf, skipping\n");
326 return;
327 }
328
329 /*
330 * Enough to give us a reasonable test, less than piobuf size, and
331 * likely multiple of store buffer length.
332 */
333 cnt = 1024;
334
335 addr = vmalloc(cnt);
336 if (!addr) {
337 dev_info(&dd->pcidev->dev,
338 "Couldn't get memory for checking PIO perf,"
339 " skipping\n");
340 goto done;
341 }
342
343 preempt_disable(); /* we want reasonably accurate elapsed time */
344 msecs = 1 + jiffies_to_msecs(jiffies);
345 for (lcnt = 0; lcnt < 10000U; lcnt++) {
346 /* wait until we cross msec boundary */
347 if (jiffies_to_msecs(jiffies) >= msecs)
348 break;
349 udelay(1);
350 }
351
6ac50727
DO		 352 ipath_disable_armlaunch(dd);
353
bb917144
AJ		 354 /*
355 * length 0, no dwords actually sent, and mark as VL15
356 * on chips where that may matter (due to IB flowcontrol)
357 */
358 if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
359 writeq(1UL << 63, piobuf);
360 else
361 writeq(0, piobuf);
9bec3992
DO		 362 ipath_flush_wc();
363
364 /*
365 * this is only roughly accurate, since even with preempt we
366 * still take interrupts that could take a while. Running for
367 * >= 5 msec seems to get us "close enough" to accurate values
368 */
369 msecs = jiffies_to_msecs(jiffies);
370 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
371 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
372 emsecs = jiffies_to_msecs(jiffies) - msecs;
373 }
374
375 /* 1 GiB/sec, slightly over IB SDR line rate */
376 if (lcnt < (emsecs * 1024U))
377 ipath_dev_err(dd,
378 "Performance problem: bandwidth to PIO buffers is "
379 "only %u MiB/sec\n",
380 lcnt / (u32) emsecs);
381 else
382 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
383 lcnt / (u32) emsecs);
384
385 preempt_enable();
386
387 vfree(addr);
388
389done:
390 /* disarm piobuf, so it's available again */
391 ipath_disarm_piobufs(dd, pbnum, 1);
6ac50727 392 ipath_enable_armlaunch(dd);
9bec3992
DO		 393}
394
7bb206e3
BS		 395static int __devinit ipath_init_one(struct pci_dev *pdev,
396 const struct pci_device_id *ent)
397{
398 int ret, len, j;
399 struct ipath_devdata *dd;
400 unsigned long long addr;
401 u32 bar0 = 0, bar1 = 0;
bb917144 402 u8 rev;
7bb206e3 403
7bb206e3
BS		 404 dd = ipath_alloc_devdata(pdev);
405 if (IS_ERR(dd)) {
406 ret = PTR_ERR(dd);
407 printk(KERN_ERR IPATH_DRV_NAME
408 ": Could not allocate devdata: error %d\n", -ret);
f37bda92 409 goto bail;
7bb206e3
BS		 410 }
411
412 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
413
7bb206e3
BS		 414 ret = pci_enable_device(pdev);
415 if (ret) {
416 /* This can happen iff:
417 *
418 * We did a chip reset, and then failed to reprogram the
419 * BAR, or the chip reset due to an internal error. We then
420 * unloaded the driver and reloaded it.
421 *
422 * Both reset cases set the BAR back to initial state. For
423 * the latter case, the AER sticky error bit at offset 0x718
424 * should be set, but the Linux kernel doesn't yet know
425 * about that, it appears. If the original BAR was retained
426 * in the kernel data structures, this may be OK.
427 */
428 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
429 dd->ipath_unit, -ret);
430 goto bail_devdata;
431 }
432 addr = pci_resource_start(pdev, 0);
433 len = pci_resource_len(pdev, 0);
bb917144 434 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
7bb206e3
BS		 435 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
436 ent->device, ent->driver_data);
437
438 read_bars(dd, pdev, &bar0, &bar1);
439
440 if (!bar1 && !(bar0 & ~0xf)) {
441 if (addr) {
442 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
443 "rewriting as %llx\n", addr);
444 ret = pci_write_config_dword(
445 pdev, PCI_BASE_ADDRESS_0, addr);
446 if (ret) {
447 ipath_dev_err(dd, "rewrite of BAR0 "
448 "failed: err %d\n", -ret);
449 goto bail_disable;
450 }
451 ret = pci_write_config_dword(
452 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
453 if (ret) {
454 ipath_dev_err(dd, "rewrite of BAR1 "
455 "failed: err %d\n", -ret);
456 goto bail_disable;
457 }
458 } else {
459 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
460 "not usable until reboot\n");
461 ret = -ENODEV;
462 goto bail_disable;
463 }
464 }
465
466 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
467 if (ret) {
468 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
469 "err %d\n", dd->ipath_unit, -ret);
470 goto bail_disable;
471 }
472
473 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
474 if (ret) {
68dd43a1
BS		 475 /*
476 * if the 64 bit setup fails, try 32 bit. Some systems
477 * do not setup 64 bit maps on systems with 2GB or less
478 * memory installed.
479 */
480 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
481 if (ret) {
b1d8865a
BS		 482 dev_info(&pdev->dev,
483 "Unable to set DMA mask for unit %u: %d\n",
484 dd->ipath_unit, ret);
68dd43a1
BS		 485 goto bail_regions;
486 }
b1d8865a 487 else {
68dd43a1 488 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
b1d8865a
BS		 489 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
490 if (ret)
491 dev_info(&pdev->dev,
492 "Unable to set DMA consistent mask "
493 "for unit %u: %d\n",
494 dd->ipath_unit, ret);
495
496 }
497 }
498 else {
499 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
500 if (ret)
501 dev_info(&pdev->dev,
502 "Unable to set DMA consistent mask "
503 "for unit %u: %d\n",
504 dd->ipath_unit, ret);
7bb206e3
BS		 505 }
506
507 pci_set_master(pdev);
508
509 /*
510 * Save BARs to rewrite after device reset. Save all 64 bits of
511 * BAR, just in case.
512 */
513 dd->ipath_pcibar0 = addr;
514 dd->ipath_pcibar1 = addr >> 32;
515 dd->ipath_deviceid = ent->device; /* save for later use */
516 dd->ipath_vendorid = ent->vendor;
517
518 /* setup the chip-specific functions, as early as possible. */
519 switch (ent->device) {
520 case PCI_DEVICE_ID_INFINIPATH_HT:
820054b7 521#ifdef CONFIG_HT_IRQ
525d0ca1 522 ipath_init_iba6110_funcs(dd);
7bb206e3 523 break;
820054b7
BS		 524#else
525 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
526 "CONFIG_HT_IRQ is not enabled\n", ent->device);
527 return -ENODEV;
e757bef2 528#endif
7bb206e3 529 case PCI_DEVICE_ID_INFINIPATH_PE800:
820054b7 530#ifdef CONFIG_PCI_MSI
525d0ca1 531 ipath_init_iba6120_funcs(dd);
7bb206e3 532 break;
820054b7
BS		 533#else
534 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
535 "CONFIG_PCI_MSI is not enabled\n", ent->device);
536 return -ENODEV;
e757bef2 537#endif
124b4dcb
DO		 538 case PCI_DEVICE_ID_INFINIPATH_7220:
539#ifndef CONFIG_PCI_MSI
540 ipath_dbg("CONFIG_PCI_MSI is not enabled, "
bc751fe6 541 "using INTx for unit %u\n", dd->ipath_unit);
124b4dcb
DO		 542#endif
543 ipath_init_iba7220_funcs(dd);
544 break;
7bb206e3 545 default:
759d5768 546 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
7bb206e3
BS		 547 "failing\n", ent->device);
548 return -ENODEV;
549 }
550
551 for (j = 0; j < 6; j++) {
552 if (!pdev->resource[j].start)
553 continue;
e29419ff
GKH		 554 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
555 j, (unsigned long long)pdev->resource[j].start,
556 (unsigned long long)pdev->resource[j].end,
557 (unsigned long long)pci_resource_len(pdev, j));
7bb206e3
BS		 558 }
559
560 if (!addr) {
561 ipath_dev_err(dd, "No valid address in BAR 0!\n");
562 ret = -ENODEV;
563 goto bail_regions;
564 }
565
bb917144
AJ		 566 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
567 if (ret) {
568 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
569 "%u: err %d\n", dd->ipath_unit, -ret);
570 goto bail_regions; /* shouldn't ever happen */
571 }
572 dd->ipath_pcirev = rev;
7bb206e3 573
eb9dc6f4
BS		 574#if defined(__powerpc__)
575 /* There isn't a generic way to specify writethrough mappings */
576 dd->ipath_kregbase = __ioremap(addr, len,
577 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
578#else
7bb206e3 579 dd->ipath_kregbase = ioremap_nocache(addr, len);
eb9dc6f4 580#endif
7bb206e3
BS		 581
582 if (!dd->ipath_kregbase) {
583 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
584 addr);
585 ret = -ENOMEM;
586 goto bail_iounmap;
587 }
588 dd->ipath_kregend = (u64 __iomem *)
589 ((void __iomem *)dd->ipath_kregbase + len);
590 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
591 /* for user mmap */
b35f004d
BS		 592 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
593 addr, dd->ipath_kregbase);
7bb206e3 594
7bb206e3
BS		 595 if (dd->ipath_f_bus(dd, pdev))
596 ipath_dev_err(dd, "Failed to setup config space; "
597 "continuing anyway\n");
598
599 /*
dace1453 600 * set up our interrupt handler; IRQF_SHARED probably not needed,
7bb206e3
BS		 601 * since MSI interrupts shouldn't be shared but won't hurt for now.
602 * check 0 irq after we return from chip-specific bus setup, since
603 * that can affect this due to setup
604 */
51f65ebc 605 if (!dd->ipath_irq)
7bb206e3
BS		 606 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
607 "work\n");
608 else {
51f65ebc 609 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
7bb206e3
BS		 610 IPATH_DRV_NAME, dd);
611 if (ret) {
612 ipath_dev_err(dd, "Couldn't setup irq handler, "
51f65ebc 613 "irq=%d: %d\n", dd->ipath_irq, ret);
7bb206e3
BS		 614 goto bail_iounmap;
615 }
616 }
617
618 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
619 if (ret)
7b196e2f 620 goto bail_irqsetup;
7bb206e3
BS		 621
622 ret = ipath_enable_wc(dd);
623
624 if (ret) {
625 ipath_dev_err(dd, "Write combining not enabled "
626 "(err %d): performance may be poor\n",
627 -ret);
628 ret = 0;
629 }
630
9bec3992
DO		 631 ipath_verify_pioperf(dd);
632
7bb206e3
BS		 633 ipath_device_create_group(&pdev->dev, dd);
634 ipathfs_add_device(dd);
635 ipath_user_add(dd);
a2acb2ff 636 ipath_diag_add(dd);
b1c1b6a3 637 ipath_register_ib_device(dd);
7bb206e3
BS		 638
639 goto bail;
640
7b196e2f 641bail_irqsetup:
2ba3f56e
RC		 642 if (pdev->irq)
643 free_irq(pdev->irq, dd);
7b196e2f 644
7bb206e3
BS		 645bail_iounmap:
646 iounmap((volatile void __iomem *) dd->ipath_kregbase);
647
648bail_regions:
649 pci_release_regions(pdev);
650
651bail_disable:
652 pci_disable_device(pdev);
653
654bail_devdata:
655 ipath_free_devdata(pdev, dd);
656
7bb206e3
BS		 657bail:
658 return ret;
659}
660
7227aac4 661static void __devexit cleanup_device(struct ipath_devdata *dd)
7bb206e3 662{
7227aac4 663 int port;
3d089098
DO		 664 struct ipath_portdata **tmp;
665 unsigned long flags;
7bb206e3 666
7227aac4
BS		 667 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
668 /* can't do anything more with chip; needs re-init */
669 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
670 if (dd->ipath_kregbase) {
671 /*
672 * if we haven't already cleaned up before these are
673 * to ensure any register reads/writes "fail" until
674 * re-init
675 */
676 dd->ipath_kregbase = NULL;
677 dd->ipath_uregbase = 0;
678 dd->ipath_sregbase = 0;
679 dd->ipath_cregbase = 0;
680 dd->ipath_kregsize = 0;
681 }
682 ipath_disable_wc(dd);
683 }
c78f6415 684
bb917144
AJ		 685 if (dd->ipath_spectriggerhit)
686 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
687 dd->ipath_spectriggerhit);
688
7227aac4
BS		 689 if (dd->ipath_pioavailregs_dma) {
690 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
691 (void *) dd->ipath_pioavailregs_dma,
692 dd->ipath_pioavailregs_phys);
693 dd->ipath_pioavailregs_dma = NULL;
694 }
695 if (dd->ipath_dummy_hdrq) {
696 dma_free_coherent(&dd->pcidev->dev,
697 dd->ipath_pd[0]->port_rcvhdrq_size,
698 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
699 dd->ipath_dummy_hdrq = NULL;
700 }
701
702 if (dd->ipath_pageshadow) {
703 struct page **tmpp = dd->ipath_pageshadow;
704 dma_addr_t *tmpd = dd->ipath_physshadow;
705 int i, cnt = 0;
706
707 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
708 "locked\n");
709 for (port = 0; port < dd->ipath_cfgports; port++) {
710 int port_tidbase = port * dd->ipath_rcvtidcnt;
711 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
712 for (i = port_tidbase; i < maxtid; i++) {
713 if (!tmpp[i])
714 continue;
715 pci_unmap_page(dd->pcidev, tmpd[i],
716 PAGE_SIZE, PCI_DMA_FROMDEVICE);
717 ipath_release_user_pages(&tmpp[i], 1);
718 tmpp[i] = NULL;
719 cnt++;
720 }
721 }
722 if (cnt) {
723 ipath_stats.sps_pageunlocks += cnt;
724 ipath_cdbg(VERBOSE, "There were still %u expTID "
725 "entries locked\n", cnt);
726 }
727 if (ipath_stats.sps_pagelocks ||
728 ipath_stats.sps_pageunlocks)
729 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
730 "unlocked via ipath_m{un}lock\n",
731 (unsigned long long)
732 ipath_stats.sps_pagelocks,
733 (unsigned long long)
734 ipath_stats.sps_pageunlocks);
735
736 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
737 dd->ipath_pageshadow);
9783ab40 738 tmpp = dd->ipath_pageshadow;
7227aac4 739 dd->ipath_pageshadow = NULL;
9783ab40 740 vfree(tmpp);
9355fb6a
RC		 741
742 dd->ipath_egrtidbase = NULL;
c78f6415
BS		 743 }
744
7227aac4
BS		 745 /*
746 * free any resources still in use (usually just kernel ports)
3d089098
DO		 747 * at unload; we do for portcnt, because that's what we allocate.
748 * We acquire lock to be really paranoid that ipath_pd isn't being
749 * accessed from some interrupt-related code (that should not happen,
750 * but best to be sure).
7227aac4 751 */
3d089098
DO		 752 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
753 tmp = dd->ipath_pd;
754 dd->ipath_pd = NULL;
755 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
7227aac4 756 for (port = 0; port < dd->ipath_portcnt; port++) {
3d089098
DO		 757 struct ipath_portdata *pd = tmp[port];
758 tmp[port] = NULL; /* debugging paranoia */
7227aac4
BS		 759 ipath_free_pddata(dd, pd);
760 }
3d089098 761 kfree(tmp);
7227aac4
BS		 762}
763
764static void __devexit ipath_remove_one(struct pci_dev *pdev)
765{
766 struct ipath_devdata *dd = pci_get_drvdata(pdev);
767
768 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
769
53c1d2c9
BS		 770 /*
771 * disable the IB link early, to be sure no new packets arrive, which
772 * complicates the shutdown process
773 */
774 ipath_shutdown_device(dd);
775
3588423f
AJ		 776 flush_scheduled_work();
777
7227aac4
BS		 778 if (dd->verbs_dev)
779 ipath_unregister_ib_device(dd->verbs_dev);
780
a2acb2ff
BS		 781 ipath_diag_remove(dd);
782 ipath_user_remove(dd);
7bb206e3
BS		 783 ipathfs_remove_device(dd);
784 ipath_device_remove_group(&pdev->dev, dd);
7227aac4 785
7bb206e3
BS		 786 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
787 "unit %u\n", dd, (u32) dd->ipath_unit);
7227aac4
BS		 788
789 cleanup_device(dd);
790
791 /*
792 * turn off rcv, send, and interrupts for all ports, all drivers
793 * should also hard reset the chip here?
794 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
795 * for all versions of the driver, if they were allocated
796 */
51f65ebc
BS		 797 if (dd->ipath_irq) {
798 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
799 dd->ipath_unit, dd->ipath_irq);
800 dd->ipath_f_free_irq(dd);
7227aac4
BS		 801 } else
802 ipath_dbg("irq is 0, not doing free_irq "
803 "for unit %u\n", dd->ipath_unit);
804 /*
805 * we check for NULL here, because it's outside
806 * the kregbase check, and we need to call it
807 * after the free_irq. Thus it's possible that
808 * the function pointers were never initialized.
809 */
810 if (dd->ipath_f_cleanup)
811 /* clean up chip-specific stuff */
812 dd->ipath_f_cleanup(dd);
813
814 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
815 iounmap((volatile void __iomem *) dd->ipath_kregbase);
7bb206e3
BS		 816 pci_release_regions(pdev);
817 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
818 pci_disable_device(pdev);
819
820 ipath_free_devdata(pdev, dd);
7bb206e3
BS		 821}
822
823/* general driver use */
824DEFINE_MUTEX(ipath_mutex);
825
826static DEFINE_SPINLOCK(ipath_pioavail_lock);
827
828/**
829 * ipath_disarm_piobufs - cancel a range of PIO buffers
830 * @dd: the infinipath device
831 * @first: the first PIO buffer to cancel
832 * @cnt: the number of PIO buffers to cancel
833 *
834 * cancel a range of PIO buffers, used when they might be armed, but
835 * not triggered. Used at init to ensure buffer state, and also user
836 * process close, in case it died while writing to a PIO buffer
837 * Also after errors.
838 */
839void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
840 unsigned cnt)
841{
842 unsigned i, last = first + cnt;
e342c119 843 unsigned long flags;
7bb206e3
BS		 844
845 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
7bb206e3 846 for (i = first; i < last; i++) {
e342c119
JG		 847 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
848 /*
849 * The disarm-related bits are write-only, so it
850 * is ok to OR them in with our copy of sendctrl
851 * while we hold the lock.
852 */
7bb206e3 853 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
e342c119
JG		 854 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
855 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
856 /* can't disarm bufs back-to-back per iba7220 spec */
857 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
858 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
7bb206e3 859 }
c4b4d16e
RC		 860 /* on some older chips, update may not happen after cancel */
861 ipath_force_pio_avail_update(dd);
7bb206e3
BS		 862}
863
864/**
865 * ipath_wait_linkstate - wait for an IB link state change to occur
866 * @dd: the infinipath device
867 * @state: the state to wait for
868 * @msecs: the number of milliseconds to wait
869 *
870 * wait up to msecs milliseconds for IB link state change to occur for
871 * now, take the easy polling route. Currently used only by
34b2aafe 872 * ipath_set_linkstate. Returns 0 if state reached, otherwise
7bb206e3
BS		 873 * -ETIMEDOUT state can have multiple states set, for any of several
874 * transitions.
875 */
140277e9 876int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
7bb206e3 877{
0fd41363
BS		 878 dd->ipath_state_wanted = state;
879 wait_event_interruptible_timeout(ipath_state_wait,
7bb206e3
BS		 880 (dd->ipath_flags & state),
881 msecs_to_jiffies(msecs));
0fd41363 882 dd->ipath_state_wanted = 0;
7bb206e3
BS		 883
884 if (!(dd->ipath_flags & state)) {
885 u64 val;
0fd41363
BS		 886 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
887 " ms\n",
7bb206e3
BS		 888 /* test INIT ahead of DOWN, both can be set */
889 (state & IPATH_LINKINIT) ? "INIT" :
890 ((state & IPATH_LINKDOWN) ? "DOWN" :
891 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
892 msecs);
893 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
894 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
895 (unsigned long long) ipath_read_kreg64(
896 dd, dd->ipath_kregs->kr_ibcctrl),
897 (unsigned long long) val,
bb917144 898 ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
7bb206e3
BS		 899 }
900 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
901}
902
124b4dcb
DO		 903static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err,
904 char *buf, size_t blen)
905{
906 static const struct {
907 ipath_err_t err;
908 const char *msg;
909 } errs[] = {
910 { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" },
911 { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" },
912 { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" },
913 { INFINIPATH_E_SDMABASE, "SDmaBase" },
914 { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" },
915 { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" },
916 { INFINIPATH_E_SDMADWEN, "SDmaDwEn" },
917 { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" },
918 { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" },
919 { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" },
920 { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" },
921 { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" },
922 };
923 int i;
924 int expected;
925 size_t bidx = 0;
926
927 for (i = 0; i < ARRAY_SIZE(errs); i++) {
928 expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 :
929 test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
930 if ((err & errs[i].err) && !expected)
931 bidx += snprintf(buf + bidx, blen - bidx,
932 "%s ", errs[i].msg);
933 }
934}
935
8ec1077b
BS		 936/*
937 * Decode the error status into strings, deciding whether to always
938 * print * it or not depending on "normal packet errors" vs everything
939 * else. Return 1 if "real" errors, otherwise 0 if only packet
940 * errors, so caller can decide what to print with the string.
941 */
124b4dcb
DO		 942int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
943 ipath_err_t err)
7bb206e3 944{
8ec1077b 945 int iserr = 1;
7bb206e3 946 *buf = '\0';
8ec1077b
BS		 947 if (err & INFINIPATH_E_PKTERRS) {
948 if (!(err & ~INFINIPATH_E_PKTERRS))
949 iserr = 0; // if only packet errors.
950 if (ipath_debug & __IPATH_ERRPKTDBG) {
951 if (err & INFINIPATH_E_REBP)
952 strlcat(buf, "EBP ", blen);
953 if (err & INFINIPATH_E_RVCRC)
954 strlcat(buf, "VCRC ", blen);
955 if (err & INFINIPATH_E_RICRC) {
956 strlcat(buf, "CRC ", blen);
957 // clear for check below, so only once
958 err &= INFINIPATH_E_RICRC;
959 }
960 if (err & INFINIPATH_E_RSHORTPKTLEN)
961 strlcat(buf, "rshortpktlen ", blen);
962 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
963 strlcat(buf, "sdroppeddatapkt ", blen);
964 if (err & INFINIPATH_E_SPKTLEN)
965 strlcat(buf, "spktlen ", blen);
966 }
967 if ((err & INFINIPATH_E_RICRC) &&
968 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
969 strlcat(buf, "CRC ", blen);
970 if (!iserr)
971 goto done;
972 }
7bb206e3
BS		 973 if (err & INFINIPATH_E_RHDRLEN)
974 strlcat(buf, "rhdrlen ", blen);
975 if (err & INFINIPATH_E_RBADTID)
976 strlcat(buf, "rbadtid ", blen);
977 if (err & INFINIPATH_E_RBADVERSION)
978 strlcat(buf, "rbadversion ", blen);
979 if (err & INFINIPATH_E_RHDR)
980 strlcat(buf, "rhdr ", blen);
bb917144
AJ		 981 if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
982 strlcat(buf, "sendspecialtrigger ", blen);
7bb206e3
BS		 983 if (err & INFINIPATH_E_RLONGPKTLEN)
984 strlcat(buf, "rlongpktlen ", blen);
7bb206e3
BS		 985 if (err & INFINIPATH_E_RMAXPKTLEN)
986 strlcat(buf, "rmaxpktlen ", blen);
987 if (err & INFINIPATH_E_RMINPKTLEN)
988 strlcat(buf, "rminpktlen ", blen);
8ec1077b
BS		 989 if (err & INFINIPATH_E_SMINPKTLEN)
990 strlcat(buf, "sminpktlen ", blen);
7bb206e3
BS		 991 if (err & INFINIPATH_E_RFORMATERR)
992 strlcat(buf, "rformaterr ", blen);
993 if (err & INFINIPATH_E_RUNSUPVL)
994 strlcat(buf, "runsupvl ", blen);
995 if (err & INFINIPATH_E_RUNEXPCHAR)
996 strlcat(buf, "runexpchar ", blen);
997 if (err & INFINIPATH_E_RIBFLOW)
998 strlcat(buf, "ribflow ", blen);
7bb206e3
BS		 999 if (err & INFINIPATH_E_SUNDERRUN)
1000 strlcat(buf, "sunderrun ", blen);
1001 if (err & INFINIPATH_E_SPIOARMLAUNCH)
1002 strlcat(buf, "spioarmlaunch ", blen);
1003 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
1004 strlcat(buf, "sunexperrpktnum ", blen);
7bb206e3
BS		 1005 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
1006 strlcat(buf, "sdroppedsmppkt ", blen);
1007 if (err & INFINIPATH_E_SMAXPKTLEN)
1008 strlcat(buf, "smaxpktlen ", blen);
7bb206e3
BS		 1009 if (err & INFINIPATH_E_SUNSUPVL)
1010 strlcat(buf, "sunsupVL ", blen);
7bb206e3
BS		 1011 if (err & INFINIPATH_E_INVALIDADDR)
1012 strlcat(buf, "invalidaddr ", blen);
7bb206e3
BS		 1013 if (err & INFINIPATH_E_RRCVEGRFULL)
1014 strlcat(buf, "rcvegrfull ", blen);
1015 if (err & INFINIPATH_E_RRCVHDRFULL)
1016 strlcat(buf, "rcvhdrfull ", blen);
1017 if (err & INFINIPATH_E_IBSTATUSCHANGED)
1018 strlcat(buf, "ibcstatuschg ", blen);
1019 if (err & INFINIPATH_E_RIBLOSTLINK)
1020 strlcat(buf, "riblostlink ", blen);
1021 if (err & INFINIPATH_E_HARDWARE)
1022 strlcat(buf, "hardware ", blen);
1023 if (err & INFINIPATH_E_RESET)
1024 strlcat(buf, "reset ", blen);
124b4dcb
DO		 1025 if (err & INFINIPATH_E_SDMAERRS)
1026 decode_sdma_errs(dd, err, buf, blen);
bb917144
AJ		 1027 if (err & INFINIPATH_E_INVALIDEEPCMD)
1028 strlcat(buf, "invalideepromcmd ", blen);
8ec1077b
BS		 1029done:
1030 return iserr;
7bb206e3
BS		 1031}
1032
1033/**
1034 * get_rhf_errstring - decode RHF errors
1035 * @err: the err number
1036 * @msg: the output buffer
1037 * @len: the length of the output buffer
1038 *
1039 * only used one place now, may want more later
1040 */
1041static void get_rhf_errstring(u32 err, char *msg, size_t len)
1042{
1043 /* if no errors, and so don't need to check what's first */
1044 *msg = '\0';
1045
1046 if (err & INFINIPATH_RHF_H_ICRCERR)
1047 strlcat(msg, "icrcerr ", len);
1048 if (err & INFINIPATH_RHF_H_VCRCERR)
1049 strlcat(msg, "vcrcerr ", len);
1050 if (err & INFINIPATH_RHF_H_PARITYERR)
1051 strlcat(msg, "parityerr ", len);
1052 if (err & INFINIPATH_RHF_H_LENERR)
1053 strlcat(msg, "lenerr ", len);
1054 if (err & INFINIPATH_RHF_H_MTUERR)
1055 strlcat(msg, "mtuerr ", len);
1056 if (err & INFINIPATH_RHF_H_IHDRERR)
1057 /* infinipath hdr checksum error */
1058 strlcat(msg, "ipathhdrerr ", len);
1059 if (err & INFINIPATH_RHF_H_TIDERR)
1060 strlcat(msg, "tiderr ", len);
1061 if (err & INFINIPATH_RHF_H_MKERR)
1062 /* bad port, offset, etc. */
1063 strlcat(msg, "invalid ipathhdr ", len);
1064 if (err & INFINIPATH_RHF_H_IBERR)
1065 strlcat(msg, "iberr ", len);
1066 if (err & INFINIPATH_RHF_L_SWA)
1067 strlcat(msg, "swA ", len);
1068 if (err & INFINIPATH_RHF_L_SWB)
1069 strlcat(msg, "swB ", len);
1070}
1071
1072/**
1073 * ipath_get_egrbuf - get an eager buffer
1074 * @dd: the infinipath device
1075 * @bufnum: the eager buffer to get
7bb206e3
BS		 1076 *
1077 * must only be called if ipath_pd[port] is known to be allocated
1078 */
d65708f3 1079static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
7bb206e3 1080{
1fd3b40f
BS		 1081 return dd->ipath_port0_skbinfo ?
1082 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
7bb206e3
BS		 1083}
1084
1085/**
1086 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1087 * @dd: the infinipath device
1088 * @gfp_mask: the sk_buff SFP mask
1089 */
1090struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1091 gfp_t gfp_mask)
1092{
1093 struct sk_buff *skb;
1094 u32 len;
1095
1096 /*
1097 * Only fully supported way to handle this is to allocate lots
1098 * extra, align as needed, and then do skb_reserve(). That wastes
1099 * a lot of memory... I'll have to hack this into infinipath_copy
1100 * also.
1101 */
1102
1103 /*
1fd3b40f
BS		 1104 * We need 2 extra bytes for ipath_ether data sent in the
1105 * key header. In order to keep everything dword aligned,
1106 * we'll reserve 4 bytes.
7bb206e3 1107 */
1fd3b40f
BS		 1108 len = dd->ipath_ibmaxlen + 4;
1109
7bb206e3 1110 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1fd3b40f 1111 /* We need a 2KB multiple alignment, and there is no way
7bb206e3
BS		 1112 * to do it except to allocate extra and then skb_reserve
1113 * enough to bring it up to the right alignment.
1114 */
1fd3b40f 1115 len += 2047;
7bb206e3 1116 }
1fd3b40f 1117
7bb206e3
BS		 1118 skb = __dev_alloc_skb(len, gfp_mask);
1119 if (!skb) {
1120 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1121 len);
1122 goto bail;
1123 }
1fd3b40f
BS		 1124
1125 skb_reserve(skb, 4);
1126
7bb206e3 1127 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1fd3b40f 1128 u32 una = (unsigned long)skb->data & 2047;
7bb206e3 1129 if (una)
1fd3b40f
BS		 1130 skb_reserve(skb, 2048 - una);
1131 }
7bb206e3
BS		 1132
1133bail:
1134 return skb;
1135}
1136
3d37b9e2
RC		 1137static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1138 u32 eflags,
1139 u32 l,
1140 u32 etail,
9355fb6a
RC		 1141 __le32 *rhf_addr,
1142 struct ipath_message_header *hdr)
3d37b9e2
RC		 1143{
1144 char emsg[128];
3d37b9e2
RC		 1145
1146 get_rhf_errstring(eflags, emsg, sizeof emsg);
3d37b9e2
RC		 1147 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1148 "tlen=%x opcode=%x egridx=%x: %s\n",
1149 eflags, l,
9355fb6a
RC		 1150 ipath_hdrget_rcv_type(rhf_addr),
1151 ipath_hdrget_length_in_bytes(rhf_addr),
3d37b9e2
RC		 1152 be32_to_cpu(hdr->bth[0]) >> 24,
1153 etail, emsg);
1154
1155 /* Count local link integrity errors. */
1156 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1157 u8 n = (dd->ipath_ibcctrl >>
1158 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1159 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1160
1161 if (++dd->ipath_lli_counter > n) {
1162 dd->ipath_lli_counter = 0;
1163 dd->ipath_lli_errors++;
1164 }
1165 }
1166}
1167
7bb206e3
BS		 1168/*
1169 * ipath_kreceive - receive a packet
c59a80ac 1170 * @pd: the infinipath port
7bb206e3
BS		 1171 *
1172 * called from interrupt handler for errors or receive interrupt
1173 */
c59a80ac 1174void ipath_kreceive(struct ipath_portdata *pd)
7bb206e3 1175{
c59a80ac 1176 struct ipath_devdata *dd = pd->port_dd;
9355fb6a 1177 __le32 *rhf_addr;
7bb206e3
BS		 1178 void *ebuf;
1179 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1180 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1181 u32 etail = -1, l, hdrqtail;
27b678dd 1182 struct ipath_message_header *hdr;
9355fb6a 1183 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
7bb206e3 1184 static u64 totcalls; /* stats, may eventually remove */
9355fb6a 1185 int last;
7bb206e3 1186
c59a80ac 1187 l = pd->port_head;
9355fb6a
RC		 1188 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1189 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1190 u32 seq = ipath_hdrget_seq(rhf_addr);
7bb206e3 1191
9355fb6a
RC		 1192 if (seq != pd->port_seq_cnt)
1193 goto bail;
1194 hdrqtail = 0;
1195 } else {
1196 hdrqtail = ipath_get_rcvhdrtail(pd);
1197 if (l == hdrqtail)
1198 goto bail;
1199 smp_rmb();
1200 }
7bb206e3 1201
9355fb6a 1202reloop:
2889d1ef 1203 for (last = 0, i = 1; !last; i += !last) {
9355fb6a
RC		 1204 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1205 eflags = ipath_hdrget_err_flags(rhf_addr);
1206 etype = ipath_hdrget_rcv_type(rhf_addr);
7bb206e3 1207 /* total length */
9355fb6a 1208 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
7bb206e3 1209 ebuf = NULL;
9355fb6a
RC		 1210 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1211 ipath_hdrget_use_egr_buf(rhf_addr) :
1212 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
7bb206e3 1213 /*
9355fb6a 1214 * It turns out that the chip uses an eager buffer
7bb206e3
BS		 1215 * for all non-expected packets, whether it "needs"
1216 * one or not. So always get the index, but don't
1217 * set ebuf (so we try to copy data) unless the
1218 * length requires it.
1219 */
9355fb6a
RC		 1220 etail = ipath_hdrget_index(rhf_addr);
1221 updegr = 1;
7bb206e3
BS		 1222 if (tlen > sizeof(*hdr) ||
1223 etype == RCVHQ_RCV_TYPE_NON_KD)
d65708f3 1224 ebuf = ipath_get_egrbuf(dd, etail);
7bb206e3
BS		 1225 }
1226
1227 /*
1228 * both tiderr and ipathhdrerr are set for all plain IB
1229 * packets; only ipathhdrerr should be set.
1230 */
1231
9355fb6a
RC		 1232 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1233 etype != RCVHQ_RCV_TYPE_ERROR &&
1234 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1235 IPS_PROTO_VERSION)
7bb206e3
BS		 1236 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1237 "%x\n", etype);
7bb206e3 1238
3d37b9e2 1239 if (unlikely(eflags))
9355fb6a 1240 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
3d37b9e2 1241 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
9355fb6a 1242 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
34b2aafe
BS		 1243 if (dd->ipath_lli_counter)
1244 dd->ipath_lli_counter--;
9355fb6a
RC		 1245 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1246 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1247 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
34b2aafe
BS		 1248 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1249 "qp=%x), len %x; ignored\n",
9355fb6a 1250 etype, opcode, qp, tlen);
7bb206e3
BS		 1251 }
1252 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1253 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
9355fb6a 1254 be32_to_cpu(hdr->bth[0]) >> 24);
3d37b9e2 1255 else {
7bb206e3 1256 /*
9e2ef36b 1257 * error packet, type of error unknown.
7bb206e3
BS		 1258 * Probably type 3, but we don't know, so don't
1259 * even try to print the opcode, etc.
9355fb6a
RC		 1260 * Usually caused by a "bad packet", that has no
1261 * BTH, when the LRH says it should.
7bb206e3 1262 */
9355fb6a
RC		 1263 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1264 " %x, len %x hdrq+%x rhf: %Lx\n",
70117b9e 1265 etail, tlen, l, (unsigned long long)
9355fb6a
RC		 1266 le64_to_cpu(*(__le64 *) rhf_addr));
1267 if (ipath_debug & __IPATH_ERRPKTDBG) {
1268 u32 j, *d, dw = rsize-2;
1269 if (rsize > (tlen>>2))
1270 dw = tlen>>2;
1271 d = (u32 *)hdr;
1272 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1273 dw);
1274 for (j = 0; j < dw; j++)
1275 printk(KERN_DEBUG "%8x%s", d[j],
1276 (j%8) == 7 ? "\n" : " ");
1277 printk(KERN_DEBUG ".\n");
1278 }
7bb206e3
BS		 1279 }
1280 l += rsize;
1281 if (l >= maxcnt)
1282 l = 0;
9355fb6a
RC		 1283 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1284 l + dd->ipath_rhf_offset;
1285 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1286 u32 seq = ipath_hdrget_seq(rhf_addr);
1287
1288 if (++pd->port_seq_cnt > 13)
1289 pd->port_seq_cnt = 1;
1290 if (seq != pd->port_seq_cnt)
1291 last = 1;
1292 } else if (l == hdrqtail)
1293 last = 1;
7bb206e3 1294 /*
f5f99929
BS		 1295 * update head regs on last packet, and every 16 packets.
1296 * Reduce bus traffic, while still trying to prevent
1297 * rcvhdrq overflows, for when the queue is nearly full
7bb206e3 1298 */
9355fb6a
RC		 1299 if (last || !(i & 0xf)) {
1300 u64 lval = l;
1301
1302 /* request IBA6120 and 7220 interrupt only on last */
1303 if (last)
1304 lval |= dd->ipath_rhdrhead_intr_off;
1305 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1306 pd->port_port);
f5f99929 1307 if (updegr) {
8c641d4b 1308 ipath_write_ureg(dd, ur_rcvegrindexhead,
9355fb6a 1309 etail, pd->port_port);
f5f99929
BS		 1310 updegr = 0;
1311 }
1312 }
7bb206e3
BS		 1313 }
1314
9355fb6a
RC		 1315 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1316 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
525d0ca1 1317 /* IBA6110 workaround; we can have a race clearing chip
57abad25
BS		 1318 * interrupt with another interrupt about to be delivered,
1319 * and can clear it before it is delivered on the GPIO
1320 * workaround. By doing the extra check here for the
1321 * in-memory tail register updating while we were doing
1322 * earlier packets, we "almost" guarantee we have covered
1323 * that case.
1324 */
c59a80ac 1325 u32 hqtail = ipath_get_rcvhdrtail(pd);
57abad25
BS		 1326 if (hqtail != hdrqtail) {
1327 hdrqtail = hqtail;
1328 reloop = 1; /* loop 1 extra time at most */
1329 goto reloop;
1330 }
1331 }
1332
7bb206e3
BS		 1333 pkttot += i;
1334
c59a80ac 1335 pd->port_head = l;
7bb206e3 1336
7bb206e3
BS		 1337 if (pkttot > ipath_stats.sps_maxpkts_call)
1338 ipath_stats.sps_maxpkts_call = pkttot;
1339 ipath_stats.sps_port0pkts += pkttot;
1340 ipath_stats.sps_avgpkts_call =
1341 ipath_stats.sps_port0pkts / ++totcalls;
1342
7bb206e3
BS		 1343bail:;
1344}
1345
1346/**
1347 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1348 * @dd: the infinipath device
1349 *
1350 * called whenever our local copy indicates we have run out of send buffers
1351 * NOTE: This can be called from interrupt context by some code
1352 * and from non-interrupt context by ipath_getpiobuf().
1353 */
1354
1355static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1356{
1357 unsigned long flags;
1358 int i;
1359 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1360
1361 /* If the generation (check) bits have changed, then we update the
1362 * busy bit for the corresponding PIO buffer. This algorithm will
1363 * modify positions to the value they already have in some cases
1364 * (i.e., no change), but it's faster than changing only the bits
1365 * that have changed.
1366 *
1367 * We would like to do this atomicly, to avoid spinlocks in the
1368 * critical send path, but that's not really possible, given the
1369 * type of changes, and that this routine could be called on
1370 * multiple cpu's simultaneously, so we lock in this routine only,
1371 * to avoid conflicting updates; all we change is the shadow, and
1372 * it's a single 64 bit memory location, so by definition the update
1373 * is atomic in terms of what other cpu's can see in testing the
1374 * bits. The spin_lock overhead isn't too bad, since it only
1375 * happens when all buffers are in use, so only cpu overhead, not
1376 * latency or bandwidth is affected.
1377 */
7bb206e3
BS		 1378 if (!dd->ipath_pioavailregs_dma) {
1379 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1380 return;
1381 }
1382 if (ipath_debug & __IPATH_VERBDBG) {
1383 /* only if packet debug and verbose */
1384 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1385 unsigned long *shadow = dd->ipath_pioavailshadow;
1386
1387 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1388 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1389 "s3=%lx\n",
1390 (unsigned long long) le64_to_cpu(dma[0]),
1391 shadow[0],
1392 (unsigned long long) le64_to_cpu(dma[1]),
1393 shadow[1],
1394 (unsigned long long) le64_to_cpu(dma[2]),
1395 shadow[2],
1396 (unsigned long long) le64_to_cpu(dma[3]),
1397 shadow[3]);
1398 if (piobregs > 4)
1399 ipath_cdbg(
1400 PKT, "2nd group, dma4=%llx shad4=%lx, "
1401 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1402 "d7=%llx s7=%lx\n",
1403 (unsigned long long) le64_to_cpu(dma[4]),
1404 shadow[4],
1405 (unsigned long long) le64_to_cpu(dma[5]),
1406 shadow[5],
1407 (unsigned long long) le64_to_cpu(dma[6]),
1408 shadow[6],
1409 (unsigned long long) le64_to_cpu(dma[7]),
1410 shadow[7]);
1411 }
1412 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1413 for (i = 0; i < piobregs; i++) {
1414 u64 pchbusy, pchg, piov, pnew;
1415 /*
1416 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1417 */
4ea61b54
RC		 1418 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1419 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1420 else
7bb206e3 1421 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
c4b4d16e 1422 pchg = dd->ipath_pioavailkernel[i] &
7bb206e3
BS		 1423 ~(dd->ipath_pioavailshadow[i] ^ piov);
1424 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1425 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1426 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1427 pnew |= piov & pchbusy;
1428 dd->ipath_pioavailshadow[i] = pnew;
1429 }
1430 }
1431 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1432}
1433
e2ab41ca
DO		 1434/*
1435 * used to force update of pioavailshadow if we can't get a pio buffer.
1436 * Needed primarily due to exitting freeze mode after recovering
1437 * from errors. Done lazily, because it's safer (known to not
1438 * be writing pio buffers).
1439 */
1440static void ipath_reset_availshadow(struct ipath_devdata *dd)
1441{
1442 int i, im;
1443 unsigned long flags;
1444
1445 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1446 for (i = 0; i < dd->ipath_pioavregs; i++) {
1447 u64 val, oldval;
1448 /* deal with 6110 chip bug on high register #s */
1449 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1450 i ^ 1 : i;
1451 val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
1452 /*
1453 * busy out the buffers not in the kernel avail list,
1454 * without changing the generation bits.
1455 */
1456 oldval = dd->ipath_pioavailshadow[i];
1457 dd->ipath_pioavailshadow[i] = val |
1458 ((~dd->ipath_pioavailkernel[i] <<
1459 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
1460 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
1461 if (oldval != dd->ipath_pioavailshadow[i])
1462 ipath_dbg("shadow[%d] was %Lx, now %lx\n",
70117b9e
AB		 1463 i, (unsigned long long) oldval,
1464 dd->ipath_pioavailshadow[i]);
e2ab41ca
DO		 1465 }
1466 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1467}
1468
7bb206e3
BS		 1469/**
1470 * ipath_setrcvhdrsize - set the receive header size
1471 * @dd: the infinipath device
1472 * @rhdrsize: the receive header size
1473 *
1474 * called from user init code, and also layered driver init
1475 */
1476int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1477{
1478 int ret = 0;
1479
1480 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1481 if (dd->ipath_rcvhdrsize != rhdrsize) {
1482 dev_info(&dd->pcidev->dev,
1483 "Error: can't set protocol header "
1484 "size %u, already %u\n",
1485 rhdrsize, dd->ipath_rcvhdrsize);
1486 ret = -EAGAIN;
1487 } else
1488 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1489 "size %u\n", dd->ipath_rcvhdrsize);
1490 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1491 (sizeof(u64) / sizeof(u32)))) {
1492 ipath_dbg("Error: can't set protocol header size %u "
1493 "(> max %u)\n", rhdrsize,
1494 dd->ipath_rcvhdrentsize -
1495 (u32) (sizeof(u64) / sizeof(u32)));
1496 ret = -EOVERFLOW;
1497 } else {
1498 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1499 dd->ipath_rcvhdrsize = rhdrsize;
1500 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1501 dd->ipath_rcvhdrsize);
1502 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1503 dd->ipath_rcvhdrsize);
1504 }
1505 return ret;
1506}
1507
c4b4d16e
RC		 1508/*
1509 * debugging code and stats updates if no pio buffers available.
1510 */
1511static noinline void no_pio_bufs(struct ipath_devdata *dd)
1512{
1513 unsigned long *shadow = dd->ipath_pioavailshadow;
1514 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1515
1516 dd->ipath_upd_pio_shadow = 1;
1517
1518 /*
1519 * not atomic, but if we lose a stat count in a while, that's OK
1520 */
1521 ipath_stats.sps_nopiobufs++;
1522 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
e2ab41ca
DO		 1523 ipath_force_pio_avail_update(dd); /* at start */
1524 ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
1525 "%llx %llx %llx %llx\n"
1526 "ipath shadow: %lx %lx %lx %lx\n",
c4b4d16e 1527 dd->ipath_consec_nopiobuf,
e2ab41ca 1528 (unsigned long)get_cycles(),
c4b4d16e
RC		 1529 (unsigned long long) le64_to_cpu(dma[0]),
1530 (unsigned long long) le64_to_cpu(dma[1]),
1531 (unsigned long long) le64_to_cpu(dma[2]),
1532 (unsigned long long) le64_to_cpu(dma[3]),
1533 shadow[0], shadow[1], shadow[2], shadow[3]);
1534 /*
1535 * 4 buffers per byte, 4 registers above, cover rest
1536 * below
1537 */
1538 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1539 (sizeof(shadow[0]) * 4 * 4))
e2ab41ca
DO		 1540 ipath_dbg("2nd group: dmacopy: "
1541 "%llx %llx %llx %llx\n"
1542 "ipath shadow: %lx %lx %lx %lx\n",
c4b4d16e
RC		 1543 (unsigned long long)le64_to_cpu(dma[4]),
1544 (unsigned long long)le64_to_cpu(dma[5]),
1545 (unsigned long long)le64_to_cpu(dma[6]),
1546 (unsigned long long)le64_to_cpu(dma[7]),
e2ab41ca
DO		 1547 shadow[4], shadow[5], shadow[6], shadow[7]);
1548
1549 /* at end, so update likely happened */
1550 ipath_reset_availshadow(dd);
c4b4d16e
RC		 1551 }
1552}
1553
1554/*
1555 * common code for normal driver pio buffer allocation, and reserved
1556 * allocation.
7bb206e3
BS		 1557 *
1558 * do appropriate marking as busy, etc.
1559 * returns buffer number if one found (>=0), negative number is error.
7bb206e3 1560 */
c4b4d16e
RC		 1561static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1562 u32 *pbufnum, u32 first, u32 last, u32 firsti)
7bb206e3 1563{
c4b4d16e
RC		 1564 int i, j, updated = 0;
1565 unsigned piobcnt;
7bb206e3
BS		 1566 unsigned long flags;
1567 unsigned long *shadow = dd->ipath_pioavailshadow;
1568 u32 __iomem *buf;
1569
c4b4d16e 1570 piobcnt = last - first;
7bb206e3
BS		 1571 if (dd->ipath_upd_pio_shadow) {
1572 /*
1573 * Minor optimization. If we had no buffers on last call,
1574 * start out by doing the update; continue and do scan even
1575 * if no buffers were updated, to be paranoid
1576 */
1577 ipath_update_pio_bufs(dd);
c4b4d16e
RC		 1578 updated++;
1579 i = first;
7bb206e3 1580 } else
c4b4d16e 1581 i = firsti;
7bb206e3
BS		 1582rescan:
1583 /*
1584 * while test_and_set_bit() is atomic, we do that and then the
1585 * change_bit(), and the pair is not. See if this is the cause
1586 * of the remaining armlaunch errors.
1587 */
1588 spin_lock_irqsave(&ipath_pioavail_lock, flags);
c4b4d16e
RC		 1589 for (j = 0; j < piobcnt; j++, i++) {
1590 if (i >= last)
1591 i = first;
1592 if (__test_and_set_bit((2 * i) + 1, shadow))
7bb206e3
BS		 1593 continue;
1594 /* flip generation bit */
c4b4d16e 1595 __change_bit(2 * i, shadow);
7bb206e3
BS		 1596 break;
1597 }
1598 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1599
c4b4d16e 1600 if (j == piobcnt) {
7bb206e3 1601 if (!updated) {
c4b4d16e
RC		 1602 /*
1603 * first time through; shadow exhausted, but may be
1604 * buffers available, try an update and then rescan.
1605 */
7bb206e3 1606 ipath_update_pio_bufs(dd);
c4b4d16e
RC		 1607 updated++;
1608 i = first;
7bb206e3 1609 goto rescan;
c4b4d16e
RC		 1610 } else if (updated == 1 && piobcnt <=
1611 ((dd->ipath_sendctrl
1612 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1613 INFINIPATH_S_UPDTHRESH_MASK)) {
7bb206e3 1614 /*
c4b4d16e
RC		 1615 * for chips supporting and using the update
1616 * threshold we need to force an update of the
1617 * in-memory copy if the count is less than the
1618 * thershold, then check one more time.
7bb206e3 1619 */
c4b4d16e
RC		 1620 ipath_force_pio_avail_update(dd);
1621 ipath_update_pio_bufs(dd);
1622 updated++;
1623 i = first;
1624 goto rescan;
7bb206e3 1625 }
c4b4d16e
RC		 1626
1627 no_pio_bufs(dd);
7bb206e3 1628 buf = NULL;
c4b4d16e
RC		 1629 } else {
1630 if (i < dd->ipath_piobcnt2k)
1631 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1632 i * dd->ipath_palign);
1633 else
1634 buf = (u32 __iomem *)
1635 (dd->ipath_pio4kbase +
1636 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1637 if (pbufnum)
1638 *pbufnum = i;
7bb206e3
BS		 1639 }
1640
c4b4d16e
RC		 1641 return buf;
1642}
7bb206e3 1643
c4b4d16e
RC		 1644/**
1645 * ipath_getpiobuf - find an available pio buffer
1646 * @dd: the infinipath device
1647 * @plen: the size of the PIO buffer needed in 32-bit words
1648 * @pbufnum: the buffer number is placed here
1649 */
1650u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1651{
1652 u32 __iomem *buf;
1653 u32 pnum, nbufs;
1654 u32 first, lasti;
1655
1656 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1657 first = dd->ipath_piobcnt2k;
1658 lasti = dd->ipath_lastpioindexl;
1659 } else {
1660 first = 0;
1661 lasti = dd->ipath_lastpioindex;
1662 }
1663 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1664 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1665
1666 if (buf) {
1667 /*
1668 * Set next starting place. It's just an optimization,
1669 * it doesn't matter who wins on this, so no locking
1670 */
1671 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1672 dd->ipath_lastpioindexl = pnum + 1;
1673 else
1674 dd->ipath_lastpioindex = pnum + 1;
1675 if (dd->ipath_upd_pio_shadow)
1676 dd->ipath_upd_pio_shadow = 0;
1677 if (dd->ipath_consec_nopiobuf)
1678 dd->ipath_consec_nopiobuf = 0;
1679 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1680 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1681 if (pbufnum)
1682 *pbufnum = pnum;
1683
1684 }
7bb206e3
BS		 1685 return buf;
1686}
1687
c4b4d16e
RC		 1688/**
1689 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1690 * @dd: the infinipath device
1691 * @start: the starting send buffer number
1692 * @len: the number of send buffers
1693 * @avail: true if the buffers are available for kernel use, false otherwise
1694 */
1695void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1696 unsigned len, int avail)
1697{
1698 unsigned long flags;
e2ab41ca 1699 unsigned end, cnt = 0, next;
c4b4d16e
RC		 1700
1701 /* There are two bits per send buffer (busy and generation) */
1702 start *= 2;
e2ab41ca 1703 end = start + len * 2;
c4b4d16e 1704
c4b4d16e 1705 spin_lock_irqsave(&ipath_pioavail_lock, flags);
e2ab41ca 1706 /* Set or clear the busy bit in the shadow. */
c4b4d16e
RC		 1707 while (start < end) {
1708 if (avail) {
e2ab41ca
DO		 1709 unsigned long dma;
1710 int i, im;
1711 /*
1712 * the BUSY bit will never be set, because we disarm
1713 * the user buffers before we hand them back to the
1714 * kernel. We do have to make sure the generation
1715 * bit is set correctly in shadow, since it could
1716 * have changed many times while allocated to user.
1717 * We can't use the bitmap functions on the full
1718 * dma array because it is always little-endian, so
1719 * we have to flip to host-order first.
1720 * BITS_PER_LONG is slightly wrong, since it's
1721 * always 64 bits per register in chip...
1722 * We only work on 64 bit kernels, so that's OK.
1723 */
1724 /* deal with 6110 chip bug on high register #s */
1725 i = start / BITS_PER_LONG;
1726 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1727 i ^ 1 : i;
1728 __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
1729 + start, dd->ipath_pioavailshadow);
1730 dma = (unsigned long) le64_to_cpu(
1731 dd->ipath_pioavailregs_dma[im]);
1732 if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1733 + start) % BITS_PER_LONG, &dma))
1734 __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1735 + start, dd->ipath_pioavailshadow);
1736 else
1737 __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1738 + start, dd->ipath_pioavailshadow);
c4b4d16e
RC		 1739 __set_bit(start, dd->ipath_pioavailkernel);
1740 } else {
1741 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1742 dd->ipath_pioavailshadow);
1743 __clear_bit(start, dd->ipath_pioavailkernel);
1744 }
1745 start += 2;
1746 }
e2ab41ca
DO		 1747
1748 if (dd->ipath_pioupd_thresh) {
1749 end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1750 next = find_first_bit(dd->ipath_pioavailkernel, end);
1751 while (next < end) {
1752 cnt++;
1753 next = find_next_bit(dd->ipath_pioavailkernel, end,
1754 next + 1);
1755 }
1756 }
c4b4d16e 1757 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
e2ab41ca
DO		 1758
1759 /*
1760 * When moving buffers from kernel to user, if number assigned to
1761 * the user is less than the pio update threshold, and threshold
1762 * is supported (cnt was computed > 0), drop the update threshold
1763 * so we update at least once per allocated number of buffers.
1764 * In any case, if the kernel buffers are less than the threshold,
1765 * drop the threshold. We don't bother increasing it, having once
1766 * decreased it, since it would typically just cycle back and forth.
1767 * If we don't decrease below buffers in use, we can wait a long
1768 * time for an update, until some other context uses PIO buffers.
1769 */
1770 if (!avail && len < cnt)
1771 cnt = len;
1772 if (cnt < dd->ipath_pioupd_thresh) {
1773 dd->ipath_pioupd_thresh = cnt;
1774 ipath_dbg("Decreased pio update threshold to %u\n",
1775 dd->ipath_pioupd_thresh);
1776 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1777 dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
1778 << INFINIPATH_S_UPDTHRESH_SHIFT);
1779 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
1780 << INFINIPATH_S_UPDTHRESH_SHIFT;
1781 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1782 dd->ipath_sendctrl);
1783 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1784 }
c4b4d16e
RC		 1785}
1786
7bb206e3
BS		 1787/**
1788 * ipath_create_rcvhdrq - create a receive header queue
1789 * @dd: the infinipath device
1790 * @pd: the port data
1791 *
f37bda92
BS		 1792 * this must be contiguous memory (from an i/o perspective), and must be
1793 * DMA'able (which means for some systems, it will go through an IOMMU,
1794 * or be forced into a low address range).
7bb206e3
BS		 1795 */
1796int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1797 struct ipath_portdata *pd)
1798{
f37bda92 1799 int ret = 0;
7bb206e3 1800
7bb206e3 1801 if (!pd->port_rcvhdrq) {
f37bda92 1802 dma_addr_t phys_hdrqtail;
7bb206e3 1803 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
f37bda92
BS		 1804 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1805 sizeof(u32), PAGE_SIZE);
7bb206e3
BS		 1806
1807 pd->port_rcvhdrq = dma_alloc_coherent(
1808 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1809 gfp_flags);
1810
1811 if (!pd->port_rcvhdrq) {
1812 ipath_dev_err(dd, "attempt to allocate %d bytes "
1813 "for port %u rcvhdrq failed\n",
1814 amt, pd->port_port);
1815 ret = -ENOMEM;
1816 goto bail;
1817 }
9355fb6a
RC		 1818
1819 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1820 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1821 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1822 GFP_KERNEL);
1823 if (!pd->port_rcvhdrtail_kvaddr) {
1824 ipath_dev_err(dd, "attempt to allocate 1 page "
1825 "for port %u rcvhdrqtailaddr "
1826 "failed\n", pd->port_port);
1827 ret = -ENOMEM;
1828 dma_free_coherent(&dd->pcidev->dev, amt,
1829 pd->port_rcvhdrq,
1830 pd->port_rcvhdrq_phys);
1831 pd->port_rcvhdrq = NULL;
1832 goto bail;
1833 }
1834 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1835 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1836 "physical\n", pd->port_port,
1837 (unsigned long long) phys_hdrqtail);
f37bda92 1838 }
7bb206e3
BS		 1839
1840 pd->port_rcvhdrq_size = amt;
1841
1842 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1843 "for port %u rcvhdr Q\n",
1844 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1845 (unsigned long) pd->port_rcvhdrq_phys,
1846 (unsigned long) pd->port_rcvhdrq_size,
1847 pd->port_port);
7bb206e3 1848 }
f37bda92
BS		 1849 else
1850 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1851 "hdrtailaddr@%p %llx physical\n",
1852 pd->port_port, pd->port_rcvhdrq,
1fd3b40f
BS		 1853 (unsigned long long) pd->port_rcvhdrq_phys,
1854 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1855 pd->port_rcvhdrqtailaddr_phys);
f37bda92
BS		 1856
1857 /* clear for security and sanity on each use */
1858 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
c59a80ac
RC		 1859 if (pd->port_rcvhdrtail_kvaddr)
1860 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
7bb206e3
BS		 1861
1862 /*
1863 * tell chip each time we init it, even if we are re-using previous
f37bda92 1864 * memory (we zero the register at process close)
7bb206e3 1865 */
f37bda92
BS		 1866 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1867 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
7bb206e3
BS		 1868 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1869 pd->port_port, pd->port_rcvhdrq_phys);
1870
7bb206e3
BS		 1871bail:
1872 return ret;
1873}
1874
9380068f
DO		 1875
1876/*
1877 * Flush all sends that might be in the ready to send state, as well as any
1878 * that are in the process of being sent. Used whenever we need to be
1879 * sure the send side is idle. Cleans up all buffer state by canceling
1880 * all pio buffers, and issuing an abort, which cleans up anything in the
1881 * launch fifo. The cancel is superfluous on some chip versions, but
1882 * it's safer to always do it.
1883 * PIOAvail bits are updated by the chip as if normal send had happened.
1884 */
3810f2a8 1885void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
9380068f 1886{
124b4dcb
DO		 1887 unsigned long flags;
1888
bb917144
AJ		 1889 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1890 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1891 goto bail;
1892 }
124b4dcb
DO		 1893 /*
1894 * If we have SDMA, and it's not disabled, we have to kick off the
1895 * abort state machine, provided we aren't already aborting.
1896 * If we are in the process of aborting SDMA (!DISABLED, but ABORTING),
1897 * we skip the rest of this routine. It is already "in progress"
1898 */
1899 if (dd->ipath_flags & IPATH_HAS_SEND_DMA) {
1900 int skip_cancel;
f018c7e1 1901 unsigned long *statp = &dd->ipath_sdma_status;
124b4dcb
DO		 1902
1903 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1904 skip_cancel =
ab69b3cf
JG		 1905 test_and_set_bit(IPATH_SDMA_ABORTING, statp)
1906 && !test_bit(IPATH_SDMA_DISABLED, statp);
124b4dcb
DO		 1907 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1908 if (skip_cancel)
1909 goto bail;
1910 }
1911
9380068f 1912 ipath_dbg("Cancelling all in-progress send buffers\n");
2ba3f56e
RC		 1913
1914 /* skip armlaunch errs for a while */
1915 dd->ipath_lastcancel = jiffies + HZ / 2;
1916
9380068f 1917 /*
124b4dcb
DO		 1918 * The abort bit is auto-clearing. We also don't want pioavail
1919 * update happening during this, and we don't want any other
1920 * sends going out, so turn those off for the duration. We read
1921 * the scratch register to be sure that cancels and the abort
1922 * have taken effect in the chip. Otherwise two parts are same
1923 * as ipath_force_pio_avail_update()
9380068f 1924 */
124b4dcb
DO		 1925 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1926 dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD
1927 | INFINIPATH_S_PIOENABLE);
9380068f 1928 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
124b4dcb 1929 dd->ipath_sendctrl | INFINIPATH_S_ABORT);
9380068f 1930 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
124b4dcb
DO		 1931 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1932
1933 /* disarm all send buffers */
9380068f 1934 ipath_disarm_piobufs(dd, 0,
124b4dcb
DO		 1935 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1936
ab69b3cf
JG		 1937 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1938 set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status);
1939
124b4dcb
DO		 1940 if (restore_sendctrl) {
1941 /* else done by caller later if needed */
1942 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1943 dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD |
1944 INFINIPATH_S_PIOENABLE;
3810f2a8 1945 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
124b4dcb
DO		 1946 dd->ipath_sendctrl);
1947 /* and again, be sure all have hit the chip */
1948 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1949 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1950 }
9380068f 1951
124b4dcb
DO		 1952 if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) &&
1953 !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) &&
1954 test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) {
1955 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1956 /* only wait so long for intr */
1957 dd->ipath_sdma_abort_intr_timeout = jiffies + HZ;
1958 dd->ipath_sdma_reset_wait = 200;
124b4dcb
DO		 1959 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
1960 tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
1961 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1962 }
bb917144 1963bail:;
9380068f
DO		 1964}
1965
c4b4d16e
RC		 1966/*
1967 * Force an update of in-memory copy of the pioavail registers, when
1968 * needed for any of a variety of reasons. We read the scratch register
1969 * to make it highly likely that the update will have happened by the
1970 * time we return. If already off (as in cancel_sends above), this
1971 * routine is a nop, on the assumption that the caller will "do the
1972 * right thing".
1973 */
1974void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1975{
1976 unsigned long flags;
1977
1978 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1979 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1980 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1981 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1982 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1983 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1984 dd->ipath_sendctrl);
1985 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1986 }
1987 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1988}
1989
4330e4da
MA		 1990static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1991 int linitcmd)
7bb206e3 1992{
4330e4da 1993 u64 mod_wd;
7bb206e3 1994 static const char *what[4] = {
140277e9
RC		 1995 [0] = "NOP",
1996 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
7bb206e3
BS		 1997 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1998 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1999 };
f37bda92 2000
4330e4da
MA		 2001 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
2002 /*
2003 * If we are told to disable, note that so link-recovery
2004 * code does not attempt to bring us back up.
2005 */
2006 preempt_disable();
2007 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
2008 preempt_enable();
2009 } else if (linitcmd) {
2010 /*
2011 * Any other linkinitcmd will lead to LINKDOWN and then
2012 * to INIT (if all is well), so clear flag to let
2013 * link-recovery code attempt to bring us back up.
2014 */
2015 preempt_disable();
2016 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
2017 preempt_enable();
2018 }
2019
2020 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
2021 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
2022 ipath_cdbg(VERBOSE,
2023 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
2024 dd->ipath_unit, what[linkcmd], linitcmd,
2025 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
58411d1c 2026 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
7bb206e3
BS		 2027
2028 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
4330e4da
MA		 2029 dd->ipath_ibcctrl | mod_wd);
2030 /* read from chip so write is flushed */
2031 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
7bb206e3
BS		 2032}
2033
34b2aafe
BS		 2034int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
2035{
2036 u32 lstate;
2037 int ret;
2038
2039 switch (newstate) {
140277e9 2040 case IPATH_IB_LINKDOWN_ONLY:
4330e4da 2041 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
140277e9
RC		 2042 /* don't wait */
2043 ret = 0;
2044 goto bail;
2045
34b2aafe 2046 case IPATH_IB_LINKDOWN:
4330e4da
MA		 2047 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2048 INFINIPATH_IBCC_LINKINITCMD_POLL);
34b2aafe
BS		 2049 /* don't wait */
2050 ret = 0;
2051 goto bail;
2052
2053 case IPATH_IB_LINKDOWN_SLEEP:
4330e4da
MA		 2054 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2055 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
34b2aafe
BS		 2056 /* don't wait */
2057 ret = 0;
2058 goto bail;
2059
2060 case IPATH_IB_LINKDOWN_DISABLE:
4330e4da
MA		 2061 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2062 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
34b2aafe
BS		 2063 /* don't wait */
2064 ret = 0;
2065 goto bail;
2066
34b2aafe
BS		 2067 case IPATH_IB_LINKARM:
2068 if (dd->ipath_flags & IPATH_LINKARMED) {
2069 ret = 0;
2070 goto bail;
2071 }
2072 if (!(dd->ipath_flags &
2073 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
2074 ret = -EINVAL;
2075 goto bail;
2076 }
4330e4da
MA		 2077 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
2078
34b2aafe
BS		 2079 /*
2080 * Since the port can transition to ACTIVE by receiving
2081 * a non VL 15 packet, wait for either state.
2082 */
2083 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
2084 break;
2085
2086 case IPATH_IB_LINKACTIVE:
2087 if (dd->ipath_flags & IPATH_LINKACTIVE) {
2088 ret = 0;
2089 goto bail;
2090 }
2091 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
2092 ret = -EINVAL;
2093 goto bail;
2094 }
4330e4da 2095 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
34b2aafe
BS		 2096 lstate = IPATH_LINKACTIVE;
2097 break;
2098
946db67f
BS		 2099 case IPATH_IB_LINK_LOOPBACK:
2100 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
2101 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
2102 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2103 dd->ipath_ibcctrl);
b3e8f541
DO		 2104
2105 /* turn heartbeat off, as it causes loopback to fail */
2106 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2107 IPATH_IB_HRTBT_OFF);
2108 /* don't wait */
946db67f 2109 ret = 0;
b3e8f541 2110 goto bail;
946db67f
BS		 2111
2112 case IPATH_IB_LINK_EXTERNAL:
b3e8f541
DO		 2113 dev_info(&dd->pcidev->dev,
2114 "Disabling IB local loopback (normal)\n");
2115 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2116 IPATH_IB_HRTBT_ON);
946db67f
BS		 2117 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
2118 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2119 dd->ipath_ibcctrl);
b3e8f541 2120 /* don't wait */
946db67f 2121 ret = 0;
b3e8f541
DO		 2122 goto bail;
2123
2124 /*
2125 * Heartbeat can be explicitly enabled by the user via
2126 * "hrtbt_enable" "file", and if disabled, trying to enable here
2127 * will have no effect. Implicit changes (heartbeat off when
2128 * loopback on, and vice versa) are included to ease testing.
2129 */
2130 case IPATH_IB_LINK_HRTBT:
2131 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2132 IPATH_IB_HRTBT_ON);
2133 goto bail;
2134
2135 case IPATH_IB_LINK_NO_HRTBT:
2136 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2137 IPATH_IB_HRTBT_OFF);
2138 goto bail;
946db67f 2139
34b2aafe
BS		 2140 default:
2141 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
2142 ret = -EINVAL;
2143 goto bail;
2144 }
2145 ret = ipath_wait_linkstate(dd, lstate, 2000);
2146
2147bail:
2148 return ret;
2149}
2150
2151/**
2152 * ipath_set_mtu - set the MTU
2153 * @dd: the infinipath device
2154 * @arg: the new MTU
2155 *
2156 * we can handle "any" incoming size, the issue here is whether we
2157 * need to restrict our outgoing size. For now, we don't do any
2158 * sanity checking on this, and we don't deal with what happens to
2159 * programs that are already running when the size changes.
2160 * NOTE: changing the MTU will usually cause the IBC to go back to
124b4dcb 2161 * link INIT state...
34b2aafe
BS		 2162 */
2163int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
2164{
2165 u32 piosize;
2166 int changed = 0;
2167 int ret;
2168
2169 /*
2170 * mtu is IB data payload max. It's the largest power of 2 less
2171 * than piosize (or even larger, since it only really controls the
2172 * largest we can receive; we can send the max of the mtu and
2173 * piosize). We check that it's one of the valid IB sizes.
2174 */
2175 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
826d8010 2176 (arg != 4096 || !ipath_mtu4096)) {
34b2aafe
BS		 2177 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
2178 ret = -EINVAL;
2179 goto bail;
2180 }
2181 if (dd->ipath_ibmtu == arg) {
2182 ret = 0; /* same as current */
2183 goto bail;
2184 }
2185
2186 piosize = dd->ipath_ibmaxlen;
2187 dd->ipath_ibmtu = arg;
2188
2189 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
2190 /* Only if it's not the initial value (or reset to it) */
2191 if (piosize != dd->ipath_init_ibmaxlen) {
826d8010
DO		 2192 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
2193 piosize = dd->ipath_init_ibmaxlen;
34b2aafe
BS		 2194 dd->ipath_ibmaxlen = piosize;
2195 changed = 1;
2196 }
2197 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
2198 piosize = arg + IPATH_PIO_MAXIBHDR;
2199 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
2200 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
2201 arg);
2202 dd->ipath_ibmaxlen = piosize;
2203 changed = 1;
2204 }
2205
2206 if (changed) {
826d8010 2207 u64 ibc = dd->ipath_ibcctrl, ibdw;
34b2aafe 2208 /*
826d8010
DO		 2209 * update our housekeeping variables, and set IBC max
2210 * size, same as init code; max IBC is max we allow in
2211 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
34b2aafe 2212 */
826d8010
DO		 2213 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2214 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
34b2aafe 2215 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
826d8010
DO		 2216 dd->ibcc_mpl_shift);
2217 ibc |= ibdw << dd->ibcc_mpl_shift;
34b2aafe
BS		 2218 dd->ipath_ibcctrl = ibc;
2219 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2220 dd->ipath_ibcctrl);
2221 dd->ipath_f_tidtemplate(dd);
2222 }
2223
2224 ret = 0;
2225
2226bail:
2227 return ret;
2228}
2229
0ab6b2b9 2230int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
34b2aafe 2231{
0ab6b2b9 2232 dd->ipath_lid = lid;
34b2aafe
BS		 2233 dd->ipath_lmc = lmc;
2234
0ab6b2b9
DO		 2235 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2236 (~((1U << lmc) - 1)) << 16);
2237
2238 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2239
34b2aafe
BS		 2240 return 0;
2241}
2242
7bb206e3
BS		 2243
2244/**
2245 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2246 * @dd: the infinipath device
2247 * @regno: the register number to write
2248 * @port: the port containing the register
2249 * @value: the value to write
2250 *
2251 * Registers that vary with the chip implementation constants (port)
2252 * use this routine.
2253 */
2254void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2255 unsigned port, u64 value)
2256{
2257 u16 where;
2258
2259 if (port < dd->ipath_portcnt &&
2260 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2261 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2262 where = regno + port;
2263 else
2264 where = -1;
2265
2266 ipath_write_kreg(dd, where, value);
2267}
2268
82466f00
MA		 2269/*
2270 * Following deal with the "obviously simple" task of overriding the state
2271 * of the LEDS, which normally indicate link physical and logical status.
2272 * The complications arise in dealing with different hardware mappings
2273 * and the board-dependent routine being called from interrupts.
2274 * and then there's the requirement to _flash_ them.
2275 */
2276#define LED_OVER_FREQ_SHIFT 8
2277#define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2278/* Below is "non-zero" to force override, but both actual LEDs are off */
2279#define LED_OVER_BOTH_OFF (8)
2280
da9aec7b 2281static void ipath_run_led_override(unsigned long opaque)
82466f00
MA		 2282{
2283 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2284 int timeoff;
2285 int pidx;
2286 u64 lstate, ltstate, val;
2287
2288 if (!(dd->ipath_flags & IPATH_INITTED))
2289 return;
2290
2291 pidx = dd->ipath_led_override_phase++ & 1;
2292 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2293 timeoff = dd->ipath_led_override_timeoff;
2294
2295 /*
2296 * below potentially restores the LED values per current status,
2297 * should also possibly setup the traffic-blink register,
2298 * but leave that to per-chip functions.
2299 */
2300 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
124b4dcb
DO		 2301 ltstate = ipath_ib_linktrstate(dd, val);
2302 lstate = ipath_ib_linkstate(dd, val);
82466f00
MA		 2303
2304 dd->ipath_f_setextled(dd, lstate, ltstate);
2305 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2306}
2307
2308void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2309{
2310 int timeoff, freq;
2311
2312 if (!(dd->ipath_flags & IPATH_INITTED))
2313 return;
2314
2315 /* First check if we are blinking. If not, use 1HZ polling */
2316 timeoff = HZ;
2317 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2318
2319 if (freq) {
2320 /* For blink, set each phase from one nybble of val */
2321 dd->ipath_led_override_vals[0] = val & 0xF;
2322 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2323 timeoff = (HZ << 4)/freq;
2324 } else {
2325 /* Non-blink set both phases the same. */
2326 dd->ipath_led_override_vals[0] = val & 0xF;
2327 dd->ipath_led_override_vals[1] = val & 0xF;
2328 }
2329 dd->ipath_led_override_timeoff = timeoff;
2330
2331 /*
2332 * If the timer has not already been started, do so. Use a "quick"
2333 * timeout so the function will be called soon, to look at our request.
2334 */
2335 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2336 /* Need to start timer */
2337 init_timer(&dd->ipath_led_override_timer);
2338 dd->ipath_led_override_timer.function =
2339 ipath_run_led_override;
2340 dd->ipath_led_override_timer.data = (unsigned long) dd;
2341 dd->ipath_led_override_timer.expires = jiffies + 1;
2342 add_timer(&dd->ipath_led_override_timer);
2ba3f56e 2343 } else
82466f00 2344 atomic_dec(&dd->ipath_led_override_timer_active);
82466f00
MA		 2345}
2346
7bb206e3
BS		 2347/**
2348 * ipath_shutdown_device - shut down a device
2349 * @dd: the infinipath device
2350 *
2351 * This is called to make the device quiet when we are about to
2352 * unload the driver, and also when the device is administratively
2353 * disabled. It does not free any data structures.
2354 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2355 */
2356void ipath_shutdown_device(struct ipath_devdata *dd)
2357{
e342c119
JG		 2358 unsigned long flags;
2359
7bb206e3
BS		 2360 ipath_dbg("Shutting down the device\n");
2361
58411d1c
JG		 2362 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2363
7bb206e3
BS		 2364 dd->ipath_flags |= IPATH_LINKUNK;
2365 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2366 IPATH_LINKINIT | IPATH_LINKARMED |
2367 IPATH_LINKACTIVE);
2368 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2369 IPATH_STATUS_IB_READY);
2370
2371 /* mask interrupts, but not errors */
2372 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2373
2374 dd->ipath_rcvctrl = 0;
2375 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2376 dd->ipath_rcvctrl);
2377
124b4dcb
DO		 2378 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2379 teardown_sdma(dd);
2380
7bb206e3
BS		 2381 /*
2382 * gracefully stop all sends allowing any in progress to trickle out
2383 * first.
2384 */
e342c119
JG		 2385 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2386 dd->ipath_sendctrl = 0;
2387 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
7bb206e3 2388 /* flush it */
44f8e3f3 2389 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
e342c119
JG		 2390 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2391
7bb206e3
BS		 2392 /*
2393 * enough for anything that's going to trickle out to have actually
2394 * done so.
2395 */
2396 udelay(5);
2397
124b4dcb
DO		 2398 dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */
2399
4330e4da 2400 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
3810f2a8 2401 ipath_cancel_sends(dd, 0);
7bb206e3 2402
124b4dcb
DO		 2403 /*
2404 * we are shutting down, so tell components that care. We don't do
2405 * this on just a link state change, much like ethernet, a cable
2406 * unplug, etc. doesn't change driver state
2407 */
49739b3e
RC		 2408 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2409
7bb206e3
BS		 2410 /* disable IBC */
2411 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2412 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
a40f55fc 2413 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
7bb206e3
BS		 2414
2415 /*
2416 * clear SerdesEnable and turn the leds off; do this here because
2417 * we are unloading, so don't count on interrupts to move along
2418 * Turn the LEDs off explictly for the same reason.
2419 */
2420 dd->ipath_f_quiet_serdes(dd);
7bb206e3 2421
58411d1c
JG		 2422 /* stop all the timers that might still be running */
2423 del_timer_sync(&dd->ipath_hol_timer);
7bb206e3
BS		 2424 if (dd->ipath_stats_timer_active) {
2425 del_timer_sync(&dd->ipath_stats_timer);
2426 dd->ipath_stats_timer_active = 0;
2427 }
9b436eb4
DO		 2428 if (dd->ipath_intrchk_timer.data) {
2429 del_timer_sync(&dd->ipath_intrchk_timer);
2430 dd->ipath_intrchk_timer.data = 0;
2431 }
124b4dcb
DO		 2432 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2433 del_timer_sync(&dd->ipath_led_override_timer);
2434 atomic_set(&dd->ipath_led_override_timer_active, 0);
2435 }
7bb206e3
BS		 2436
2437 /*
2438 * clear all interrupts and errors, so that the next time the driver
2439 * is loaded or device is enabled, we know that whatever is set
2440 * happened while we were unloaded
2441 */
2442 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2443 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2444 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2445 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
aecd3b5a
MA		 2446
2447 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2448 ipath_update_eeprom_log(dd);
7bb206e3
BS		 2449}
2450
2451/**
2452 * ipath_free_pddata - free a port's allocated data
2453 * @dd: the infinipath device
f37bda92 2454 * @pd: the portdata structure
7bb206e3 2455 *
f37bda92
BS		 2456 * free up any allocated data for a port
2457 * This should not touch anything that would affect a simultaneous
2458 * re-allocation of port data, because it is called after ipath_mutex
2459 * is released (and can be called from reinit as well).
2460 * It should never change any chip state, or global driver state.
2461 * (The only exception to global state is freeing the port0 port0_skbs.)
7bb206e3 2462 */
f37bda92 2463void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
7bb206e3 2464{
7bb206e3
BS		 2465 if (!pd)
2466 return;
f37bda92
BS		 2467
2468 if (pd->port_rcvhdrq) {
7bb206e3
BS		 2469 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2470 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2471 (unsigned long) pd->port_rcvhdrq_size);
2472 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2473 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2474 pd->port_rcvhdrq = NULL;
f37bda92
BS		 2475 if (pd->port_rcvhdrtail_kvaddr) {
2476 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
076fafcd 2477 pd->port_rcvhdrtail_kvaddr,
f37bda92
BS		 2478 pd->port_rcvhdrqtailaddr_phys);
2479 pd->port_rcvhdrtail_kvaddr = NULL;
2480 }
7bb206e3 2481 }
f37bda92
BS		 2482 if (pd->port_port && pd->port_rcvegrbuf) {
2483 unsigned e;
2484
2485 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2486 void *base = pd->port_rcvegrbuf[e];
2487 size_t size = pd->port_rcvegrbuf_size;
2488
2489 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2490 "chunk %u/%u\n", base,
2491 (unsigned long) size,
2492 e, pd->port_rcvegrbuf_chunks);
2493 dma_free_coherent(&dd->pcidev->dev, size,
2494 base, pd->port_rcvegrbuf_phys[e]);
7bb206e3 2495 }
9929b0fb 2496 kfree(pd->port_rcvegrbuf);
f37bda92 2497 pd->port_rcvegrbuf = NULL;
9929b0fb 2498 kfree(pd->port_rcvegrbuf_phys);
f37bda92 2499 pd->port_rcvegrbuf_phys = NULL;
7bb206e3 2500 pd->port_rcvegrbuf_chunks = 0;
1fd3b40f 2501 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
7bb206e3 2502 unsigned e;
1fd3b40f 2503 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
7bb206e3 2504
1fd3b40f
BS		 2505 dd->ipath_port0_skbinfo = NULL;
2506 ipath_cdbg(VERBOSE, "free closed port %d "
2507 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2508 skbinfo);
9355fb6a 2509 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2ba3f56e
RC		 2510 if (skbinfo[e].skb) {
2511 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2512 dd->ipath_ibmaxlen,
2513 PCI_DMA_FROMDEVICE);
2514 dev_kfree_skb(skbinfo[e].skb);
2515 }
1fd3b40f 2516 vfree(skbinfo);
7bb206e3 2517 }
f37bda92 2518 kfree(pd->port_tid_pg_list);
9929b0fb
BS		 2519 vfree(pd->subport_uregbase);
2520 vfree(pd->subport_rcvegrbuf);
2521 vfree(pd->subport_rcvhdr_base);
f37bda92 2522 kfree(pd);
7bb206e3
BS		 2523}
2524
ac2ae4c9 2525static int __init infinipath_init(void)
7bb206e3
BS		 2526{
2527 int ret;
2528
39c0d0b9
BS		 2529 if (ipath_debug & __IPATH_DBG)
2530 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
7bb206e3
BS		 2531
2532 /*
2533 * These must be called before the driver is registered with
2534 * the PCI subsystem.
2535 */
2536 idr_init(&unit_table);
2537 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
bb917144 2538 printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n");
7bb206e3
BS		 2539 ret = -ENOMEM;
2540 goto bail;
2541 }
2542
2543 ret = pci_register_driver(&ipath_driver);
2544 if (ret < 0) {
2545 printk(KERN_ERR IPATH_DRV_NAME
2546 ": Unable to register driver: error %d\n", -ret);
2547 goto bail_unit;
2548 }
2549
7bb206e3
BS		 2550 ret = ipath_init_ipathfs();
2551 if (ret < 0) {
2552 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2553 "ipathfs: error %d\n", -ret);
23b9c1ab 2554 goto bail_pci;
7bb206e3
BS		 2555 }
2556
2557 goto bail;
2558
7bb206e3
BS		 2559bail_pci:
2560 pci_unregister_driver(&ipath_driver);
2561
2562bail_unit:
2563 idr_destroy(&unit_table);
2564
2565bail:
2566 return ret;
2567}
2568
7bb206e3
BS		 2569static void __exit infinipath_cleanup(void)
2570{
7bb206e3
BS		 2571 ipath_exit_ipathfs();
2572
7bb206e3
BS		 2573 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2574 pci_unregister_driver(&ipath_driver);
2575
2576 idr_destroy(&unit_table);
2577}
2578
2579/**
2580 * ipath_reset_device - reset the chip if possible
2581 * @unit: the device to reset
2582 *
2583 * Whether or not reset is successful, we attempt to re-initialize the chip
2584 * (that is, much like a driver unload/reload). We clear the INITTED flag
2585 * so that the various entry points will fail until we reinitialize. For
2586 * now, we only allow this if no user ports are open that use chip resources
2587 */
2588int ipath_reset_device(int unit)
2589{
2590 int ret, i;
2591 struct ipath_devdata *dd = ipath_lookup(unit);
3d089098 2592 unsigned long flags;
7bb206e3
BS		 2593
2594 if (!dd) {
2595 ret = -ENODEV;
2596 goto bail;
2597 }
2598
82466f00
MA		 2599 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2600 /* Need to stop LED timer, _then_ shut off LEDs */
2601 del_timer_sync(&dd->ipath_led_override_timer);
2602 atomic_set(&dd->ipath_led_override_timer_active, 0);
2603 }
2604
2605 /* Shut off LEDs after we are sure timer is not running */
2606 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2607 dd->ipath_f_setextled(dd, 0, 0);
2608
7bb206e3
BS		 2609 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2610
2611 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2612 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2613 "not initialized or not present\n", unit);
2614 ret = -ENXIO;
2615 goto bail;
2616 }
2617
3d089098 2618 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
7bb206e3 2619 if (dd->ipath_pd)
23e86a45 2620 for (i = 1; i < dd->ipath_cfgports; i++) {
3d089098
DO		 2621 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2622 continue;
2623 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2624 ipath_dbg("unit %u port %d is in use "
2625 "(PID %u cmd %s), can't reset\n",
2626 unit, i,
2627 pid_nr(dd->ipath_pd[i]->port_pid),
2628 dd->ipath_pd[i]->port_comm);
2629 ret = -EBUSY;
2630 goto bail;
7bb206e3 2631 }
3d089098 2632 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
7bb206e3 2633
124b4dcb
DO		 2634 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2635 teardown_sdma(dd);
2636
7bb206e3 2637 dd->ipath_flags &= ~IPATH_INITTED;
124b4dcb 2638 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
7bb206e3 2639 ret = dd->ipath_f_reset(dd);
124b4dcb
DO		 2640 if (ret == 1) {
2641 ipath_dbg("Reinitializing unit %u after reset attempt\n",
2642 unit);
2643 ret = ipath_init_chip(dd, 1);
2644 } else
2645 ret = -EAGAIN;
7bb206e3
BS		 2646 if (ret)
2647 ipath_dev_err(dd, "Reinitialize unit %u after "
2648 "reset failed with %d\n", unit, ret);
2649 else
2650 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2651 "resetting\n", unit);
2652
2653bail:
2654 return ret;
2655}
2656
58411d1c
JG		 2657/*
2658 * send a signal to all the processes that have the driver open
2659 * through the normal interfaces (i.e., everything other than diags
2660 * interface). Returns number of signalled processes.
2661 */
2662static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2663{
2664 int i, sub, any = 0;
40d97692 2665 struct pid *pid;
3d089098 2666 unsigned long flags;
58411d1c
JG		 2667
2668 if (!dd->ipath_pd)
2669 return 0;
3d089098
DO		 2670
2671 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
58411d1c 2672 for (i = 1; i < dd->ipath_cfgports; i++) {
40d97692 2673 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
58411d1c
JG		 2674 continue;
2675 pid = dd->ipath_pd[i]->port_pid;
40d97692
PE		 2676 if (!pid)
2677 continue;
2678
58411d1c
JG		 2679 dev_info(&dd->pcidev->dev, "context %d in use "
2680 "(PID %u), sending signal %d\n",
40d97692
PE		 2681 i, pid_nr(pid), sig);
2682 kill_pid(pid, sig, 1);
58411d1c
JG		 2683 any++;
2684 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2685 pid = dd->ipath_pd[i]->port_subpid[sub];
2686 if (!pid)
2687 continue;
2688 dev_info(&dd->pcidev->dev, "sub-context "
2689 "%d:%d in use (PID %u), sending "
40d97692
PE		 2690 "signal %d\n", i, sub, pid_nr(pid), sig);
2691 kill_pid(pid, sig, 1);
58411d1c
JG		 2692 any++;
2693 }
2694 }
3d089098 2695 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
58411d1c
JG		 2696 return any;
2697}
2698
2699static void ipath_hol_signal_down(struct ipath_devdata *dd)
2700{
2701 if (ipath_signal_procs(dd, SIGSTOP))
2702 ipath_dbg("Stopped some processes\n");
2703 ipath_cancel_sends(dd, 1);
2704}
2705
2706
2707static void ipath_hol_signal_up(struct ipath_devdata *dd)
2708{
2709 if (ipath_signal_procs(dd, SIGCONT))
2710 ipath_dbg("Continued some processes\n");
2711}
2712
2713/*
2714 * link is down, stop any users processes, and flush pending sends
2715 * to prevent HoL blocking, then start the HoL timer that
2716 * periodically continues, then stop procs, so they can detect
2717 * link down if they want, and do something about it.
74019224 2718 * Timer may already be running, so use mod_timer, not add_timer.
58411d1c
JG		 2719 */
2720void ipath_hol_down(struct ipath_devdata *dd)
2721{
2722 dd->ipath_hol_state = IPATH_HOL_DOWN;
2723 ipath_hol_signal_down(dd);
2724 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2725 dd->ipath_hol_timer.expires = jiffies +
2726 msecs_to_jiffies(ipath_hol_timeout_ms);
74019224 2727 mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
58411d1c
JG		 2728}
2729
2730/*
2731 * link is up, continue any user processes, and ensure timer
2732 * is a nop, if running. Let timer keep running, if set; it
2733 * will nop when it sees the link is up
2734 */
2735void ipath_hol_up(struct ipath_devdata *dd)
2736{
2737 ipath_hol_signal_up(dd);
2738 dd->ipath_hol_state = IPATH_HOL_UP;
2739}
2740
2741/*
2742 * toggle the running/not running state of user proceses
2743 * to prevent HoL blocking on chip resources, but still allow
2744 * user processes to do link down special case handling.
2745 * Should only be called via the timer
2746 */
2747void ipath_hol_event(unsigned long opaque)
2748{
2749 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2750
2751 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2752 && dd->ipath_hol_state != IPATH_HOL_UP) {
2753 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2754 ipath_dbg("Stopping processes\n");
2755 ipath_hol_signal_down(dd);
2756 } else { /* may do "extra" if also in ipath_hol_up() */
2757 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2758 ipath_dbg("Continuing processes\n");
2759 ipath_hol_signal_up(dd);
2760 }
2761 if (dd->ipath_hol_state == IPATH_HOL_UP)
2762 ipath_dbg("link's up, don't resched timer\n");
2763 else {
2764 dd->ipath_hol_timer.expires = jiffies +
2765 msecs_to_jiffies(ipath_hol_timeout_ms);
74019224 2766 mod_timer(&dd->ipath_hol_timer,
58411d1c
JG		 2767 dd->ipath_hol_timer.expires);
2768 }
2769}
2770
30fc5c31
BS		 2771int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2772{
2773 u64 val;
2ba3f56e
RC		 2774
2775 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
30fc5c31 2776 return -1;
2ba3f56e 2777 if (dd->ipath_rx_pol_inv != new_pol_inv) {
30fc5c31
BS		 2778 dd->ipath_rx_pol_inv = new_pol_inv;
2779 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2780 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
3cd96564
RD		 2781 INFINIPATH_XGXS_RX_POL_SHIFT);
2782 val |= ((u64)dd->ipath_rx_pol_inv) <<
2783 INFINIPATH_XGXS_RX_POL_SHIFT;
30fc5c31
BS		 2784 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2785 }
2786 return 0;
2787}
6ac50727
DO		 2788
2789/*
2790 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2791 * the 7220, which is count-based, rather than trigger-based. Safe for the
2792 * driver check, since it's at init. Not completely safe when used for
2793 * user-mode checking, since some error checking can be lost, but not
2794 * particularly risky, and only has problematic side-effects in the face of
2795 * very buggy user code. There is no reference counting, but that's also
2796 * fine, given the intended use.
2797 */
2798void ipath_enable_armlaunch(struct ipath_devdata *dd)
2799{
2800 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2801 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2802 INFINIPATH_E_SPIOARMLAUNCH);
2803 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2804 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2805 dd->ipath_errormask);
2806}
2807
2808void ipath_disable_armlaunch(struct ipath_devdata *dd)
2809{
2810 /* so don't re-enable if already set */
2811 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2812 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2813 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2814 dd->ipath_errormask);
2815}
2816
7bb206e3
BS		 2817module_init(infinipath_init);
2818module_exit(infinipath_cleanup);
kernel source for telekom puls (alcatel/mediatek)