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Merge tag 'v3.10.76' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / scc_pata.c
CommitLineData
bde18a2e
KI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
ccd32e22 8 * Copyright (C) 2003 Red Hat
bde18a2e
KI		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
bde18a2e
KI		 29#include <linux/ide.h>
30#include <linux/init.h>
31
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
33
34#define SCC_PATA_NAME "scc IDE"
35
36#define TDVHSEL_MASTER 0x00000001
37#define TDVHSEL_SLAVE 0x00000004
38
39#define MODE_JCUSFEN 0x00000080
40
41#define CCKCTRL_ATARESET 0x00040000
42#define CCKCTRL_BUFCNT 0x00020000
43#define CCKCTRL_CRST 0x00010000
44#define CCKCTRL_OCLKEN 0x00000100
45#define CCKCTRL_ATACLKOEN 0x00000002
46#define CCKCTRL_LCLKEN 0x00000001
47
48#define QCHCD_IOS_SS 0x00000001
49
50#define QCHSD_STPDIAG 0x00020000
51
52#define INTMASK_MSK 0xD1000012
53#define INTSTS_SERROR 0x80000000
54#define INTSTS_PRERR 0x40000000
55#define INTSTS_RERR 0x10000000
56#define INTSTS_ICERR 0x01000000
57#define INTSTS_BMSINT 0x00000010
58#define INTSTS_BMHE 0x00000008
59#define INTSTS_IOIRQS 0x00000004
60#define INTSTS_INTRQ 0x00000002
61#define INTSTS_ACTEINT 0x00000001
62
63#define ECMODE_VALUE 0x01
64
65static struct scc_ports {
66 unsigned long ctl, dma;
48c3c107 67 struct ide_host *host; /* for removing port from system */
bde18a2e
KI		 68} scc_ports[MAX_HWIFS];
69
70/* PIO transfer mode table */
71/* JCHST */
72static unsigned long JCHSTtbl[2][7] = {
73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
75};
76
77/* JCHHT */
78static unsigned long JCHHTtbl[2][7] = {
79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
81};
82
83/* JCHCT */
84static unsigned long JCHCTtbl[2][7] = {
85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
87};
88
89
90/* DMA transfer mode table */
91/* JCHDCTM/JCHDCTS */
92static unsigned long JCHDCTxtbl[2][7] = {
93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
95};
96
97/* JCSTWTM/JCSTWTS */
98static unsigned long JCSTWTxtbl[2][7] = {
99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
101};
102
103/* JCTSS */
104static unsigned long JCTSStbl[2][7] = {
105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
107};
108
109/* JCENVT */
110static unsigned long JCENVTtbl[2][7] = {
111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
113};
114
115/* JCACTSELS/JCACTSELM */
116static unsigned long JCACTSELtbl[2][7] = {
117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
119};
120
121
122static u8 scc_ide_inb(unsigned long port)
123{
124 u32 data = in_be32((void*)port);
125 return (u8)data;
126}
127
c6dfa867
BZ		 128static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
129{
130 out_be32((void *)hwif->io_ports.command_addr, cmd);
131 eieio();
132 in_be32((void *)(hwif->dma_base + 0x01c));
133 eieio();
134}
135
b73c7ee2
BZ		 136static u8 scc_read_status(ide_hwif_t *hwif)
137{
138 return (u8)in_be32((void *)hwif->io_ports.status_addr);
139}
140
1f6d8a0f
BZ		 141static u8 scc_read_altstatus(ide_hwif_t *hwif)
142{
143 return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
144}
145
592b5315 146static u8 scc_dma_sff_read_status(ide_hwif_t *hwif)
b2f951aa 147{
cab7f8ed 148 return (u8)in_be32((void *)(hwif->dma_base + 4));
b2f951aa
BZ		 149}
150
ecf3a31d 151static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl)
6e6afb3b 152{
6e6afb3b
BZ		 153 out_be32((void *)hwif->io_ports.ctl_addr, ctl);
154 eieio();
155 in_be32((void *)(hwif->dma_base + 0x01c));
156 eieio();
157}
158
bde18a2e
KI		 159static void scc_ide_insw(unsigned long port, void *addr, u32 count)
160{
161 u16 *ptr = (u16 *)addr;
162 while (count--) {
163 *ptr++ = le16_to_cpu(in_be32((void*)port));
164 }
165}
166
167static void scc_ide_insl(unsigned long port, void *addr, u32 count)
168{
169 u16 *ptr = (u16 *)addr;
170 while (count--) {
171 *ptr++ = le16_to_cpu(in_be32((void*)port));
172 *ptr++ = le16_to_cpu(in_be32((void*)port));
173 }
174}
175
176static void scc_ide_outb(u8 addr, unsigned long port)
177{
178 out_be32((void*)port, addr);
179}
180
bde18a2e
KI		 181static void
182scc_ide_outsw(unsigned long port, void *addr, u32 count)
183{
184 u16 *ptr = (u16 *)addr;
185 while (count--) {
186 out_be32((void*)port, cpu_to_le16(*ptr++));
187 }
188}
189
190static void
191scc_ide_outsl(unsigned long port, void *addr, u32 count)
192{
193 u16 *ptr = (u16 *)addr;
194 while (count--) {
195 out_be32((void*)port, cpu_to_le16(*ptr++));
196 out_be32((void*)port, cpu_to_le16(*ptr++));
197 }
198}
199
bde18a2e 200/**
88b2b32b 201 * scc_set_pio_mode - set host controller for PIO mode
e085b3ca 202 * @hwif: port
88b2b32b 203 * @drive: drive
bde18a2e
KI		 204 *
205 * Load the timing settings for this device mode into the
206 * controller.
207 */
208
e085b3ca 209static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
bde18a2e 210{
bde18a2e
KI		 211 struct scc_ports *ports = ide_get_hwifdata(hwif);
212 unsigned long ctl_base = ports->ctl;
213 unsigned long cckctrl_port = ctl_base + 0xff0;
214 unsigned long piosht_port = ctl_base + 0x000;
215 unsigned long pioct_port = ctl_base + 0x004;
216 unsigned long reg;
bde18a2e 217 int offset;
e085b3ca 218 const u8 pio = drive->pio_mode - XFER_PIO_0;
bde18a2e 219
0ecdca26 220 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 221 if (reg & CCKCTRL_ATACLKOEN) {
222 offset = 1; /* 133MHz */
223 } else {
224 offset = 0; /* 100MHz */
225 }
3fcece66 226 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
0ecdca26 227 out_be32((void __iomem *)piosht_port, reg);
3fcece66 228 reg = JCHCTtbl[offset][pio];
0ecdca26 229 out_be32((void __iomem *)pioct_port, reg);
3fcece66 230}
bde18a2e 231
bde18a2e 232/**
88b2b32b 233 * scc_set_dma_mode - set host controller for DMA mode
8776168c 234 * @hwif: port
88b2b32b 235 * @drive: drive
bde18a2e
KI		 236 *
237 * Load the timing settings for this device mode into the
238 * controller.
239 */
240
8776168c 241static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
bde18a2e 242{
bde18a2e
KI		 243 struct scc_ports *ports = ide_get_hwifdata(hwif);
244 unsigned long ctl_base = ports->ctl;
245 unsigned long cckctrl_port = ctl_base + 0xff0;
246 unsigned long mdmact_port = ctl_base + 0x008;
247 unsigned long mcrcst_port = ctl_base + 0x00c;
248 unsigned long sdmact_port = ctl_base + 0x010;
249 unsigned long scrcst_port = ctl_base + 0x014;
250 unsigned long udenvt_port = ctl_base + 0x018;
251 unsigned long tdvhsel_port = ctl_base + 0x020;
5e7f3a46 252 int is_slave = drive->dn & 1;
bde18a2e
KI		 253 int offset, idx;
254 unsigned long reg;
255 unsigned long jcactsel;
8776168c 256 const u8 speed = drive->dma_mode;
bde18a2e 257
0ecdca26 258 reg = in_be32((void __iomem *)cckctrl_port);
bde18a2e
KI		 259 if (reg & CCKCTRL_ATACLKOEN) {
260 offset = 1; /* 133MHz */
261 } else {
262 offset = 0; /* 100MHz */
263 }
264
4db90a14 265 idx = speed - XFER_UDMA_0;
bde18a2e
KI		 266
267 jcactsel = JCACTSELtbl[offset][idx];
268 if (is_slave) {
0ecdca26
BZ		 269 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
270 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
271 jcactsel = jcactsel << 2;
272 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
bde18a2e 273 } else {
0ecdca26
BZ		 274 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
275 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
276 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
bde18a2e
KI		 277 }
278 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
0ecdca26 279 out_be32((void __iomem *)udenvt_port, reg);
bde18a2e
KI		 280}
281
669185e9
BZ		 282static void scc_dma_host_set(ide_drive_t *drive, int on)
283{
284 ide_hwif_t *hwif = drive->hwif;
123995b9 285 u8 unit = drive->dn & 1;
c2ce5ca0 286 u8 dma_stat = scc_dma_sff_read_status(hwif);
669185e9
BZ		 287
288 if (on)
289 dma_stat |= (1 << (5 + unit));
290 else
291 dma_stat &= ~(1 << (5 + unit));
292
cab7f8ed 293 scc_ide_outb(dma_stat, hwif->dma_base + 4);
669185e9
BZ		 294}
295
0ecdca26 296/**
22981694 297 * scc_dma_setup - begin a DMA phase
0ecdca26 298 * @drive: target device
22981694 299 * @cmd: command
0ecdca26
BZ		 300 *
301 * Build an IDE DMA PRD (IDE speak for scatter gather table)
302 * and then set up the DMA transfer registers.
303 *
304 * Returns 0 on success. If a PIO fallback is required then 1
305 * is returned.
306 */
307
22981694 308static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
0ecdca26
BZ		 309{
310 ide_hwif_t *hwif = drive->hwif;
22981694 311 u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
0ecdca26
BZ		 312 u8 dma_stat;
313
0ecdca26 314 /* fall back to pio! */
11998b31 315 if (ide_build_dmatable(drive, cmd) == 0)
0ecdca26 316 return 1;
0ecdca26
BZ		 317
318 /* PRD table */
55224bc8 319 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
0ecdca26
BZ		 320
321 /* specify r/w */
22981694 322 out_be32((void __iomem *)hwif->dma_base, rw);
0ecdca26 323
cab7f8ed 324 /* read DMA status for INTR & ERROR flags */
c2ce5ca0 325 dma_stat = scc_dma_sff_read_status(hwif);
0ecdca26
BZ		 326
327 /* clear INTR & ERROR flags */
cab7f8ed 328 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
88b4132e 329
0ecdca26
BZ		 330 return 0;
331}
332
669185e9
BZ		 333static void scc_dma_start(ide_drive_t *drive)
334{
335 ide_hwif_t *hwif = drive->hwif;
cab7f8ed 336 u8 dma_cmd = scc_ide_inb(hwif->dma_base);
669185e9
BZ		 337
338 /* start DMA */
cab7f8ed 339 scc_ide_outb(dma_cmd | 1, hwif->dma_base);
669185e9
BZ		 340}
341
342static int __scc_dma_end(ide_drive_t *drive)
343{
344 ide_hwif_t *hwif = drive->hwif;
345 u8 dma_stat, dma_cmd;
346
669185e9 347 /* get DMA command mode */
cab7f8ed 348 dma_cmd = scc_ide_inb(hwif->dma_base);
669185e9 349 /* stop DMA */
cab7f8ed 350 scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
669185e9 351 /* get DMA status */
c2ce5ca0 352 dma_stat = scc_dma_sff_read_status(hwif);
669185e9 353 /* clear the INTR & ERROR bits */
cab7f8ed 354 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
669185e9 355 /* verify good DMA status */
669185e9
BZ		 356 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
357}
0ecdca26 358
bde18a2e 359/**
5e37bdc0 360 * scc_dma_end - Stop DMA
bde18a2e
KI		 361 * @drive: IDE drive
362 *
363 * Check and clear INT Status register.
669185e9 364 * Then call __scc_dma_end().
bde18a2e
KI		 365 */
366
5e37bdc0 367static int scc_dma_end(ide_drive_t *drive)
bde18a2e 368{
898ec223 369 ide_hwif_t *hwif = drive->hwif;
cab7f8ed 370 void __iomem *dma_base = (void __iomem *)hwif->dma_base;
bde18a2e
KI		 371 unsigned long intsts_port = hwif->dma_base + 0x014;
372 u32 reg;
4ae41ff8
KI		 373 int dma_stat, data_loss = 0;
374 static int retry = 0;
375
376 /* errata A308 workaround: Step5 (check data loss) */
377 /* We don't check non ide_disk because it is limited to UDMA4 */
4c3032d8 378 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
3a7d2484 379 & ATA_ERR) &&
4ae41ff8
KI		 380 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
381 reg = in_be32((void __iomem *)intsts_port);
382 if (!(reg & INTSTS_ACTEINT)) {
383 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
384 drive->name);
385 data_loss = 1;
386 if (retry++) {
b65fac32 387 struct request *rq = hwif->rq;
2bd24a1c
BZ		 388 ide_drive_t *drive;
389 int i;
390
4ae41ff8
KI		 391 /* ERROR_RESET and drive->crc_count are needed
392 * to reduce DMA transfer mode in retry process.
393 */
394 if (rq)
395 rq->errors |= ERROR_RESET;
5e7f3a46 396
2bd24a1c 397 ide_port_for_each_dev(i, drive, hwif)
4ae41ff8 398 drive->crc_count++;
4ae41ff8
KI		 399 }
400 }
401 }
bde18a2e
KI		 402
403 while (1) {
0ecdca26 404 reg = in_be32((void __iomem *)intsts_port);
bde18a2e
KI		 405
406 if (reg & INTSTS_SERROR) {
407 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
0ecdca26 408 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
bde18a2e 409
cab7f8ed 410 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 411 continue;
412 }
413
414 if (reg & INTSTS_PRERR) {
415 u32 maea0, maec0;
416 unsigned long ctl_base = hwif->config_data;
417
0ecdca26
BZ		 418 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
419 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
bde18a2e
KI		 420
421 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
422
0ecdca26 423 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
bde18a2e 424
cab7f8ed 425 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 426 continue;
427 }
428
429 if (reg & INTSTS_RERR) {
430 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
0ecdca26 431 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
bde18a2e 432
cab7f8ed 433 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 434 continue;
435 }
436
437 if (reg & INTSTS_ICERR) {
cab7f8ed 438 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
bde18a2e
KI		 439
440 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
0ecdca26 441 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
bde18a2e
KI		 442 continue;
443 }
444
445 if (reg & INTSTS_BMSINT) {
446 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
0ecdca26 447 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
bde18a2e
KI		 448
449 ide_do_reset(drive);
450 continue;
451 }
452
453 if (reg & INTSTS_BMHE) {
0ecdca26 454 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
bde18a2e
KI		 455 continue;
456 }
457
458 if (reg & INTSTS_ACTEINT) {
0ecdca26 459 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
bde18a2e
KI		 460 continue;
461 }
462
463 if (reg & INTSTS_IOIRQS) {
0ecdca26 464 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
bde18a2e
KI		 465 continue;
466 }
467 break;
468 }
469
669185e9 470 dma_stat = __scc_dma_end(drive);
4ae41ff8
KI		 471 if (data_loss)
472 dma_stat |= 2; /* emulate DMA error (to retry command) */
473 return dma_stat;
bde18a2e
KI		 474}
475
06a9952b
AI		 476/* returns 1 if dma irq issued, 0 otherwise */
477static int scc_dma_test_irq(ide_drive_t *drive)
478{
898ec223 479 ide_hwif_t *hwif = drive->hwif;
4ae41ff8 480 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
06a9952b 481
4ae41ff8 482 /* SCC errata A252,A308 workaround: Step4 */
4c3032d8 483 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
3a7d2484 484 & ATA_ERR) &&
4ae41ff8 485 (int_stat & INTSTS_INTRQ))
06a9952b
AI		 486 return 1;
487
4ae41ff8
KI		 488 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
489 if (int_stat & INTSTS_IOIRQS)
06a9952b
AI		 490 return 1;
491
06a9952b
AI		 492 return 0;
493}
494
4ae41ff8
KI		 495static u8 scc_udma_filter(ide_drive_t *drive)
496{
497 ide_hwif_t *hwif = drive->hwif;
498 u8 mask = hwif->ultra_mask;
499
500 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
501 if ((drive->media != ide_disk) && (mask & 0xE0)) {
502 printk(KERN_INFO "%s: limit %s to UDMA4\n",
503 SCC_PATA_NAME, drive->name);
5f8b6c34 504 mask = ATA_UDMA4;
4ae41ff8
KI		 505 }
506
507 return mask;
508}
509
bde18a2e
KI		 510/**
511 * setup_mmio_scc - map CTRL/BMID region
512 * @dev: PCI device we are configuring
513 * @name: device name
514 *
515 */
516
517static int setup_mmio_scc (struct pci_dev *dev, const char *name)
518{
0bd8496b
AV		 519 void __iomem *ctl_addr;
520 void __iomem *dma_addr;
0d1bad21 521 int i, ret;
bde18a2e
KI		 522
523 for (i = 0; i < MAX_HWIFS; i++) {
524 if (scc_ports[i].ctl == 0)
525 break;
526 }
527 if (i >= MAX_HWIFS)
528 return -ENOMEM;
529
0d1bad21
BZ		 530 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
531 if (ret < 0) {
532 printk(KERN_ERR "%s: can't reserve resources\n", name);
533 return ret;
bde18a2e
KI		 534 }
535
1f1ab274
AV		 536 ctl_addr = pci_ioremap_bar(dev, 0);
537 if (!ctl_addr)
0d1bad21 538 goto fail_0;
bde18a2e 539
1f1ab274
AV		 540 dma_addr = pci_ioremap_bar(dev, 1);
541 if (!dma_addr)
0d1bad21 542 goto fail_1;
bde18a2e
KI		 543
544 pci_set_master(dev);
545 scc_ports[i].ctl = (unsigned long)ctl_addr;
546 scc_ports[i].dma = (unsigned long)dma_addr;
547 pci_set_drvdata(dev, (void *) &scc_ports[i]);
548
549 return 1;
550
bde18a2e 551 fail_1:
0d1bad21 552 iounmap(ctl_addr);
bde18a2e
KI		 553 fail_0:
554 return -ENOMEM;
555}
556
3d53ba87
AI		 557static int scc_ide_setup_pci_device(struct pci_dev *dev,
558 const struct ide_port_info *d)
559{
560 struct scc_ports *ports = pci_get_drvdata(dev);
48c3c107 561 struct ide_host *host;
9f36d314 562 struct ide_hw hw, *hws[] = { &hw };
6f904d01 563 int i, rc;
3d53ba87 564
3d53ba87 565 memset(&hw, 0, sizeof(hw));
4c3032d8
BZ		 566 for (i = 0; i <= 8; i++)
567 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
3d53ba87
AI		 568 hw.irq = dev->irq;
569 hw.dev = &dev->dev;
3d53ba87 570
dca39830 571 rc = ide_host_add(d, hws, 1, &host);
6f904d01
BZ		 572 if (rc)
573 return rc;
48c3c107
BZ		 574
575 ports->host = host;
3d53ba87
AI		 576
577 return 0;
578}
579
bde18a2e
KI		 580/**
581 * init_setup_scc - set up an SCC PATA Controller
582 * @dev: PCI device
039788e1 583 * @d: IDE port info
bde18a2e
KI		 584 *
585 * Perform the initial set up for this device.
586 */
587
fe31edc8 588static int init_setup_scc(struct pci_dev *dev, const struct ide_port_info *d)
bde18a2e
KI		 589{
590 unsigned long ctl_base;
591 unsigned long dma_base;
592 unsigned long cckctrl_port;
593 unsigned long intmask_port;
594 unsigned long mode_port;
595 unsigned long ecmode_port;
bde18a2e
KI		 596 u32 reg = 0;
597 struct scc_ports *ports;
598 int rc;
599
3d53ba87
AI		 600 rc = pci_enable_device(dev);
601 if (rc)
602 goto end;
603
bde18a2e 604 rc = setup_mmio_scc(dev, d->name);
3d53ba87
AI		 605 if (rc < 0)
606 goto end;
bde18a2e
KI		 607
608 ports = pci_get_drvdata(dev);
609 ctl_base = ports->ctl;
610 dma_base = ports->dma;
611 cckctrl_port = ctl_base + 0xff0;
612 intmask_port = dma_base + 0x010;
613 mode_port = ctl_base + 0x024;
614 ecmode_port = ctl_base + 0xf00;
bde18a2e
KI		 615
616 /* controller initialization */
617 reg = 0;
618 out_be32((void*)cckctrl_port, reg);
619 reg |= CCKCTRL_ATACLKOEN;
620 out_be32((void*)cckctrl_port, reg);
621 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
622 out_be32((void*)cckctrl_port, reg);
623 reg |= CCKCTRL_CRST;
624 out_be32((void*)cckctrl_port, reg);
625
626 for (;;) {
627 reg = in_be32((void*)cckctrl_port);
628 if (reg & CCKCTRL_CRST)
629 break;
630 udelay(5000);
631 }
632
633 reg |= CCKCTRL_ATARESET;
634 out_be32((void*)cckctrl_port, reg);
635
636 out_be32((void*)ecmode_port, ECMODE_VALUE);
637 out_be32((void*)mode_port, MODE_JCUSFEN);
638 out_be32((void*)intmask_port, INTMASK_MSK);
639
3d53ba87
AI		 640 rc = scc_ide_setup_pci_device(dev, d);
641
642 end:
643 return rc;
bde18a2e
KI		 644}
645
c9ff9e7b 646static void scc_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
db2432c4
BZ		 647{
648 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
60f85019
SS		 649
650 if (valid & IDE_VALID_FEATURE)
db2432c4 651 scc_ide_outb(tf->feature, io_ports->feature_addr);
60f85019 652 if (valid & IDE_VALID_NSECT)
db2432c4 653 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
60f85019 654 if (valid & IDE_VALID_LBAL)
db2432c4 655 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
60f85019 656 if (valid & IDE_VALID_LBAM)
db2432c4 657 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
60f85019 658 if (valid & IDE_VALID_LBAH)
db2432c4 659 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
60f85019 660 if (valid & IDE_VALID_DEVICE)
4109d19a 661 scc_ide_outb(tf->device, io_ports->device_addr);
db2432c4
BZ		 662}
663
3153c26b 664static void scc_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
db2432c4
BZ		 665{
666 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
db2432c4 667
60f85019 668 if (valid & IDE_VALID_ERROR)
67625119 669 tf->error = scc_ide_inb(io_ports->feature_addr);
60f85019 670 if (valid & IDE_VALID_NSECT)
db2432c4 671 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
60f85019 672 if (valid & IDE_VALID_LBAL)
db2432c4 673 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
60f85019 674 if (valid & IDE_VALID_LBAM)
db2432c4 675 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
60f85019 676 if (valid & IDE_VALID_LBAH)
db2432c4 677 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
60f85019 678 if (valid & IDE_VALID_DEVICE)
db2432c4 679 tf->device = scc_ide_inb(io_ports->device_addr);
db2432c4
BZ		 680}
681
adb1af98 682static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
efa3db1b
BZ		 683 void *buf, unsigned int len)
684{
685 unsigned long data_addr = drive->hwif->io_ports.data_addr;
686
687 len++;
688
689 if (drive->io_32bit) {
690 scc_ide_insl(data_addr, buf, len / 4);
691
692 if ((len & 3) >= 2)
693 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
694 } else
695 scc_ide_insw(data_addr, buf, len / 2);
696}
697
adb1af98 698static void scc_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
efa3db1b
BZ		 699 void *buf, unsigned int len)
700{
701 unsigned long data_addr = drive->hwif->io_ports.data_addr;
702
703 len++;
704
705 if (drive->io_32bit) {
706 scc_ide_outsl(data_addr, buf, len / 4);
707
708 if ((len & 3) >= 2)
709 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
710 } else
711 scc_ide_outsw(data_addr, buf, len / 2);
712}
713
bde18a2e
KI		 714/**
715 * init_mmio_iops_scc - set up the iops for MMIO
716 * @hwif: interface to set up
717 *
718 */
719
fe31edc8 720static void init_mmio_iops_scc(ide_hwif_t *hwif)
bde18a2e 721{
36501650 722 struct pci_dev *dev = to_pci_dev(hwif->dev);
bde18a2e
KI		 723 struct scc_ports *ports = pci_get_drvdata(dev);
724 unsigned long dma_base = ports->dma;
725
726 ide_set_hwifdata(hwif, ports);
727
bde18a2e
KI		 728 hwif->dma_base = dma_base;
729 hwif->config_data = ports->ctl;
bde18a2e
KI		 730}
731
732/**
733 * init_iops_scc - set up iops
734 * @hwif: interface to set up
735 *
736 * Do the basic setup for the SCC hardware interface
737 * and then do the MMIO setup.
738 */
739
fe31edc8 740static void init_iops_scc(ide_hwif_t *hwif)
bde18a2e 741{
36501650
BZ		 742 struct pci_dev *dev = to_pci_dev(hwif->dev);
743
bde18a2e
KI		 744 hwif->hwif_data = NULL;
745 if (pci_get_drvdata(dev) == NULL)
746 return;
747 init_mmio_iops_scc(hwif);
748}
749
fe31edc8 750static int scc_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
2bbd57ca
BZ		 751{
752 return ide_allocate_dma_engine(hwif);
753}
754
f454cbe8 755static u8 scc_cable_detect(ide_hwif_t *hwif)
b4d1c73d
BZ		 756{
757 return ATA_CBL_PATA80;
758}
759
bde18a2e
KI		 760/**
761 * init_hwif_scc - set up hwif
762 * @hwif: interface to set up
763 *
764 * We do the basic set up of the interface structure. The SCC
765 * requires several custom handlers so we override the default
766 * ide DMA handlers appropriately.
767 */
768
fe31edc8 769static void init_hwif_scc(ide_hwif_t *hwif)
bde18a2e 770{
0ecdca26
BZ		 771 /* PTERADD */
772 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
bde18a2e 773
5f8b6c34
BZ		 774 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
775 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
776 else
777 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
bde18a2e
KI		 778}
779
374e042c
BZ		 780static const struct ide_tp_ops scc_tp_ops = {
781 .exec_command = scc_exec_command,
782 .read_status = scc_read_status,
783 .read_altstatus = scc_read_altstatus,
ecf3a31d 784 .write_devctl = scc_write_devctl,
374e042c 785
abb596b2 786 .dev_select = ide_dev_select,
374e042c
BZ		 787 .tf_load = scc_tf_load,
788 .tf_read = scc_tf_read,
789
790 .input_data = scc_input_data,
791 .output_data = scc_output_data,
792};
793
ac95beed
BZ		 794static const struct ide_port_ops scc_port_ops = {
795 .set_pio_mode = scc_set_pio_mode,
796 .set_dma_mode = scc_set_dma_mode,
797 .udma_filter = scc_udma_filter,
798 .cable_detect = scc_cable_detect,
799};
800
f37afdac 801static const struct ide_dma_ops scc_dma_ops = {
669185e9 802 .dma_host_set = scc_dma_host_set,
5e37bdc0 803 .dma_setup = scc_dma_setup,
669185e9 804 .dma_start = scc_dma_start,
5e37bdc0
BZ		 805 .dma_end = scc_dma_end,
806 .dma_test_irq = scc_dma_test_irq,
f37afdac 807 .dma_lost_irq = ide_dma_lost_irq,
22117d6e 808 .dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315 809 .dma_sff_read_status = scc_dma_sff_read_status,
5e37bdc0
BZ		 810};
811
fe31edc8 812static const struct ide_port_info scc_chipset = {
304ffd6d
BZ		 813 .name = "sccIDE",
814 .init_iops = init_iops_scc,
815 .init_dma = scc_init_dma,
816 .init_hwif = init_hwif_scc,
817 .tp_ops = &scc_tp_ops,
818 .port_ops = &scc_port_ops,
819 .dma_ops = &scc_dma_ops,
820 .host_flags = IDE_HFLAG_SINGLE,
255115fb 821 .irq_flags = IRQF_SHARED,
304ffd6d 822 .pio_mask = ATA_PIO4,
29e52cf7 823 .chipset = ide_pci,
bde18a2e
KI		 824};
825
826/**
827 * scc_init_one - pci layer discovery entry
828 * @dev: PCI device
829 * @id: ident table entry
830 *
831 * Called by the PCI code when it finds an SCC PATA controller.
832 * We then use the IDE PCI generic helper to do most of the work.
833 */
834
fe31edc8 835static int scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
bde18a2e 836{
304ffd6d 837 return init_setup_scc(dev, &scc_chipset);
bde18a2e
KI		 838}
839
840/**
841 * scc_remove - pci layer remove entry
842 * @dev: PCI device
843 *
844 * Called by the PCI code when it removes an SCC PATA controller.
845 */
846
fe31edc8 847static void scc_remove(struct pci_dev *dev)
bde18a2e
KI		 848{
849 struct scc_ports *ports = pci_get_drvdata(dev);
48c3c107 850 struct ide_host *host = ports->host;
bde18a2e 851
48c3c107 852 ide_host_remove(host);
bde18a2e 853
bde18a2e
KI		 854 iounmap((void*)ports->dma);
855 iounmap((void*)ports->ctl);
0d1bad21 856 pci_release_selected_regions(dev, (1 << 2) - 1);
bde18a2e
KI		 857 memset(ports, 0, sizeof(*ports));
858}
859
9cbcc5e3
BZ		 860static const struct pci_device_id scc_pci_tbl[] = {
861 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
bde18a2e
KI		 862 { 0, },
863};
864MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
865
a9ab09e2 866static struct pci_driver scc_pci_driver = {
bde18a2e
KI		 867 .name = "SCC IDE",
868 .id_table = scc_pci_tbl,
869 .probe = scc_init_one,
fe31edc8 870 .remove = scc_remove,
bde18a2e
KI		 871};
872
4cd7d924 873static int __init scc_ide_init(void)
bde18a2e 874{
a9ab09e2 875 return ide_pci_register_driver(&scc_pci_driver);
bde18a2e
KI		 876}
877
4cd7d924 878static void __exit scc_ide_exit(void)
bde18a2e 879{
4cd7d924 880 pci_unregister_driver(&scc_pci_driver);
bde18a2e 881}
bde18a2e 882
4cd7d924
BZ		 883module_init(scc_ide_init);
884module_exit(scc_ide_exit);
bde18a2e
KI		 885
886MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
887MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)