[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / sc1200.c

/*
 * Copyright (C) 2000-2002		Mark Lord <mlord@pobox.com>
 * Copyright (C)      2007		Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	Available from National Semiconductor
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/pm.h>

#include <asm/io.h>

#define DRV_NAME "sc1200"

#define SC1200_REV_A	0x00
#define SC1200_REV_B1	0x01
#define SC1200_REV_B3	0x02
#define SC1200_REV_C1	0x03
#define SC1200_REV_D1	0x04

#define PCI_CLK_33	0x00
#define PCI_CLK_48	0x01
#define PCI_CLK_66	0x02
#define PCI_CLK_33A	0x03

static unsigned short sc1200_get_pci_clock (void)
{
	unsigned char chip_id, silicon_revision;
	unsigned int pci_clock;
	/*
	 * Check the silicon revision, as not all versions of the chip
	 * have the register with the fast PCI bus timings.
	 */
	chip_id = inb (0x903c);
	silicon_revision = inb (0x903d);

	// Read the fast pci clock frequency
	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
		pci_clock = PCI_CLK_33;
	} else {
		// check clock generator configuration (cfcc)
		// the clock is in bits 8 and 9 of this word

		pci_clock = inw (0x901e);
		pci_clock >>= 8;
		pci_clock &= 0x03;
		if (pci_clock == PCI_CLK_33A)
			pci_clock = PCI_CLK_33;
	}
	return pci_clock;
}

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static const unsigned int sc1200_pio_timings[4][5] =
	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},	// format0  33Mhz
	 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},	// format1, 33Mhz
	 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},	// format1, 48Mhz
	 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}};	// format1, 66Mhz

/*
 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
 */
//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)

static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;

	pci_read_config_dword(pdev, basereg + 4, &format);
	format = (format >> 31) & 1;
	if (format)
		format += sc1200_get_pci_clock();
	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
			       sc1200_pio_timings[format][pio]);
}

/*
 *	The SC1200 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 */
static u8 sc1200_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = ide_get_pair_dev(drive);
	u16 *mateid;
	u8 mask = hwif->ultra_mask;

	if (mate == NULL)
		goto out;
	mateid = mate->id;

	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
		    (mateid[ATA_ID_UDMA_MODES] & 7))
			goto out;
		if (mateid[ATA_ID_MWDMA_MODES] & 7)
			mask = 0;
	}
out:
	return mask;
}

static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev		*dev = to_pci_dev(hwif->dev);
	unsigned int		reg, timings;
	unsigned short		pci_clock;
	unsigned int		basereg = hwif->channel ? 0x50 : 0x40;
	const u8		mode = drive->dma_mode;

	static const u32 udma_timing[3][3] = {
		{ 0x00921250, 0x00911140, 0x00911030 },
		{ 0x00932470, 0x00922260, 0x00922140 },
		{ 0x009436a1, 0x00933481, 0x00923261 },
	};

	static const u32 mwdma_timing[3][3] = {
		{ 0x00077771, 0x00012121, 0x00002020 },
		{ 0x000bbbb2, 0x00024241, 0x00013131 },
		{ 0x000ffff3, 0x00035352, 0x00015151 },
	};

	pci_clock = sc1200_get_pci_clock();

	/*
	 * Note that each DMA mode has several timings associated with it.
	 * The correct timing depends on the fast PCI clock freq.
	 */

	if (mode >= XFER_UDMA_0)
		timings =  udma_timing[pci_clock][mode - XFER_UDMA_0];
	else
		timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];

	if ((drive->dn & 1) == 0) {
		pci_read_config_dword(dev, basereg + 4, &reg);
		timings |= reg & 0x80000000;	/* preserve PIO format bit */
		pci_write_config_dword(dev, basereg + 4, timings);
	} else
		pci_write_config_dword(dev, basereg + 12, timings);
}

/*  Replacement for the standard ide_dma_end action in
 *  dma_proc.
 *
 *  returns 1 on error, 0 otherwise
 */
static int sc1200_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	unsigned long dma_base = hwif->dma_base;
	u8 dma_stat;

	dma_stat = inb(dma_base+2);		/* get DMA status */

	if (!(dma_stat & 4))
		printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
		  dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));

	outb(dma_stat|0x1b, dma_base+2);	/* clear the INTR & ERROR bits */
	outb(inb(dma_base)&~1, dma_base);	/* !! DO THIS HERE !! stop DMA */

	return (dma_stat & 7) != 4;		/* verify good DMA status */
}

/*
 * sc1200_set_pio_mode() handles setting of PIO modes
 * for both the chipset and drive.
 *
 * All existing BIOSs for this chipset guarantee that all drives
 * will have valid default PIO timings set up before we get here.
 */

static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	int		mode = -1;
	const u8	pio = drive->pio_mode - XFER_PIO_0;

	/*
	 * bad abuse of ->set_pio_mode interface
	 */
	switch (pio) {
		case 200: mode = XFER_UDMA_0;	break;
		case 201: mode = XFER_UDMA_1;	break;
		case 202: mode = XFER_UDMA_2;	break;
		case 100: mode = XFER_MW_DMA_0;	break;
		case 101: mode = XFER_MW_DMA_1;	break;
		case 102: mode = XFER_MW_DMA_2;	break;
	}
	if (mode != -1) {
		printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
		ide_dma_off_quietly(drive);
		if (ide_set_dma_mode(drive, mode) == 0 &&
		    (drive->dev_flags & IDE_DFLAG_USING_DMA))
			hwif->dma_ops->dma_host_set(drive, 1);
		return;
	}

	sc1200_tunepio(drive, pio);
}

#ifdef CONFIG_PM
struct sc1200_saved_state {
	u32 regs[8];
};

static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
{
	printk("SC1200: suspend(%u)\n", state.event);

	/*
	 * we only save state when going from full power to less
	 */
	if (state.event == PM_EVENT_ON) {
		struct ide_host *host = pci_get_drvdata(dev);
		struct sc1200_saved_state *ss = host->host_priv;
		unsigned int r;

		/*
		 * save timing registers
		 * (this may be unnecessary if BIOS also does it)
		 */
		for (r = 0; r < 8; r++)
			pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	}

	pci_disable_device(dev);
	pci_set_power_state(dev, pci_choose_state(dev, state));
	return 0;
}

static int sc1200_resume (struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct sc1200_saved_state *ss = host->host_priv;
	unsigned int r;
	int i;

	i = pci_enable_device(dev);
	if (i)
		return i;

	/*
	 * restore timing registers
	 * (this may be unnecessary if BIOS also does it)
	 */
	for (r = 0; r < 8; r++)
		pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);

	return 0;
}
#endif

static const struct ide_port_ops sc1200_port_ops = {
	.set_pio_mode		= sc1200_set_pio_mode,
	.set_dma_mode		= sc1200_set_dma_mode,
	.udma_filter		= sc1200_udma_filter,
};

static const struct ide_dma_ops sc1200_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= sc1200_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info sc1200_chipset = {
	.name		= DRV_NAME,
	.port_ops	= &sc1200_port_ops,
	.dma_ops	= &sc1200_dma_ops,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_ABUSE_DMA_MODES,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct sc1200_saved_state *ss = NULL;
	int rc;

#ifdef CONFIG_PM
	ss = kmalloc(sizeof(*ss), GFP_KERNEL);
	if (ss == NULL)
		return -ENOMEM;
#endif
	rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
	if (rc)
		kfree(ss);

	return rc;
}

static const struct pci_device_id sc1200_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);

static struct pci_driver sc1200_pci_driver = {
	.name		= "SC1200_IDE",
	.id_table	= sc1200_pci_tbl,
	.probe		= sc1200_init_one,
	.remove		= ide_pci_remove,
#ifdef CONFIG_PM
	.suspend	= sc1200_suspend,
	.resume		= sc1200_resume,
#endif
};

static int __init sc1200_ide_init(void)
{
	return ide_pci_register_driver(&sc1200_pci_driver);
}

static void __exit sc1200_ide_exit(void)
{
	pci_unregister_driver(&sc1200_pci_driver);
}

module_init(sc1200_ide_init);
module_exit(sc1200_ide_exit);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5fd216bb BZ	3	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	4	*
1da177e4 LT	5	* May be copied or modified under the terms of the GNU General Public License
	6	*
	7	* Development of this chipset driver was funded
	8	* by the nice folks at National Semiconductor.
	9	*
	10	* Documentation:
	11	* Available from National Semiconductor
	12	*/
	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
5a0e3ad6	17	#include <linux/slab.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/ide.h>
	21	#include <linux/pm.h>
78829dd9	22
1da177e4	23	#include <asm/io.h>
1da177e4	24
ced3ec8a BZ	25	#define DRV_NAME "sc1200"
ced3ec8a BZ	26
1da177e4 LT	27	#define SC1200_REV_A 0x00
	28	#define SC1200_REV_B1 0x01
	29	#define SC1200_REV_B3 0x02
	30	#define SC1200_REV_C1 0x03
	31	#define SC1200_REV_D1 0x04
	32
	33	#define PCI_CLK_33 0x00
	34	#define PCI_CLK_48 0x01
	35	#define PCI_CLK_66 0x02
	36	#define PCI_CLK_33A 0x03
	37
	38	static unsigned short sc1200_get_pci_clock (void)
	39	{
	40	unsigned char chip_id, silicon_revision;
	41	unsigned int pci_clock;
	42	/*
	43	* Check the silicon revision, as not all versions of the chip
	44	* have the register with the fast PCI bus timings.
	45	*/
	46	chip_id = inb (0x903c);
	47	silicon_revision = inb (0x903d);
	48
	49	// Read the fast pci clock frequency
	50	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
	51	pci_clock = PCI_CLK_33;
	52	} else {
	53	// check clock generator configuration (cfcc)
	54	// the clock is in bits 8 and 9 of this word
	55
	56	pci_clock = inw (0x901e);
	57	pci_clock >>= 8;
	58	pci_clock &= 0x03;
	59	if (pci_clock == PCI_CLK_33A)
	60	pci_clock = PCI_CLK_33;
	61	}
	62	return pci_clock;
	63	}
	64
1da177e4 LT	65	/*
	66	* Here are the standard PIO mode 0-4 timings for each "format".
	67	* Format-0 uses fast data reg timings, with slower command reg timings.
	68	* Format-1 uses fast timings for all registers, but won't work with all drives.
	69	*/
	70	static const unsigned int sc1200_pio_timings[4][5] =
	71	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
	72	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
	73	{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
	74	{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
	75
	76	/*
	77	* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
	78	*/
	79	//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
	80
3c3f5d2c BZ	81	static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
	82	{
	83	ide_hwif_t *hwif = drive->hwif;
36501650	84	struct pci_dev *pdev = to_pci_dev(hwif->dev);
3c3f5d2c BZ	85	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
	86
	87	pci_read_config_dword(pdev, basereg + 4, &format);
	88	format = (format >> 31) & 1;
	89	if (format)
	90	format += sc1200_get_pci_clock();
	91	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
	92	sc1200_pio_timings[format][pio]);
	93	}
	94
5fd216bb BZ	95	/*
	96	* The SC1200 specifies that two drives sharing a cable cannot mix
	97	* UDMA/MDMA. It has to be one or the other, for the pair, though
	98	* different timings can still be chosen for each drive. We could
	99	* set the appropriate timing bits on the fly, but that might be
	100	* a bit confusing. So, for now we statically handle this requirement
	101	* by looking at our mate drive to see what it is capable of, before
	102	* choosing a mode for our own drive.
	103	*/
	104	static u8 sc1200_udma_filter(ide_drive_t *drive)
1da177e4	105	{
5fd216bb	106	ide_hwif_t *hwif = drive->hwif;
7e59ea21	107	ide_drive_t *mate = ide_get_pair_dev(drive);
9ecab6e5	108	u16 *mateid;
5fd216bb BZ	109	u8 mask = hwif->ultra_mask;
5fd216bb BZ	110
7e59ea21	111	if (mate == NULL)
5fd216bb	112	goto out;
9ecab6e5	113	mateid = mate->id;
5fd216bb	114
48fb2688	115	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
4dde4492 BZ	116	if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
4dde4492 BZ	117	(mateid[ATA_ID_UDMA_MODES] & 7))
5fd216bb	118	goto out;
8d64fcd9	119	if (mateid[ATA_ID_MWDMA_MODES] & 7)
5fd216bb	120	mask = 0;
1da177e4	121	}
5fd216bb BZ	122	out:
5fd216bb BZ	123	return mask;
1da177e4 LT	124	}
1da177e4 LT	125
8776168c	126	static void sc1200_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	127	{
36501650	128	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	129	unsigned int reg, timings;
	130	unsigned short pci_clock;
	131	unsigned int basereg = hwif->channel ? 0x50 : 0x40;
8776168c	132	const u8 mode = drive->dma_mode;
1da177e4	133
4eed504d BZ	134	static const u32 udma_timing[3][3] = {
	135	{ 0x00921250, 0x00911140, 0x00911030 },
	136	{ 0x00932470, 0x00922260, 0x00922140 },
	137	{ 0x009436a1, 0x00933481, 0x00923261 },
	138	};
	139
	140	static const u32 mwdma_timing[3][3] = {
	141	{ 0x00077771, 0x00012121, 0x00002020 },
	142	{ 0x000bbbb2, 0x00024241, 0x00013131 },
	143	{ 0x000ffff3, 0x00035352, 0x00015151 },
	144	};
	145
1da177e4 LT	146	pci_clock = sc1200_get_pci_clock();
	147
	148	/*
1da177e4 LT	149	* Note that each DMA mode has several timings associated with it.
	150	* The correct timing depends on the fast PCI clock freq.
	151	*/
4eed504d BZ	152
	153	if (mode >= XFER_UDMA_0)
	154	timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
	155	else
	156	timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
1da177e4	157
123995b9	158	if ((drive->dn & 1) == 0) {
36501650	159	pci_read_config_dword(dev, basereg + 4, &reg);
1da177e4	160	timings \|= reg & 0x80000000; /* preserve PIO format bit */
36501650 BZ	161	pci_write_config_dword(dev, basereg + 4, timings);
	162	} else
	163	pci_write_config_dword(dev, basereg + 12, timings);
1da177e4 LT	164	}
1da177e4 LT	165
1da177e4 LT	166	/* Replacement for the standard ide_dma_end action in
	167	* dma_proc.
	168	*
	169	* returns 1 on error, 0 otherwise
	170	*/
5e37bdc0	171	static int sc1200_dma_end(ide_drive_t *drive)
1da177e4	172	{
898ec223	173	ide_hwif_t *hwif = drive->hwif;
1da177e4	174	unsigned long dma_base = hwif->dma_base;
9892ec54	175	u8 dma_stat;
1da177e4 LT	176
	177	dma_stat = inb(dma_base+2); /* get DMA status */
	178
	179	if (!(dma_stat & 4))
	180	printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
	181	dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
	182
	183	outb(dma_stat\|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
	184	outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
	185
1da177e4 LT	186	return (dma_stat & 7) != 4; /* verify good DMA status */
	187	}
	188
	189	/*
26bcb879	190	* sc1200_set_pio_mode() handles setting of PIO modes
1da177e4 LT	191	* for both the chipset and drive.
	192	*
	193	* All existing BIOSs for this chipset guarantee that all drives
	194	* will have valid default PIO timings set up before we get here.
	195	*/
26bcb879	196
e085b3ca	197	static void sc1200_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	198	{
1da177e4	199	int mode = -1;
e085b3ca	200	const u8 pio = drive->pio_mode - XFER_PIO_0;
1da177e4	201
a01ba401	202	/*
26bcb879	203	* bad abuse of ->set_pio_mode interface
a01ba401	204	*/
1da177e4 LT	205	switch (pio) {
	206	case 200: mode = XFER_UDMA_0; break;
	207	case 201: mode = XFER_UDMA_1; break;
	208	case 202: mode = XFER_UDMA_2; break;
	209	case 100: mode = XFER_MW_DMA_0; break;
	210	case 101: mode = XFER_MW_DMA_1; break;
	211	case 102: mode = XFER_MW_DMA_2; break;
	212	}
	213	if (mode != -1) {
	214	printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
4a546e04	215	ide_dma_off_quietly(drive);
97100fc8 BZ	216	if (ide_set_dma_mode(drive, mode) == 0 &&
97100fc8 BZ	217	(drive->dev_flags & IDE_DFLAG_USING_DMA))
5e37bdc0	218	hwif->dma_ops->dma_host_set(drive, 1);
1da177e4 LT	219	return;
	220	}
	221
88b2b32b	222	sc1200_tunepio(drive, pio);
1da177e4 LT	223	}
1da177e4 LT	224
b86cc29d	225	#ifdef CONFIG_PM
7c0e2666 BZ	226	struct sc1200_saved_state {
	227	u32 regs[8];
	228	};
1da177e4	229
3bfffd97	230	static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
1da177e4	231	{
ca078bae	232	printk("SC1200: suspend(%u)\n", state.event);
1da177e4	233
7c0e2666 BZ	234	/*
	235	* we only save state when going from full power to less
	236	*/
ca078bae	237	if (state.event == PM_EVENT_ON) {
96776f3b BZ	238	struct ide_host *host = pci_get_drvdata(dev);
96776f3b BZ	239	struct sc1200_saved_state *ss = host->host_priv;
7c0e2666 BZ	240	unsigned int r;
7c0e2666 BZ	241
7c0e2666 BZ	242	/*
	243	* save timing registers
	244	* (this may be unnecessary if BIOS also does it)
	245	*/
	246	for (r = 0; r < 8; r++)
	247	pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	248	}
1da177e4 LT	249
1da177e4 LT	250	pci_disable_device(dev);
ca078bae	251	pci_set_power_state(dev, pci_choose_state(dev, state));
1da177e4 LT	252	return 0;
	253	}
	254
	255	static int sc1200_resume (struct pci_dev *dev)
	256	{
96776f3b BZ	257	struct ide_host *host = pci_get_drvdata(dev);
96776f3b BZ	258	struct sc1200_saved_state *ss = host->host_priv;
7c0e2666 BZ	259	unsigned int r;
7c0e2666 BZ	260	int i;
9d434813 JG	261
	262	i = pci_enable_device(dev);
	263	if (i)
	264	return i;
1da177e4	265
7c0e2666 BZ	266	/*
	267	* restore timing registers
	268	* (this may be unnecessary if BIOS also does it)
	269	*/
96776f3b BZ	270	for (r = 0; r < 8; r++)
96776f3b BZ	271	pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
7c0e2666	272
1da177e4 LT	273	return 0;
1da177e4 LT	274	}
b86cc29d	275	#endif
1da177e4	276
ac95beed BZ	277	static const struct ide_port_ops sc1200_port_ops = {
	278	.set_pio_mode = sc1200_set_pio_mode,
	279	.set_dma_mode = sc1200_set_dma_mode,
	280	.udma_filter = sc1200_udma_filter,
	281	};
	282
f37afdac BZ	283	static const struct ide_dma_ops sc1200_dma_ops = {
	284	.dma_host_set = ide_dma_host_set,
	285	.dma_setup = ide_dma_setup,
f37afdac	286	.dma_start = ide_dma_start,
5e37bdc0	287	.dma_end = sc1200_dma_end,
f37afdac BZ	288	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	289	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	290	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	291	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	292	};
5e37bdc0 BZ	293
fe31edc8	294	static const struct ide_port_info sc1200_chipset = {
ced3ec8a	295	.name = DRV_NAME,
ac95beed	296	.port_ops = &sc1200_port_ops,
5e37bdc0	297	.dma_ops = &sc1200_dma_ops,
1c51361a BZ	298	.host_flags = IDE_HFLAG_SERIALIZE \|
1c51361a BZ	299	IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	300	IDE_HFLAG_ABUSE_DMA_MODES,
4099d143	301	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	302	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	303	.udma_mask = ATA_UDMA2,
1da177e4 LT	304	};
1da177e4 LT	305
fe31edc8	306	static int sc1200_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	307	{
96776f3b BZ	308	struct sc1200_saved_state *ss = NULL;
	309	int rc;
	310
	311	#ifdef CONFIG_PM
	312	ss = kmalloc(sizeof(*ss), GFP_KERNEL);
	313	if (ss == NULL)
	314	return -ENOMEM;
	315	#endif
	316	rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
	317	if (rc)
	318	kfree(ss);
	319
	320	return rc;
1da177e4 LT	321	}
1da177e4 LT	322
9cbcc5e3 BZ	323	static const struct pci_device_id sc1200_pci_tbl[] = {
9cbcc5e3 BZ	324	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
1da177e4 LT	325	{ 0, },
	326	};
	327	MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
	328
a9ab09e2	329	static struct pci_driver sc1200_pci_driver = {
1da177e4 LT	330	.name = "SC1200_IDE",
	331	.id_table = sc1200_pci_tbl,
	332	.probe = sc1200_init_one,
991f5e69	333	.remove = ide_pci_remove,
b86cc29d	334	#ifdef CONFIG_PM
1da177e4 LT	335	.suspend = sc1200_suspend,
1da177e4 LT	336	.resume = sc1200_resume,
b86cc29d	337	#endif
1da177e4 LT	338	};
1da177e4 LT	339
82ab1eec	340	static int __init sc1200_ide_init(void)
1da177e4	341	{
a9ab09e2	342	return ide_pci_register_driver(&sc1200_pci_driver);
1da177e4 LT	343	}
1da177e4 LT	344
991f5e69 BZ	345	static void __exit sc1200_ide_exit(void)
991f5e69 BZ	346	{
a9ab09e2	347	pci_unregister_driver(&sc1200_pci_driver);
991f5e69 BZ	348	}
991f5e69 BZ	349
1da177e4	350	module_init(sc1200_ide_init);
991f5e69	351	module_exit(sc1200_ide_exit);
1da177e4 LT	352
	353	MODULE_AUTHOR("Mark Lord");
	354	MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
	355	MODULE_LICENSE("GPL");