[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / q40ide.c

/*
 *  Q40 I/O port IDE Driver
 *
 *     (c) Richard Zidlicky
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive for
 *  more details.
 *
 *
 */

#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/ide.h>
#include <linux/module.h>

#include <asm/ide.h>

    /*
     *  Bases of the IDE interfaces
     */

#define Q40IDE_NUM_HWIFS	2

#define PCIDE_BASE1	0x1f0
#define PCIDE_BASE2	0x170
#define PCIDE_BASE3	0x1e8
#define PCIDE_BASE4	0x168
#define PCIDE_BASE5	0x1e0
#define PCIDE_BASE6	0x160

static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
    PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
    PCIDE_BASE6 */
};

static int q40ide_default_irq(unsigned long base)
{
           switch (base) {
	            case 0x1f0: return 14;
		    case 0x170: return 15;
		    case 0x1e8: return 11;
		    default:
			return 0;
	   }
}


/*
 * Addresses are pretranslated for Q40 ISA access.
 */
static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq)
{
	memset(hw, 0, sizeof(*hw));
	/* BIG FAT WARNING: 
	   assumption: only DATA port is ever used in 16 bit mode */
	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);

	hw->irq = irq;
}

static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
			      void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
		__ide_mm_insw(data_addr, buf, (len + 1) / 2);
		return;
	}

	raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
}

static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
			       void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
		__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
		return;
	}

	raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
}

/* Q40 has a byte-swapped IDE interface */
static const struct ide_tp_ops q40ide_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ide_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= q40ide_input_data,
	.output_data		= q40ide_output_data,
};

static const struct ide_port_info q40ide_port_info = {
	.tp_ops			= &q40ide_tp_ops,
	.host_flags		= IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
	.irq_flags		= IRQF_SHARED,
	.chipset		= ide_generic,
};

/* 
 * the static array is needed to have the name reported in /proc/ioports,
 * hwif->name unfortunately isn't available yet
 */
static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	"ide0", "ide1"
};

/*
 *  Probe for Q40 IDE interfaces
 */

static int __init q40ide_init(void)
{
    int i;
    struct ide_hw hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL };

    if (!MACH_IS_Q40)
      return -ENODEV;

    printk(KERN_INFO "ide: Q40 IDE controller\n");

    for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
	const char *name = q40_ide_names[i];

	if (!request_region(pcide_bases[i], 8, name)) {
		printk("could not reserve ports %lx-%lx for %s\n",
		       pcide_bases[i],pcide_bases[i]+8,name);
		continue;
	}
	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
		printk("could not reserve port %lx for %s\n",
		       pcide_bases[i]+0x206,name);
		release_region(pcide_bases[i], 8);
		continue;
	}
	q40_ide_setup_ports(&hw[i], pcide_bases[i],
			q40ide_default_irq(pcide_bases[i]));

	hws[i] = &hw[i];
    }

    return ide_host_add(&q40ide_port_info, hws, Q40IDE_NUM_HWIFS, NULL);
}

module_init(q40ide_init);

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
58f189fc	2	* Q40 I/O port IDE Driver
1da177e4 LT	3	*
	4	* (c) Richard Zidlicky
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file COPYING in the main directory of this archive for
	8	* more details.
	9	*
	10	*
	11	*/
	12
	13	#include <linux/types.h>
	14	#include <linux/mm.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/blkdev.h>
1da177e4	17	#include <linux/ide.h>
bff7832d	18	#include <linux/module.h>
1da177e4	19
d1881207 GU	20	#include <asm/ide.h>
d1881207 GU	21
1da177e4 LT	22	/*
	23	* Bases of the IDE interfaces
	24	*/
	25
	26	#define Q40IDE_NUM_HWIFS 2
	27
	28	#define PCIDE_BASE1 0x1f0
	29	#define PCIDE_BASE2 0x170
	30	#define PCIDE_BASE3 0x1e8
	31	#define PCIDE_BASE4 0x168
	32	#define PCIDE_BASE5 0x1e0
	33	#define PCIDE_BASE6 0x160
	34
	35	static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
	36	PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
	37	PCIDE_BASE6 */
	38	};
	39
1da177e4 LT	40	static int q40ide_default_irq(unsigned long base)
	41	{
	42	switch (base) {
	43	case 0x1f0: return 14;
	44	case 0x170: return 15;
	45	case 0x1e8: return 11;
	46	default:
	47	return 0;
	48	}
	49	}
	50
	51
	52	/*
29dd5975	53	* Addresses are pretranslated for Q40 ISA access.
1da177e4	54	*/
f4d3ffa5	55	static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq)
1da177e4	56	{
9f36d314	57	memset(hw, 0, sizeof(*hw));
d28aa3ac AV	58	/* BIG FAT WARNING:
	59	assumption: only DATA port is ever used in 16 bit mode */
	60	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	61	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	62	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	63	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	64	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	65	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	66	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	67	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	68	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
86f3a492	69
1da177e4	70	hw->irq = irq;
1da177e4 LT	71	}
1da177e4 LT	72
adb1af98	73	static void q40ide_input_data(ide_drive_t drive, struct ide_cmd cmd,
9567b349	74	void *buf, unsigned int len)
92d3ab27	75	{
9567b349	76	unsigned long data_addr = drive->hwif->io_ports.data_addr;
92d3ab27	77
d1881207 GU	78	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
	79	__ide_mm_insw(data_addr, buf, (len + 1) / 2);
	80	return;
	81	}
92d3ab27	82
f94116ae	83	raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
92d3ab27 BZ	84	}
92d3ab27 BZ	85
adb1af98	86	static void q40ide_output_data(ide_drive_t drive, struct ide_cmd cmd,
9567b349	87	void *buf, unsigned int len)
92d3ab27	88	{
9567b349 BZ	89	unsigned long data_addr = drive->hwif->io_ports.data_addr;
9567b349 BZ	90
d1881207 GU	91	if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
	92	__ide_mm_outsw(data_addr, buf, (len + 1) / 2);
	93	return;
	94	}
92d3ab27	95
f94116ae	96	raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
92d3ab27	97	}
1da177e4	98
374e042c BZ	99	/* Q40 has a byte-swapped IDE interface */
	100	static const struct ide_tp_ops q40ide_tp_ops = {
	101	.exec_command = ide_exec_command,
	102	.read_status = ide_read_status,
	103	.read_altstatus = ide_read_altstatus,
ecf3a31d	104	.write_devctl = ide_write_devctl,
374e042c	105
abb596b2	106	.dev_select = ide_dev_select,
374e042c BZ	107	.tf_load = ide_tf_load,
	108	.tf_read = ide_tf_read,
	109
	110	.input_data = q40ide_input_data,
	111	.output_data = q40ide_output_data,
	112	};
	113
	114	static const struct ide_port_info q40ide_port_info = {
	115	.tp_ops = &q40ide_tp_ops,
09a3e791	116	.host_flags = IDE_HFLAG_MMIO \| IDE_HFLAG_NO_DMA,
255115fb	117	.irq_flags = IRQF_SHARED,
29e52cf7	118	.chipset = ide_generic,
374e042c BZ	119	};
374e042c BZ	120
1da177e4 LT	121	/*
1da177e4 LT	122	* the static array is needed to have the name reported in /proc/ioports,
96de0e25	123	* hwif->name unfortunately isn't available yet
1da177e4 LT	124	*/
	125	static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	126	"ide0", "ide1"
	127	};
	128
	129	/*
	130	* Probe for Q40 IDE interfaces
	131	*/
	132
ade2daf9	133	static int __init q40ide_init(void)
1da177e4 LT	134	{
1da177e4 LT	135	int i;
9f36d314	136	struct ide_hw hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL };
1da177e4 LT	137
1da177e4 LT	138	if (!MACH_IS_Q40)
ade2daf9	139	return -ENODEV;
1da177e4	140
c99c92c5 BZ	141	printk(KERN_INFO "ide: Q40 IDE controller\n");
c99c92c5 BZ	142
1da177e4	143	for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
c97c6aca	144	const char *name = q40_ide_names[i];
1da177e4	145
1da177e4 LT	146	if (!request_region(pcide_bases[i], 8, name)) {
	147	printk("could not reserve ports %lx-%lx for %s\n",
	148	pcide_bases[i],pcide_bases[i]+8,name);
	149	continue;
	150	}
	151	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
	152	printk("could not reserve port %lx for %s\n",
	153	pcide_bases[i]+0x206,name);
	154	release_region(pcide_bases[i], 8);
	155	continue;
	156	}
f4d3ffa5	157	q40_ide_setup_ports(&hw[i], pcide_bases[i],
1da177e4	158	q40ide_default_irq(pcide_bases[i]));
cbb010c1	159
48c3c107	160	hws[i] = &hw[i];
1da177e4	161	}
8ac4ce74	162
dca39830	163	return ide_host_add(&q40ide_port_info, hws, Q40IDE_NUM_HWIFS, NULL);
1da177e4 LT	164	}
1da177e4 LT	165
ade2daf9	166	module_init(q40ide_init);
f743d04d AB	167
f743d04d AB	168	MODULE_LICENSE("GPL");