[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007, 2009	MontaVista Software, Inc.
 *  Copyright (C) 2007-2010		Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "pdc202xx_old"

static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);
	const u8 speed		= drive->dma_mode;

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}
}

static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	drive->dma_mode = drive->pio_mode;
	pdc202xx_set_mode(hwif, drive);
}

static int pdc202xx_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long high_16	= pci_resource_start(dev, 4);
	u8 sc1d			= inb(high_16 + 0x1d);

	if (hwif->channel) {
		/*
		 * bit 7: error, bit 6: interrupting,
		 * bit 5: FIFO full, bit 4: FIFO empty
		 */
		return (sc1d & 0x40) ? 1 : 0;
	} else	{
		/*
		 * bit 3: error, bit 2: interrupting,
		 * bit 1: FIFO full, bit 0: FIFO empty
		 */
		return (sc1d & 0x04) ? 1 : 0;
	}
}

static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc2026x_init_hwif(ide_hwif_t *hwif)
{
	pdc_old_disable_66MHz_clock(hwif);
}

static void pdc202xx_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		struct request *rq	= hwif->rq;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (blk_rq_sectors(rq) << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
		ide_hwif_t *hwif	= drive->hwif;
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return ide_dma_end(drive);
}

static int init_chipset_pdc202xx(struct pci_dev *dev)
{
	unsigned long dmabase = pci_resource_start(dev, 4);
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (dmabase == 0)
		goto out;

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", pci_name(dev),
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			pci_name(dev), udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
out:
	return 0;
}

static void pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s %s: PCI config space interrupt "
				"mirror fixed\n", name, pci_name(dev));
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.test_irq		= pdc202xx_test_irq,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.test_irq		= pdc202xx_test_irq,
	.cable_detect		= pdc2026x_cable_detect,
};

static const struct ide_dma_ops pdc2026x_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= pdc202xx_dma_start,
	.dma_end		= pdc202xx_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

#define DECLARE_PDC2026X_DEV(udma, sectors) \
	{ \
		.name		= DRV_NAME, \
		.init_chipset	= init_chipset_pdc202xx, \
		.init_hwif	= pdc2026x_init_hwif, \
		.port_ops	= &pdc2026x_port_ops, \
		.dma_ops	= &pdc2026x_dma_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
		.max_sectors	= sectors, \
	}

static const struct ide_port_info pdc202xx_chipsets[] = {
	{	/* 0: PDC20246 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.dma_ops	= &sff_dma_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1: PDC2026{2,3} */
	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int pdc202xx_init_one(struct pci_dev *dev,
			     const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 2)
		pdc202ata4_fixup_irq(dev, d->name);

	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO DRV_NAME " %s: skipping Promise "
				"PDC20265 attached to I2O RAID controller\n",
				pci_name(dev));
			return -ENODEV;
		}
	}

	return ide_pci_init_one(dev, d, NULL);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver pdc202xx_pci_driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_ide_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

module_init(pdc202xx_ide_init);
module_exit(pdc202xx_ide_exit);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
669165da	3	* Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
a337c227	4	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/ide.h>
	19
	20	#include <asm/io.h>
1da177e4	21
ced3ec8a BZ	22	#define DRV_NAME "pdc202xx_old"
ced3ec8a BZ	23
8776168c	24	static void pdc202xx_set_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	25	{
36501650	26	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	27	u8 drive_pci = 0x60 + (drive->dn << 2);
8776168c	28	const u8 speed = drive->dma_mode;
1da177e4	29
4fce3164	30	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	31	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	32
4fce3164 BZ	33	pci_read_config_byte(dev, drive_pci, &AP);
	34	pci_read_config_byte(dev, drive_pci + 1, &BP);
	35	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	36
1da177e4 LT	37	switch(speed) {
1da177e4 LT	38	case XFER_UDMA_5:
	39	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	40	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	41	case XFER_UDMA_3:
	42	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	43	case XFER_UDMA_0:
	44	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	45	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	46	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	47	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	48	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	49	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	50	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	51	case XFER_PIO_0:
	52	default: TA = 0x09; TB = 0x13; break;
	53	}
	54
	55	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	56	/*
	57	* preserve SYNC_INT / ERDDY_EN bits while clearing
	58	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	59	*/
	60	AP &= ~0x3f;
c9ef59ff	61	if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
4fce3164 BZ	62	AP \|= 0x20; /* set IORDY_EN bit */
	63	if (drive->media == ide_disk)
	64	AP \|= 0x10; /* set Prefetch_EN bit */
	65	/* clear PB[4:0] bits of register B */
	66	BP &= ~0x1f;
	67	pci_write_config_byte(dev, drive_pci, AP \| TA);
	68	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	69	} else {
4fce3164 BZ	70	/* clear MB[2:0] bits of register B */
	71	BP &= ~0xe0;
	72	/* clear MC[3:0] bits of register C */
	73	CP &= ~0x0f;
	74	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	75	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4	76	}
1da177e4 LT	77	}
1da177e4 LT	78
e085b3ca	79	static void pdc202xx_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	80	{
8776168c BZ	81	drive->dma_mode = drive->pio_mode;
8776168c BZ	82	pdc202xx_set_mode(hwif, drive);
1da177e4 LT	83	}
1da177e4 LT	84
e0321fbe SS	85	static int pdc202xx_test_irq(ide_hwif_t *hwif)
	86	{
	87	struct pci_dev *dev = to_pci_dev(hwif->dev);
	88	unsigned long high_16 = pci_resource_start(dev, 4);
	89	u8 sc1d = inb(high_16 + 0x1d);
	90
	91	if (hwif->channel) {
	92	/*
	93	* bit 7: error, bit 6: interrupting,
	94	* bit 5: FIFO full, bit 4: FIFO empty
	95	*/
f693be4d	96	return (sc1d & 0x40) ? 1 : 0;
e0321fbe SS	97	} else {
	98	/*
	99	* bit 3: error, bit 2: interrupting,
	100	* bit 1: FIFO full, bit 0: FIFO empty
	101	*/
f693be4d	102	return (sc1d & 0x04) ? 1 : 0;
e0321fbe SS	103	}
	104	}
	105
f454cbe8	106	static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	107	{
36501650	108	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	109	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	110
36501650	111	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	112
49521f97 BZ	113	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	114	}
	115
	116	/*
	117	* Set the control register to use the 66MHz system
	118	* clock for UDMA 3/4/5 mode operation when necessary.
	119	*
4fce3164 BZ	120	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	121	*
1da177e4 LT	122	* It may also be possible to leave the 66MHz clock on
	123	* and readjust the timing parameters.
	124	*/
	125	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	126	{
1c029fd6	127	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	128	u8 clock = inb(clock_reg);
1da177e4	129
0ecdca26	130	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	131	}
	132
	133	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	134	{
1c029fd6	135	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	136	u8 clock = inb(clock_reg);
1da177e4	137
0ecdca26	138	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	139	}
1da177e4 LT	140
a337c227 BZ	141	static void pdc2026x_init_hwif(ide_hwif_t *hwif)
	142	{
	143	pdc_old_disable_66MHz_clock(hwif);
	144	}
	145
5e37bdc0	146	static void pdc202xx_dma_start(ide_drive_t *drive)
1da177e4 LT	147	{
	148	if (drive->current_speed > XFER_UDMA_2)
	149	pdc_old_enable_66MHz_clock(drive->hwif);
97100fc8	150	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	151	ide_hwif_t *hwif = drive->hwif;
b65fac32	152	struct request *rq = hwif->rq;
1c029fd6	153	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	154	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	155	u32 word_count = 0;
0ecdca26	156	u8 clock = inb(high_16 + 0x11);
1da177e4	157
0ecdca26	158	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
9780e2dd	159	word_count = (blk_rq_sectors(rq) << 8);
1da177e4 LT	160	word_count = (rq_data_dir(rq) == READ) ?
	161	word_count \| 0x05000000 :
	162	word_count \| 0x06000000;
0ecdca26	163	outl(word_count, atapi_reg);
1da177e4 LT	164	}
	165	ide_dma_start(drive);
	166	}
	167
5e37bdc0	168	static int pdc202xx_dma_end(ide_drive_t *drive)
1da177e4	169	{
97100fc8	170	if (drive->media != ide_disk \|\| (drive->dev_flags & IDE_DFLAG_LBA48)) {
898ec223	171	ide_hwif_t *hwif = drive->hwif;
1c029fd6	172	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	173	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	174	u8 clock = 0;
	175
0ecdca26 BZ	176	outl(0, atapi_reg); /* zero out extra */
	177	clock = inb(high_16 + 0x11);
	178	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	179	}
	180	if (drive->current_speed > XFER_UDMA_2)
	181	pdc_old_disable_66MHz_clock(drive->hwif);
653bcf52	182	return ide_dma_end(drive);
1da177e4 LT	183	}
1da177e4 LT	184
2ed0ef54	185	static int init_chipset_pdc202xx(struct pci_dev *dev)
1da177e4	186	{
73369d2a	187	unsigned long dmabase = pci_resource_start(dev, 4);
1da177e4 LT	188	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
1da177e4 LT	189
73369d2a BZ	190	if (dmabase == 0)
73369d2a BZ	191	goto out;
1da177e4	192
0ecdca26 BZ	193	udma_speed_flag = inb(dmabase \| 0x1f);
	194	primary_mode = inb(dmabase \| 0x1a);
	195	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	196	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
1da177e4 LT	197	"Primary %s Mode " \
5e59c236	198	"Secondary %s Mode.\n", pci_name(dev),
1da177e4 LT	199	(udma_speed_flag & 1) ? "EN" : "DIS",
	200	(primary_mode & 1) ? "MASTER" : "PCI",
	201	(secondary_mode & 1) ? "MASTER" : "PCI" );
	202
1da177e4 LT	203	if (!(udma_speed_flag & 1)) {
1da177e4 LT	204	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
5e59c236	205	pci_name(dev), udma_speed_flag,
1da177e4	206	(udma_speed_flag\|1));
0ecdca26 BZ	207	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	208	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	209	}
73369d2a	210	out:
2ed0ef54	211	return 0;
1da177e4 LT	212	}
1da177e4 LT	213
fe31edc8	214	static void pdc202ata4_fixup_irq(struct pci_dev dev, const char name)
1da177e4 LT	215	{
	216	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	217	u8 irq = 0, irq2 = 0;
	218	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	219	/* 0xbc */
	220	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	221	if (irq != irq2) {
	222	pci_write_config_byte(dev,
	223	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
28cfd8af BZ	224	printk(KERN_INFO "%s %s: PCI config space interrupt "
28cfd8af BZ	225	"mirror fixed\n", name, pci_name(dev));
1da177e4 LT	226	}
1da177e4 LT	227	}
1da177e4 LT	228	}
1da177e4 LT	229
4db90a14 BZ	230	#define IDE_HFLAGS_PDC202XX \
4db90a14 BZ	231	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
4db90a14 BZ	232	IDE_HFLAG_OFF_BOARD)
4db90a14 BZ	233
ac95beed BZ	234	static const struct ide_port_ops pdc20246_port_ops = {
	235	.set_pio_mode = pdc202xx_set_pio_mode,
	236	.set_dma_mode = pdc202xx_set_mode,
e0321fbe	237	.test_irq = pdc202xx_test_irq,
ac95beed BZ	238	};
	239
	240	static const struct ide_port_ops pdc2026x_port_ops = {
	241	.set_pio_mode = pdc202xx_set_pio_mode,
	242	.set_dma_mode = pdc202xx_set_mode,
63e7cf91	243	.test_irq = pdc202xx_test_irq,
ac95beed BZ	244	.cable_detect = pdc2026x_cable_detect,
	245	};
	246
f37afdac BZ	247	static const struct ide_dma_ops pdc2026x_dma_ops = {
	248	.dma_host_set = ide_dma_host_set,
	249	.dma_setup = ide_dma_setup,
5e37bdc0 BZ	250	.dma_start = pdc202xx_dma_start,
5e37bdc0 BZ	251	.dma_end = pdc202xx_dma_end,
72b9304f	252	.dma_test_irq = ide_dma_test_irq,
1221e241	253	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	254	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	255	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	256	};
5e37bdc0 BZ	257
6b492496	258	#define DECLARE_PDC2026X_DEV(udma, sectors) \
5ef8cb5d	259	{ \
ced3ec8a	260	.name = DRV_NAME, \
5ef8cb5d	261	.init_chipset = init_chipset_pdc202xx, \
a337c227	262	.init_hwif = pdc2026x_init_hwif, \
ac95beed	263	.port_ops = &pdc2026x_port_ops, \
5e37bdc0	264	.dma_ops = &pdc2026x_dma_ops, \
6b492496	265	.host_flags = IDE_HFLAGS_PDC202XX, \
5ef8cb5d BZ	266	.pio_mask = ATA_PIO4, \
	267	.mwdma_mask = ATA_MWDMA2, \
	268	.udma_mask = udma, \
6b492496	269	.max_sectors = sectors, \
5ef8cb5d BZ	270	}
5ef8cb5d BZ	271
fe31edc8	272	static const struct ide_port_info pdc202xx_chipsets[] = {
ced3ec8a BZ	273	{ /* 0: PDC20246 */
ced3ec8a BZ	274	.name = DRV_NAME,
1da177e4	275	.init_chipset = init_chipset_pdc202xx,
ac95beed	276	.port_ops = &pdc20246_port_ops,
72b9304f	277	.dma_ops = &sff_dma_ops,
4db90a14	278	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	279	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	280	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	281	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	282	},
5ef8cb5d BZ	283
ced3ec8a BZ	284	/* 1: PDC2026{2,3} */
ced3ec8a BZ	285	DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
6b492496 BZ	286	/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
6b492496 BZ	287	DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
1da177e4 LT	288	};
	289
	290	/**
	291	* pdc202xx_init_one - called when a PDC202xx is found
	292	* @dev: the pdc202xx device
	293	* @id: the matching pci id
	294	*
	295	* Called when the PCI registration layer (or the IDE initialization)
	296	* finds a device matching our IDE device tables.
	297	*/
	298
fe31edc8 GKH	299	static int pdc202xx_init_one(struct pci_dev *dev,
fe31edc8 GKH	300	const struct pci_device_id *id)
1da177e4	301	{
85620436	302	const struct ide_port_info *d;
97f84baa BZ	303	u8 idx = id->driver_data;
	304
	305	d = &pdc202xx_chipsets[idx];
	306
ced3ec8a	307	if (idx < 2)
97f84baa BZ	308	pdc202ata4_fixup_irq(dev, d->name);
97f84baa BZ	309
ced3ec8a	310	if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
97f84baa	311	struct pci_dev *bridge = dev->bus->self;
1da177e4	312
97f84baa BZ	313	if (bridge &&
	314	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	315	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	316	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
ced3ec8a	317	printk(KERN_INFO DRV_NAME " %s: skipping Promise "
28cfd8af BZ	318	"PDC20265 attached to I2O RAID controller\n",
28cfd8af BZ	319	pci_name(dev));
97f84baa BZ	320	return -ENODEV;
	321	}
	322	}
	323
6cdf6eb3	324	return ide_pci_init_one(dev, d, NULL);
1da177e4 LT	325	}
1da177e4 LT	326
9cbcc5e3 BZ	327	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	328	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	329	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
ced3ec8a BZ	330	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	331	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	332	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
1da177e4 LT	333	{ 0, },
	334	};
	335	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	336
a9ab09e2	337	static struct pci_driver pdc202xx_pci_driver = {
1da177e4 LT	338	.name = "Promise_Old_IDE",
	339	.id_table = pdc202xx_pci_tbl,
	340	.probe = pdc202xx_init_one,
574a1c24	341	.remove = ide_pci_remove,
feb22b7f BZ	342	.suspend = ide_pci_suspend,
feb22b7f BZ	343	.resume = ide_pci_resume,
1da177e4 LT	344	};
1da177e4 LT	345
82ab1eec	346	static int __init pdc202xx_ide_init(void)
1da177e4	347	{
a9ab09e2	348	return ide_pci_register_driver(&pdc202xx_pci_driver);
1da177e4 LT	349	}
1da177e4 LT	350
574a1c24 BZ	351	static void __exit pdc202xx_ide_exit(void)
574a1c24 BZ	352	{
a9ab09e2	353	pci_unregister_driver(&pdc202xx_pci_driver);
574a1c24 BZ	354	}
574a1c24 BZ	355
1da177e4	356	module_init(pdc202xx_ide_init);
574a1c24	357	module_exit(pdc202xx_ide_exit);
1da177e4	358
a337c227	359	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
1da177e4 LT	360	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
1da177e4 LT	361	MODULE_LICENSE("GPL");