[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / cy82c693.c

/*
 *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
 *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
 *  Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
 *
 * CYPRESS CY82C693 chipset IDE controller
 *
 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cy82c693"

/*
 *	NOTE: the value for busmaster timeout is tricky and I got it by
 *	trial and error!  By using a to low value will cause DMA timeouts
 *	and drop IDE performance, and by using a to high value will cause
 *	audio playback to scatter.
 *	If you know a better value or how to calc it, please let me know.
 */

/* twice the value written in cy82c693ub datasheet */
#define BUSMASTER_TIMEOUT	0x50
/*
 * the value above was tested on my machine and it seems to work okay
 */

/* here are the offset definitions for the registers */
#define CY82_IDE_CMDREG		0x04
#define CY82_IDE_ADDRSETUP	0x48
#define CY82_IDE_MASTER_IOR	0x4C
#define CY82_IDE_MASTER_IOW	0x4D
#define CY82_IDE_SLAVE_IOR	0x4E
#define CY82_IDE_SLAVE_IOW	0x4F
#define CY82_IDE_MASTER_8BIT	0x50
#define CY82_IDE_SLAVE_8BIT	0x51

#define CY82_INDEX_PORT		0x22
#define CY82_DATA_PORT		0x23

#define CY82_INDEX_CHANNEL0	0x30
#define CY82_INDEX_CHANNEL1	0x31
#define CY82_INDEX_TIMEOUT	0x32

/*
 * set DMA mode a specific channel for CY82C693
 */

static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	const u8 mode = drive->dma_mode;
	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;

	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;

	data = (mode & 3) | (single << 2);

	outb(index, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);

	/*
	 * note: below we set the value for Bus Master IDE TimeOut Register
	 * I'm not absolutely sure what this does, but it solved my problem
	 * with IDE DMA and sound, so I now can play sound and work with
	 * my IDE driver at the same time :-)
	 *
	 * If you know the correct (best) value for this register please
	 * let me know - ASK
	 */

	data = BUSMASTER_TIMEOUT;
	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
	outb(data, CY82_DATA_PORT);
}

static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	const unsigned long T = 1000000 / bus_speed;
	unsigned int addrCtrl;
	struct ide_timing t;
	u8 time_16, time_8;

	/* select primary or secondary channel */
	if (drive->dn > 1) {  /* drive is on the secondary channel */
		dev = pci_get_slot(dev->bus, dev->devfn+1);
		if (!dev) {
			printk(KERN_ERR "%s: tune_drive: "
				"Cannot find secondary interface!\n",
				drive->name);
			return;
		}
	}

	ide_timing_compute(drive, drive->pio_mode, &t, T, 1);

	time_16 = clamp_val(t.recover - 1, 0, 15) |
		  (clamp_val(t.active - 1, 0, 15) << 4);
	time_8 = clamp_val(t.act8b - 1, 0, 15) |
		 (clamp_val(t.rec8b - 1, 0, 15) << 4);

	/* now let's write  the clocks registers */
	if ((drive->dn & 1) == 0) {
		/*
		 * set master drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF);
		addrCtrl |= clamp_val(t.setup - 1, 0, 15);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
		pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
		pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
	} else {
		/*
		 * set slave drive
		 * address setup control register
		 * is 32 bit !!!
		 */
		pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);

		addrCtrl &= (~0xF0);
		addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
		pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);

		/* now let's set the remaining registers */
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
		pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
	}
	if (drive->dn > 1)
		pci_dev_put(dev);
}

static void init_iops_cy82c693(ide_hwif_t *hwif)
{
	static ide_hwif_t *primary;
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_FUNC(dev->devfn) == 1)
		primary = hwif;
	else {
		hwif->mate = primary;
		hwif->channel = 1;
	}
}

static const struct ide_port_ops cy82c693_port_ops = {
	.set_pio_mode		= cy82c693_set_pio_mode,
	.set_dma_mode		= cy82c693_set_dma_mode,
};

static const struct ide_port_info cy82c693_chipset = {
	.name		= DRV_NAME,
	.init_iops	= init_iops_cy82c693,
	.port_ops	= &cy82c693_port_ops,
	.host_flags	= IDE_HFLAG_SINGLE,
	.pio_mask	= ATA_PIO4,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int cy82c693_init_one(struct pci_dev *dev,
			     const struct pci_device_id *id)
{
	struct pci_dev *dev2;
	int ret = -ENODEV;

	/* CY82C693 is more than only a IDE controller.
	   Function 1 is primary IDE channel, function 2 - secondary. */
	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
	    PCI_FUNC(dev->devfn) == 1) {
		dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
		ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
		if (ret)
			pci_dev_put(dev2);
	}
	return ret;
}

static void cy82c693_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;

	ide_pci_remove(dev);
	pci_dev_put(dev2);
}

static const struct pci_device_id cy82c693_pci_tbl[] = {
	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);

static struct pci_driver cy82c693_pci_driver = {
	.name		= "Cypress_IDE",
	.id_table	= cy82c693_pci_tbl,
	.probe		= cy82c693_init_one,
	.remove		= cy82c693_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cy82c693_ide_init(void)
{
	return ide_pci_register_driver(&cy82c693_pci_driver);
}

static void __exit cy82c693_ide_exit(void)
{
	pci_unregister_driver(&cy82c693_pci_driver);
}

module_init(cy82c693_ide_init);
module_exit(cy82c693_ide_exit);

MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
1da177e4 LT	3	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
0ab3d8b3	4	* Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
1da177e4 LT	5	*
	6	* CYPRESS CY82C693 chipset IDE controller
	7	*
	8	* The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
1da177e4 LT	9	*/
1da177e4 LT	10
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/types.h>
	13	#include <linux/pci.h>
1da177e4 LT	14	#include <linux/ide.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/io.h>
	18
ced3ec8a BZ	19	#define DRV_NAME "cy82c693"
ced3ec8a BZ	20
1da177e4 LT	21	/*
	22	* NOTE: the value for busmaster timeout is tricky and I got it by
	23	* trial and error! By using a to low value will cause DMA timeouts
	24	* and drop IDE performance, and by using a to high value will cause
	25	* audio playback to scatter.
	26	* If you know a better value or how to calc it, please let me know.
	27	*/
	28
	29	/* twice the value written in cy82c693ub datasheet */
	30	#define BUSMASTER_TIMEOUT 0x50
	31	/*
	32	* the value above was tested on my machine and it seems to work okay
	33	*/
	34
	35	/* here are the offset definitions for the registers */
	36	#define CY82_IDE_CMDREG 0x04
	37	#define CY82_IDE_ADDRSETUP 0x48
	38	#define CY82_IDE_MASTER_IOR 0x4C
	39	#define CY82_IDE_MASTER_IOW 0x4D
	40	#define CY82_IDE_SLAVE_IOR 0x4E
	41	#define CY82_IDE_SLAVE_IOW 0x4F
	42	#define CY82_IDE_MASTER_8BIT 0x50
	43	#define CY82_IDE_SLAVE_8BIT 0x51
	44
	45	#define CY82_INDEX_PORT 0x22
	46	#define CY82_DATA_PORT 0x23
	47
1da177e4 LT	48	#define CY82_INDEX_CHANNEL0 0x30
	49	#define CY82_INDEX_CHANNEL1 0x31
	50	#define CY82_INDEX_TIMEOUT 0x32
	51
1da177e4 LT	52	/*
	53	* set DMA mode a specific channel for CY82C693
	54	*/
	55
8776168c	56	static void cy82c693_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	57	{
8776168c	58	const u8 mode = drive->dma_mode;
8704de8f	59	u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
1da177e4	60
8704de8f	61	index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
1da177e4	62
8704de8f	63	data = (mode & 3) \| (single << 2);
1da177e4	64
0ecdca26 BZ	65	outb(index, CY82_INDEX_PORT);
0ecdca26 BZ	66	outb(data, CY82_DATA_PORT);
1da177e4	67
175f354b	68	/*
1da177e4	69	* note: below we set the value for Bus Master IDE TimeOut Register
25985edc	70	* I'm not absolutely sure what this does, but it solved my problem
1da177e4 LT	71	* with IDE DMA and sound, so I now can play sound and work with
	72	* my IDE driver at the same time :-)
	73	*
	74	* If you know the correct (best) value for this register please
	75	* let me know - ASK
	76	*/
	77
	78	data = BUSMASTER_TIMEOUT;
0ecdca26 BZ	79	outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
0ecdca26 BZ	80	outb(data, CY82_DATA_PORT);
1da177e4 LT	81	}
1da177e4 LT	82
e085b3ca	83	static void cy82c693_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	84	{
36501650	85	struct pci_dev *dev = to_pci_dev(hwif->dev);
4d6b3289 BZ	86	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
4d6b3289 BZ	87	const unsigned long T = 1000000 / bus_speed;
1da177e4	88	unsigned int addrCtrl;
4d6b3289 BZ	89	struct ide_timing t;
4d6b3289 BZ	90	u8 time_16, time_8;
1da177e4 LT	91
1da177e4 LT	92	/* select primary or secondary channel */
0ab3d8b3	93	if (drive->dn > 1) { /* drive is on the secondary channel */
652aa162	94	dev = pci_get_slot(dev->bus, dev->devfn+1);
1da177e4 LT	95	if (!dev) {
	96	printk(KERN_ERR "%s: tune_drive: "
	97	"Cannot find secondary interface!\n",
	98	drive->name);
	99	return;
	100	}
	101	}
	102
e085b3ca	103	ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
4d6b3289 BZ	104
	105	time_16 = clamp_val(t.recover - 1, 0, 15) \|
	106	(clamp_val(t.active - 1, 0, 15) << 4);
	107	time_8 = clamp_val(t.act8b - 1, 0, 15) \|
	108	(clamp_val(t.rec8b - 1, 0, 15) << 4);
1da177e4 LT	109
1da177e4 LT	110	/* now let's write the clocks registers */
123995b9	111	if ((drive->dn & 1) == 0) {
1da177e4 LT	112	/*
	113	* set master drive
	114	* address setup control register
	115	* is 32 bit !!!
175f354b	116	*/
1da177e4	117	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
175f354b	118
1da177e4	119	addrCtrl &= (~0xF);
4d6b3289	120	addrCtrl \|= clamp_val(t.setup - 1, 0, 15);
1da177e4 LT	121	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	122
	123	/* now let's set the remaining registers */
4d6b3289 BZ	124	pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
	125	pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
	126	pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
1da177e4 LT	127	} else {
	128	/*
	129	* set slave drive
	130	* address setup control register
	131	* is 32 bit !!!
175f354b	132	*/
1da177e4 LT	133	pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
	134
	135	addrCtrl &= (~0xF0);
4d6b3289	136	addrCtrl \|= (clamp_val(t.setup - 1, 0, 15) << 4);
1da177e4 LT	137	pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
	138
	139	/* now let's set the remaining registers */
4d6b3289 BZ	140	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
	141	pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
	142	pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
175f354b	143	}
0ab3d8b3	144	if (drive->dn > 1)
0302899e	145	pci_dev_put(dev);
1da177e4 LT	146	}
1da177e4 LT	147
fe31edc8	148	static void init_iops_cy82c693(ide_hwif_t *hwif)
1da177e4	149	{
f32d26ae	150	static ide_hwif_t *primary;
36501650	151	struct pci_dev *dev = to_pci_dev(hwif->dev);
f32d26ae	152
36501650	153	if (PCI_FUNC(dev->devfn) == 1)
1da177e4 LT	154	primary = hwif;
	155	else {
	156	hwif->mate = primary;
	157	hwif->channel = 1;
	158	}
	159	}
	160
ac95beed BZ	161	static const struct ide_port_ops cy82c693_port_ops = {
	162	.set_pio_mode = cy82c693_set_pio_mode,
	163	.set_dma_mode = cy82c693_set_dma_mode,
	164	};
	165
fe31edc8	166	static const struct ide_port_info cy82c693_chipset = {
ced3ec8a	167	.name = DRV_NAME,
7b77d864	168	.init_iops = init_iops_cy82c693,
ac95beed	169	.port_ops = &cy82c693_port_ops,
951784b6	170	.host_flags = IDE_HFLAG_SINGLE,
4099d143	171	.pio_mask = ATA_PIO4,
8704de8f BZ	172	.swdma_mask = ATA_SWDMA2,
8704de8f BZ	173	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	174	};
1da177e4 LT	175
fe31edc8 GKH	176	static int cy82c693_init_one(struct pci_dev *dev,
fe31edc8 GKH	177	const struct pci_device_id *id)
1da177e4	178	{
1da177e4 LT	179	struct pci_dev *dev2;
	180	int ret = -ENODEV;
	181
	182	/* CY82C693 is more than only a IDE controller.
	183	Function 1 is primary IDE channel, function 2 - secondary. */
175f354b	184	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
1da177e4	185	PCI_FUNC(dev->devfn) == 1) {
652aa162	186	dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
6cdf6eb3	187	ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
cd68841b BZ	188	if (ret)
cd68841b BZ	189	pci_dev_put(dev2);
1da177e4 LT	190	}
	191	return ret;
	192	}
	193
fe31edc8	194	static void cy82c693_remove(struct pci_dev *dev)
cd68841b BZ	195	{
	196	struct ide_host *host = pci_get_drvdata(dev);
	197	struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
	198
	199	ide_pci_remove(dev);
	200	pci_dev_put(dev2);
	201	}
	202
9cbcc5e3 BZ	203	static const struct pci_device_id cy82c693_pci_tbl[] = {
9cbcc5e3 BZ	204	{ PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
1da177e4 LT	205	{ 0, },
	206	};
	207	MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
	208
a9ab09e2	209	static struct pci_driver cy82c693_pci_driver = {
1da177e4 LT	210	.name = "Cypress_IDE",
	211	.id_table = cy82c693_pci_tbl,
	212	.probe = cy82c693_init_one,
fe31edc8	213	.remove = cy82c693_remove,
feb22b7f BZ	214	.suspend = ide_pci_suspend,
feb22b7f BZ	215	.resume = ide_pci_resume,
1da177e4 LT	216	};
1da177e4 LT	217
82ab1eec	218	static int __init cy82c693_ide_init(void)
1da177e4	219	{
a9ab09e2	220	return ide_pci_register_driver(&cy82c693_pci_driver);
1da177e4 LT	221	}
1da177e4 LT	222
cd68841b BZ	223	static void __exit cy82c693_ide_exit(void)
cd68841b BZ	224	{
a9ab09e2	225	pci_unregister_driver(&cy82c693_pci_driver);
cd68841b BZ	226	}
cd68841b BZ	227
1da177e4	228	module_init(cy82c693_ide_init);
cd68841b	229	module_exit(cy82c693_ide_exit);
1da177e4	230
4d6b3289	231	MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	232	MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
1da177e4 LT	233	MODULE_LICENSE("GPL");