[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / cs5530.c

/*
 * Copyright (C) 2000			Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2000			Mark Lord <mlord@pobox.com>
 * Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	CS5530 documentation available from National Semiconductor.
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define DRV_NAME "cs5530"

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static unsigned int cs5530_pio_timings[2][5] = {
	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
};

/*
 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
 */
#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
#define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))

/**
 *	cs5530_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Handles setting of PIO mode for the chipset.
 *
 *	The init_hwif_cs5530() routine guarantees that all drives
 *	will have valid default PIO timings set up before we get here.
 */

static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	unsigned long basereg = CS5530_BASEREG(hwif);
	unsigned int format = (inl(basereg + 4) >> 31) & 1;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
}

/**
 *	cs5530_udma_filter	-	UDMA filter
 *	@drive: drive
 *
 *	cs5530_udma_filter() does UDMA mask filtering for the given drive
 *	taking into the consideration capabilities of the mate device.
 *
 *	The CS5530 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 *
 *	Note: This relies on the fact we never fail from UDMA to MWDMA2
 *	but instead drop to PIO.
 */

static u8 cs5530_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = ide_get_pair_dev(drive);
	u16 *mateid;
	u8 mask = hwif->ultra_mask;

	if (mate == NULL)
		goto out;
	mateid = mate->id;

	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
		    (mateid[ATA_ID_UDMA_MODES] & 7))
			goto out;
		if (mateid[ATA_ID_MWDMA_MODES] & 7)
			mask = 0;
	}
out:
	return mask;
}

static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	unsigned long basereg;
	unsigned int reg, timings = 0;

	switch (drive->dma_mode) {
		case XFER_UDMA_0:	timings = 0x00921250; break;
		case XFER_UDMA_1:	timings = 0x00911140; break;
		case XFER_UDMA_2:	timings = 0x00911030; break;
		case XFER_MW_DMA_0:	timings = 0x00077771; break;
		case XFER_MW_DMA_1:	timings = 0x00012121; break;
		case XFER_MW_DMA_2:	timings = 0x00002020; break;
	}
	basereg = CS5530_BASEREG(hwif);
	reg = inl(basereg + 4);			/* get drive0 config register */
	timings |= reg & 0x80000000;		/* preserve PIO format bit */
	if ((drive-> dn & 1) == 0) {		/* are we configuring drive0? */
		outl(timings, basereg + 4);	/* write drive0 config register */
	} else {
		if (timings & 0x00100000)
			reg |=  0x00100000;	/* enable UDMA timings for both drives */
		else
			reg &= ~0x00100000;	/* disable UDMA timings for both drives */
		outl(reg, basereg + 4);		/* write drive0 config register */
		outl(timings, basereg + 12);	/* write drive1 config register */
	}
}

/**
 *	init_chipset_5530	-	set up 5530 bridge
 *	@dev: PCI device
 *
 *	Initialize the cs5530 bridge for reliable IDE DMA operation.
 */

static int init_chipset_cs5530(struct pci_dev *dev)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;

	if (pci_resource_start(dev, 4) == 0)
		return -EFAULT;

	dev = NULL;
	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
		goto out;
	}
	if (!cs5530_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
		goto out;
	}

	/*
	 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	 */

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/* 
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

out:
	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
}

/**
 *	init_hwif_cs5530	-	initialise an IDE channel
 *	@hwif: IDE to initialize
 *
 *	This gets invoked by the IDE driver once for each channel. It
 *	performs channel-specific pre-initialization before drive probing.
 */

static void init_hwif_cs5530 (ide_hwif_t *hwif)
{
	unsigned long basereg;
	u32 d0_timings;

	basereg = CS5530_BASEREG(hwif);
	d0_timings = inl(basereg + 0);
	if (CS5530_BAD_PIO(d0_timings))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
	if (CS5530_BAD_PIO(inl(basereg + 8)))
		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
}

static const struct ide_port_ops cs5530_port_ops = {
	.set_pio_mode		= cs5530_set_pio_mode,
	.set_dma_mode		= cs5530_set_dma_mode,
	.udma_filter		= cs5530_udma_filter,
};

static const struct ide_port_info cs5530_chipset = {
	.name		= DRV_NAME,
	.init_chipset	= init_chipset_cs5530,
	.init_hwif	= init_hwif_cs5530,
	.port_ops	= &cs5530_port_ops,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &cs5530_chipset, NULL);
}

static const struct pci_device_id cs5530_pci_tbl[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);

static struct pci_driver cs5530_pci_driver = {
	.name		= "CS5530 IDE",
	.id_table	= cs5530_pci_tbl,
	.probe		= cs5530_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cs5530_ide_init(void)
{
	return ide_pci_register_driver(&cs5530_pci_driver);
}

static void __exit cs5530_ide_exit(void)
{
	pci_unregister_driver(&cs5530_pci_driver);
}

module_init(cs5530_ide_init);
module_exit(cs5530_ide_exit);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
1da177e4	3	* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
5fd216bb BZ	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	5	*
1da177e4 LT	6	* May be copied or modified under the terms of the GNU General Public License
	7	*
	8	* Development of this chipset driver was funded
	9	* by the nice folks at National Semiconductor.
	10	*
	11	* Documentation:
	12	* CS5530 documentation available from National Semiconductor.
	13	*/
	14
1da177e4 LT	15	#include <linux/module.h>
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/ide.h>
78829dd9	21
1da177e4	22	#include <asm/io.h>
1da177e4	23
ced3ec8a BZ	24	#define DRV_NAME "cs5530"
ced3ec8a BZ	25
1da177e4 LT	26	/*
	27	* Here are the standard PIO mode 0-4 timings for each "format".
	28	* Format-0 uses fast data reg timings, with slower command reg timings.
	29	* Format-1 uses fast timings for all registers, but won't work with all drives.
	30	*/
	31	static unsigned int cs5530_pio_timings[2][5] = {
	32	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	33	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	34	};
	35
	36	/*
	37	* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
	38	*/
	39	#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
	40	#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
	41
	42	/**
88b2b32b	43	* cs5530_set_pio_mode - set host controller for PIO mode
e085b3ca	44	* @hwif: port
26bcb879	45	* @drive: drive
1da177e4	46	*
88b2b32b	47	* Handles setting of PIO mode for the chipset.
1da177e4	48	*
26bcb879	49	* The init_hwif_cs5530() routine guarantees that all drives
1da177e4 LT	50	* will have valid default PIO timings set up before we get here.
	51	*/
	52
e085b3ca	53	static void cs5530_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	54	{
e085b3ca	55	unsigned long basereg = CS5530_BASEREG(hwif);
88b2b32b	56	unsigned int format = (inl(basereg + 4) >> 31) & 1;
e085b3ca	57	const u8 pio = drive->pio_mode - XFER_PIO_0;
88b2b32b BZ	58
88b2b32b BZ	59	outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
1da177e4 LT	60	}
	61
	62	/**
5fd216bb BZ	63	* cs5530_udma_filter - UDMA filter
	64	* @drive: drive
	65	*
	66	* cs5530_udma_filter() does UDMA mask filtering for the given drive
	67	* taking into the consideration capabilities of the mate device.
	68	*
	69	* The CS5530 specifies that two drives sharing a cable cannot mix
	70	* UDMA/MDMA. It has to be one or the other, for the pair, though
	71	* different timings can still be chosen for each drive. We could
	72	* set the appropriate timing bits on the fly, but that might be
	73	* a bit confusing. So, for now we statically handle this requirement
	74	* by looking at our mate drive to see what it is capable of, before
	75	* choosing a mode for our own drive.
	76	*
	77	* Note: This relies on the fact we never fail from UDMA to MWDMA2
	78	* but instead drop to PIO.
	79	*/
	80
	81	static u8 cs5530_udma_filter(ide_drive_t *drive)
	82	{
	83	ide_hwif_t *hwif = drive->hwif;
7e59ea21	84	ide_drive_t *mate = ide_get_pair_dev(drive);
9ecab6e5	85	u16 *mateid;
5fd216bb BZ	86	u8 mask = hwif->ultra_mask;
5fd216bb BZ	87
7e59ea21	88	if (mate == NULL)
5fd216bb	89	goto out;
9ecab6e5	90	mateid = mate->id;
5fd216bb	91
48fb2688	92	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
4dde4492 BZ	93	if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
4dde4492 BZ	94	(mateid[ATA_ID_UDMA_MODES] & 7))
5fd216bb	95	goto out;
8d64fcd9	96	if (mateid[ATA_ID_MWDMA_MODES] & 7)
5fd216bb BZ	97	mask = 0;
	98	}
	99	out:
	100	return mask;
	101	}
	102
8776168c	103	static void cs5530_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
3c3f5d2c	104	{
5fd216bb	105	unsigned long basereg;
3c3f5d2c	106	unsigned int reg, timings = 0;
1da177e4	107
8776168c	108	switch (drive->dma_mode) {
1da177e4 LT	109	case XFER_UDMA_0: timings = 0x00921250; break;
	110	case XFER_UDMA_1: timings = 0x00911140; break;
	111	case XFER_UDMA_2: timings = 0x00911030; break;
	112	case XFER_MW_DMA_0: timings = 0x00077771; break;
	113	case XFER_MW_DMA_1: timings = 0x00012121; break;
	114	case XFER_MW_DMA_2: timings = 0x00002020; break;
1da177e4	115	}
8776168c	116	basereg = CS5530_BASEREG(hwif);
0ecdca26	117	reg = inl(basereg + 4); /* get drive0 config register */
1da177e4	118	timings \|= reg & 0x80000000; /* preserve PIO format bit */
3c3f5d2c	119	if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
0ecdca26	120	outl(timings, basereg + 4); /* write drive0 config register */
1da177e4 LT	121	} else {
	122	if (timings & 0x00100000)
	123	reg \|= 0x00100000; /* enable UDMA timings for both drives */
	124	else
	125	reg &= ~0x00100000; /* disable UDMA timings for both drives */
0ecdca26 BZ	126	outl(reg, basereg + 4); /* write drive0 config register */
0ecdca26 BZ	127	outl(timings, basereg + 12); /* write drive1 config register */
1da177e4	128	}
1da177e4 LT	129	}
	130
	131	/**
	132	* init_chipset_5530 - set up 5530 bridge
	133	* @dev: PCI device
1da177e4 LT	134	*
	135	* Initialize the cs5530 bridge for reliable IDE DMA operation.
	136	*/
	137
2ed0ef54	138	static int init_chipset_cs5530(struct pci_dev *dev)
1da177e4 LT	139	{
1da177e4 LT	140	struct pci_dev master_0 = NULL, cs5530_0 = NULL;
1da177e4	141
f7b0d2df BZ	142	if (pci_resource_start(dev, 4) == 0)
	143	return -EFAULT;
	144
1da177e4	145	dev = NULL;
652aa162	146	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
1da177e4 LT	147	switch (dev->device) {
1da177e4 LT	148	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
652aa162	149	master_0 = pci_dev_get(dev);
1da177e4 LT	150	break;
1da177e4 LT	151	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
652aa162	152	cs5530_0 = pci_dev_get(dev);
1da177e4 LT	153	break;
	154	}
	155	}
	156	if (!master_0) {
a326b02b	157	printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
652aa162	158	goto out;
1da177e4 LT	159	}
1da177e4 LT	160	if (!cs5530_0) {
a326b02b	161	printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
652aa162	162	goto out;
1da177e4 LT	163	}
1da177e4 LT	164
1da177e4 LT	165	/*
	166	* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
	167	* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
	168	*/
	169
	170	pci_set_master(cs5530_0);
694625c0	171	pci_try_set_mwi(cs5530_0);
1da177e4 LT	172
	173	/*
	174	* Set PCI CacheLineSize to 16-bytes:
	175	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	176	*/
	177
	178	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	179
	180	/*
	181	* Disable trapping of UDMA register accesses (Win98 hack):
	182	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	183	*/
	184
	185	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	186
	187	/*
	188	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	189	* The other settings are what is necessary to get the register
	190	* into a sane state for IDE DMA operation.
	191	*/
	192
	193	pci_write_config_byte(master_0, 0x40, 0x1e);
	194
	195	/*
	196	* Set max PCI burst size (16-bytes seems to work best):
	197	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	198	* all others: clear bit-1 at 0x41, and do:
	199	* 128bytes: OR 0x00 at 0x41
	200	* 256bytes: OR 0x04 at 0x41
	201	* 512bytes: OR 0x08 at 0x41
	202	* 1024bytes: OR 0x0c at 0x41
	203	*/
	204
	205	pci_write_config_byte(master_0, 0x41, 0x14);
	206
	207	/*
	208	* These settings are necessary to get the chip
	209	* into a sane state for IDE DMA operation.
	210	*/
	211
	212	pci_write_config_byte(master_0, 0x42, 0x00);
	213	pci_write_config_byte(master_0, 0x43, 0xc1);
	214
652aa162 AC	215	out:
	216	pci_dev_put(master_0);
	217	pci_dev_put(cs5530_0);
1da177e4 LT	218	return 0;
	219	}
	220
	221	/**
	222	* init_hwif_cs5530 - initialise an IDE channel
	223	* @hwif: IDE to initialize
	224	*
	225	* This gets invoked by the IDE driver once for each channel. It
	226	* performs channel-specific pre-initialization before drive probing.
	227	*/
	228
fe31edc8	229	static void init_hwif_cs5530 (ide_hwif_t *hwif)
1da177e4 LT	230	{
	231	unsigned long basereg;
	232	u32 d0_timings;
1da177e4	233
1da177e4	234	basereg = CS5530_BASEREG(hwif);
0ecdca26	235	d0_timings = inl(basereg + 0);
93104654	236	if (CS5530_BAD_PIO(d0_timings))
0ecdca26	237	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
93104654	238	if (CS5530_BAD_PIO(inl(basereg + 8)))
0ecdca26	239	outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
1da177e4 LT	240	}
1da177e4 LT	241
ac95beed BZ	242	static const struct ide_port_ops cs5530_port_ops = {
	243	.set_pio_mode = cs5530_set_pio_mode,
	244	.set_dma_mode = cs5530_set_dma_mode,
	245	.udma_filter = cs5530_udma_filter,
	246	};
	247
fe31edc8	248	static const struct ide_port_info cs5530_chipset = {
ced3ec8a	249	.name = DRV_NAME,
1da177e4 LT	250	.init_chipset = init_chipset_cs5530,
1da177e4 LT	251	.init_hwif = init_hwif_cs5530,
ac95beed	252	.port_ops = &cs5530_port_ops,
1c51361a	253	.host_flags = IDE_HFLAG_SERIALIZE \|
5e71d9c5	254	IDE_HFLAG_POST_SET_MODE,
4099d143	255	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	256	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	257	.udma_mask = ATA_UDMA2,
1da177e4 LT	258	};
1da177e4 LT	259
fe31edc8	260	static int cs5530_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	261	{
6cdf6eb3	262	return ide_pci_init_one(dev, &cs5530_chipset, NULL);
1da177e4 LT	263	}
1da177e4 LT	264
9cbcc5e3 BZ	265	static const struct pci_device_id cs5530_pci_tbl[] = {
9cbcc5e3 BZ	266	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
1da177e4 LT	267	{ 0, },
	268	};
	269	MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
	270
a9ab09e2	271	static struct pci_driver cs5530_pci_driver = {
1da177e4 LT	272	.name = "CS5530 IDE",
	273	.id_table = cs5530_pci_tbl,
	274	.probe = cs5530_init_one,
d16492a9	275	.remove = ide_pci_remove,
feb22b7f BZ	276	.suspend = ide_pci_suspend,
feb22b7f BZ	277	.resume = ide_pci_resume,
1da177e4 LT	278	};
1da177e4 LT	279
82ab1eec	280	static int __init cs5530_ide_init(void)
1da177e4	281	{
a9ab09e2	282	return ide_pci_register_driver(&cs5530_pci_driver);
1da177e4 LT	283	}
1da177e4 LT	284
d16492a9 BZ	285	static void __exit cs5530_ide_exit(void)
d16492a9 BZ	286	{
a9ab09e2	287	pci_unregister_driver(&cs5530_pci_driver);
d16492a9 BZ	288	}
d16492a9 BZ	289
1da177e4	290	module_init(cs5530_ide_init);
d16492a9	291	module_exit(cs5530_ide_exit);
1da177e4 LT	292
	293	MODULE_AUTHOR("Mark Lord");
	294	MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
	295	MODULE_LICENSE("GPL");