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Merge tag 'v3.10.86' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / hwmon / dme1737.c
CommitLineData
9431996f 1/*
ea694431
JH		 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
3 * and SCH5127 Super-I/O chips integrated hardware monitoring
4 * features.
5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
9431996f 6 *
e95c237d 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
549edb83 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
ea694431
JH		 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
10 * similar hardware monitoring capabilities but differ in the way they can be
11 * accessed.
9431996f
JH		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
9c6e13b4
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9431996f
JH		 30#include <linux/module.h>
31#include <linux/init.h>
32#include <linux/slab.h>
33#include <linux/jiffies.h>
34#include <linux/i2c.h>
e95c237d 35#include <linux/platform_device.h>
9431996f
JH		 36#include <linux/hwmon.h>
37#include <linux/hwmon-sysfs.h>
38#include <linux/hwmon-vid.h>
39#include <linux/err.h>
40#include <linux/mutex.h>
b9acb64a 41#include <linux/acpi.h>
6055fae8 42#include <linux/io.h>
9431996f 43
e95c237d
JH		 44/* ISA device, if found */
45static struct platform_device *pdev;
46
9431996f 47/* Module load parameters */
90ab5ee9 48static bool force_start;
9431996f
JH		 49module_param(force_start, bool, 0);
50MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");
51
67b671bc
JD		 52static unsigned short force_id;
53module_param(force_id, ushort, 0);
54MODULE_PARM_DESC(force_id, "Override the detected device ID");
55
90ab5ee9 56static bool probe_all_addr;
92430b6f 57module_param(probe_all_addr, bool, 0);
b55f3757
GR		 58MODULE_PARM_DESC(probe_all_addr,
59 "Include probing of non-standard LPC addresses");
92430b6f 60
9431996f 61/* Addresses to scan */
25e9c86d 62static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
9431996f 63
ea694431 64enum chips { dme1737, sch5027, sch311x, sch5127 };
9431996f 65
b55f3757
GR		 66#define DO_REPORT "Please report to the driver maintainer."
67
9431996f
JH		 68/* ---------------------------------------------------------------------
69 * Registers
70 *
71 * The sensors are defined as follows:
72 *
73 * Voltages Temperatures
74 * -------- ------------
75 * in0 +5VTR (+5V stdby) temp1 Remote diode 1
76 * in1 Vccp (proc core) temp2 Internal temp
77 * in2 VCC (internal +3.3V) temp3 Remote diode 2
78 * in3 +5V
79 * in4 +12V
80 * in5 VTR (+3.3V stby)
81 * in6 Vbat
d4b94e1f 82 * in7 Vtrip (sch5127 only)
9431996f
JH		 83 *
84 * --------------------------------------------------------------------- */
85
d4b94e1f 86/* Voltages (in) numbered 0-7 (ix) */
c8de8362 87#define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \
d4b94e1f
JH		 88 (ix) < 7 ? 0x94 + (ix) : \
89 0x1f)
c8de8362 90#define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \
9431996f 91 : 0x91 + (ix) * 2)
c8de8362 92#define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \
9431996f
JH		 93 : 0x92 + (ix) * 2)
94
95/* Temperatures (temp) numbered 0-2 (ix) */
96#define DME1737_REG_TEMP(ix) (0x25 + (ix))
97#define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2)
98#define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2)
99#define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \
100 : 0x1c + (ix))
101
c8de8362
GR		 102/*
103 * Voltage and temperature LSBs
9431996f
JH		 104 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
105 * IN_TEMP_LSB(0) = [in5, in6]
106 * IN_TEMP_LSB(1) = [temp3, temp1]
107 * IN_TEMP_LSB(2) = [in4, temp2]
108 * IN_TEMP_LSB(3) = [in3, in0]
d4b94e1f 109 * IN_TEMP_LSB(4) = [in2, in1]
c8de8362
GR		 110 * IN_TEMP_LSB(5) = [res, in7]
111 */
9431996f 112#define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix))
d4b94e1f
JH		 113static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
114static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
9431996f
JH		 115static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
116static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};
117
118/* Fans numbered 0-5 (ix) */
119#define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \
120 : 0xa1 + (ix) * 2)
121#define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \
122 : 0xa5 + (ix) * 2)
123#define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \
124 : 0xb2 + (ix))
125#define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */
126
127/* PWMs numbered 0-2, 4-5 (ix) */
128#define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \
129 : 0xa1 + (ix))
130#define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */
131#define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */
132#define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \
133 : 0xa3 + (ix))
c8de8362
GR		 134/*
135 * The layout of the ramp rate registers is different from the other pwm
9431996f
JH		 136 * registers. The bits for the 3 PWMs are stored in 2 registers:
137 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0]
c8de8362
GR		 138 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
139 */
9431996f
JH		 140#define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */
141
142/* Thermal zones 0-2 */
143#define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix))
144#define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix))
c8de8362
GR		 145/*
146 * The layout of the hysteresis registers is different from the other zone
9431996f
JH		 147 * registers. The bits for the 3 zones are stored in 2 registers:
148 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
c8de8362
GR		 149 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES]
150 */
9431996f
JH		 151#define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix))
152
c8de8362
GR		 153/*
154 * Alarm registers and bit mapping
9431996f 155 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
c8de8362
GR		 156 * alarm value [0, ALARM3, ALARM2, ALARM1].
157 */
9431996f
JH		 158#define DME1737_REG_ALARM1 0x41
159#define DME1737_REG_ALARM2 0x42
160#define DME1737_REG_ALARM3 0x83
d4b94e1f 161static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
9431996f
JH		 162static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
163static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};
164
165/* Miscellaneous registers */
e95c237d 166#define DME1737_REG_DEVICE 0x3d
9431996f
JH		 167#define DME1737_REG_COMPANY 0x3e
168#define DME1737_REG_VERSTEP 0x3f
169#define DME1737_REG_CONFIG 0x40
170#define DME1737_REG_CONFIG2 0x7f
171#define DME1737_REG_VID 0x43
172#define DME1737_REG_TACH_PWM 0x81
173
174/* ---------------------------------------------------------------------
175 * Misc defines
176 * --------------------------------------------------------------------- */
177
178/* Chip identification */
179#define DME1737_COMPANY_SMSC 0x5c
180#define DME1737_VERSTEP 0x88
181#define DME1737_VERSTEP_MASK 0xf8
e95c237d 182#define SCH311X_DEVICE 0x8c
549edb83 183#define SCH5027_VERSTEP 0x69
ea694431
JH		 184#define SCH5127_DEVICE 0x8e
185
186/* Device ID values (global configuration register index 0x20) */
187#define DME1737_ID_1 0x77
188#define DME1737_ID_2 0x78
189#define SCH3112_ID 0x7c
190#define SCH3114_ID 0x7d
191#define SCH3116_ID 0x7f
192#define SCH5027_ID 0x89
193#define SCH5127_ID 0x86
e95c237d
JH		 194
195/* Length of ISA address segment */
196#define DME1737_EXTENT 2
9431996f 197
ea694431
JH		 198/* chip-dependent features */
199#define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */
200#define HAS_VID (1 << 1) /* bit 1 */
201#define HAS_ZONE3 (1 << 2) /* bit 2 */
202#define HAS_ZONE_HYST (1 << 3) /* bit 3 */
203#define HAS_PWM_MIN (1 << 4) /* bit 4 */
204#define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */
205#define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */
d4b94e1f 206#define HAS_IN7 (1 << 17) /* bit 17 */
ea694431 207
9431996f
JH		 208/* ---------------------------------------------------------------------
209 * Data structures and manipulation thereof
210 * --------------------------------------------------------------------- */
211
212struct dme1737_data {
dbc2bc25 213 struct i2c_client *client; /* for I2C devices only */
1beeffe4 214 struct device *hwmon_dev;
dbc2bc25
JD		 215 const char *name;
216 unsigned int addr; /* for ISA devices only */
9431996f
JH		 217
218 struct mutex update_lock;
219 int valid; /* !=0 if following fields are valid */
220 unsigned long last_update; /* in jiffies */
221 unsigned long last_vbat; /* in jiffies */
f994fb23 222 enum chips type;
549edb83 223 const int *in_nominal; /* pointer to IN_NOMINAL array */
9431996f
JH		 224
225 u8 vid;
226 u8 pwm_rr_en;
ea694431 227 u32 has_features;
9431996f
JH		 228
229 /* Register values */
d4b94e1f
JH		 230 u16 in[8];
231 u8 in_min[8];
232 u8 in_max[8];
9431996f
JH		 233 s16 temp[3];
234 s8 temp_min[3];
235 s8 temp_max[3];
236 s8 temp_offset[3];
237 u8 config;
238 u8 config2;
239 u8 vrm;
240 u16 fan[6];
241 u16 fan_min[6];
242 u8 fan_max[2];
243 u8 fan_opt[6];
244 u8 pwm[6];
245 u8 pwm_min[3];
246 u8 pwm_config[3];
247 u8 pwm_acz[3];
248 u8 pwm_freq[6];
249 u8 pwm_rr[2];
30b72362
AL		 250 s8 zone_low[3];
251 s8 zone_abs[3];
9431996f
JH		 252 u8 zone_hyst[2];
253 u32 alarms;
254};
255
256/* Nominal voltage values */
f994fb23
JH		 257static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
258 3300};
259static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
260 3300};
549edb83
JH		 261static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
262 3300};
ea694431 263static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
d4b94e1f 264 3300, 1500};
549edb83
JH		 265#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \
266 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
ea694431 267 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
549edb83 268 IN_NOMINAL_DME1737)
9431996f 269
c8de8362
GR		 270/*
271 * Voltage input
9431996f 272 * Voltage inputs have 16 bits resolution, limit values have 8 bits
c8de8362
GR		 273 * resolution.
274 */
549edb83 275static inline int IN_FROM_REG(int reg, int nominal, int res)
9431996f 276{
549edb83 277 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
9431996f
JH		 278}
279
30b72362 280static inline int IN_TO_REG(long val, int nominal)
9431996f 281{
2a844c14 282 return clamp_val((val * 192 + nominal / 2) / nominal, 0, 255);
9431996f
JH		 283}
284
c8de8362
GR		 285/*
286 * Temperature input
9431996f
JH		 287 * The register values represent temperatures in 2's complement notation from
288 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
c8de8362
GR		 289 * values have 8 bits resolution.
290 */
9431996f
JH		 291static inline int TEMP_FROM_REG(int reg, int res)
292{
293 return (reg * 1000) >> (res - 8);
294}
295
30b72362 296static inline int TEMP_TO_REG(long val)
9431996f 297{
2a844c14 298 return clamp_val((val < 0 ? val - 500 : val + 500) / 1000, -128, 127);
9431996f
JH		 299}
300
301/* Temperature range */
302static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
303 10000, 13333, 16000, 20000, 26666, 32000,
304 40000, 53333, 80000};
305
306static inline int TEMP_RANGE_FROM_REG(int reg)
307{
308 return TEMP_RANGE[(reg >> 4) & 0x0f];
309}
310
30b72362 311static int TEMP_RANGE_TO_REG(long val, int reg)
9431996f
JH		 312{
313 int i;
314
315 for (i = 15; i > 0; i--) {
c8de8362 316 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
9431996f 317 break;
9431996f
JH		 318 }
319
320 return (reg & 0x0f) | (i << 4);
321}
322
c8de8362
GR		 323/*
324 * Temperature hysteresis
9431996f
JH		 325 * Register layout:
326 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
c8de8362
GR		 327 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
328 */
9431996f
JH		 329static inline int TEMP_HYST_FROM_REG(int reg, int ix)
330{
331 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
332}
333
30b72362 334static inline int TEMP_HYST_TO_REG(long val, int ix, int reg)
9431996f 335{
2a844c14 336 int hyst = clamp_val((val + 500) / 1000, 0, 15);
9431996f
JH		 337
338 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
339}
340
341/* Fan input RPM */
342static inline int FAN_FROM_REG(int reg, int tpc)
343{
c8de8362 344 if (tpc)
ff8421f7 345 return tpc * reg;
c8de8362 346 else
ff8421f7 347 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
9431996f
JH		 348}
349
30b72362 350static inline int FAN_TO_REG(long val, int tpc)
9431996f 351{
ff8421f7 352 if (tpc) {
2a844c14 353 return clamp_val(val / tpc, 0, 0xffff);
ff8421f7
JH		 354 } else {
355 return (val <= 0) ? 0xffff :
2a844c14 356 clamp_val(90000 * 60 / val, 0, 0xfffe);
ff8421f7 357 }
9431996f
JH		 358}
359
c8de8362
GR		 360/*
361 * Fan TPC (tach pulse count)
9431996f 362 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
c8de8362
GR		 363 * is configured in legacy (non-tpc) mode
364 */
9431996f
JH		 365static inline int FAN_TPC_FROM_REG(int reg)
366{
367 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
368}
369
c8de8362
GR		 370/*
371 * Fan type
9431996f 372 * The type of a fan is expressed in number of pulses-per-revolution that it
c8de8362
GR		 373 * emits
374 */
9431996f
JH		 375static inline int FAN_TYPE_FROM_REG(int reg)
376{
377 int edge = (reg >> 1) & 0x03;
378
379 return (edge > 0) ? 1 << (edge - 1) : 0;
380}
381
30b72362 382static inline int FAN_TYPE_TO_REG(long val, int reg)
9431996f
JH		 383{
384 int edge = (val == 4) ? 3 : val;
385
386 return (reg & 0xf9) | (edge << 1);
387}
388
389/* Fan max RPM */
390static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
391 0x11, 0x0f, 0x0e};
392
393static int FAN_MAX_FROM_REG(int reg)
394{
395 int i;
396
397 for (i = 10; i > 0; i--) {
c8de8362 398 if (reg == FAN_MAX[i])
9431996f 399 break;
9431996f
JH		 400 }
401
402 return 1000 + i * 500;
403}
404
30b72362 405static int FAN_MAX_TO_REG(long val)
9431996f
JH		 406{
407 int i;
408
409 for (i = 10; i > 0; i--) {
c8de8362 410 if (val > (1000 + (i - 1) * 500))
9431996f 411 break;
9431996f
JH		 412 }
413
414 return FAN_MAX[i];
415}
416
c8de8362
GR		 417/*
418 * PWM enable
9431996f
JH		 419 * Register to enable mapping:
420 * 000: 2 fan on zone 1 auto
421 * 001: 2 fan on zone 2 auto
422 * 010: 2 fan on zone 3 auto
423 * 011: 0 fan full on
424 * 100: -1 fan disabled
425 * 101: 2 fan on hottest of zones 2,3 auto
426 * 110: 2 fan on hottest of zones 1,2,3 auto
c8de8362
GR		 427 * 111: 1 fan in manual mode
428 */
9431996f
JH		 429static inline int PWM_EN_FROM_REG(int reg)
430{
431 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};
432
433 return en[(reg >> 5) & 0x07];
434}
435
436static inline int PWM_EN_TO_REG(int val, int reg)
437{
438 int en = (val == 1) ? 7 : 3;
439
440 return (reg & 0x1f) | ((en & 0x07) << 5);
441}
442
c8de8362
GR		 443/*
444 * PWM auto channels zone
9431996f
JH		 445 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
446 * corresponding to zone x+1):
447 * 000: 001 fan on zone 1 auto
448 * 001: 010 fan on zone 2 auto
449 * 010: 100 fan on zone 3 auto
450 * 011: 000 fan full on
451 * 100: 000 fan disabled
452 * 101: 110 fan on hottest of zones 2,3 auto
453 * 110: 111 fan on hottest of zones 1,2,3 auto
c8de8362
GR		 454 * 111: 000 fan in manual mode
455 */
9431996f
JH		 456static inline int PWM_ACZ_FROM_REG(int reg)
457{
458 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};
459
460 return acz[(reg >> 5) & 0x07];
461}
462
30b72362 463static inline int PWM_ACZ_TO_REG(long val, int reg)
9431996f
JH		 464{
465 int acz = (val == 4) ? 2 : val - 1;
466
467 return (reg & 0x1f) | ((acz & 0x07) << 5);
468}
469
470/* PWM frequency */
471static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
472 15000, 20000, 30000, 25000, 0, 0, 0, 0};
473
474static inline int PWM_FREQ_FROM_REG(int reg)
475{
476 return PWM_FREQ[reg & 0x0f];
477}
478
30b72362 479static int PWM_FREQ_TO_REG(long val, int reg)
9431996f
JH		 480{
481 int i;
482
483 /* the first two cases are special - stupid chip design! */
484 if (val > 27500) {
485 i = 10;
486 } else if (val > 22500) {
487 i = 11;
488 } else {
489 for (i = 9; i > 0; i--) {
c8de8362 490 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
9431996f 491 break;
9431996f
JH		 492 }
493 }
494
495 return (reg & 0xf0) | i;
496}
497
c8de8362
GR		 498/*
499 * PWM ramp rate
9431996f
JH		 500 * Register layout:
501 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0]
c8de8362
GR		 502 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
503 */
9431996f
JH		 504static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};
505
506static inline int PWM_RR_FROM_REG(int reg, int ix)
507{
508 int rr = (ix == 1) ? reg >> 4 : reg;
509
510 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
511}
512
30b72362 513static int PWM_RR_TO_REG(long val, int ix, int reg)
9431996f
JH		 514{
515 int i;
516
517 for (i = 0; i < 7; i++) {
c8de8362 518 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
9431996f 519 break;
9431996f
JH		 520 }
521
522 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
523}
524
525/* PWM ramp rate enable */
526static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
527{
528 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
529}
530
30b72362 531static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg)
9431996f
JH		 532{
533 int en = (ix == 1) ? 0x80 : 0x08;
534
535 return val ? reg | en : reg & ~en;
536}
537
c8de8362
GR		 538/*
539 * PWM min/off
9431996f 540 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
c8de8362
GR		 541 * the register layout).
542 */
9431996f
JH		 543static inline int PWM_OFF_FROM_REG(int reg, int ix)
544{
545 return (reg >> (ix + 5)) & 0x01;
546}
547
548static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
549{
550 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
551}
552
553/* ---------------------------------------------------------------------
554 * Device I/O access
e95c237d
JH		 555 *
556 * ISA access is performed through an index/data register pair and needs to
557 * be protected by a mutex during runtime (not required for initialization).
558 * We use data->update_lock for this and need to ensure that we acquire it
559 * before calling dme1737_read or dme1737_write.
9431996f
JH		 560 * --------------------------------------------------------------------- */
561
dbc2bc25 562static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
9431996f 563{
dbc2bc25 564 struct i2c_client *client = data->client;
e95c237d 565 s32 val;
9431996f 566
dbc2bc25 567 if (client) { /* I2C device */
e95c237d
JH		 568 val = i2c_smbus_read_byte_data(client, reg);
569
570 if (val < 0) {
b55f3757
GR		 571 dev_warn(&client->dev,
572 "Read from register 0x%02x failed! %s\n",
573 reg, DO_REPORT);
e95c237d
JH		 574 }
575 } else { /* ISA device */
dbc2bc25
JD		 576 outb(reg, data->addr);
577 val = inb(data->addr + 1);
9431996f
JH		 578 }
579
580 return val;
581}
582
dbc2bc25 583static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
9431996f 584{
dbc2bc25 585 struct i2c_client *client = data->client;
e95c237d
JH		 586 s32 res = 0;
587
dbc2bc25 588 if (client) { /* I2C device */
e95c237d 589 res = i2c_smbus_write_byte_data(client, reg, val);
9431996f 590
e95c237d 591 if (res < 0) {
b55f3757
GR		 592 dev_warn(&client->dev,
593 "Write to register 0x%02x failed! %s\n",
594 reg, DO_REPORT);
e95c237d
JH		 595 }
596 } else { /* ISA device */
dbc2bc25
JD		 597 outb(reg, data->addr);
598 outb(val, data->addr + 1);
9431996f
JH		 599 }
600
601 return res;
602}
603
604static struct dme1737_data *dme1737_update_device(struct device *dev)
605{
b237eb25 606 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f 607 int ix;
d4b94e1f 608 u8 lsb[6];
9431996f
JH		 609
610 mutex_lock(&data->update_lock);
611
612 /* Enable a Vbat monitoring cycle every 10 mins */
613 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
dbc2bc25 614 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
9431996f
JH		 615 DME1737_REG_CONFIG) | 0x10);
616 data->last_vbat = jiffies;
617 }
618
619 /* Sample register contents every 1 sec */
620 if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
ea694431 621 if (data->has_features & HAS_VID) {
dbc2bc25 622 data->vid = dme1737_read(data, DME1737_REG_VID) &
549edb83
JH		 623 0x3f;
624 }
9431996f
JH		 625
626 /* In (voltage) registers */
627 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
c8de8362
GR		 628 /*
629 * Voltage inputs are stored as 16 bit values even
9431996f 630 * though they have only 12 bits resolution. This is
c8de8362
GR		 631 * to make it consistent with the temp inputs.
632 */
633 if (ix == 7 && !(data->has_features & HAS_IN7))
d4b94e1f 634 continue;
dbc2bc25 635 data->in[ix] = dme1737_read(data,
9431996f 636 DME1737_REG_IN(ix)) << 8;
dbc2bc25 637 data->in_min[ix] = dme1737_read(data,
9431996f 638 DME1737_REG_IN_MIN(ix));
dbc2bc25 639 data->in_max[ix] = dme1737_read(data,
9431996f
JH		 640 DME1737_REG_IN_MAX(ix));
641 }
642
643 /* Temp registers */
644 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
c8de8362
GR		 645 /*
646 * Temp inputs are stored as 16 bit values even
9431996f
JH		 647 * though they have only 12 bits resolution. This is
648 * to take advantage of implicit conversions between
649 * register values (2's complement) and temp values
c8de8362
GR		 650 * (signed decimal).
651 */
dbc2bc25 652 data->temp[ix] = dme1737_read(data,
9431996f 653 DME1737_REG_TEMP(ix)) << 8;
dbc2bc25 654 data->temp_min[ix] = dme1737_read(data,
9431996f 655 DME1737_REG_TEMP_MIN(ix));
dbc2bc25 656 data->temp_max[ix] = dme1737_read(data,
9431996f 657 DME1737_REG_TEMP_MAX(ix));
ea694431 658 if (data->has_features & HAS_TEMP_OFFSET) {
dbc2bc25 659 data->temp_offset[ix] = dme1737_read(data,
549edb83
JH		 660 DME1737_REG_TEMP_OFFSET(ix));
661 }
9431996f
JH		 662 }
663
c8de8362
GR		 664 /*
665 * In and temp LSB registers
9431996f
JH		 666 * The LSBs are latched when the MSBs are read, so the order in
667 * which the registers are read (MSB first, then LSB) is
c8de8362
GR		 668 * important!
669 */
9431996f 670 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
c8de8362 671 if (ix == 5 && !(data->has_features & HAS_IN7))
d4b94e1f 672 continue;
dbc2bc25 673 lsb[ix] = dme1737_read(data,
9431996f
JH		 674 DME1737_REG_IN_TEMP_LSB(ix));
675 }
676 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
c8de8362 677 if (ix == 7 && !(data->has_features & HAS_IN7))
d4b94e1f 678 continue;
9431996f
JH		 679 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
680 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
681 }
682 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
683 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
684 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
685 }
686
687 /* Fan registers */
688 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
c8de8362
GR		 689 /*
690 * Skip reading registers if optional fans are not
691 * present
692 */
693 if (!(data->has_features & HAS_FAN(ix)))
9431996f 694 continue;
dbc2bc25 695 data->fan[ix] = dme1737_read(data,
9431996f 696 DME1737_REG_FAN(ix));
dbc2bc25 697 data->fan[ix] |= dme1737_read(data,
9431996f 698 DME1737_REG_FAN(ix) + 1) << 8;
dbc2bc25 699 data->fan_min[ix] = dme1737_read(data,
9431996f 700 DME1737_REG_FAN_MIN(ix));
dbc2bc25 701 data->fan_min[ix] |= dme1737_read(data,
9431996f 702 DME1737_REG_FAN_MIN(ix) + 1) << 8;
dbc2bc25 703 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 704 DME1737_REG_FAN_OPT(ix));
705 /* fan_max exists only for fan[5-6] */
706 if (ix > 3) {
dbc2bc25 707 data->fan_max[ix - 4] = dme1737_read(data,
9431996f
JH		 708 DME1737_REG_FAN_MAX(ix));
709 }
710 }
711
712 /* PWM registers */
713 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
c8de8362
GR		 714 /*
715 * Skip reading registers if optional PWMs are not
716 * present
717 */
718 if (!(data->has_features & HAS_PWM(ix)))
9431996f 719 continue;
dbc2bc25 720 data->pwm[ix] = dme1737_read(data,
9431996f 721 DME1737_REG_PWM(ix));
dbc2bc25 722 data->pwm_freq[ix] = dme1737_read(data,
9431996f
JH		 723 DME1737_REG_PWM_FREQ(ix));
724 /* pwm_config and pwm_min exist only for pwm[1-3] */
725 if (ix < 3) {
dbc2bc25 726 data->pwm_config[ix] = dme1737_read(data,
9431996f 727 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 728 data->pwm_min[ix] = dme1737_read(data,
9431996f
JH		 729 DME1737_REG_PWM_MIN(ix));
730 }
731 }
732 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
dbc2bc25 733 data->pwm_rr[ix] = dme1737_read(data,
9431996f
JH		 734 DME1737_REG_PWM_RR(ix));
735 }
736
737 /* Thermal zone registers */
738 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
ea694431 739 /* Skip reading registers if zone3 is not present */
c8de8362 740 if ((ix == 2) && !(data->has_features & HAS_ZONE3))
ea694431 741 continue;
ea694431
JH		 742 /* sch5127 zone2 registers are special */
743 if ((ix == 1) && (data->type == sch5127)) {
744 data->zone_low[1] = dme1737_read(data,
745 DME1737_REG_ZONE_LOW(2));
746 data->zone_abs[1] = dme1737_read(data,
747 DME1737_REG_ZONE_ABS(2));
748 } else {
749 data->zone_low[ix] = dme1737_read(data,
750 DME1737_REG_ZONE_LOW(ix));
751 data->zone_abs[ix] = dme1737_read(data,
752 DME1737_REG_ZONE_ABS(ix));
753 }
9431996f 754 }
ea694431 755 if (data->has_features & HAS_ZONE_HYST) {
549edb83 756 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
dbc2bc25 757 data->zone_hyst[ix] = dme1737_read(data,
9431996f 758 DME1737_REG_ZONE_HYST(ix));
549edb83 759 }
9431996f
JH		 760 }
761
762 /* Alarm registers */
dbc2bc25 763 data->alarms = dme1737_read(data,
9431996f 764 DME1737_REG_ALARM1);
c8de8362
GR		 765 /*
766 * Bit 7 tells us if the other alarm registers are non-zero and
767 * therefore also need to be read
768 */
9431996f 769 if (data->alarms & 0x80) {
dbc2bc25 770 data->alarms |= dme1737_read(data,
9431996f 771 DME1737_REG_ALARM2) << 8;
dbc2bc25 772 data->alarms |= dme1737_read(data,
9431996f
JH		 773 DME1737_REG_ALARM3) << 16;
774 }
775
c8de8362
GR		 776 /*
777 * The ISA chips require explicit clearing of alarm bits.
e95c237d 778 * Don't worry, an alarm will come back if the condition
c8de8362
GR		 779 * that causes it still exists
780 */
dbc2bc25 781 if (!data->client) {
c8de8362
GR		 782 if (data->alarms & 0xff0000)
783 dme1737_write(data, DME1737_REG_ALARM3, 0xff);
784 if (data->alarms & 0xff00)
785 dme1737_write(data, DME1737_REG_ALARM2, 0xff);
786 if (data->alarms & 0xff)
787 dme1737_write(data, DME1737_REG_ALARM1, 0xff);
e95c237d
JH		 788 }
789
9431996f
JH		 790 data->last_update = jiffies;
791 data->valid = 1;
792 }
793
794 mutex_unlock(&data->update_lock);
795
796 return data;
797}
798
799/* ---------------------------------------------------------------------
800 * Voltage sysfs attributes
d4b94e1f 801 * ix = [0-7]
9431996f
JH		 802 * --------------------------------------------------------------------- */
803
804#define SYS_IN_INPUT 0
805#define SYS_IN_MIN 1
806#define SYS_IN_MAX 2
807#define SYS_IN_ALARM 3
808
809static ssize_t show_in(struct device *dev, struct device_attribute *attr,
810 char *buf)
811{
812 struct dme1737_data *data = dme1737_update_device(dev);
813 struct sensor_device_attribute_2
814 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
815 int ix = sensor_attr_2->index;
816 int fn = sensor_attr_2->nr;
817 int res;
818
819 switch (fn) {
820 case SYS_IN_INPUT:
549edb83 821 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
9431996f
JH		 822 break;
823 case SYS_IN_MIN:
549edb83 824 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
9431996f
JH		 825 break;
826 case SYS_IN_MAX:
549edb83 827 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
9431996f
JH		 828 break;
829 case SYS_IN_ALARM:
830 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
831 break;
832 default:
833 res = 0;
b237eb25 834 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 835 }
836
837 return sprintf(buf, "%d\n", res);
838}
839
840static ssize_t set_in(struct device *dev, struct device_attribute *attr,
841 const char *buf, size_t count)
842{
b237eb25 843 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 844 struct sensor_device_attribute_2
845 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
846 int ix = sensor_attr_2->index;
847 int fn = sensor_attr_2->nr;
c8de8362
GR		 848 long val;
849 int err;
850
851 err = kstrtol(buf, 10, &val);
852 if (err)
853 return err;
9431996f
JH		 854
855 mutex_lock(&data->update_lock);
856 switch (fn) {
857 case SYS_IN_MIN:
549edb83 858 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 859 dme1737_write(data, DME1737_REG_IN_MIN(ix),
9431996f
JH		 860 data->in_min[ix]);
861 break;
862 case SYS_IN_MAX:
549edb83 863 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
dbc2bc25 864 dme1737_write(data, DME1737_REG_IN_MAX(ix),
9431996f
JH		 865 data->in_max[ix]);
866 break;
867 default:
b237eb25 868 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 869 }
870 mutex_unlock(&data->update_lock);
871
872 return count;
873}
874
875/* ---------------------------------------------------------------------
876 * Temperature sysfs attributes
877 * ix = [0-2]
878 * --------------------------------------------------------------------- */
879
880#define SYS_TEMP_INPUT 0
881#define SYS_TEMP_MIN 1
882#define SYS_TEMP_MAX 2
883#define SYS_TEMP_OFFSET 3
884#define SYS_TEMP_ALARM 4
885#define SYS_TEMP_FAULT 5
886
887static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
888 char *buf)
889{
890 struct dme1737_data *data = dme1737_update_device(dev);
891 struct sensor_device_attribute_2
892 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
893 int ix = sensor_attr_2->index;
894 int fn = sensor_attr_2->nr;
895 int res;
896
897 switch (fn) {
898 case SYS_TEMP_INPUT:
899 res = TEMP_FROM_REG(data->temp[ix], 16);
900 break;
901 case SYS_TEMP_MIN:
902 res = TEMP_FROM_REG(data->temp_min[ix], 8);
903 break;
904 case SYS_TEMP_MAX:
905 res = TEMP_FROM_REG(data->temp_max[ix], 8);
906 break;
907 case SYS_TEMP_OFFSET:
908 res = TEMP_FROM_REG(data->temp_offset[ix], 8);
909 break;
910 case SYS_TEMP_ALARM:
911 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
912 break;
913 case SYS_TEMP_FAULT:
c0f31403 914 res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
9431996f
JH		 915 break;
916 default:
917 res = 0;
b237eb25 918 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 919 }
920
921 return sprintf(buf, "%d\n", res);
922}
923
924static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
925 const char *buf, size_t count)
926{
b237eb25 927 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 928 struct sensor_device_attribute_2
929 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
930 int ix = sensor_attr_2->index;
931 int fn = sensor_attr_2->nr;
c8de8362
GR		 932 long val;
933 int err;
934
935 err = kstrtol(buf, 10, &val);
936 if (err)
937 return err;
9431996f
JH		 938
939 mutex_lock(&data->update_lock);
940 switch (fn) {
941 case SYS_TEMP_MIN:
942 data->temp_min[ix] = TEMP_TO_REG(val);
dbc2bc25 943 dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
9431996f
JH		 944 data->temp_min[ix]);
945 break;
946 case SYS_TEMP_MAX:
947 data->temp_max[ix] = TEMP_TO_REG(val);
dbc2bc25 948 dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
9431996f
JH		 949 data->temp_max[ix]);
950 break;
951 case SYS_TEMP_OFFSET:
952 data->temp_offset[ix] = TEMP_TO_REG(val);
dbc2bc25 953 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
9431996f
JH		 954 data->temp_offset[ix]);
955 break;
956 default:
b237eb25 957 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 958 }
959 mutex_unlock(&data->update_lock);
960
961 return count;
962}
963
964/* ---------------------------------------------------------------------
965 * Zone sysfs attributes
966 * ix = [0-2]
967 * --------------------------------------------------------------------- */
968
969#define SYS_ZONE_AUTO_CHANNELS_TEMP 0
970#define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1
971#define SYS_ZONE_AUTO_POINT1_TEMP 2
972#define SYS_ZONE_AUTO_POINT2_TEMP 3
973#define SYS_ZONE_AUTO_POINT3_TEMP 4
974
975static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
976 char *buf)
977{
978 struct dme1737_data *data = dme1737_update_device(dev);
979 struct sensor_device_attribute_2
980 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
981 int ix = sensor_attr_2->index;
982 int fn = sensor_attr_2->nr;
983 int res;
984
985 switch (fn) {
986 case SYS_ZONE_AUTO_CHANNELS_TEMP:
987 /* check config2 for non-standard temp-to-zone mapping */
c8de8362 988 if ((ix == 1) && (data->config2 & 0x02))
9431996f 989 res = 4;
c8de8362 990 else
9431996f 991 res = 1 << ix;
9431996f
JH		 992 break;
993 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
994 res = TEMP_FROM_REG(data->zone_low[ix], 8) -
995 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
996 break;
997 case SYS_ZONE_AUTO_POINT1_TEMP:
998 res = TEMP_FROM_REG(data->zone_low[ix], 8);
999 break;
1000 case SYS_ZONE_AUTO_POINT2_TEMP:
1001 /* pwm_freq holds the temp range bits in the upper nibble */
1002 res = TEMP_FROM_REG(data->zone_low[ix], 8) +
1003 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
1004 break;
1005 case SYS_ZONE_AUTO_POINT3_TEMP:
1006 res = TEMP_FROM_REG(data->zone_abs[ix], 8);
1007 break;
1008 default:
1009 res = 0;
b237eb25 1010 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1011 }
1012
1013 return sprintf(buf, "%d\n", res);
1014}
1015
1016static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
1017 const char *buf, size_t count)
1018{
b237eb25 1019 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1020 struct sensor_device_attribute_2
1021 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1022 int ix = sensor_attr_2->index;
1023 int fn = sensor_attr_2->nr;
c8de8362
GR		 1024 long val;
1025 int err;
1026
1027 err = kstrtol(buf, 10, &val);
1028 if (err)
1029 return err;
9431996f
JH		 1030
1031 mutex_lock(&data->update_lock);
1032 switch (fn) {
1033 case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
1034 /* Refresh the cache */
dbc2bc25 1035 data->zone_low[ix] = dme1737_read(data,
9431996f
JH		 1036 DME1737_REG_ZONE_LOW(ix));
1037 /* Modify the temp hyst value */
1038 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(
1039 TEMP_FROM_REG(data->zone_low[ix], 8) -
dbc2bc25 1040 val, ix, dme1737_read(data,
9431996f 1041 DME1737_REG_ZONE_HYST(ix == 2)));
dbc2bc25 1042 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2),
9431996f
JH		 1043 data->zone_hyst[ix == 2]);
1044 break;
1045 case SYS_ZONE_AUTO_POINT1_TEMP:
1046 data->zone_low[ix] = TEMP_TO_REG(val);
dbc2bc25 1047 dme1737_write(data, DME1737_REG_ZONE_LOW(ix),
9431996f
JH		 1048 data->zone_low[ix]);
1049 break;
1050 case SYS_ZONE_AUTO_POINT2_TEMP:
1051 /* Refresh the cache */
dbc2bc25 1052 data->zone_low[ix] = dme1737_read(data,
9431996f 1053 DME1737_REG_ZONE_LOW(ix));
c8de8362
GR		 1054 /*
1055 * Modify the temp range value (which is stored in the upper
1056 * nibble of the pwm_freq register)
1057 */
9431996f
JH		 1058 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val -
1059 TEMP_FROM_REG(data->zone_low[ix], 8),
dbc2bc25 1060 dme1737_read(data,
9431996f 1061 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1062 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1063 data->pwm_freq[ix]);
1064 break;
1065 case SYS_ZONE_AUTO_POINT3_TEMP:
1066 data->zone_abs[ix] = TEMP_TO_REG(val);
dbc2bc25 1067 dme1737_write(data, DME1737_REG_ZONE_ABS(ix),
9431996f
JH		 1068 data->zone_abs[ix]);
1069 break;
1070 default:
b237eb25 1071 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1072 }
1073 mutex_unlock(&data->update_lock);
1074
1075 return count;
1076}
1077
1078/* ---------------------------------------------------------------------
1079 * Fan sysfs attributes
1080 * ix = [0-5]
1081 * --------------------------------------------------------------------- */
1082
1083#define SYS_FAN_INPUT 0
1084#define SYS_FAN_MIN 1
1085#define SYS_FAN_MAX 2
1086#define SYS_FAN_ALARM 3
1087#define SYS_FAN_TYPE 4
1088
1089static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1090 char *buf)
1091{
1092 struct dme1737_data *data = dme1737_update_device(dev);
1093 struct sensor_device_attribute_2
1094 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1095 int ix = sensor_attr_2->index;
1096 int fn = sensor_attr_2->nr;
1097 int res;
1098
1099 switch (fn) {
1100 case SYS_FAN_INPUT:
1101 res = FAN_FROM_REG(data->fan[ix],
1102 ix < 4 ? 0 :
1103 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1104 break;
1105 case SYS_FAN_MIN:
1106 res = FAN_FROM_REG(data->fan_min[ix],
1107 ix < 4 ? 0 :
1108 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1109 break;
1110 case SYS_FAN_MAX:
1111 /* only valid for fan[5-6] */
1112 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]);
1113 break;
1114 case SYS_FAN_ALARM:
1115 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01;
1116 break;
1117 case SYS_FAN_TYPE:
1118 /* only valid for fan[1-4] */
1119 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]);
1120 break;
1121 default:
1122 res = 0;
b237eb25 1123 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1124 }
1125
1126 return sprintf(buf, "%d\n", res);
1127}
1128
1129static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1130 const char *buf, size_t count)
1131{
b237eb25 1132 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1133 struct sensor_device_attribute_2
1134 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1135 int ix = sensor_attr_2->index;
1136 int fn = sensor_attr_2->nr;
c8de8362
GR		 1137 long val;
1138 int err;
1139
1140 err = kstrtol(buf, 10, &val);
1141 if (err)
1142 return err;
9431996f
JH		 1143
1144 mutex_lock(&data->update_lock);
1145 switch (fn) {
1146 case SYS_FAN_MIN:
1147 if (ix < 4) {
1148 data->fan_min[ix] = FAN_TO_REG(val, 0);
1149 } else {
1150 /* Refresh the cache */
dbc2bc25 1151 data->fan_opt[ix] = dme1737_read(data,
9431996f
JH		 1152 DME1737_REG_FAN_OPT(ix));
1153 /* Modify the fan min value */
1154 data->fan_min[ix] = FAN_TO_REG(val,
1155 FAN_TPC_FROM_REG(data->fan_opt[ix]));
1156 }
dbc2bc25 1157 dme1737_write(data, DME1737_REG_FAN_MIN(ix),
9431996f 1158 data->fan_min[ix] & 0xff);
dbc2bc25 1159 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1,
9431996f
JH		 1160 data->fan_min[ix] >> 8);
1161 break;
1162 case SYS_FAN_MAX:
1163 /* Only valid for fan[5-6] */
1164 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val);
dbc2bc25 1165 dme1737_write(data, DME1737_REG_FAN_MAX(ix),
9431996f
JH		 1166 data->fan_max[ix - 4]);
1167 break;
1168 case SYS_FAN_TYPE:
1169 /* Only valid for fan[1-4] */
1170 if (!(val == 1 || val == 2 || val == 4)) {
1171 count = -EINVAL;
b55f3757
GR		 1172 dev_warn(dev,
1173 "Fan type value %ld not supported. Choose one of 1, 2, or 4.\n",
9431996f
JH		 1174 val);
1175 goto exit;
1176 }
dbc2bc25 1177 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data,
9431996f 1178 DME1737_REG_FAN_OPT(ix)));
dbc2bc25 1179 dme1737_write(data, DME1737_REG_FAN_OPT(ix),
9431996f
JH		 1180 data->fan_opt[ix]);
1181 break;
1182 default:
b237eb25 1183 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1184 }
1185exit:
1186 mutex_unlock(&data->update_lock);
1187
1188 return count;
1189}
1190
1191/* ---------------------------------------------------------------------
1192 * PWM sysfs attributes
1193 * ix = [0-4]
1194 * --------------------------------------------------------------------- */
1195
1196#define SYS_PWM 0
1197#define SYS_PWM_FREQ 1
1198#define SYS_PWM_ENABLE 2
1199#define SYS_PWM_RAMP_RATE 3
1200#define SYS_PWM_AUTO_CHANNELS_ZONE 4
1201#define SYS_PWM_AUTO_PWM_MIN 5
1202#define SYS_PWM_AUTO_POINT1_PWM 6
1203#define SYS_PWM_AUTO_POINT2_PWM 7
1204
1205static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1206 char *buf)
1207{
1208 struct dme1737_data *data = dme1737_update_device(dev);
1209 struct sensor_device_attribute_2
1210 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1211 int ix = sensor_attr_2->index;
1212 int fn = sensor_attr_2->nr;
1213 int res;
1214
1215 switch (fn) {
1216 case SYS_PWM:
c8de8362 1217 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0)
9431996f 1218 res = 255;
c8de8362 1219 else
9431996f 1220 res = data->pwm[ix];
9431996f
JH		 1221 break;
1222 case SYS_PWM_FREQ:
1223 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]);
1224 break;
1225 case SYS_PWM_ENABLE:
c8de8362 1226 if (ix >= 3)
9431996f 1227 res = 1; /* pwm[5-6] hard-wired to manual mode */
c8de8362 1228 else
9431996f 1229 res = PWM_EN_FROM_REG(data->pwm_config[ix]);
9431996f
JH		 1230 break;
1231 case SYS_PWM_RAMP_RATE:
1232 /* Only valid for pwm[1-3] */
1233 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix);
1234 break;
1235 case SYS_PWM_AUTO_CHANNELS_ZONE:
1236 /* Only valid for pwm[1-3] */
c8de8362 1237 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2)
9431996f 1238 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]);
c8de8362 1239 else
9431996f 1240 res = data->pwm_acz[ix];
9431996f
JH		 1241 break;
1242 case SYS_PWM_AUTO_PWM_MIN:
1243 /* Only valid for pwm[1-3] */
c8de8362 1244 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix))
9431996f 1245 res = data->pwm_min[ix];
c8de8362 1246 else
9431996f 1247 res = 0;
9431996f
JH		 1248 break;
1249 case SYS_PWM_AUTO_POINT1_PWM:
1250 /* Only valid for pwm[1-3] */
1251 res = data->pwm_min[ix];
1252 break;
1253 case SYS_PWM_AUTO_POINT2_PWM:
1254 /* Only valid for pwm[1-3] */
1255 res = 255; /* hard-wired */
1256 break;
1257 default:
1258 res = 0;
b237eb25 1259 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1260 }
1261
1262 return sprintf(buf, "%d\n", res);
1263}
1264
73ce48f6 1265static struct attribute *dme1737_pwm_chmod_attr[];
48176a97 1266static void dme1737_chmod_file(struct device*, struct attribute*, umode_t);
9431996f
JH		 1267
1268static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1269 const char *buf, size_t count)
1270{
b237eb25 1271 struct dme1737_data *data = dev_get_drvdata(dev);
9431996f
JH		 1272 struct sensor_device_attribute_2
1273 *sensor_attr_2 = to_sensor_dev_attr_2(attr);
1274 int ix = sensor_attr_2->index;
1275 int fn = sensor_attr_2->nr;
c8de8362
GR		 1276 long val;
1277 int err;
1278
1279 err = kstrtol(buf, 10, &val);
1280 if (err)
1281 return err;
9431996f
JH		 1282
1283 mutex_lock(&data->update_lock);
1284 switch (fn) {
1285 case SYS_PWM:
2a844c14 1286 data->pwm[ix] = clamp_val(val, 0, 255);
dbc2bc25 1287 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]);
9431996f
JH		 1288 break;
1289 case SYS_PWM_FREQ:
dbc2bc25 1290 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data,
9431996f 1291 DME1737_REG_PWM_FREQ(ix)));
dbc2bc25 1292 dme1737_write(data, DME1737_REG_PWM_FREQ(ix),
9431996f
JH		 1293 data->pwm_freq[ix]);
1294 break;
1295 case SYS_PWM_ENABLE:
1296 /* Only valid for pwm[1-3] */
1297 if (val < 0 || val > 2) {
1298 count = -EINVAL;
b55f3757
GR		 1299 dev_warn(dev,
1300 "PWM enable %ld not supported. Choose one of 0, 1, or 2.\n",
9431996f
JH		 1301 val);
1302 goto exit;
1303 }
1304 /* Refresh the cache */
dbc2bc25 1305 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1306 DME1737_REG_PWM_CONFIG(ix));
1307 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) {
1308 /* Bail out if no change */
1309 goto exit;
1310 }
1311 /* Do some housekeeping if we are currently in auto mode */
1312 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1313 /* Save the current zone channel assignment */
1314 data->pwm_acz[ix] = PWM_ACZ_FROM_REG(
1315 data->pwm_config[ix]);
1316 /* Save the current ramp rate state and disable it */
dbc2bc25 1317 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1318 DME1737_REG_PWM_RR(ix > 0));
1319 data->pwm_rr_en &= ~(1 << ix);
1320 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) {
1321 data->pwm_rr_en |= (1 << ix);
1322 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix,
1323 data->pwm_rr[ix > 0]);
dbc2bc25 1324 dme1737_write(data,
9431996f
JH		 1325 DME1737_REG_PWM_RR(ix > 0),
1326 data->pwm_rr[ix > 0]);
1327 }
1328 }
1329 /* Set the new PWM mode */
1330 switch (val) {
1331 case 0:
1332 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1333 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1334 S_IRUGO);
1335 /* Turn fan fully on */
1336 data->pwm_config[ix] = PWM_EN_TO_REG(0,
1337 data->pwm_config[ix]);
dbc2bc25 1338 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1339 data->pwm_config[ix]);
1340 break;
1341 case 1:
1342 /* Turn on manual mode */
1343 data->pwm_config[ix] = PWM_EN_TO_REG(1,
1344 data->pwm_config[ix]);
dbc2bc25 1345 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1346 data->pwm_config[ix]);
1347 /* Change permissions of pwm[ix] to read-writeable */
73ce48f6 1348 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f
JH		 1349 S_IRUGO | S_IWUSR);
1350 break;
1351 case 2:
1352 /* Change permissions of pwm[ix] to read-only */
73ce48f6 1353 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix],
9431996f 1354 S_IRUGO);
c8de8362
GR		 1355 /*
1356 * Turn on auto mode using the saved zone channel
1357 * assignment
1358 */
9431996f
JH		 1359 data->pwm_config[ix] = PWM_ACZ_TO_REG(
1360 data->pwm_acz[ix],
1361 data->pwm_config[ix]);
dbc2bc25 1362 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1363 data->pwm_config[ix]);
1364 /* Enable PWM ramp rate if previously enabled */
1365 if (data->pwm_rr_en & (1 << ix)) {
1366 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix,
dbc2bc25 1367 dme1737_read(data,
9431996f 1368 DME1737_REG_PWM_RR(ix > 0)));
dbc2bc25 1369 dme1737_write(data,
9431996f
JH		 1370 DME1737_REG_PWM_RR(ix > 0),
1371 data->pwm_rr[ix > 0]);
1372 }
1373 break;
1374 }
1375 break;
1376 case SYS_PWM_RAMP_RATE:
1377 /* Only valid for pwm[1-3] */
1378 /* Refresh the cache */
dbc2bc25 1379 data->pwm_config[ix] = dme1737_read(data,
9431996f 1380 DME1737_REG_PWM_CONFIG(ix));
dbc2bc25 1381 data->pwm_rr[ix > 0] = dme1737_read(data,
9431996f
JH		 1382 DME1737_REG_PWM_RR(ix > 0));
1383 /* Set the ramp rate value */
1384 if (val > 0) {
1385 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix,
1386 data->pwm_rr[ix > 0]);
1387 }
c8de8362
GR		 1388 /*
1389 * Enable/disable the feature only if the associated PWM
1390 * output is in automatic mode.
1391 */
9431996f
JH		 1392 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
1393 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix,
1394 data->pwm_rr[ix > 0]);
1395 }
dbc2bc25 1396 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0),
9431996f
JH		 1397 data->pwm_rr[ix > 0]);
1398 break;
1399 case SYS_PWM_AUTO_CHANNELS_ZONE:
1400 /* Only valid for pwm[1-3] */
1401 if (!(val == 1 || val == 2 || val == 4 ||
1402 val == 6 || val == 7)) {
1403 count = -EINVAL;
b55f3757
GR		 1404 dev_warn(dev,
1405 "PWM auto channels zone %ld not supported. Choose one of 1, 2, 4, 6, "
9431996f
JH		 1406 "or 7.\n", val);
1407 goto exit;
1408 }
1409 /* Refresh the cache */
dbc2bc25 1410 data->pwm_config[ix] = dme1737_read(data,
9431996f
JH		 1411 DME1737_REG_PWM_CONFIG(ix));
1412 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) {
c8de8362
GR		 1413 /*
1414 * PWM is already in auto mode so update the temp
1415 * channel assignment
1416 */
9431996f
JH		 1417 data->pwm_config[ix] = PWM_ACZ_TO_REG(val,
1418 data->pwm_config[ix]);
dbc2bc25 1419 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix),
9431996f
JH		 1420 data->pwm_config[ix]);
1421 } else {
c8de8362
GR		 1422 /*
1423 * PWM is not in auto mode so we save the temp
1424 * channel assignment for later use
1425 */
9431996f
JH		 1426 data->pwm_acz[ix] = val;
1427 }
1428 break;
1429 case SYS_PWM_AUTO_PWM_MIN:
1430 /* Only valid for pwm[1-3] */
1431 /* Refresh the cache */
dbc2bc25 1432 data->pwm_min[ix] = dme1737_read(data,
9431996f 1433 DME1737_REG_PWM_MIN(ix));
c8de8362
GR		 1434 /*
1435 * There are only 2 values supported for the auto_pwm_min
9431996f
JH		 1436 * value: 0 or auto_point1_pwm. So if the temperature drops
1437 * below the auto_point1_temp_hyst value, the fan either turns
c8de8362
GR		 1438 * off or runs at auto_point1_pwm duty-cycle.
1439 */
9431996f
JH		 1440 if (val > ((data->pwm_min[ix] + 1) / 2)) {
1441 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix,
dbc2bc25 1442 dme1737_read(data,
9431996f 1443 DME1737_REG_PWM_RR(0)));
9431996f
JH		 1444 } else {
1445 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix,
dbc2bc25 1446 dme1737_read(data,
9431996f 1447 DME1737_REG_PWM_RR(0)));
9431996f 1448 }
dbc2bc25 1449 dme1737_write(data, DME1737_REG_PWM_RR(0),
9431996f
JH		 1450 data->pwm_rr[0]);
1451 break;
1452 case SYS_PWM_AUTO_POINT1_PWM:
1453 /* Only valid for pwm[1-3] */
2a844c14 1454 data->pwm_min[ix] = clamp_val(val, 0, 255);
dbc2bc25 1455 dme1737_write(data, DME1737_REG_PWM_MIN(ix),
9431996f
JH		 1456 data->pwm_min[ix]);
1457 break;
1458 default:
b237eb25 1459 dev_dbg(dev, "Unknown function %d.\n", fn);
9431996f
JH		 1460 }
1461exit:
1462 mutex_unlock(&data->update_lock);
1463
1464 return count;
1465}
1466
1467/* ---------------------------------------------------------------------
1468 * Miscellaneous sysfs attributes
1469 * --------------------------------------------------------------------- */
1470
1471static ssize_t show_vrm(struct device *dev, struct device_attribute *attr,
1472 char *buf)
1473{
1474 struct i2c_client *client = to_i2c_client(dev);
1475 struct dme1737_data *data = i2c_get_clientdata(client);
1476
1477 return sprintf(buf, "%d\n", data->vrm);
1478}
1479
1480static ssize_t set_vrm(struct device *dev, struct device_attribute *attr,
1481 const char *buf, size_t count)
1482{
b237eb25 1483 struct dme1737_data *data = dev_get_drvdata(dev);
30b72362 1484 unsigned long val;
c8de8362
GR		 1485 int err;
1486
30b72362 1487 err = kstrtoul(buf, 10, &val);
c8de8362
GR		 1488 if (err)
1489 return err;
9431996f 1490
30b72362
AL		 1491 if (val > 255)
1492 return -EINVAL;
1493
9431996f
JH		 1494 data->vrm = val;
1495 return count;
1496}
1497
1498static ssize_t show_vid(struct device *dev, struct device_attribute *attr,
1499 char *buf)
1500{
1501 struct dme1737_data *data = dme1737_update_device(dev);
1502
1503 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1504}
1505
e95c237d
JH		 1506static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1507 char *buf)
1508{
1509 struct dme1737_data *data = dev_get_drvdata(dev);
1510
dbc2bc25 1511 return sprintf(buf, "%s\n", data->name);
e95c237d
JH		 1512}
1513
9431996f
JH		 1514/* ---------------------------------------------------------------------
1515 * Sysfs device attribute defines and structs
1516 * --------------------------------------------------------------------- */
1517
d4b94e1f 1518/* Voltages 0-7 */
9431996f
JH		 1519
1520#define SENSOR_DEVICE_ATTR_IN(ix) \
1521static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \
b237eb25 1522 show_in, NULL, SYS_IN_INPUT, ix); \
9431996f 1523static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1524 show_in, set_in, SYS_IN_MIN, ix); \
9431996f 1525static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1526 show_in, set_in, SYS_IN_MAX, ix); \
9431996f 1527static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \
b237eb25 1528 show_in, NULL, SYS_IN_ALARM, ix)
9431996f
JH		 1529
1530SENSOR_DEVICE_ATTR_IN(0);
1531SENSOR_DEVICE_ATTR_IN(1);
1532SENSOR_DEVICE_ATTR_IN(2);
1533SENSOR_DEVICE_ATTR_IN(3);
1534SENSOR_DEVICE_ATTR_IN(4);
1535SENSOR_DEVICE_ATTR_IN(5);
1536SENSOR_DEVICE_ATTR_IN(6);
d4b94e1f 1537SENSOR_DEVICE_ATTR_IN(7);
9431996f
JH		 1538
1539/* Temperatures 1-3 */
1540
1541#define SENSOR_DEVICE_ATTR_TEMP(ix) \
1542static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \
b237eb25 1543 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \
9431996f 1544static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1545 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \
9431996f 1546static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1547 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \
9431996f 1548static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \
b237eb25 1549 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \
9431996f 1550static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \
b237eb25 1551 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \
9431996f 1552static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \
b237eb25 1553 show_temp, NULL, SYS_TEMP_FAULT, ix-1)
9431996f
JH		 1554
1555SENSOR_DEVICE_ATTR_TEMP(1);
1556SENSOR_DEVICE_ATTR_TEMP(2);
1557SENSOR_DEVICE_ATTR_TEMP(3);
1558
1559/* Zones 1-3 */
1560
1561#define SENSOR_DEVICE_ATTR_ZONE(ix) \
1562static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \
b237eb25 1563 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \
9431996f 1564static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \
b237eb25 1565 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \
9431996f 1566static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \
b237eb25 1567 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \
9431996f 1568static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \
b237eb25 1569 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \
9431996f 1570static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \
b237eb25 1571 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1)
9431996f
JH		 1572
1573SENSOR_DEVICE_ATTR_ZONE(1);
1574SENSOR_DEVICE_ATTR_ZONE(2);
1575SENSOR_DEVICE_ATTR_ZONE(3);
1576
1577/* Fans 1-4 */
1578
1579#define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \
1580static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1581 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1582static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1583 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1584static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1585 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1586static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \
b237eb25 1587 show_fan, set_fan, SYS_FAN_TYPE, ix-1)
9431996f
JH		 1588
1589SENSOR_DEVICE_ATTR_FAN_1TO4(1);
1590SENSOR_DEVICE_ATTR_FAN_1TO4(2);
1591SENSOR_DEVICE_ATTR_FAN_1TO4(3);
1592SENSOR_DEVICE_ATTR_FAN_1TO4(4);
1593
1594/* Fans 5-6 */
1595
1596#define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \
1597static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \
b237eb25 1598 show_fan, NULL, SYS_FAN_INPUT, ix-1); \
9431996f 1599static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \
b237eb25 1600 show_fan, set_fan, SYS_FAN_MIN, ix-1); \
9431996f 1601static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \
b237eb25 1602 show_fan, NULL, SYS_FAN_ALARM, ix-1); \
9431996f 1603static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \
b237eb25 1604 show_fan, set_fan, SYS_FAN_MAX, ix-1)
9431996f
JH		 1605
1606SENSOR_DEVICE_ATTR_FAN_5TO6(5);
1607SENSOR_DEVICE_ATTR_FAN_5TO6(6);
1608
1609/* PWMs 1-3 */
1610
1611#define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \
1612static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1613 show_pwm, set_pwm, SYS_PWM, ix-1); \
9431996f 1614static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1615 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1616static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1617 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \
9431996f 1618static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \
b237eb25 1619 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \
9431996f 1620static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \
b237eb25 1621 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \
9431996f 1622static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \
b237eb25 1623 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \
9431996f 1624static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \
b237eb25 1625 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \
9431996f 1626static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \
b237eb25 1627 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1)
9431996f
JH		 1628
1629SENSOR_DEVICE_ATTR_PWM_1TO3(1);
1630SENSOR_DEVICE_ATTR_PWM_1TO3(2);
1631SENSOR_DEVICE_ATTR_PWM_1TO3(3);
1632
1633/* PWMs 5-6 */
1634
1635#define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \
9b257714 1636static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \
b237eb25 1637 show_pwm, set_pwm, SYS_PWM, ix-1); \
9b257714 1638static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \
b237eb25 1639 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \
9431996f 1640static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \
b237eb25 1641 show_pwm, NULL, SYS_PWM_ENABLE, ix-1)
9431996f
JH		 1642
1643SENSOR_DEVICE_ATTR_PWM_5TO6(5);
1644SENSOR_DEVICE_ATTR_PWM_5TO6(6);
1645
1646/* Misc */
1647
1648static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm);
1649static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
e95c237d 1650static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */
9431996f 1651
c8de8362
GR		 1652/*
1653 * This struct holds all the attributes that are always present and need to be
9431996f
JH		 1654 * created unconditionally. The attributes that need modification of their
1655 * permissions are created read-only and write permissions are added or removed
c8de8362
GR		 1656 * on the fly when required
1657 */
06f3d9fb 1658static struct attribute *dme1737_attr[] = {
b237eb25 1659 /* Voltages */
9b257714
JH		 1660 &sensor_dev_attr_in0_input.dev_attr.attr,
1661 &sensor_dev_attr_in0_min.dev_attr.attr,
1662 &sensor_dev_attr_in0_max.dev_attr.attr,
1663 &sensor_dev_attr_in0_alarm.dev_attr.attr,
1664 &sensor_dev_attr_in1_input.dev_attr.attr,
1665 &sensor_dev_attr_in1_min.dev_attr.attr,
1666 &sensor_dev_attr_in1_max.dev_attr.attr,
1667 &sensor_dev_attr_in1_alarm.dev_attr.attr,
1668 &sensor_dev_attr_in2_input.dev_attr.attr,
1669 &sensor_dev_attr_in2_min.dev_attr.attr,
1670 &sensor_dev_attr_in2_max.dev_attr.attr,
1671 &sensor_dev_attr_in2_alarm.dev_attr.attr,
1672 &sensor_dev_attr_in3_input.dev_attr.attr,
1673 &sensor_dev_attr_in3_min.dev_attr.attr,
1674 &sensor_dev_attr_in3_max.dev_attr.attr,
1675 &sensor_dev_attr_in3_alarm.dev_attr.attr,
1676 &sensor_dev_attr_in4_input.dev_attr.attr,
1677 &sensor_dev_attr_in4_min.dev_attr.attr,
1678 &sensor_dev_attr_in4_max.dev_attr.attr,
1679 &sensor_dev_attr_in4_alarm.dev_attr.attr,
1680 &sensor_dev_attr_in5_input.dev_attr.attr,
1681 &sensor_dev_attr_in5_min.dev_attr.attr,
1682 &sensor_dev_attr_in5_max.dev_attr.attr,
1683 &sensor_dev_attr_in5_alarm.dev_attr.attr,
1684 &sensor_dev_attr_in6_input.dev_attr.attr,
1685 &sensor_dev_attr_in6_min.dev_attr.attr,
1686 &sensor_dev_attr_in6_max.dev_attr.attr,
1687 &sensor_dev_attr_in6_alarm.dev_attr.attr,
b237eb25 1688 /* Temperatures */
9b257714
JH		 1689 &sensor_dev_attr_temp1_input.dev_attr.attr,
1690 &sensor_dev_attr_temp1_min.dev_attr.attr,
1691 &sensor_dev_attr_temp1_max.dev_attr.attr,
1692 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
1693 &sensor_dev_attr_temp1_fault.dev_attr.attr,
9b257714
JH		 1694 &sensor_dev_attr_temp2_input.dev_attr.attr,
1695 &sensor_dev_attr_temp2_min.dev_attr.attr,
1696 &sensor_dev_attr_temp2_max.dev_attr.attr,
1697 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
1698 &sensor_dev_attr_temp2_fault.dev_attr.attr,
9b257714
JH		 1699 &sensor_dev_attr_temp3_input.dev_attr.attr,
1700 &sensor_dev_attr_temp3_min.dev_attr.attr,
1701 &sensor_dev_attr_temp3_max.dev_attr.attr,
1702 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
1703 &sensor_dev_attr_temp3_fault.dev_attr.attr,
b237eb25 1704 /* Zones */
9b257714
JH		 1705 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1706 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1707 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
1708 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr,
9b257714
JH		 1709 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1710 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1711 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
1712 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr,
549edb83
JH		 1713 NULL
1714};
1715
1716static const struct attribute_group dme1737_group = {
1717 .attrs = dme1737_attr,
1718};
1719
c8de8362
GR		 1720/*
1721 * The following struct holds temp offset attributes, which are not available
ea694431 1722 * in all chips. The following chips support them:
c8de8362
GR		 1723 * DME1737, SCH311x
1724 */
ea694431 1725static struct attribute *dme1737_temp_offset_attr[] = {
549edb83
JH		 1726 &sensor_dev_attr_temp1_offset.dev_attr.attr,
1727 &sensor_dev_attr_temp2_offset.dev_attr.attr,
1728 &sensor_dev_attr_temp3_offset.dev_attr.attr,
9431996f
JH		 1729 NULL
1730};
1731
ea694431
JH		 1732static const struct attribute_group dme1737_temp_offset_group = {
1733 .attrs = dme1737_temp_offset_attr,
9431996f
JH		 1734};
1735
c8de8362
GR		 1736/*
1737 * The following struct holds VID related attributes, which are not available
ea694431 1738 * in all chips. The following chips support them:
c8de8362
GR		 1739 * DME1737
1740 */
9d091446
JD		 1741static struct attribute *dme1737_vid_attr[] = {
1742 &dev_attr_vrm.attr,
1743 &dev_attr_cpu0_vid.attr,
1744 NULL
1745};
1746
1747static const struct attribute_group dme1737_vid_group = {
1748 .attrs = dme1737_vid_attr,
1749};
1750
c8de8362
GR		 1751/*
1752 * The following struct holds temp zone 3 related attributes, which are not
ea694431 1753 * available in all chips. The following chips support them:
c8de8362
GR		 1754 * DME1737, SCH311x, SCH5027
1755 */
ea694431
JH		 1756static struct attribute *dme1737_zone3_attr[] = {
1757 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1758 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1759 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
1760 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr,
1761 NULL
1762};
1763
1764static const struct attribute_group dme1737_zone3_group = {
1765 .attrs = dme1737_zone3_attr,
1766};
1767
1768
c8de8362
GR		 1769/*
1770 * The following struct holds temp zone hysteresis related attributes, which
ea694431 1771 * are not available in all chips. The following chips support them:
c8de8362
GR		 1772 * DME1737, SCH311x
1773 */
ea694431
JH		 1774static struct attribute *dme1737_zone_hyst_attr[] = {
1775 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr,
1776 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr,
1777 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr,
1778 NULL
1779};
1780
1781static const struct attribute_group dme1737_zone_hyst_group = {
1782 .attrs = dme1737_zone_hyst_attr,
1783};
1784
c8de8362
GR		 1785/*
1786 * The following struct holds voltage in7 related attributes, which
d4b94e1f 1787 * are not available in all chips. The following chips support them:
c8de8362
GR		 1788 * SCH5127
1789 */
d4b94e1f
JH		 1790static struct attribute *dme1737_in7_attr[] = {
1791 &sensor_dev_attr_in7_input.dev_attr.attr,
1792 &sensor_dev_attr_in7_min.dev_attr.attr,
1793 &sensor_dev_attr_in7_max.dev_attr.attr,
1794 &sensor_dev_attr_in7_alarm.dev_attr.attr,
1795 NULL
1796};
1797
1798static const struct attribute_group dme1737_in7_group = {
1799 .attrs = dme1737_in7_attr,
1800};
1801
c8de8362
GR		 1802/*
1803 * The following structs hold the PWM attributes, some of which are optional.
9431996f 1804 * Their creation depends on the chip configuration which is determined during
c8de8362
GR		 1805 * module load.
1806 */
73ce48f6 1807static struct attribute *dme1737_pwm1_attr[] = {
9b257714
JH		 1808 &sensor_dev_attr_pwm1.dev_attr.attr,
1809 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1810 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1811 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1812 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1813 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
1814 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1815 NULL
1816};
73ce48f6 1817static struct attribute *dme1737_pwm2_attr[] = {
9b257714
JH		 1818 &sensor_dev_attr_pwm2.dev_attr.attr,
1819 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1820 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1821 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1822 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1823 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
1824 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1825 NULL
1826};
73ce48f6 1827static struct attribute *dme1737_pwm3_attr[] = {
9b257714
JH		 1828 &sensor_dev_attr_pwm3.dev_attr.attr,
1829 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1830 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1831 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1832 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714
JH		 1833 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
1834 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
9431996f
JH		 1835 NULL
1836};
73ce48f6 1837static struct attribute *dme1737_pwm5_attr[] = {
9b257714
JH		 1838 &sensor_dev_attr_pwm5.dev_attr.attr,
1839 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
1840 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
9431996f
JH		 1841 NULL
1842};
73ce48f6 1843static struct attribute *dme1737_pwm6_attr[] = {
9b257714
JH		 1844 &sensor_dev_attr_pwm6.dev_attr.attr,
1845 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
1846 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
9431996f
JH		 1847 NULL
1848};
1849
1850static const struct attribute_group dme1737_pwm_group[] = {
73ce48f6
JH		 1851 { .attrs = dme1737_pwm1_attr },
1852 { .attrs = dme1737_pwm2_attr },
1853 { .attrs = dme1737_pwm3_attr },
9431996f 1854 { .attrs = NULL },
73ce48f6
JH		 1855 { .attrs = dme1737_pwm5_attr },
1856 { .attrs = dme1737_pwm6_attr },
9431996f
JH		 1857};
1858
c8de8362
GR		 1859/*
1860 * The following struct holds auto PWM min attributes, which are not available
ea694431 1861 * in all chips. Their creation depends on the chip type which is determined
c8de8362
GR		 1862 * during module load.
1863 */
ea694431 1864static struct attribute *dme1737_auto_pwm_min_attr[] = {
549edb83
JH		 1865 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr,
1866 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr,
1867 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr,
1868};
1869
c8de8362
GR		 1870/*
1871 * The following structs hold the fan attributes, some of which are optional.
9431996f 1872 * Their creation depends on the chip configuration which is determined during
c8de8362
GR		 1873 * module load.
1874 */
73ce48f6 1875static struct attribute *dme1737_fan1_attr[] = {
9b257714
JH		 1876 &sensor_dev_attr_fan1_input.dev_attr.attr,
1877 &sensor_dev_attr_fan1_min.dev_attr.attr,
1878 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
1879 &sensor_dev_attr_fan1_type.dev_attr.attr,
9431996f
JH		 1880 NULL
1881};
73ce48f6 1882static struct attribute *dme1737_fan2_attr[] = {
9b257714
JH		 1883 &sensor_dev_attr_fan2_input.dev_attr.attr,
1884 &sensor_dev_attr_fan2_min.dev_attr.attr,
1885 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
1886 &sensor_dev_attr_fan2_type.dev_attr.attr,
9431996f
JH		 1887 NULL
1888};
73ce48f6 1889static struct attribute *dme1737_fan3_attr[] = {
9b257714
JH		 1890 &sensor_dev_attr_fan3_input.dev_attr.attr,
1891 &sensor_dev_attr_fan3_min.dev_attr.attr,
1892 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
1893 &sensor_dev_attr_fan3_type.dev_attr.attr,
9431996f
JH		 1894 NULL
1895};
73ce48f6 1896static struct attribute *dme1737_fan4_attr[] = {
9b257714
JH		 1897 &sensor_dev_attr_fan4_input.dev_attr.attr,
1898 &sensor_dev_attr_fan4_min.dev_attr.attr,
1899 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
1900 &sensor_dev_attr_fan4_type.dev_attr.attr,
9431996f
JH		 1901 NULL
1902};
73ce48f6 1903static struct attribute *dme1737_fan5_attr[] = {
9b257714
JH		 1904 &sensor_dev_attr_fan5_input.dev_attr.attr,
1905 &sensor_dev_attr_fan5_min.dev_attr.attr,
1906 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
1907 &sensor_dev_attr_fan5_max.dev_attr.attr,
9431996f
JH		 1908 NULL
1909};
73ce48f6 1910static struct attribute *dme1737_fan6_attr[] = {
9b257714
JH		 1911 &sensor_dev_attr_fan6_input.dev_attr.attr,
1912 &sensor_dev_attr_fan6_min.dev_attr.attr,
1913 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
1914 &sensor_dev_attr_fan6_max.dev_attr.attr,
9431996f
JH		 1915 NULL
1916};
1917
1918static const struct attribute_group dme1737_fan_group[] = {
73ce48f6
JH		 1919 { .attrs = dme1737_fan1_attr },
1920 { .attrs = dme1737_fan2_attr },
1921 { .attrs = dme1737_fan3_attr },
1922 { .attrs = dme1737_fan4_attr },
1923 { .attrs = dme1737_fan5_attr },
1924 { .attrs = dme1737_fan6_attr },
9431996f
JH		 1925};
1926
c8de8362
GR		 1927/*
1928 * The permissions of the following zone attributes are changed to read-
1929 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1930 */
549edb83 1931static struct attribute *dme1737_zone_chmod_attr[] = {
9b257714
JH		 1932 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr,
1933 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr,
1934 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr,
9b257714
JH		 1935 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr,
1936 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr,
1937 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr,
ea694431
JH		 1938 NULL
1939};
1940
1941static const struct attribute_group dme1737_zone_chmod_group = {
1942 .attrs = dme1737_zone_chmod_attr,
1943};
1944
1945
c8de8362
GR		 1946/*
1947 * The permissions of the following zone 3 attributes are changed to read-
1948 * writeable if the chip is *not* locked. Otherwise they stay read-only.
1949 */
ea694431 1950static struct attribute *dme1737_zone3_chmod_attr[] = {
9b257714
JH		 1951 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr,
1952 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr,
1953 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr,
9431996f
JH		 1954 NULL
1955};
1956
ea694431
JH		 1957static const struct attribute_group dme1737_zone3_chmod_group = {
1958 .attrs = dme1737_zone3_chmod_attr,
9431996f
JH		 1959};
1960
c8de8362
GR		 1961/*
1962 * The permissions of the following PWM attributes are changed to read-
9431996f 1963 * writeable if the chip is *not* locked and the respective PWM is available.
c8de8362
GR		 1964 * Otherwise they stay read-only.
1965 */
73ce48f6 1966static struct attribute *dme1737_pwm1_chmod_attr[] = {
9b257714
JH		 1967 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
1968 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1969 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr,
1970 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr,
9b257714 1971 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1972 NULL
1973};
73ce48f6 1974static struct attribute *dme1737_pwm2_chmod_attr[] = {
9b257714
JH		 1975 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
1976 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
1977 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr,
1978 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr,
9b257714 1979 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1980 NULL
1981};
73ce48f6 1982static struct attribute *dme1737_pwm3_chmod_attr[] = {
9b257714
JH		 1983 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
1984 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
1985 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr,
1986 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr,
9b257714 1987 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,
9431996f
JH		 1988 NULL
1989};
73ce48f6 1990static struct attribute *dme1737_pwm5_chmod_attr[] = {
9b257714
JH		 1991 &sensor_dev_attr_pwm5.dev_attr.attr,
1992 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
9431996f
JH		 1993 NULL
1994};
73ce48f6 1995static struct attribute *dme1737_pwm6_chmod_attr[] = {
9b257714
JH		 1996 &sensor_dev_attr_pwm6.dev_attr.attr,
1997 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
9431996f
JH		 1998 NULL
1999};
2000
73ce48f6
JH		 2001static const struct attribute_group dme1737_pwm_chmod_group[] = {
2002 { .attrs = dme1737_pwm1_chmod_attr },
2003 { .attrs = dme1737_pwm2_chmod_attr },
2004 { .attrs = dme1737_pwm3_chmod_attr },
9431996f 2005 { .attrs = NULL },
73ce48f6
JH		 2006 { .attrs = dme1737_pwm5_chmod_attr },
2007 { .attrs = dme1737_pwm6_chmod_attr },
9431996f
JH		 2008};
2009
c8de8362
GR		 2010/*
2011 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the
2012 * chip is not locked. Otherwise they are read-only.
2013 */
73ce48f6 2014static struct attribute *dme1737_pwm_chmod_attr[] = {
9431996f
JH		 2015 &sensor_dev_attr_pwm1.dev_attr.attr,
2016 &sensor_dev_attr_pwm2.dev_attr.attr,
2017 &sensor_dev_attr_pwm3.dev_attr.attr,
2018};
2019
2020/* ---------------------------------------------------------------------
2021 * Super-IO functions
2022 * --------------------------------------------------------------------- */
2023
b237eb25
JH		 2024static inline void dme1737_sio_enter(int sio_cip)
2025{
2026 outb(0x55, sio_cip);
2027}
2028
2029static inline void dme1737_sio_exit(int sio_cip)
2030{
2031 outb(0xaa, sio_cip);
2032}
2033
9431996f
JH		 2034static inline int dme1737_sio_inb(int sio_cip, int reg)
2035{
2036 outb(reg, sio_cip);
2037 return inb(sio_cip + 1);
2038}
2039
2040static inline void dme1737_sio_outb(int sio_cip, int reg, int val)
2041{
2042 outb(reg, sio_cip);
2043 outb(val, sio_cip + 1);
2044}
2045
9431996f 2046/* ---------------------------------------------------------------------
e95c237d 2047 * Device initialization
9431996f
JH		 2048 * --------------------------------------------------------------------- */
2049
67e2f328 2050static int dme1737_i2c_get_features(int, struct dme1737_data*);
9431996f 2051
b237eb25 2052static void dme1737_chmod_file(struct device *dev,
48176a97 2053 struct attribute *attr, umode_t mode)
9431996f 2054{
b237eb25
JH		 2055 if (sysfs_chmod_file(&dev->kobj, attr, mode)) {
2056 dev_warn(dev, "Failed to change permissions of %s.\n",
9431996f
JH		 2057 attr->name);
2058 }
2059}
2060
b237eb25 2061static void dme1737_chmod_group(struct device *dev,
9431996f 2062 const struct attribute_group *group,
48176a97 2063 umode_t mode)
9431996f
JH		 2064{
2065 struct attribute **attr;
2066
c8de8362 2067 for (attr = group->attrs; *attr; attr++)
b237eb25 2068 dme1737_chmod_file(dev, *attr, mode);
9431996f
JH		 2069}
2070
b237eb25 2071static void dme1737_remove_files(struct device *dev)
9431996f 2072{
b237eb25
JH		 2073 struct dme1737_data *data = dev_get_drvdata(dev);
2074 int ix;
2075
2076 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 2077 if (data->has_features & HAS_FAN(ix)) {
b237eb25
JH		 2078 sysfs_remove_group(&dev->kobj,
2079 &dme1737_fan_group[ix]);
2080 }
2081 }
2082
2083 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 2084 if (data->has_features & HAS_PWM(ix)) {
b237eb25
JH		 2085 sysfs_remove_group(&dev->kobj,
2086 &dme1737_pwm_group[ix]);
ea694431 2087 if ((data->has_features & HAS_PWM_MIN) && ix < 3) {
549edb83 2088 sysfs_remove_file(&dev->kobj,
ea694431 2089 dme1737_auto_pwm_min_attr[ix]);
549edb83 2090 }
b237eb25
JH		 2091 }
2092 }
2093
c8de8362 2094 if (data->has_features & HAS_TEMP_OFFSET)
ea694431 2095 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group);
c8de8362 2096 if (data->has_features & HAS_VID)
9d091446 2097 sysfs_remove_group(&dev->kobj, &dme1737_vid_group);
c8de8362 2098 if (data->has_features & HAS_ZONE3)
ea694431 2099 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group);
c8de8362 2100 if (data->has_features & HAS_ZONE_HYST)
ea694431 2101 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group);
c8de8362 2102 if (data->has_features & HAS_IN7)
d4b94e1f 2103 sysfs_remove_group(&dev->kobj, &dme1737_in7_group);
b237eb25 2104 sysfs_remove_group(&dev->kobj, &dme1737_group);
e95c237d 2105
c8de8362 2106 if (!data->client)
e95c237d 2107 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr);
b237eb25
JH		 2108}
2109
2110static int dme1737_create_files(struct device *dev)
2111{
2112 struct dme1737_data *data = dev_get_drvdata(dev);
2113 int err, ix;
2114
e95c237d 2115 /* Create a name attribute for ISA devices */
06f3d9fb
JH		 2116 if (!data->client) {
2117 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr);
c8de8362 2118 if (err)
06f3d9fb 2119 goto exit;
e95c237d
JH		 2120 }
2121
b237eb25 2122 /* Create standard sysfs attributes */
06f3d9fb 2123 err = sysfs_create_group(&dev->kobj, &dme1737_group);
c8de8362 2124 if (err)
e95c237d 2125 goto exit_remove;
b237eb25 2126
ea694431 2127 /* Create chip-dependent sysfs attributes */
06f3d9fb
JH		 2128 if (data->has_features & HAS_TEMP_OFFSET) {
2129 err = sysfs_create_group(&dev->kobj,
2130 &dme1737_temp_offset_group);
c8de8362 2131 if (err)
06f3d9fb 2132 goto exit_remove;
549edb83 2133 }
06f3d9fb
JH		 2134 if (data->has_features & HAS_VID) {
2135 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group);
c8de8362 2136 if (err)
06f3d9fb 2137 goto exit_remove;
9d091446 2138 }
06f3d9fb
JH		 2139 if (data->has_features & HAS_ZONE3) {
2140 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group);
c8de8362 2141 if (err)
06f3d9fb 2142 goto exit_remove;
ea694431 2143 }
06f3d9fb
JH		 2144 if (data->has_features & HAS_ZONE_HYST) {
2145 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group);
c8de8362 2146 if (err)
06f3d9fb 2147 goto exit_remove;
ea694431 2148 }
d4b94e1f
JH		 2149 if (data->has_features & HAS_IN7) {
2150 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group);
c8de8362 2151 if (err)
d4b94e1f 2152 goto exit_remove;
d4b94e1f 2153 }
9d091446 2154
b237eb25
JH		 2155 /* Create fan sysfs attributes */
2156 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) {
ea694431 2157 if (data->has_features & HAS_FAN(ix)) {
06f3d9fb
JH		 2158 err = sysfs_create_group(&dev->kobj,
2159 &dme1737_fan_group[ix]);
c8de8362 2160 if (err)
b237eb25 2161 goto exit_remove;
b237eb25
JH		 2162 }
2163 }
2164
2165 /* Create PWM sysfs attributes */
2166 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) {
ea694431 2167 if (data->has_features & HAS_PWM(ix)) {
06f3d9fb
JH		 2168 err = sysfs_create_group(&dev->kobj,
2169 &dme1737_pwm_group[ix]);
c8de8362 2170 if (err)
b237eb25 2171 goto exit_remove;
06f3d9fb
JH		 2172 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) {
2173 err = sysfs_create_file(&dev->kobj,
2174 dme1737_auto_pwm_min_attr[ix]);
c8de8362 2175 if (err)
06f3d9fb 2176 goto exit_remove;
549edb83 2177 }
b237eb25
JH		 2178 }
2179 }
2180
c8de8362
GR		 2181 /*
2182 * Inform if the device is locked. Otherwise change the permissions of
2183 * selected attributes from read-only to read-writeable.
2184 */
b237eb25 2185 if (data->config & 0x02) {
b55f3757
GR		 2186 dev_info(dev,
2187 "Device is locked. Some attributes will be read-only.\n");
b237eb25 2188 } else {
549edb83
JH		 2189 /* Change permissions of zone sysfs attributes */
2190 dme1737_chmod_group(dev, &dme1737_zone_chmod_group,
b237eb25
JH		 2191 S_IRUGO | S_IWUSR);
2192
ea694431
JH		 2193 /* Change permissions of chip-dependent sysfs attributes */
2194 if (data->has_features & HAS_TEMP_OFFSET) {
2195 dme1737_chmod_group(dev, &dme1737_temp_offset_group,
2196 S_IRUGO | S_IWUSR);
2197 }
2198 if (data->has_features & HAS_ZONE3) {
2199 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group,
2200 S_IRUGO | S_IWUSR);
2201 }
2202 if (data->has_features & HAS_ZONE_HYST) {
2203 dme1737_chmod_group(dev, &dme1737_zone_hyst_group,
549edb83
JH		 2204 S_IRUGO | S_IWUSR);
2205 }
2206
73ce48f6
JH		 2207 /* Change permissions of PWM sysfs attributes */
2208 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) {
ea694431 2209 if (data->has_features & HAS_PWM(ix)) {
b237eb25 2210 dme1737_chmod_group(dev,
73ce48f6 2211 &dme1737_pwm_chmod_group[ix],
b237eb25 2212 S_IRUGO | S_IWUSR);
ea694431
JH		 2213 if ((data->has_features & HAS_PWM_MIN) &&
2214 ix < 3) {
549edb83 2215 dme1737_chmod_file(dev,
ea694431 2216 dme1737_auto_pwm_min_attr[ix],
549edb83
JH		 2217 S_IRUGO | S_IWUSR);
2218 }
b237eb25
JH		 2219 }
2220 }
2221
2222 /* Change permissions of pwm[1-3] if in manual mode */
2223 for (ix = 0; ix < 3; ix++) {
ea694431 2224 if ((data->has_features & HAS_PWM(ix)) &&
b237eb25
JH		 2225 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) {
2226 dme1737_chmod_file(dev,
73ce48f6 2227 dme1737_pwm_chmod_attr[ix],
b237eb25
JH		 2228 S_IRUGO | S_IWUSR);
2229 }
2230 }
2231 }
2232
2233 return 0;
2234
2235exit_remove:
2236 dme1737_remove_files(dev);
2237exit:
2238 return err;
2239}
2240
2241static int dme1737_init_device(struct device *dev)
2242{
2243 struct dme1737_data *data = dev_get_drvdata(dev);
dbc2bc25 2244 struct i2c_client *client = data->client;
9431996f
JH		 2245 int ix;
2246 u8 reg;
2247
549edb83
JH		 2248 /* Point to the right nominal voltages array */
2249 data->in_nominal = IN_NOMINAL(data->type);
2250
dbc2bc25 2251 data->config = dme1737_read(data, DME1737_REG_CONFIG);
b237eb25
JH		 2252 /* Inform if part is not monitoring/started */
2253 if (!(data->config & 0x01)) {
2254 if (!force_start) {
b55f3757
GR		 2255 dev_err(dev,
2256 "Device is not monitoring. Use the force_start load parameter to override.\n");
b237eb25
JH		 2257 return -EFAULT;
2258 }
2259
2260 /* Force monitoring */
2261 data->config |= 0x01;
dbc2bc25 2262 dme1737_write(data, DME1737_REG_CONFIG, data->config);
b237eb25 2263 }
9431996f
JH		 2264 /* Inform if part is not ready */
2265 if (!(data->config & 0x04)) {
b237eb25 2266 dev_err(dev, "Device is not ready.\n");
9431996f
JH		 2267 return -EFAULT;
2268 }
2269
c8de8362
GR		 2270 /*
2271 * Determine which optional fan and pwm features are enabled (only
2272 * valid for I2C devices)
2273 */
dbc2bc25
JD		 2274 if (client) { /* I2C chip */
2275 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2);
e95c237d 2276 /* Check if optional fan3 input is enabled */
c8de8362 2277 if (data->config2 & 0x04)
ea694431 2278 data->has_features |= HAS_FAN(2);
9431996f 2279
c8de8362
GR		 2280 /*
2281 * Fan4 and pwm3 are only available if the client's I2C address
e95c237d 2282 * is the default 0x2e. Otherwise the I/Os associated with
c8de8362
GR		 2283 * these functions are used for addr enable/select.
2284 */
2285 if (client->addr == 0x2e)
ea694431 2286 data->has_features |= HAS_FAN(3) | HAS_PWM(2);
9431996f 2287
c8de8362
GR		 2288 /*
2289 * Determine which of the optional fan[5-6] and pwm[5-6]
e95c237d
JH		 2290 * features are enabled. For this, we need to query the runtime
2291 * registers through the Super-IO LPC interface. Try both
c8de8362
GR		 2292 * config ports 0x2e and 0x4e.
2293 */
e95c237d
JH		 2294 if (dme1737_i2c_get_features(0x2e, data) &&
2295 dme1737_i2c_get_features(0x4e, data)) {
b55f3757
GR		 2296 dev_warn(dev,
2297 "Failed to query Super-IO for optional features.\n");
e95c237d 2298 }
9431996f
JH		 2299 }
2300
ea694431
JH		 2301 /* Fan[1-2] and pwm[1-2] are present in all chips */
2302 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1);
2303
2304 /* Chip-dependent features */
2305 switch (data->type) {
2306 case dme1737:
2307 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 |
2308 HAS_ZONE_HYST | HAS_PWM_MIN;
2309 break;
2310 case sch311x:
2311 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 |
2312 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2);
2313 break;
2314 case sch5027:
2315 data->has_features |= HAS_ZONE3;
2316 break;
2317 case sch5127:
d4b94e1f 2318 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7;
ea694431
JH		 2319 break;
2320 default:
2321 break;
2322 }
9431996f 2323
b55f3757
GR		 2324 dev_info(dev,
2325 "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n",
ea694431
JH		 2326 (data->has_features & HAS_PWM(2)) ? "yes" : "no",
2327 (data->has_features & HAS_PWM(4)) ? "yes" : "no",
2328 (data->has_features & HAS_PWM(5)) ? "yes" : "no",
2329 (data->has_features & HAS_FAN(2)) ? "yes" : "no",
2330 (data->has_features & HAS_FAN(3)) ? "yes" : "no",
2331 (data->has_features & HAS_FAN(4)) ? "yes" : "no",
2332 (data->has_features & HAS_FAN(5)) ? "yes" : "no");
9431996f 2333
dbc2bc25 2334 reg = dme1737_read(data, DME1737_REG_TACH_PWM);
9431996f 2335 /* Inform if fan-to-pwm mapping differs from the default */
dbc2bc25 2336 if (client && reg != 0xa4) { /* I2C chip */
b55f3757
GR		 2337 dev_warn(dev,
2338 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, fan4->pwm%d. %s\n",
9431996f 2339 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
b55f3757
GR		 2340 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1,
2341 DO_REPORT);
dbc2bc25 2342 } else if (!client && reg != 0x24) { /* ISA chip */
b55f3757
GR		 2343 dev_warn(dev,
2344 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. %s\n",
e95c237d 2345 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1,
b55f3757 2346 ((reg >> 4) & 0x03) + 1, DO_REPORT);
9431996f
JH		 2347 }
2348
c8de8362
GR		 2349 /*
2350 * Switch pwm[1-3] to manual mode if they are currently disabled and
9431996f 2351 * set the duty-cycles to 0% (which is identical to the PWMs being
c8de8362
GR		 2352 * disabled).
2353 */
9431996f
JH		 2354 if (!(data->config & 0x02)) {
2355 for (ix = 0; ix < 3; ix++) {
dbc2bc25 2356 data->pwm_config[ix] = dme1737_read(data,
9431996f 2357 DME1737_REG_PWM_CONFIG(ix));
ea694431 2358 if ((data->has_features & HAS_PWM(ix)) &&
9431996f 2359 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) {
b55f3757
GR		 2360 dev_info(dev,
2361 "Switching pwm%d to manual mode.\n",
2362 ix + 1);
9431996f
JH		 2363 data->pwm_config[ix] = PWM_EN_TO_REG(1,
2364 data->pwm_config[ix]);
dbc2bc25
JD		 2365 dme1737_write(data, DME1737_REG_PWM(ix), 0);
2366 dme1737_write(data,
9431996f
JH		 2367 DME1737_REG_PWM_CONFIG(ix),
2368 data->pwm_config[ix]);
2369 }
2370 }
2371 }
2372
2373 /* Initialize the default PWM auto channels zone (acz) assignments */
2374 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */
2375 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */
2376 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */
2377
2378 /* Set VRM */
c8de8362 2379 if (data->has_features & HAS_VID)
549edb83 2380 data->vrm = vid_which_vrm();
9431996f
JH		 2381
2382 return 0;
2383}
2384
67e2f328
JH		 2385/* ---------------------------------------------------------------------
2386 * I2C device detection and registration
2387 * --------------------------------------------------------------------- */
2388
2389static struct i2c_driver dme1737_i2c_driver;
2390
2391static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data)
2392{
2393 int err = 0, reg;
2394 u16 addr;
2395
2396 dme1737_sio_enter(sio_cip);
2397
c8de8362
GR		 2398 /*
2399 * Check device ID
2400 * We currently know about two kinds of DME1737 and SCH5027.
2401 */
345a2224 2402 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2403 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 ||
2404 reg == SCH5027_ID)) {
67e2f328
JH		 2405 err = -ENODEV;
2406 goto exit;
2407 }
2408
2409 /* Select logical device A (runtime registers) */
2410 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2411
2412 /* Get the base address of the runtime registers */
06f3d9fb
JH		 2413 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2414 dme1737_sio_inb(sio_cip, 0x61);
2415 if (!addr) {
67e2f328
JH		 2416 err = -ENODEV;
2417 goto exit;
2418 }
2419
c8de8362
GR		 2420 /*
2421 * Read the runtime registers to determine which optional features
67e2f328 2422 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set
c8de8362
GR		 2423 * to '10' if the respective feature is enabled.
2424 */
2425 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */
ea694431 2426 data->has_features |= HAS_FAN(5);
c8de8362 2427 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */
ea694431 2428 data->has_features |= HAS_PWM(5);
c8de8362 2429 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */
ea694431 2430 data->has_features |= HAS_FAN(4);
c8de8362 2431 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */
ea694431 2432 data->has_features |= HAS_PWM(4);
67e2f328
JH		 2433
2434exit:
2435 dme1737_sio_exit(sio_cip);
2436
2437 return err;
2438}
2439
67a37308 2440/* Return 0 if detection is successful, -ENODEV otherwise */
310ec792 2441static int dme1737_i2c_detect(struct i2c_client *client,
67a37308 2442 struct i2c_board_info *info)
9431996f 2443{
67a37308
JD		 2444 struct i2c_adapter *adapter = client->adapter;
2445 struct device *dev = &adapter->dev;
9431996f 2446 u8 company, verstep = 0;
9431996f
JH		 2447 const char *name;
2448
c8de8362 2449 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
67a37308 2450 return -ENODEV;
9431996f 2451
52df6440
JD		 2452 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY);
2453 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP);
9431996f 2454
52df6440
JD		 2455 if (company == DME1737_COMPANY_SMSC &&
2456 verstep == SCH5027_VERSTEP) {
549edb83 2457 name = "sch5027";
52df6440
JD		 2458 } else if (company == DME1737_COMPANY_SMSC &&
2459 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) {
549edb83 2460 name = "dme1737";
52df6440
JD		 2461 } else {
2462 return -ENODEV;
549edb83 2463 }
9431996f 2464
549edb83 2465 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n",
52df6440
JD		 2466 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737",
2467 client->addr, verstep);
67a37308
JD		 2468 strlcpy(info->type, name, I2C_NAME_SIZE);
2469
2470 return 0;
2471}
2472
2473static int dme1737_i2c_probe(struct i2c_client *client,
2474 const struct i2c_device_id *id)
2475{
2476 struct dme1737_data *data;
2477 struct device *dev = &client->dev;
2478 int err;
2479
805fd8c5
GR		 2480 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2481 if (!data)
2482 return -ENOMEM;
67a37308
JD		 2483
2484 i2c_set_clientdata(client, data);
2485 data->type = id->driver_data;
2486 data->client = client;
2487 data->name = client->name;
2488 mutex_init(&data->update_lock);
b237eb25 2489
9431996f 2490 /* Initialize the DME1737 chip */
06f3d9fb
JH		 2491 err = dme1737_init_device(dev);
2492 if (err) {
b237eb25 2493 dev_err(dev, "Failed to initialize device.\n");
805fd8c5 2494 return err;
9431996f
JH		 2495 }
2496
b237eb25 2497 /* Create sysfs files */
06f3d9fb
JH		 2498 err = dme1737_create_files(dev);
2499 if (err) {
b237eb25 2500 dev_err(dev, "Failed to create sysfs files.\n");
805fd8c5 2501 return err;
9431996f
JH		 2502 }
2503
2504 /* Register device */
62ee3e10 2505 data->hwmon_dev = hwmon_device_register(dev);
1beeffe4 2506 if (IS_ERR(data->hwmon_dev)) {
b237eb25 2507 dev_err(dev, "Failed to register device.\n");
1beeffe4 2508 err = PTR_ERR(data->hwmon_dev);
9431996f
JH		 2509 goto exit_remove;
2510 }
2511
9431996f
JH		 2512 return 0;
2513
2514exit_remove:
b237eb25 2515 dme1737_remove_files(dev);
9431996f
JH		 2516 return err;
2517}
2518
67a37308 2519static int dme1737_i2c_remove(struct i2c_client *client)
9431996f
JH		 2520{
2521 struct dme1737_data *data = i2c_get_clientdata(client);
9431996f 2522
1beeffe4 2523 hwmon_device_unregister(data->hwmon_dev);
b237eb25 2524 dme1737_remove_files(&client->dev);
9431996f 2525
9431996f
JH		 2526 return 0;
2527}
2528
67a37308
JD		 2529static const struct i2c_device_id dme1737_id[] = {
2530 { "dme1737", dme1737 },
2531 { "sch5027", sch5027 },
2532 { }
2533};
2534MODULE_DEVICE_TABLE(i2c, dme1737_id);
2535
b237eb25 2536static struct i2c_driver dme1737_i2c_driver = {
67a37308 2537 .class = I2C_CLASS_HWMON,
9431996f
JH		 2538 .driver = {
2539 .name = "dme1737",
2540 },
67a37308
JD		 2541 .probe = dme1737_i2c_probe,
2542 .remove = dme1737_i2c_remove,
2543 .id_table = dme1737_id,
2544 .detect = dme1737_i2c_detect,
c3813d6a 2545 .address_list = normal_i2c,
9431996f
JH		 2546};
2547
e95c237d
JH		 2548/* ---------------------------------------------------------------------
2549 * ISA device detection and registration
2550 * --------------------------------------------------------------------- */
2551
2552static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr)
2553{
2554 int err = 0, reg;
2555 unsigned short base_addr;
2556
2557 dme1737_sio_enter(sio_cip);
2558
c8de8362
GR		 2559 /*
2560 * Check device ID
2561 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127
2562 */
67b671bc 2563 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20);
ea694431
JH		 2564 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID ||
2565 reg == SCH5127_ID)) {
e95c237d
JH		 2566 err = -ENODEV;
2567 goto exit;
2568 }
2569
2570 /* Select logical device A (runtime registers) */
2571 dme1737_sio_outb(sio_cip, 0x07, 0x0a);
2572
2573 /* Get the base address of the runtime registers */
06f3d9fb
JH		 2574 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) |
2575 dme1737_sio_inb(sio_cip, 0x61);
2576 if (!base_addr) {
9c6e13b4 2577 pr_err("Base address not set\n");
e95c237d
JH		 2578 err = -ENODEV;
2579 goto exit;
2580 }
2581
c8de8362
GR		 2582 /*
2583 * Access to the hwmon registers is through an index/data register
2584 * pair located at offset 0x70/0x71.
2585 */
e95c237d
JH		 2586 *addr = base_addr + 0x70;
2587
2588exit:
2589 dme1737_sio_exit(sio_cip);
2590 return err;
2591}
2592
2593static int __init dme1737_isa_device_add(unsigned short addr)
2594{
2595 struct resource res = {
2596 .start = addr,
2597 .end = addr + DME1737_EXTENT - 1,
2598 .name = "dme1737",
2599 .flags = IORESOURCE_IO,
2600 };
2601 int err;
2602
b9acb64a
JD		 2603 err = acpi_check_resource_conflict(&res);
2604 if (err)
2605 goto exit;
2606
06f3d9fb
JH		 2607 pdev = platform_device_alloc("dme1737", addr);
2608 if (!pdev) {
9c6e13b4 2609 pr_err("Failed to allocate device\n");
e95c237d
JH		 2610 err = -ENOMEM;
2611 goto exit;
2612 }
2613
06f3d9fb
JH		 2614 err = platform_device_add_resources(pdev, &res, 1);
2615 if (err) {
9c6e13b4 2616 pr_err("Failed to add device resource (err = %d)\n", err);
e95c237d
JH		 2617 goto exit_device_put;
2618 }
2619
06f3d9fb
JH		 2620 err = platform_device_add(pdev);
2621 if (err) {
9c6e13b4 2622 pr_err("Failed to add device (err = %d)\n", err);
e95c237d
JH		 2623 goto exit_device_put;
2624 }
2625
2626 return 0;
2627
2628exit_device_put:
2629 platform_device_put(pdev);
2630 pdev = NULL;
2631exit:
2632 return err;
2633}
2634
6c931ae1 2635static int dme1737_isa_probe(struct platform_device *pdev)
e95c237d
JH		 2636{
2637 u8 company, device;
2638 struct resource *res;
e95c237d
JH		 2639 struct dme1737_data *data;
2640 struct device *dev = &pdev->dev;
2641 int err;
2642
2643 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
805fd8c5 2644 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) {
e95c237d
JH		 2645 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n",
2646 (unsigned short)res->start,
2647 (unsigned short)res->start + DME1737_EXTENT - 1);
805fd8c5 2648 return -EBUSY;
06f3d9fb 2649 }
e95c237d 2650
805fd8c5
GR		 2651 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL);
2652 if (!data)
2653 return -ENOMEM;
e95c237d 2654
dbc2bc25 2655 data->addr = res->start;
e95c237d
JH		 2656 platform_set_drvdata(pdev, data);
2657
55d68d75 2658 /* Skip chip detection if module is loaded with force_id parameter */
ea694431
JH		 2659 switch (force_id) {
2660 case SCH3112_ID:
2661 case SCH3114_ID:
2662 case SCH3116_ID:
2663 data->type = sch311x;
2664 break;
2665 case SCH5127_ID:
2666 data->type = sch5127;
2667 break;
2668 default:
dbc2bc25
JD		 2669 company = dme1737_read(data, DME1737_REG_COMPANY);
2670 device = dme1737_read(data, DME1737_REG_DEVICE);
e95c237d 2671
ea694431
JH		 2672 if ((company == DME1737_COMPANY_SMSC) &&
2673 (device == SCH311X_DEVICE)) {
2674 data->type = sch311x;
2675 } else if ((company == DME1737_COMPANY_SMSC) &&
2676 (device == SCH5127_DEVICE)) {
2677 data->type = sch5127;
2678 } else {
805fd8c5 2679 return -ENODEV;
55d68d75 2680 }
e95c237d
JH		 2681 }
2682
c8de8362 2683 if (data->type == sch5127)
ea694431 2684 data->name = "sch5127";
c8de8362 2685 else
ea694431 2686 data->name = "sch311x";
ea694431
JH		 2687
2688 /* Initialize the mutex */
e95c237d
JH		 2689 mutex_init(&data->update_lock);
2690
ea694431
JH		 2691 dev_info(dev, "Found a %s chip at 0x%04x\n",
2692 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr);
e95c237d
JH		 2693
2694 /* Initialize the chip */
06f3d9fb
JH		 2695 err = dme1737_init_device(dev);
2696 if (err) {
e95c237d 2697 dev_err(dev, "Failed to initialize device.\n");
805fd8c5 2698 return err;
e95c237d
JH		 2699 }
2700
2701 /* Create sysfs files */
06f3d9fb
JH		 2702 err = dme1737_create_files(dev);
2703 if (err) {
e95c237d 2704 dev_err(dev, "Failed to create sysfs files.\n");
805fd8c5 2705 return err;
e95c237d
JH		 2706 }
2707
2708 /* Register device */
2709 data->hwmon_dev = hwmon_device_register(dev);
2710 if (IS_ERR(data->hwmon_dev)) {
2711 dev_err(dev, "Failed to register device.\n");
2712 err = PTR_ERR(data->hwmon_dev);
2713 goto exit_remove_files;
2714 }
2715
2716 return 0;
2717
2718exit_remove_files:
2719 dme1737_remove_files(dev);
e95c237d
JH		 2720 return err;
2721}
2722
281dfd0b 2723static int dme1737_isa_remove(struct platform_device *pdev)
e95c237d
JH		 2724{
2725 struct dme1737_data *data = platform_get_drvdata(pdev);
2726
2727 hwmon_device_unregister(data->hwmon_dev);
2728 dme1737_remove_files(&pdev->dev);
e95c237d
JH		 2729
2730 return 0;
2731}
2732
2733static struct platform_driver dme1737_isa_driver = {
2734 .driver = {
2735 .owner = THIS_MODULE,
2736 .name = "dme1737",
2737 },
2738 .probe = dme1737_isa_probe,
9e5e9b7a 2739 .remove = dme1737_isa_remove,
e95c237d
JH		 2740};
2741
67e2f328
JH		 2742/* ---------------------------------------------------------------------
2743 * Module initialization and cleanup
2744 * --------------------------------------------------------------------- */
2745
9431996f
JH		 2746static int __init dme1737_init(void)
2747{
e95c237d
JH		 2748 int err;
2749 unsigned short addr;
2750
06f3d9fb 2751 err = i2c_add_driver(&dme1737_i2c_driver);
c8de8362 2752 if (err)
e95c237d 2753 goto exit;
e95c237d
JH		 2754
2755 if (dme1737_isa_detect(0x2e, &addr) &&
92430b6f
JH		 2756 dme1737_isa_detect(0x4e, &addr) &&
2757 (!probe_all_addr ||
2758 (dme1737_isa_detect(0x162e, &addr) &&
2759 dme1737_isa_detect(0x164e, &addr)))) {
e95c237d
JH		 2760 /* Return 0 if we didn't find an ISA device */
2761 return 0;
2762 }
2763
06f3d9fb 2764 err = platform_driver_register(&dme1737_isa_driver);
c8de8362 2765 if (err)
e95c237d 2766 goto exit_del_i2c_driver;
e95c237d
JH		 2767
2768 /* Sets global pdev as a side effect */
06f3d9fb 2769 err = dme1737_isa_device_add(addr);
c8de8362 2770 if (err)
e95c237d 2771 goto exit_del_isa_driver;
e95c237d
JH		 2772
2773 return 0;
2774
2775exit_del_isa_driver:
2776 platform_driver_unregister(&dme1737_isa_driver);
2777exit_del_i2c_driver:
2778 i2c_del_driver(&dme1737_i2c_driver);
2779exit:
2780 return err;
9431996f
JH		 2781}
2782
2783static void __exit dme1737_exit(void)
2784{
e95c237d
JH		 2785 if (pdev) {
2786 platform_device_unregister(pdev);
2787 platform_driver_unregister(&dme1737_isa_driver);
2788 }
2789
b237eb25 2790 i2c_del_driver(&dme1737_i2c_driver);
9431996f
JH		 2791}
2792
2793MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>");
2794MODULE_DESCRIPTION("DME1737 sensors");
2795MODULE_LICENSE("GPL");
2796
2797module_init(dme1737_init);
2798module_exit(dme1737_exit);
kernel source for telekom puls (alcatel/mediatek)