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vmwgfx: Drop 3D Legacy Display Unit support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
108 if (handle) {
7a73ba74
TH		 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface);
fb1d9738
JB		 111 if (!ret) {
112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n");
114 return -EINVAL;
115 }
116 } else {
117 ret = vmw_user_dmabuf_lookup(tfile,
118 handle, &dmabuf);
119 if (ret) {
120 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
121 return -EINVAL;
122 }
123 }
124 }
125
126 /* takedown old cursor */
127 if (du->cursor_surface) {
128 du->cursor_surface->snooper.crtc = NULL;
129 vmw_surface_unreference(&du->cursor_surface);
130 }
131 if (du->cursor_dmabuf)
132 vmw_dmabuf_unreference(&du->cursor_dmabuf);
133
134 /* setup new image */
135 if (surface) {
136 /* vmw_user_surface_lookup takes one reference */
137 du->cursor_surface = surface;
138
139 du->cursor_surface->snooper.crtc = crtc;
140 du->cursor_age = du->cursor_surface->snooper.age;
141 vmw_cursor_update_image(dev_priv, surface->snooper.image,
142 64, 64, du->hotspot_x, du->hotspot_y);
143 } else if (dmabuf) {
144 struct ttm_bo_kmap_obj map;
145 unsigned long kmap_offset;
146 unsigned long kmap_num;
147 void *virtual;
148 bool dummy;
149
150 /* vmw_user_surface_lookup takes one reference */
151 du->cursor_dmabuf = dmabuf;
152
153 kmap_offset = 0;
154 kmap_num = (64*64*4) >> PAGE_SHIFT;
155
156 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
157 if (unlikely(ret != 0)) {
158 DRM_ERROR("reserve failed\n");
159 return -EINVAL;
160 }
161
162 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
163 if (unlikely(ret != 0))
164 goto err_unreserve;
165
166 virtual = ttm_kmap_obj_virtual(&map, &dummy);
167 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
168 du->hotspot_x, du->hotspot_y);
169
170 ttm_bo_kunmap(&map);
171err_unreserve:
172 ttm_bo_unreserve(&dmabuf->base);
173
174 } else {
175 vmw_cursor_update_position(dev_priv, false, 0, 0);
176 return 0;
177 }
178
179 vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
180
181 return 0;
182}
183
184int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
185{
186 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
187 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
188 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
189
190 du->cursor_x = x + crtc->x;
191 du->cursor_y = y + crtc->y;
192
193 vmw_cursor_update_position(dev_priv, shown,
194 du->cursor_x, du->cursor_y);
195
196 return 0;
197}
198
199void vmw_kms_cursor_snoop(struct vmw_surface *srf,
200 struct ttm_object_file *tfile,
201 struct ttm_buffer_object *bo,
202 SVGA3dCmdHeader *header)
203{
204 struct ttm_bo_kmap_obj map;
205 unsigned long kmap_offset;
206 unsigned long kmap_num;
207 SVGA3dCopyBox *box;
208 unsigned box_count;
209 void *virtual;
210 bool dummy;
211 struct vmw_dma_cmd {
212 SVGA3dCmdHeader header;
213 SVGA3dCmdSurfaceDMA dma;
214 } *cmd;
215 int ret;
216
217 cmd = container_of(header, struct vmw_dma_cmd, header);
218
219 /* No snooper installed */
220 if (!srf->snooper.image)
221 return;
222
223 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
224 DRM_ERROR("face and mipmap for cursors should never != 0\n");
225 return;
226 }
227
228 if (cmd->header.size < 64) {
229 DRM_ERROR("at least one full copy box must be given\n");
230 return;
231 }
232
233 box = (SVGA3dCopyBox *)&cmd[1];
234 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
235 sizeof(SVGA3dCopyBox);
236
237 if (cmd->dma.guest.pitch != (64 * 4) ||
238 cmd->dma.guest.ptr.offset % PAGE_SIZE ||
239 box->x != 0 || box->y != 0 || box->z != 0 ||
240 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
241 box->w != 64 || box->h != 64 || box->d != 1 ||
242 box_count != 1) {
243 /* TODO handle none page aligned offsets */
244 /* TODO handle partial uploads and pitch != 256 */
245 /* TODO handle more then one copy (size != 64) */
25985edc 246 DRM_ERROR("lazy programmer, can't handle weird stuff\n");
fb1d9738
JB		 247 return;
248 }
249
250 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
251 kmap_num = (64*64*4) >> PAGE_SHIFT;
252
253 ret = ttm_bo_reserve(bo, true, false, false, 0);
254 if (unlikely(ret != 0)) {
255 DRM_ERROR("reserve failed\n");
256 return;
257 }
258
259 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
260 if (unlikely(ret != 0))
261 goto err_unreserve;
262
263 virtual = ttm_kmap_obj_virtual(&map, &dummy);
264
265 memcpy(srf->snooper.image, virtual, 64*64*4);
266 srf->snooper.age++;
267
268 /* we can't call this function from this function since execbuf has
269 * reserved fifo space.
270 *
271 * if (srf->snooper.crtc)
272 * vmw_ldu_crtc_cursor_update_image(dev_priv,
273 * srf->snooper.image, 64, 64,
274 * du->hotspot_x, du->hotspot_y);
275 */
276
277 ttm_bo_kunmap(&map);
278err_unreserve:
279 ttm_bo_unreserve(bo);
280}
281
282void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
283{
284 struct drm_device *dev = dev_priv->dev;
285 struct vmw_display_unit *du;
286 struct drm_crtc *crtc;
287
288 mutex_lock(&dev->mode_config.mutex);
289
290 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
291 du = vmw_crtc_to_du(crtc);
292 if (!du->cursor_surface ||
293 du->cursor_age == du->cursor_surface->snooper.age)
294 continue;
295
296 du->cursor_age = du->cursor_surface->snooper.age;
297 vmw_cursor_update_image(dev_priv,
298 du->cursor_surface->snooper.image,
299 64, 64, du->hotspot_x, du->hotspot_y);
300 }
301
302 mutex_unlock(&dev->mode_config.mutex);
303}
304
305/*
306 * Generic framebuffer code
307 */
308
309int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
310 struct drm_file *file_priv,
311 unsigned int *handle)
312{
313 if (handle)
314 handle = 0;
315
316 return 0;
317}
318
319/*
320 * Surface framebuffer code
321 */
322
323#define vmw_framebuffer_to_vfbs(x) \
324 container_of(x, struct vmw_framebuffer_surface, base.base)
325
326struct vmw_framebuffer_surface {
327 struct vmw_framebuffer base;
328 struct vmw_surface *surface;
22ee861c 329 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 330 struct list_head head;
331 struct drm_master *master;
fb1d9738
JB		 332};
333
334void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
335{
3a939a5e 336 struct vmw_framebuffer_surface *vfbs =
fb1d9738 337 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 338 struct vmw_master *vmaster = vmw_master(vfbs->master);
339
340
341 mutex_lock(&vmaster->fb_surf_mutex);
342 list_del(&vfbs->head);
343 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 344
3a939a5e 345 drm_master_put(&vfbs->master);
fb1d9738 346 drm_framebuffer_cleanup(framebuffer);
3a939a5e 347 vmw_surface_unreference(&vfbs->surface);
fb1d9738 348
3a939a5e 349 kfree(vfbs);
fb1d9738
JB		 350}
351
56d1c78d
JB		 352static int do_surface_dirty_sou(struct vmw_private *dev_priv,
353 struct vmw_framebuffer *framebuffer,
354 struct vmw_surface *surf,
355 unsigned flags, unsigned color,
356 struct drm_clip_rect *clips,
357 unsigned num_clips, int inc)
358{
359 int left = clips->x2, right = clips->x1;
360 int top = clips->y2, bottom = clips->y1;
361 size_t fifo_size;
362 int i;
363
364 struct {
365 SVGA3dCmdHeader header;
366 SVGA3dCmdBlitSurfaceToScreen body;
367 } *cmd;
368
369
370 fifo_size = sizeof(*cmd);
371 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
372 if (unlikely(cmd == NULL)) {
373 DRM_ERROR("Fifo reserve failed.\n");
374 return -ENOMEM;
375 }
376
377 memset(cmd, 0, fifo_size);
378
379 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
380 cmd->header.size = cpu_to_le32(sizeof(cmd->body));
381
382 cmd->body.srcImage.sid = cpu_to_le32(surf->res.id);
383 cmd->body.destScreenId = SVGA_ID_INVALID; /* virtual coords */
384
385 for (i = 0; i < num_clips; i++, clips += inc) {
386 left = min_t(int, left, (int)clips->x1);
387 right = max_t(int, right, (int)clips->x2);
388 top = min_t(int, top, (int)clips->y1);
389 bottom = max_t(int, bottom, (int)clips->y2);
390 }
391
392 cmd->body.srcRect.left = left;
393 cmd->body.srcRect.right = right;
394 cmd->body.srcRect.top = top;
395 cmd->body.srcRect.bottom = bottom;
396
397 cmd->body.destRect.left = left;
398 cmd->body.destRect.right = right;
399 cmd->body.destRect.top = top;
400 cmd->body.destRect.bottom = bottom;
401
402 vmw_fifo_commit(dev_priv, fifo_size);
403
5deb65cf
JB		 404 return 0;
405}
fb1d9738
JB		 406
407int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 408 struct drm_file *file_priv,
fb1d9738
JB		 409 unsigned flags, unsigned color,
410 struct drm_clip_rect *clips,
411 unsigned num_clips)
412{
413 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 414 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 415 struct vmw_framebuffer_surface *vfbs =
416 vmw_framebuffer_to_vfbs(framebuffer);
417 struct vmw_surface *surf = vfbs->surface;
418 struct drm_clip_rect norect;
5deb65cf 419 int ret, inc = 1;
fb1d9738 420
3a939a5e
TH		 421 if (unlikely(vfbs->master != file_priv->master))
422 return -EINVAL;
423
01e81419
JB		 424 /* Require ScreenObject support for 3D */
425 if (!dev_priv->sou_priv)
426 return -EINVAL;
427
3a939a5e
TH		 428 ret = ttm_read_lock(&vmaster->lock, true);
429 if (unlikely(ret != 0))
430 return ret;
431
fb1d9738
JB		 432 if (!num_clips) {
433 num_clips = 1;
434 clips = &norect;
435 norect.x1 = norect.y1 = 0;
436 norect.x2 = framebuffer->width;
437 norect.y2 = framebuffer->height;
438 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
439 num_clips /= 2;
440 inc = 2; /* skip source rects */
441 }
442
01e81419
JB		 443 ret = do_surface_dirty_sou(dev_priv, &vfbs->base, surf,
444 flags, color,
445 clips, num_clips, inc);
fb1d9738 446
3a939a5e 447 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 448 return 0;
449}
450
451static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
452 .destroy = vmw_framebuffer_surface_destroy,
453 .dirty = vmw_framebuffer_surface_dirty,
454 .create_handle = vmw_framebuffer_create_handle,
455};
456
d3216a0c 457static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 458 struct drm_file *file_priv,
d3216a0c
TH		 459 struct vmw_surface *surface,
460 struct vmw_framebuffer **out,
461 const struct drm_mode_fb_cmd
462 *mode_cmd)
fb1d9738
JB		 463
464{
465 struct drm_device *dev = dev_priv->dev;
466 struct vmw_framebuffer_surface *vfbs;
d3216a0c 467 enum SVGA3dSurfaceFormat format;
3a939a5e 468 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 469 int ret;
470
01e81419
JB		 471 /* 3D is only supported on HWv8 hosts which supports screen objects */
472 if (!dev_priv->sou_priv)
473 return -ENOSYS;
474
d3216a0c
TH		 475 /*
476 * Sanity checks.
477 */
478
479 if (unlikely(surface->mip_levels[0] != 1 ||
480 surface->num_sizes != 1 ||
481 surface->sizes[0].width < mode_cmd->width ||
482 surface->sizes[0].height < mode_cmd->height ||
483 surface->sizes[0].depth != 1)) {
484 DRM_ERROR("Incompatible surface dimensions "
485 "for requested mode.\n");
486 return -EINVAL;
487 }
488
489 switch (mode_cmd->depth) {
490 case 32:
491 format = SVGA3D_A8R8G8B8;
492 break;
493 case 24:
494 format = SVGA3D_X8R8G8B8;
495 break;
496 case 16:
497 format = SVGA3D_R5G6B5;
498 break;
499 case 15:
500 format = SVGA3D_A1R5G5B5;
501 break;
f01b7ba0
MD		 502 case 8:
503 format = SVGA3D_LUMINANCE8;
504 break;
d3216a0c
TH		 505 default:
506 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
507 return -EINVAL;
508 }
509
510 if (unlikely(format != surface->format)) {
511 DRM_ERROR("Invalid surface format for requested mode.\n");
512 return -EINVAL;
513 }
514
fb1d9738
JB		 515 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
516 if (!vfbs) {
517 ret = -ENOMEM;
518 goto out_err1;
519 }
520
521 ret = drm_framebuffer_init(dev, &vfbs->base.base,
522 &vmw_framebuffer_surface_funcs);
523 if (ret)
524 goto out_err2;
525
526 if (!vmw_surface_reference(surface)) {
527 DRM_ERROR("failed to reference surface %p\n", surface);
528 goto out_err3;
529 }
530
531 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 532 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
533 vfbs->base.base.pitch = mode_cmd->pitch;
534 vfbs->base.base.depth = mode_cmd->depth;
535 vfbs->base.base.width = mode_cmd->width;
536 vfbs->base.base.height = mode_cmd->height;
fb1d9738 537 vfbs->surface = surface;
3a939a5e 538 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 539
540 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 541 list_add_tail(&vfbs->head, &vmaster->fb_surf);
542 mutex_unlock(&vmaster->fb_surf_mutex);
543
fb1d9738
JB		 544 *out = &vfbs->base;
545
546 return 0;
547
548out_err3:
549 drm_framebuffer_cleanup(&vfbs->base.base);
550out_err2:
551 kfree(vfbs);
552out_err1:
553 return ret;
554}
555
556/*
557 * Dmabuf framebuffer code
558 */
559
560#define vmw_framebuffer_to_vfbd(x) \
561 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
562
563struct vmw_framebuffer_dmabuf {
564 struct vmw_framebuffer base;
565 struct vmw_dma_buffer *buffer;
56d1c78d 566 uint32_t handle;
fb1d9738
JB		 567};
568
569void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
570{
571 struct vmw_framebuffer_dmabuf *vfbd =
572 vmw_framebuffer_to_vfbd(framebuffer);
573
574 drm_framebuffer_cleanup(framebuffer);
575 vmw_dmabuf_unreference(&vfbd->buffer);
576
577 kfree(vfbd);
578}
579
5deb65cf
JB		 580static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
581 struct vmw_framebuffer *framebuffer,
582 struct vmw_dma_buffer *buffer,
583 unsigned flags, unsigned color,
584 struct drm_clip_rect *clips,
585 unsigned num_clips, int increment)
586{
587 size_t fifo_size;
588 int i;
589
590 struct {
591 uint32_t header;
592 SVGAFifoCmdUpdate body;
593 } *cmd;
594
595 fifo_size = sizeof(*cmd) * num_clips;
596 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
597 if (unlikely(cmd == NULL)) {
598 DRM_ERROR("Fifo reserve failed.\n");
599 return -ENOMEM;
600 }
601
602 memset(cmd, 0, fifo_size);
603 for (i = 0; i < num_clips; i++, clips += increment) {
604 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
605 cmd[i].body.x = cpu_to_le32(clips->x1);
606 cmd[i].body.y = cpu_to_le32(clips->y1);
607 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
608 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
609 }
610
611 vmw_fifo_commit(dev_priv, fifo_size);
612 return 0;
613}
614
56d1c78d
JB		 615static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
616 struct vmw_private *dev_priv,
617 struct vmw_framebuffer *framebuffer,
618 struct vmw_dma_buffer *buffer,
619 unsigned flags, unsigned color,
620 struct drm_clip_rect *clips,
621 unsigned num_clips, int increment)
622{
623 struct vmw_framebuffer_dmabuf *vfbd =
624 vmw_framebuffer_to_vfbd(&framebuffer->base);
625 size_t fifo_size;
626 int i, ret;
627
628 struct {
629 uint32_t header;
630 SVGAFifoCmdDefineGMRFB body;
631 } *cmd;
632 struct {
633 uint32_t header;
634 SVGAFifoCmdBlitGMRFBToScreen body;
635 } *blits;
636
637 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips;
638 cmd = kmalloc(fifo_size, GFP_KERNEL);
639 if (unlikely(cmd == NULL)) {
640 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
641 return -ENOMEM;
642 }
643
644 memset(cmd, 0, fifo_size);
645 cmd->header = SVGA_CMD_DEFINE_GMRFB;
646 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
647 cmd->body.format.colorDepth = framebuffer->base.depth;
648 cmd->body.format.reserved = 0;
649 cmd->body.bytesPerLine = framebuffer->base.pitch;
650 cmd->body.ptr.gmrId = vfbd->handle;
651 cmd->body.ptr.offset = 0;
652
653 blits = (void *)&cmd[1];
654 for (i = 0; i < num_clips; i++, clips += increment) {
655 blits[i].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
656 blits[i].body.srcOrigin.x = clips->x1;
657 blits[i].body.srcOrigin.y = clips->y1;
658 blits[i].body.destRect.left = clips->x1;
659 blits[i].body.destRect.top = clips->y1;
660 blits[i].body.destRect.right = clips->x2;
661 blits[i].body.destRect.bottom = clips->y2;
662 }
663
664 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
665 fifo_size, 0, NULL);
666
667 kfree(cmd);
668
669 return ret;
670}
671
fb1d9738 672int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 673 struct drm_file *file_priv,
fb1d9738
JB		 674 unsigned flags, unsigned color,
675 struct drm_clip_rect *clips,
676 unsigned num_clips)
677{
678 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 679 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 680 struct vmw_framebuffer_dmabuf *vfbd =
681 vmw_framebuffer_to_vfbd(framebuffer);
682 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
fb1d9738 683 struct drm_clip_rect norect;
5deb65cf 684 int ret, increment = 1;
fb1d9738 685
3a939a5e
TH		 686 ret = ttm_read_lock(&vmaster->lock, true);
687 if (unlikely(ret != 0))
688 return ret;
689
df1c93ba 690 if (!num_clips) {
fb1d9738
JB		 691 num_clips = 1;
692 clips = &norect;
693 norect.x1 = norect.y1 = 0;
694 norect.x2 = framebuffer->width;
695 norect.y2 = framebuffer->height;
696 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
697 num_clips /= 2;
698 increment = 2;
699 }
700
56d1c78d
JB		 701 if (dev_priv->ldu_priv) {
702 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base, dmabuf,
703 flags, color,
704 clips, num_clips, increment);
705 } else {
706 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
707 dmabuf, flags, color,
708 clips, num_clips, increment);
709 }
fb1d9738 710
3a939a5e 711 ttm_read_unlock(&vmaster->lock);
5deb65cf 712 return ret;
fb1d9738
JB		 713}
714
715static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
716 .destroy = vmw_framebuffer_dmabuf_destroy,
717 .dirty = vmw_framebuffer_dmabuf_dirty,
718 .create_handle = vmw_framebuffer_create_handle,
719};
720
497a3ff9
JB		 721/**
722 * Pin the dmabuffer to the start of vram.
723 */
fb1d9738
JB		 724static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
725{
726 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
727 struct vmw_framebuffer_dmabuf *vfbd =
728 vmw_framebuffer_to_vfbd(&vfb->base);
729 int ret;
730
56d1c78d
JB		 731 /* This code should not be used with screen objects */
732 BUG_ON(dev_priv->sou_priv);
d7e1958d 733
fb1d9738
JB		 734 vmw_overlay_pause_all(dev_priv);
735
d991ef03 736 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 737
fb1d9738
JB		 738 vmw_overlay_resume_all(dev_priv);
739
316ab13a
JB		 740 WARN_ON(ret != 0);
741
fb1d9738
JB		 742 return 0;
743}
744
745static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
746{
747 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
748 struct vmw_framebuffer_dmabuf *vfbd =
749 vmw_framebuffer_to_vfbd(&vfb->base);
750
751 if (!vfbd->buffer) {
752 WARN_ON(!vfbd->buffer);
753 return 0;
754 }
755
d991ef03 756 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 757}
758
d3216a0c
TH		 759static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
760 struct vmw_dma_buffer *dmabuf,
761 struct vmw_framebuffer **out,
762 const struct drm_mode_fb_cmd
763 *mode_cmd)
fb1d9738
JB		 764
765{
766 struct drm_device *dev = dev_priv->dev;
767 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 768 unsigned int requested_size;
fb1d9738
JB		 769 int ret;
770
d3216a0c
TH		 771 requested_size = mode_cmd->height * mode_cmd->pitch;
772 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
773 DRM_ERROR("Screen buffer object size is too small "
774 "for requested mode.\n");
775 return -EINVAL;
776 }
777
fb1d9738
JB		 778 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
779 if (!vfbd) {
780 ret = -ENOMEM;
781 goto out_err1;
782 }
783
784 ret = drm_framebuffer_init(dev, &vfbd->base.base,
785 &vmw_framebuffer_dmabuf_funcs);
786 if (ret)
787 goto out_err2;
788
789 if (!vmw_dmabuf_reference(dmabuf)) {
790 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
791 goto out_err3;
792 }
793
d3216a0c
TH		 794 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
795 vfbd->base.base.pitch = mode_cmd->pitch;
796 vfbd->base.base.depth = mode_cmd->depth;
797 vfbd->base.base.width = mode_cmd->width;
798 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 799 if (!dev_priv->sou_priv) {
800 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
801 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
802 }
fb1d9738 803 vfbd->buffer = dmabuf;
56d1c78d 804 vfbd->handle = mode_cmd->handle;
fb1d9738
JB		 805 *out = &vfbd->base;
806
807 return 0;
808
809out_err3:
810 drm_framebuffer_cleanup(&vfbd->base.base);
811out_err2:
812 kfree(vfbd);
813out_err1:
814 return ret;
815}
816
817/*
818 * Generic Kernel modesetting functions
819 */
820
821static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
822 struct drm_file *file_priv,
823 struct drm_mode_fb_cmd *mode_cmd)
824{
825 struct vmw_private *dev_priv = vmw_priv(dev);
826 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
827 struct vmw_framebuffer *vfb = NULL;
828 struct vmw_surface *surface = NULL;
829 struct vmw_dma_buffer *bo = NULL;
e133e737 830 u64 required_size;
fb1d9738
JB		 831 int ret;
832
d3216a0c
TH		 833 /**
834 * This code should be conditioned on Screen Objects not being used.
835 * If screen objects are used, we can allocate a GMR to hold the
836 * requested framebuffer.
837 */
838
839 required_size = mode_cmd->pitch * mode_cmd->height;
e133e737 840 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c
TH		 841 DRM_ERROR("VRAM size is too small for requested mode.\n");
842 return NULL;
843 }
844
845 /**
846 * End conditioned code.
847 */
848
7a73ba74
TH		 849 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
850 mode_cmd->handle, &surface);
fb1d9738
JB		 851 if (ret)
852 goto try_dmabuf;
853
5ffdb658
JB		 854 if (!surface->scanout)
855 goto err_not_scanout;
856
3a939a5e
TH		 857 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
858 &vfb, mode_cmd);
fb1d9738
JB		 859
860 /* vmw_user_surface_lookup takes one ref so does new_fb */
861 vmw_surface_unreference(&surface);
862
863 if (ret) {
864 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
cce13ff7 865 return ERR_PTR(ret);
fb1d9738
JB		 866 }
867 return &vfb->base;
868
869try_dmabuf:
870 DRM_INFO("%s: trying buffer\n", __func__);
871
872 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
873 if (ret) {
874 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 875 return ERR_PTR(-ENOENT);
fb1d9738
JB		 876 }
877
878 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
d3216a0c 879 mode_cmd);
fb1d9738
JB		 880
881 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
882 vmw_dmabuf_unreference(&bo);
883
884 if (ret) {
885 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
cce13ff7 886 return ERR_PTR(ret);
fb1d9738
JB		 887 }
888
889 return &vfb->base;
5ffdb658
JB		 890
891err_not_scanout:
892 DRM_ERROR("surface not marked as scanout\n");
893 /* vmw_user_surface_lookup takes one ref */
894 vmw_surface_unreference(&surface);
895
cce13ff7 896 return ERR_PTR(-EINVAL);
fb1d9738
JB		 897}
898
fb1d9738
JB		 899static struct drm_mode_config_funcs vmw_kms_funcs = {
900 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 901};
902
903int vmw_kms_init(struct vmw_private *dev_priv)
904{
905 struct drm_device *dev = dev_priv->dev;
906 int ret;
907
908 drm_mode_config_init(dev);
909 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 910 dev->mode_config.min_width = 1;
911 dev->mode_config.min_height = 1;
7e71f8a5
JB		 912 /* assumed largest fb size */
913 dev->mode_config.max_width = 8192;
914 dev->mode_config.max_height = 8192;
fb1d9738 915
56d1c78d
JB		 916 ret = vmw_kms_init_screen_object_display(dev_priv);
917 if (ret) /* Fallback */
918 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 919
920 return 0;
921}
922
923int vmw_kms_close(struct vmw_private *dev_priv)
924{
925 /*
926 * Docs says we should take the lock before calling this function
927 * but since it destroys encoders and our destructor calls
928 * drm_encoder_cleanup which takes the lock we deadlock.
929 */
930 drm_mode_config_cleanup(dev_priv->dev);
931 vmw_kms_close_legacy_display_system(dev_priv);
932 return 0;
933}
934
935int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
936 struct drm_file *file_priv)
937{
938 struct drm_vmw_cursor_bypass_arg *arg = data;
939 struct vmw_display_unit *du;
940 struct drm_mode_object *obj;
941 struct drm_crtc *crtc;
942 int ret = 0;
943
944
945 mutex_lock(&dev->mode_config.mutex);
946 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
947
948 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
949 du = vmw_crtc_to_du(crtc);
950 du->hotspot_x = arg->xhot;
951 du->hotspot_y = arg->yhot;
952 }
953
954 mutex_unlock(&dev->mode_config.mutex);
955 return 0;
956 }
957
958 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
959 if (!obj) {
960 ret = -EINVAL;
961 goto out;
962 }
963
964 crtc = obj_to_crtc(obj);
965 du = vmw_crtc_to_du(crtc);
966
967 du->hotspot_x = arg->xhot;
968 du->hotspot_y = arg->yhot;
969
970out:
971 mutex_unlock(&dev->mode_config.mutex);
972
973 return ret;
974}
975
0bef23f9 976int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 977 unsigned width, unsigned height, unsigned pitch,
6558429b 978 unsigned bpp, unsigned depth)
fb1d9738 979{
d7e1958d
JB		 980 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
981 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
982 else if (vmw_fifo_have_pitchlock(vmw_priv))
983 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
984 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
985 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 986 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 987
988 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
989 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
990 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
991 return -EINVAL;
992 }
993
994 return 0;
d7e1958d 995}
fb1d9738 996
d7e1958d
JB		 997int vmw_kms_save_vga(struct vmw_private *vmw_priv)
998{
7c4f7780
TH		 999 struct vmw_vga_topology_state *save;
1000 uint32_t i;
1001
fb1d9738
JB		 1002 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1003 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1004 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1005 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1006 vmw_priv->vga_pitchlock =
7c4f7780 1007 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1008 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1009 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1010 SVGA_FIFO_PITCHLOCK);
1011
1012 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1013 return 0;
fb1d9738 1014
7c4f7780
TH		 1015 vmw_priv->num_displays = vmw_read(vmw_priv,
1016 SVGA_REG_NUM_GUEST_DISPLAYS);
1017
029e50bf
TH		 1018 if (vmw_priv->num_displays == 0)
1019 vmw_priv->num_displays = 1;
1020
7c4f7780
TH		 1021 for (i = 0; i < vmw_priv->num_displays; ++i) {
1022 save = &vmw_priv->vga_save[i];
1023 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1024 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1025 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1026 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1027 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1028 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1029 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1030 if (i == 0 && vmw_priv->num_displays == 1 &&
1031 save->width == 0 && save->height == 0) {
1032
1033 /*
1034 * It should be fairly safe to assume that these
1035 * values are uninitialized.
1036 */
1037
1038 save->width = vmw_priv->vga_width - save->pos_x;
1039 save->height = vmw_priv->vga_height - save->pos_y;
1040 }
7c4f7780 1041 }
30c78bb8 1042
fb1d9738
JB		 1043 return 0;
1044}
1045
1046int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1047{
7c4f7780
TH		 1048 struct vmw_vga_topology_state *save;
1049 uint32_t i;
1050
fb1d9738
JB		 1051 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1052 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1053 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1054 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1055 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1056 vmw_priv->vga_pitchlock);
1057 else if (vmw_fifo_have_pitchlock(vmw_priv))
1058 iowrite32(vmw_priv->vga_pitchlock,
1059 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1060
7c4f7780
TH		 1061 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1062 return 0;
1063
1064 for (i = 0; i < vmw_priv->num_displays; ++i) {
1065 save = &vmw_priv->vga_save[i];
1066 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1067 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1068 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1069 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1070 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1071 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1072 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1073 }
1074
fb1d9738
JB		 1075 return 0;
1076}
d8bd19d2 1077
e133e737
TH		 1078bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1079 uint32_t pitch,
1080 uint32_t height)
1081{
1082 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1083}
1084
7a1c2f6c
TH		 1085u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1086{
1087 return 0;
1088}
626ab771
JB		 1089
1090
1091/*
1092 * Small shared kms functions.
1093 */
1094
1095int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1096 struct drm_vmw_rect *rects)
1097{
1098 struct drm_device *dev = dev_priv->dev;
1099 struct vmw_display_unit *du;
1100 struct drm_connector *con;
1101 int i;
1102
1103 mutex_lock(&dev->mode_config.mutex);
1104
1105#if 0
1106 DRM_INFO("%s: new layout ", __func__);
1107 for (i = 0; i < (int)num; i++)
1108 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1109 rects[i].w, rects[i].h);
1110 DRM_INFO("\n");
1111#else
1112 (void)i;
1113#endif
1114
1115 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1116 du = vmw_connector_to_du(con);
1117 if (num > du->unit) {
1118 du->pref_width = rects[du->unit].w;
1119 du->pref_height = rects[du->unit].h;
1120 du->pref_active = true;
1121 } else {
1122 du->pref_width = 800;
1123 du->pref_height = 600;
1124 du->pref_active = false;
1125 }
1126 con->status = vmw_du_connector_detect(con, true);
1127 }
1128
1129 mutex_unlock(&dev->mode_config.mutex);
1130
1131 return 0;
1132}
1133
1134void vmw_du_crtc_save(struct drm_crtc *crtc)
1135{
1136}
1137
1138void vmw_du_crtc_restore(struct drm_crtc *crtc)
1139{
1140}
1141
1142void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1143 u16 *r, u16 *g, u16 *b,
1144 uint32_t start, uint32_t size)
1145{
1146 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1147 int i;
1148
1149 for (i = 0; i < size; i++) {
1150 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1151 r[i], g[i], b[i]);
1152 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1153 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1154 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1155 }
1156}
1157
1158void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1159{
1160}
1161
1162void vmw_du_connector_save(struct drm_connector *connector)
1163{
1164}
1165
1166void vmw_du_connector_restore(struct drm_connector *connector)
1167{
1168}
1169
1170enum drm_connector_status
1171vmw_du_connector_detect(struct drm_connector *connector, bool force)
1172{
1173 uint32_t num_displays;
1174 struct drm_device *dev = connector->dev;
1175 struct vmw_private *dev_priv = vmw_priv(dev);
1176
1177 mutex_lock(&dev_priv->hw_mutex);
1178 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1179 mutex_unlock(&dev_priv->hw_mutex);
1180
1181 return ((vmw_connector_to_du(connector)->unit < num_displays) ?
1182 connector_status_connected : connector_status_disconnected);
1183}
1184
1185static struct drm_display_mode vmw_kms_connector_builtin[] = {
1186 /* 640x480@60Hz */
1187 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1188 752, 800, 0, 480, 489, 492, 525, 0,
1189 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1190 /* 800x600@60Hz */
1191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1192 968, 1056, 0, 600, 601, 605, 628, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1194 /* 1024x768@60Hz */
1195 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1196 1184, 1344, 0, 768, 771, 777, 806, 0,
1197 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1198 /* 1152x864@75Hz */
1199 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1200 1344, 1600, 0, 864, 865, 868, 900, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1202 /* 1280x768@60Hz */
1203 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1204 1472, 1664, 0, 768, 771, 778, 798, 0,
1205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1206 /* 1280x800@60Hz */
1207 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1208 1480, 1680, 0, 800, 803, 809, 831, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1210 /* 1280x960@60Hz */
1211 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1212 1488, 1800, 0, 960, 961, 964, 1000, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1214 /* 1280x1024@60Hz */
1215 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1216 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1218 /* 1360x768@60Hz */
1219 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1220 1536, 1792, 0, 768, 771, 777, 795, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1222 /* 1440x1050@60Hz */
1223 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1224 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1226 /* 1440x900@60Hz */
1227 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1228 1672, 1904, 0, 900, 903, 909, 934, 0,
1229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1230 /* 1600x1200@60Hz */
1231 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1232 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1234 /* 1680x1050@60Hz */
1235 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1236 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1238 /* 1792x1344@60Hz */
1239 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1240 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1242 /* 1853x1392@60Hz */
1243 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1244 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1246 /* 1920x1200@60Hz */
1247 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1248 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1250 /* 1920x1440@60Hz */
1251 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1252 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1254 /* 2560x1600@60Hz */
1255 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1256 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1258 /* Terminate */
1259 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1260};
1261
1262int vmw_du_connector_fill_modes(struct drm_connector *connector,
1263 uint32_t max_width, uint32_t max_height)
1264{
1265 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1266 struct drm_device *dev = connector->dev;
1267 struct vmw_private *dev_priv = vmw_priv(dev);
1268 struct drm_display_mode *mode = NULL;
1269 struct drm_display_mode *bmode;
1270 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1271 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1274 };
1275 int i;
1276
1277 /* Add preferred mode */
1278 {
1279 mode = drm_mode_duplicate(dev, &prefmode);
1280 if (!mode)
1281 return 0;
1282 mode->hdisplay = du->pref_width;
1283 mode->vdisplay = du->pref_height;
1284 mode->vrefresh = drm_mode_vrefresh(mode);
1285 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1286 mode->vdisplay)) {
1287 drm_mode_probed_add(connector, mode);
1288
1289 if (du->pref_mode) {
1290 list_del_init(&du->pref_mode->head);
1291 drm_mode_destroy(dev, du->pref_mode);
1292 }
1293
1294 du->pref_mode = mode;
1295 }
1296 }
1297
1298 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1299 bmode = &vmw_kms_connector_builtin[i];
1300 if (bmode->hdisplay > max_width ||
1301 bmode->vdisplay > max_height)
1302 continue;
1303
1304 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1305 bmode->vdisplay))
1306 continue;
1307
1308 mode = drm_mode_duplicate(dev, bmode);
1309 if (!mode)
1310 return 0;
1311 mode->vrefresh = drm_mode_vrefresh(mode);
1312
1313 drm_mode_probed_add(connector, mode);
1314 }
1315
1316 drm_mode_connector_list_update(connector);
1317
1318 return 1;
1319}
1320
1321int vmw_du_connector_set_property(struct drm_connector *connector,
1322 struct drm_property *property,
1323 uint64_t val)
1324{
1325 return 0;
1326}
kernel source for telekom puls (alcatel/mediatek)