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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
771fe6b9 31#include "drmP.h"
771fe6b9 32#include "radeon.h"
4153e584 33#include "radeon_drm.h"
3ce0a23d 34#include "rv770d.h"
3ce0a23d 35#include "atom.h"
d39c3b89 36#include "avivod.h"
771fe6b9 37
3ce0a23d
JG		 38#define R700_PFP_UCODE_SIZE 848
39#define R700_PM4_UCODE_SIZE 1360
771fe6b9 40
3ce0a23d
JG		 41static void rv770_gpu_init(struct radeon_device *rdev);
42void rv770_fini(struct radeon_device *rdev);
771fe6b9
JG		 43
44
45/*
3ce0a23d 46 * GART
771fe6b9 47 */
3ce0a23d 48int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 49{
3ce0a23d
JG		 50 u32 tmp;
51 int r, i;
771fe6b9 52
4aac0473
JG		 53 if (rdev->gart.table.vram.robj == NULL) {
54 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
55 return -EINVAL;
3ce0a23d 56 }
4aac0473
JG		 57 r = radeon_gart_table_vram_pin(rdev);
58 if (r)
3ce0a23d 59 return r;
82568565 60 radeon_gart_restore(rdev);
3ce0a23d
JG		 61 /* Setup L2 cache */
62 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
63 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
64 EFFECTIVE_L2_QUEUE_SIZE(7));
65 WREG32(VM_L2_CNTL2, 0);
66 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
67 /* Setup TLB control */
68 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
69 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
70 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
71 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
72 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
73 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
74 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
77 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
78 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 80 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 81 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
82 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
83 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
84 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
85 (u32)(rdev->dummy_page.addr >> 12));
86 for (i = 1; i < 7; i++)
87 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 88
3ce0a23d
JG		 89 r600_pcie_gart_tlb_flush(rdev);
90 rdev->gart.ready = true;
771fe6b9
JG		 91 return 0;
92}
93
3ce0a23d 94void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 95{
3ce0a23d 96 u32 tmp;
4c788679 97 int i, r;
3ce0a23d 98
3ce0a23d
JG		 99 /* Disable all tables */
100 for (i = 0; i < 7; i++)
101 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
102
103 /* Setup L2 cache */
104 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
105 EFFECTIVE_L2_QUEUE_SIZE(7));
106 WREG32(VM_L2_CNTL2, 0);
107 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
108 /* Setup TLB control */
109 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
110 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
111 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
112 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
115 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
116 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473 117 if (rdev->gart.table.vram.robj) {
4c788679
JG		 118 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
119 if (likely(r == 0)) {
120 radeon_bo_kunmap(rdev->gart.table.vram.robj);
121 radeon_bo_unpin(rdev->gart.table.vram.robj);
122 radeon_bo_unreserve(rdev->gart.table.vram.robj);
123 }
4aac0473
JG		 124 }
125}
126
127void rv770_pcie_gart_fini(struct radeon_device *rdev)
128{
129 rv770_pcie_gart_disable(rdev);
130 radeon_gart_table_vram_free(rdev);
131 radeon_gart_fini(rdev);
771fe6b9
JG		 132}
133
134
1a029b76
JG		 135void rv770_agp_enable(struct radeon_device *rdev)
136{
137 u32 tmp;
138 int i;
139
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
155 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
158 for (i = 0; i < 7; i++)
159 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
160}
161
a3c1945a 162static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 163{
a3c1945a 164 struct rv515_mc_save save;
3ce0a23d
JG		 165 u32 tmp;
166 int i, j;
167
168 /* Initialize HDP */
169 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
170 WREG32((0x2c14 + j), 0x00000000);
171 WREG32((0x2c18 + j), 0x00000000);
172 WREG32((0x2c1c + j), 0x00000000);
173 WREG32((0x2c20 + j), 0x00000000);
174 WREG32((0x2c24 + j), 0x00000000);
175 }
176 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
177
a3c1945a 178 rv515_mc_stop(rdev, &save);
3ce0a23d 179 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 180 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 181 }
3ce0a23d
JG		 182 /* Lockout access through VGA aperture*/
183 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 184 /* Update configuration */
1a029b76
JG		 185 if (rdev->flags & RADEON_IS_AGP) {
186 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
187 /* VRAM before AGP */
188 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
189 rdev->mc.vram_start >> 12);
190 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
191 rdev->mc.gtt_end >> 12);
192 } else {
193 /* VRAM after AGP */
194 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
195 rdev->mc.gtt_start >> 12);
196 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
197 rdev->mc.vram_end >> 12);
198 }
199 } else {
200 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
201 rdev->mc.vram_start >> 12);
202 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
203 rdev->mc.vram_end >> 12);
204 }
3ce0a23d 205 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 206 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 207 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
208 WREG32(MC_VM_FB_LOCATION, tmp);
209 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
210 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
211 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
212 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 213 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 214 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
215 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
216 } else {
217 WREG32(MC_VM_AGP_BASE, 0);
218 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
219 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
220 }
3ce0a23d 221 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 222 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 223 }
a3c1945a 224 rv515_mc_resume(rdev, &save);
698443d9
DA		 225 /* we need to own VRAM, so turn off the VGA renderer here
226 * to stop it overwriting our objects */
d39c3b89 227 rv515_vga_render_disable(rdev);
771fe6b9
JG		 228}
229
3ce0a23d
JG		 230
231/*
232 * CP.
233 */
234void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 235{
3ce0a23d 236 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
771fe6b9
JG		 237}
238
3ce0a23d
JG		 239
240static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 241{
3ce0a23d
JG		 242 const __be32 *fw_data;
243 int i;
244
245 if (!rdev->me_fw || !rdev->pfp_fw)
246 return -EINVAL;
247
248 r700_cp_stop(rdev);
249 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
250
251 /* Reset cp */
252 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
253 RREG32(GRBM_SOFT_RESET);
254 mdelay(15);
255 WREG32(GRBM_SOFT_RESET, 0);
256
257 fw_data = (const __be32 *)rdev->pfp_fw->data;
258 WREG32(CP_PFP_UCODE_ADDR, 0);
259 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
260 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
261 WREG32(CP_PFP_UCODE_ADDR, 0);
262
263 fw_data = (const __be32 *)rdev->me_fw->data;
264 WREG32(CP_ME_RAM_WADDR, 0);
265 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
266 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
267
268 WREG32(CP_PFP_UCODE_ADDR, 0);
269 WREG32(CP_ME_RAM_WADDR, 0);
270 WREG32(CP_ME_RAM_RADDR, 0);
271 return 0;
771fe6b9
JG		 272}
273
274
275/*
3ce0a23d 276 * Core functions
771fe6b9 277 */
d03f5d59
AD		 278static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
279 u32 num_tile_pipes,
280 u32 num_backends,
281 u32 backend_disable_mask)
771fe6b9 282{
3ce0a23d
JG		 283 u32 backend_map = 0;
284 u32 enabled_backends_mask;
285 u32 enabled_backends_count;
286 u32 cur_pipe;
287 u32 swizzle_pipe[R7XX_MAX_PIPES];
288 u32 cur_backend;
289 u32 i;
d03f5d59 290 bool force_no_swizzle;
3ce0a23d
JG		 291
292 if (num_tile_pipes > R7XX_MAX_PIPES)
293 num_tile_pipes = R7XX_MAX_PIPES;
294 if (num_tile_pipes < 1)
295 num_tile_pipes = 1;
296 if (num_backends > R7XX_MAX_BACKENDS)
297 num_backends = R7XX_MAX_BACKENDS;
298 if (num_backends < 1)
299 num_backends = 1;
300
301 enabled_backends_mask = 0;
302 enabled_backends_count = 0;
303 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
304 if (((backend_disable_mask >> i) & 1) == 0) {
305 enabled_backends_mask |= (1 << i);
306 ++enabled_backends_count;
307 }
308 if (enabled_backends_count == num_backends)
309 break;
310 }
311
312 if (enabled_backends_count == 0) {
313 enabled_backends_mask = 1;
314 enabled_backends_count = 1;
315 }
316
317 if (enabled_backends_count != num_backends)
318 num_backends = enabled_backends_count;
319
d03f5d59
AD		 320 switch (rdev->family) {
321 case CHIP_RV770:
322 case CHIP_RV730:
323 force_no_swizzle = false;
324 break;
325 case CHIP_RV710:
326 case CHIP_RV740:
327 default:
328 force_no_swizzle = true;
329 break;
330 }
331
3ce0a23d
JG		 332 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
333 switch (num_tile_pipes) {
334 case 1:
335 swizzle_pipe[0] = 0;
336 break;
337 case 2:
338 swizzle_pipe[0] = 0;
339 swizzle_pipe[1] = 1;
340 break;
341 case 3:
d03f5d59
AD		 342 if (force_no_swizzle) {
343 swizzle_pipe[0] = 0;
344 swizzle_pipe[1] = 1;
345 swizzle_pipe[2] = 2;
346 } else {
347 swizzle_pipe[0] = 0;
348 swizzle_pipe[1] = 2;
349 swizzle_pipe[2] = 1;
350 }
3ce0a23d
JG		 351 break;
352 case 4:
d03f5d59
AD		 353 if (force_no_swizzle) {
354 swizzle_pipe[0] = 0;
355 swizzle_pipe[1] = 1;
356 swizzle_pipe[2] = 2;
357 swizzle_pipe[3] = 3;
358 } else {
359 swizzle_pipe[0] = 0;
360 swizzle_pipe[1] = 2;
361 swizzle_pipe[2] = 3;
362 swizzle_pipe[3] = 1;
363 }
3ce0a23d
JG		 364 break;
365 case 5:
d03f5d59
AD		 366 if (force_no_swizzle) {
367 swizzle_pipe[0] = 0;
368 swizzle_pipe[1] = 1;
369 swizzle_pipe[2] = 2;
370 swizzle_pipe[3] = 3;
371 swizzle_pipe[4] = 4;
372 } else {
373 swizzle_pipe[0] = 0;
374 swizzle_pipe[1] = 2;
375 swizzle_pipe[2] = 4;
376 swizzle_pipe[3] = 1;
377 swizzle_pipe[4] = 3;
378 }
3ce0a23d
JG		 379 break;
380 case 6:
d03f5d59
AD		 381 if (force_no_swizzle) {
382 swizzle_pipe[0] = 0;
383 swizzle_pipe[1] = 1;
384 swizzle_pipe[2] = 2;
385 swizzle_pipe[3] = 3;
386 swizzle_pipe[4] = 4;
387 swizzle_pipe[5] = 5;
388 } else {
389 swizzle_pipe[0] = 0;
390 swizzle_pipe[1] = 2;
391 swizzle_pipe[2] = 4;
392 swizzle_pipe[3] = 5;
393 swizzle_pipe[4] = 3;
394 swizzle_pipe[5] = 1;
395 }
3ce0a23d
JG		 396 break;
397 case 7:
d03f5d59
AD		 398 if (force_no_swizzle) {
399 swizzle_pipe[0] = 0;
400 swizzle_pipe[1] = 1;
401 swizzle_pipe[2] = 2;
402 swizzle_pipe[3] = 3;
403 swizzle_pipe[4] = 4;
404 swizzle_pipe[5] = 5;
405 swizzle_pipe[6] = 6;
406 } else {
407 swizzle_pipe[0] = 0;
408 swizzle_pipe[1] = 2;
409 swizzle_pipe[2] = 4;
410 swizzle_pipe[3] = 6;
411 swizzle_pipe[4] = 3;
412 swizzle_pipe[5] = 1;
413 swizzle_pipe[6] = 5;
414 }
3ce0a23d
JG		 415 break;
416 case 8:
d03f5d59
AD		 417 if (force_no_swizzle) {
418 swizzle_pipe[0] = 0;
419 swizzle_pipe[1] = 1;
420 swizzle_pipe[2] = 2;
421 swizzle_pipe[3] = 3;
422 swizzle_pipe[4] = 4;
423 swizzle_pipe[5] = 5;
424 swizzle_pipe[6] = 6;
425 swizzle_pipe[7] = 7;
426 } else {
427 swizzle_pipe[0] = 0;
428 swizzle_pipe[1] = 2;
429 swizzle_pipe[2] = 4;
430 swizzle_pipe[3] = 6;
431 swizzle_pipe[4] = 3;
432 swizzle_pipe[5] = 1;
433 swizzle_pipe[6] = 7;
434 swizzle_pipe[7] = 5;
435 }
3ce0a23d
JG		 436 break;
437 }
438
439 cur_backend = 0;
440 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
441 while (((1 << cur_backend) & enabled_backends_mask) == 0)
442 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
443
444 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
445
446 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
447 }
448
449 return backend_map;
771fe6b9
JG		 450}
451
3ce0a23d 452static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 453{
3ce0a23d 454 int i, j, num_qd_pipes;
d03f5d59 455 u32 ta_aux_cntl;
3ce0a23d
JG		 456 u32 sx_debug_1;
457 u32 smx_dc_ctl0;
d03f5d59 458 u32 db_debug3;
3ce0a23d
JG		 459 u32 num_gs_verts_per_thread;
460 u32 vgt_gs_per_es;
461 u32 gs_prim_buffer_depth = 0;
462 u32 sq_ms_fifo_sizes;
463 u32 sq_config;
464 u32 sq_thread_resource_mgmt;
465 u32 hdp_host_path_cntl;
466 u32 sq_dyn_gpr_size_simd_ab_0;
467 u32 backend_map;
468 u32 gb_tiling_config = 0;
469 u32 cc_rb_backend_disable = 0;
470 u32 cc_gc_shader_pipe_config = 0;
471 u32 mc_arb_ramcfg;
472 u32 db_debug4;
771fe6b9 473
3ce0a23d
JG		 474 /* setup chip specs */
475 switch (rdev->family) {
476 case CHIP_RV770:
477 rdev->config.rv770.max_pipes = 4;
478 rdev->config.rv770.max_tile_pipes = 8;
479 rdev->config.rv770.max_simds = 10;
480 rdev->config.rv770.max_backends = 4;
481 rdev->config.rv770.max_gprs = 256;
482 rdev->config.rv770.max_threads = 248;
483 rdev->config.rv770.max_stack_entries = 512;
484 rdev->config.rv770.max_hw_contexts = 8;
485 rdev->config.rv770.max_gs_threads = 16 * 2;
486 rdev->config.rv770.sx_max_export_size = 128;
487 rdev->config.rv770.sx_max_export_pos_size = 16;
488 rdev->config.rv770.sx_max_export_smx_size = 112;
489 rdev->config.rv770.sq_num_cf_insts = 2;
490
491 rdev->config.rv770.sx_num_of_sets = 7;
492 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
493 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
494 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
495 break;
496 case CHIP_RV730:
497 rdev->config.rv770.max_pipes = 2;
498 rdev->config.rv770.max_tile_pipes = 4;
499 rdev->config.rv770.max_simds = 8;
500 rdev->config.rv770.max_backends = 2;
501 rdev->config.rv770.max_gprs = 128;
502 rdev->config.rv770.max_threads = 248;
503 rdev->config.rv770.max_stack_entries = 256;
504 rdev->config.rv770.max_hw_contexts = 8;
505 rdev->config.rv770.max_gs_threads = 16 * 2;
506 rdev->config.rv770.sx_max_export_size = 256;
507 rdev->config.rv770.sx_max_export_pos_size = 32;
508 rdev->config.rv770.sx_max_export_smx_size = 224;
509 rdev->config.rv770.sq_num_cf_insts = 2;
510
511 rdev->config.rv770.sx_num_of_sets = 7;
512 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
513 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
514 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
515 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
516 rdev->config.rv770.sx_max_export_pos_size -= 16;
517 rdev->config.rv770.sx_max_export_smx_size += 16;
518 }
519 break;
520 case CHIP_RV710:
521 rdev->config.rv770.max_pipes = 2;
522 rdev->config.rv770.max_tile_pipes = 2;
523 rdev->config.rv770.max_simds = 2;
524 rdev->config.rv770.max_backends = 1;
525 rdev->config.rv770.max_gprs = 256;
526 rdev->config.rv770.max_threads = 192;
527 rdev->config.rv770.max_stack_entries = 256;
528 rdev->config.rv770.max_hw_contexts = 4;
529 rdev->config.rv770.max_gs_threads = 8 * 2;
530 rdev->config.rv770.sx_max_export_size = 128;
531 rdev->config.rv770.sx_max_export_pos_size = 16;
532 rdev->config.rv770.sx_max_export_smx_size = 112;
533 rdev->config.rv770.sq_num_cf_insts = 1;
534
535 rdev->config.rv770.sx_num_of_sets = 7;
536 rdev->config.rv770.sc_prim_fifo_size = 0x40;
537 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
538 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
539 break;
540 case CHIP_RV740:
541 rdev->config.rv770.max_pipes = 4;
542 rdev->config.rv770.max_tile_pipes = 4;
543 rdev->config.rv770.max_simds = 8;
544 rdev->config.rv770.max_backends = 4;
545 rdev->config.rv770.max_gprs = 256;
546 rdev->config.rv770.max_threads = 248;
547 rdev->config.rv770.max_stack_entries = 512;
548 rdev->config.rv770.max_hw_contexts = 8;
549 rdev->config.rv770.max_gs_threads = 16 * 2;
550 rdev->config.rv770.sx_max_export_size = 256;
551 rdev->config.rv770.sx_max_export_pos_size = 32;
552 rdev->config.rv770.sx_max_export_smx_size = 224;
553 rdev->config.rv770.sq_num_cf_insts = 2;
554
555 rdev->config.rv770.sx_num_of_sets = 7;
556 rdev->config.rv770.sc_prim_fifo_size = 0x100;
557 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
558 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
559
560 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
561 rdev->config.rv770.sx_max_export_pos_size -= 16;
562 rdev->config.rv770.sx_max_export_smx_size += 16;
563 }
564 break;
565 default:
566 break;
567 }
568
569 /* Initialize HDP */
570 j = 0;
571 for (i = 0; i < 32; i++) {
572 WREG32((0x2c14 + j), 0x00000000);
573 WREG32((0x2c18 + j), 0x00000000);
574 WREG32((0x2c1c + j), 0x00000000);
575 WREG32((0x2c20 + j), 0x00000000);
576 WREG32((0x2c24 + j), 0x00000000);
577 j += 0x18;
578 }
579
580 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
581
582 /* setup tiling, simd, pipe config */
583 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
584
585 switch (rdev->config.rv770.max_tile_pipes) {
586 case 1:
d03f5d59 587 default:
3ce0a23d
JG		 588 gb_tiling_config |= PIPE_TILING(0);
589 break;
590 case 2:
591 gb_tiling_config |= PIPE_TILING(1);
592 break;
593 case 4:
594 gb_tiling_config |= PIPE_TILING(2);
595 break;
596 case 8:
597 gb_tiling_config |= PIPE_TILING(3);
3ce0a23d
JG		 598 break;
599 }
d03f5d59 600 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d
JG		 601
602 if (rdev->family == CHIP_RV770)
603 gb_tiling_config |= BANK_TILING(1);
604 else
e29649db 605 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
961fb597 606 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
3ce0a23d
JG		 607
608 gb_tiling_config |= GROUP_SIZE(0);
961fb597 609 rdev->config.rv770.tiling_group_size = 256;
3ce0a23d 610
e29649db 611 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 612 gb_tiling_config |= ROW_TILING(3);
613 gb_tiling_config |= SAMPLE_SPLIT(3);
614 } else {
615 gb_tiling_config |=
616 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
617 gb_tiling_config |=
618 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
619 }
620
621 gb_tiling_config |= BANK_SWAPS(1);
622
d03f5d59
AD		 623 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
624 cc_rb_backend_disable |=
625 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
3ce0a23d 626
d03f5d59
AD		 627 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
628 cc_gc_shader_pipe_config |=
3ce0a23d
JG		 629 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
630 cc_gc_shader_pipe_config |=
631 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
632
d03f5d59
AD		 633 if (rdev->family == CHIP_RV740)
634 backend_map = 0x28;
635 else
636 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
637 rdev->config.rv770.max_tile_pipes,
638 (R7XX_MAX_BACKENDS -
639 r600_count_pipe_bits((cc_rb_backend_disable &
640 R7XX_MAX_BACKENDS_MASK) >> 16)),
641 (cc_rb_backend_disable >> 16));
642 gb_tiling_config |= BACKEND_MAP(backend_map);
643
3ce0a23d
JG		 644
645 WREG32(GB_TILING_CONFIG, gb_tiling_config);
646 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
647 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
648
649 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
650 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
d03f5d59 651 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
3ce0a23d 652
3ce0a23d
JG		 653 WREG32(CGTS_SYS_TCC_DISABLE, 0);
654 WREG32(CGTS_TCC_DISABLE, 0);
3ce0a23d
JG		 655
656 num_qd_pipes =
d03f5d59 657 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 658 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
659 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
660
661 /* set HW defaults for 3D engine */
662 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 663 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 664
665 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
666
d03f5d59
AD		 667 ta_aux_cntl = RREG32(TA_CNTL_AUX);
668 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 669
670 sx_debug_1 = RREG32(SX_DEBUG_1);
671 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
672 WREG32(SX_DEBUG_1, sx_debug_1);
673
674 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
675 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
676 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
677 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
678
d03f5d59
AD		 679 if (rdev->family != CHIP_RV740)
680 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
681 GS_FLUSH_CTL(4) |
682 ACK_FLUSH_CTL(3) |
683 SYNC_FLUSH_CTL));
3ce0a23d 684
d03f5d59
AD		 685 db_debug3 = RREG32(DB_DEBUG3);
686 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
687 switch (rdev->family) {
688 case CHIP_RV770:
689 case CHIP_RV740:
690 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
691 break;
692 case CHIP_RV710:
693 case CHIP_RV730:
694 default:
695 db_debug3 |= DB_CLK_OFF_DELAY(2);
696 break;
697 }
698 WREG32(DB_DEBUG3, db_debug3);
699
700 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 701 db_debug4 = RREG32(DB_DEBUG4);
702 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
703 WREG32(DB_DEBUG4, db_debug4);
704 }
705
706 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 707 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
708 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 709
710 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 711 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
712 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 713
714 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
715
716 WREG32(VGT_NUM_INSTANCES, 1);
717
718 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
719
720 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
721
722 WREG32(CP_PERFMON_CNTL, 0);
723
724 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
725 DONE_FIFO_HIWATER(0xe0) |
726 ALU_UPDATE_FIFO_HIWATER(0x8));
727 switch (rdev->family) {
728 case CHIP_RV770:
3ce0a23d
JG		 729 case CHIP_RV730:
730 case CHIP_RV710:
d03f5d59
AD		 731 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
732 break;
3ce0a23d
JG		 733 case CHIP_RV740:
734 default:
735 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
736 break;
737 }
738 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
739
740 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
741 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
742 */
743 sq_config = RREG32(SQ_CONFIG);
744 sq_config &= ~(PS_PRIO(3) |
745 VS_PRIO(3) |
746 GS_PRIO(3) |
747 ES_PRIO(3));
748 sq_config |= (DX9_CONSTS |
749 VC_ENABLE |
750 EXPORT_SRC_C |
751 PS_PRIO(0) |
752 VS_PRIO(1) |
753 GS_PRIO(2) |
754 ES_PRIO(3));
755 if (rdev->family == CHIP_RV710)
756 /* no vertex cache */
757 sq_config &= ~VC_ENABLE;
758
759 WREG32(SQ_CONFIG, sq_config);
760
761 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 762 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
763 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 764
765 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 766 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 767
768 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
769 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
770 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
771 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
772 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
773 else
774 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
775 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
776
777 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
778 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
779
780 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
781 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
782
783 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
784 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
785 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
786 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
787
788 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
789 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
790 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
791 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
792 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
793 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
794 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
795 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
796
797 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 798 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 799
800 if (rdev->family == CHIP_RV710)
801 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 802 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 803 else
804 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 805 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 806
807 switch (rdev->family) {
808 case CHIP_RV770:
809 case CHIP_RV730:
810 case CHIP_RV740:
811 gs_prim_buffer_depth = 384;
812 break;
813 case CHIP_RV710:
814 gs_prim_buffer_depth = 128;
815 break;
816 default:
817 break;
818 }
819
820 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
821 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
822 /* Max value for this is 256 */
823 if (vgt_gs_per_es > 256)
824 vgt_gs_per_es = 256;
825
826 WREG32(VGT_ES_PER_GS, 128);
827 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
828 WREG32(VGT_GS_PER_VS, 2);
829
830 /* more default values. 2D/3D driver should adjust as needed */
831 WREG32(VGT_GS_VERTEX_REUSE, 16);
832 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
833 WREG32(VGT_STRMOUT_EN, 0);
834 WREG32(SX_MISC, 0);
835 WREG32(PA_SC_MODE_CNTL, 0);
836 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
837 WREG32(PA_SC_AA_CONFIG, 0);
838 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
839 WREG32(PA_SC_LINE_STIPPLE, 0);
840 WREG32(SPI_INPUT_Z, 0);
841 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
842 WREG32(CB_COLOR7_FRAG, 0);
843
844 /* clear render buffer base addresses */
845 WREG32(CB_COLOR0_BASE, 0);
846 WREG32(CB_COLOR1_BASE, 0);
847 WREG32(CB_COLOR2_BASE, 0);
848 WREG32(CB_COLOR3_BASE, 0);
849 WREG32(CB_COLOR4_BASE, 0);
850 WREG32(CB_COLOR5_BASE, 0);
851 WREG32(CB_COLOR6_BASE, 0);
852 WREG32(CB_COLOR7_BASE, 0);
853
854 WREG32(TCP_CNTL, 0);
855
856 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
857 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
858
859 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
860
861 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
862 NUM_CLIP_SEQ(3)));
863
864}
865
866int rv770_mc_init(struct radeon_device *rdev)
867{
868 fixed20_12 a;
869 u32 tmp;
5885b7a9 870 int chansize, numchan;
3ce0a23d
JG		 871
872 /* Get VRAM informations */
3ce0a23d 873 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 874 tmp = RREG32(MC_ARB_RAMCFG);
875 if (tmp & CHANSIZE_OVERRIDE) {
876 chansize = 16;
877 } else if (tmp & CHANSIZE_MASK) {
878 chansize = 64;
879 } else {
880 chansize = 32;
881 }
882 tmp = RREG32(MC_SHARED_CHMAP);
883 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
884 case 0:
885 default:
886 numchan = 1;
887 break;
888 case 1:
889 numchan = 2;
890 break;
891 case 2:
892 numchan = 4;
893 break;
894 case 3:
895 numchan = 8;
896 break;
897 }
898 rdev->mc.vram_width = numchan * chansize;
771fe6b9
JG		 899 /* Could aper size report 0 ? */
900 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
901 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
3ce0a23d
JG		 902 /* Setup GPU memory space */
903 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
904 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 905 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 906 /* FIXME remove this once we support unmappable VRAM */
907 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
974b16e3 908 rdev->mc.mc_vram_size = rdev->mc.aper_size;
974b16e3 909 rdev->mc.real_vram_size = rdev->mc.aper_size;
3ce0a23d 910 }
d594e46a 911 r600_vram_gtt_location(rdev, &rdev->mc);
3ce0a23d
JG		 912 /* FIXME: we should enforce default clock in case GPU is not in
913 * default setup
914 */
915 a.full = rfixed_const(100);
916 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
917 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
918 return 0;
919}
d594e46a 920
3ce0a23d
JG		 921int rv770_gpu_reset(struct radeon_device *rdev)
922{
fe62e1a4
DA		 923 /* FIXME: implement any rv770 specific bits */
924 return r600_gpu_reset(rdev);
3ce0a23d
JG		 925}
926
fc30b8ef 927static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 928{
929 int r;
930
779720a3
AD		 931 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
932 r = r600_init_microcode(rdev);
933 if (r) {
934 DRM_ERROR("Failed to load firmware!\n");
935 return r;
936 }
937 }
938
a3c1945a 939 rv770_mc_program(rdev);
1a029b76
JG		 940 if (rdev->flags & RADEON_IS_AGP) {
941 rv770_agp_enable(rdev);
942 } else {
943 r = rv770_pcie_gart_enable(rdev);
944 if (r)
945 return r;
946 }
3ce0a23d 947 rv770_gpu_init(rdev);
c38c7b64
JG		 948 r = r600_blit_init(rdev);
949 if (r) {
950 r600_blit_fini(rdev);
951 rdev->asic->copy = NULL;
952 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
953 }
ff82f052
JG		 954 /* pin copy shader into vram */
955 if (rdev->r600_blit.shader_obj) {
956 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
957 if (unlikely(r != 0))
958 return r;
959 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
960 &rdev->r600_blit.shader_gpu_addr);
961 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 962 if (r) {
ff82f052 963 DRM_ERROR("failed to pin blit object %d\n", r);
7923c615
AD		 964 return r;
965 }
966 }
d8f60cfc 967 /* Enable IRQ */
d8f60cfc
AD		 968 r = r600_irq_init(rdev);
969 if (r) {
970 DRM_ERROR("radeon: IH init failed (%d).\n", r);
971 radeon_irq_kms_fini(rdev);
972 return r;
973 }
974 r600_irq_set(rdev);
975
3ce0a23d
JG		 976 r = radeon_ring_init(rdev, rdev->cp.ring_size);
977 if (r)
978 return r;
979 r = rv770_cp_load_microcode(rdev);
980 if (r)
981 return r;
982 r = r600_cp_resume(rdev);
983 if (r)
984 return r;
81cc35bf
JG		 985 /* write back buffer are not vital so don't worry about failure */
986 r600_wb_enable(rdev);
3ce0a23d
JG		 987 return 0;
988}
989
fc30b8ef
DA		 990int rv770_resume(struct radeon_device *rdev)
991{
992 int r;
993
1a029b76
JG		 994 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
995 * posting will perform necessary task to bring back GPU into good
996 * shape.
997 */
fc30b8ef 998 /* post card */
e7d40b9a 999 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1000 /* Initialize clocks */
1001 r = radeon_clocks_init(rdev);
1002 if (r) {
1003 return r;
1004 }
1005
1006 r = rv770_startup(rdev);
1007 if (r) {
1008 DRM_ERROR("r600 startup failed on resume\n");
1009 return r;
1010 }
1011
62a8ea3f 1012 r = r600_ib_test(rdev);
fc30b8ef
DA		 1013 if (r) {
1014 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1015 return r;
1016 }
1017 return r;
1018
1019}
1020
3ce0a23d
JG		 1021int rv770_suspend(struct radeon_device *rdev)
1022{
4c788679
JG		 1023 int r;
1024
3ce0a23d
JG		 1025 /* FIXME: we should wait for ring to be empty */
1026 r700_cp_stop(rdev);
4153e584 1027 rdev->cp.ready = false;
0c45249f 1028 r600_irq_suspend(rdev);
81cc35bf 1029 r600_wb_disable(rdev);
4aac0473 1030 rv770_pcie_gart_disable(rdev);
4153e584 1031 /* unpin shaders bo */
30d2d9a5
JG		 1032 if (rdev->r600_blit.shader_obj) {
1033 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1034 if (likely(r == 0)) {
1035 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1036 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1037 }
4c788679 1038 }
3ce0a23d
JG		 1039 return 0;
1040}
1041
1042/* Plan is to move initialization in that function and use
1043 * helper function so that radeon_device_init pretty much
1044 * do nothing more than calling asic specific function. This
1045 * should also allow to remove a bunch of callback function
1046 * like vram_info.
1047 */
1048int rv770_init(struct radeon_device *rdev)
1049{
1050 int r;
1051
3ce0a23d
JG		 1052 r = radeon_dummy_page_init(rdev);
1053 if (r)
1054 return r;
1055 /* This don't do much */
1056 r = radeon_gem_init(rdev);
1057 if (r)
1058 return r;
1059 /* Read BIOS */
1060 if (!radeon_get_bios(rdev)) {
1061 if (ASIC_IS_AVIVO(rdev))
1062 return -EINVAL;
1063 }
1064 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1065 if (!rdev->is_atom_bios) {
1066 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1067 return -EINVAL;
e7d40b9a 1068 }
3ce0a23d
JG		 1069 r = radeon_atombios_init(rdev);
1070 if (r)
1071 return r;
1072 /* Post card if necessary */
72542d77
DA		 1073 if (!r600_card_posted(rdev)) {
1074 if (!rdev->bios) {
1075 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1076 return -EINVAL;
1077 }
3ce0a23d
JG		 1078 DRM_INFO("GPU not posted. posting now...\n");
1079 atom_asic_init(rdev->mode_info.atom_context);
1080 }
1081 /* Initialize scratch registers */
1082 r600_scratch_init(rdev);
1083 /* Initialize surface registers */
1084 radeon_surface_init(rdev);
7433874e 1085 /* Initialize clocks */
5e6dde7e 1086 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1087 r = radeon_clocks_init(rdev);
1088 if (r)
1089 return r;
7433874e
RM		 1090 /* Initialize power management */
1091 radeon_pm_init(rdev);
3ce0a23d
JG		 1092 /* Fence driver */
1093 r = radeon_fence_driver_init(rdev);
1094 if (r)
1095 return r;
d594e46a 1096 /* initialize AGP */
700a0cc0
JG		 1097 if (rdev->flags & RADEON_IS_AGP) {
1098 r = radeon_agp_init(rdev);
1099 if (r)
1100 radeon_agp_disable(rdev);
1101 }
3ce0a23d 1102 r = rv770_mc_init(rdev);
b574f251 1103 if (r)
3ce0a23d 1104 return r;
3ce0a23d 1105 /* Memory manager */
4c788679 1106 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1107 if (r)
1108 return r;
d8f60cfc
AD		 1109
1110 r = radeon_irq_kms_init(rdev);
1111 if (r)
1112 return r;
1113
3ce0a23d
JG		 1114 rdev->cp.ring_obj = NULL;
1115 r600_ring_init(rdev, 1024 * 1024);
1116
d8f60cfc
AD		 1117 rdev->ih.ring_obj = NULL;
1118 r600_ih_ring_init(rdev, 64 * 1024);
1119
4aac0473
JG		 1120 r = r600_pcie_gart_init(rdev);
1121 if (r)
1122 return r;
1123
779720a3 1124 rdev->accel_working = true;
fc30b8ef 1125 r = rv770_startup(rdev);
3ce0a23d 1126 if (r) {
655efd3d
JG		 1127 dev_err(rdev->dev, "disabling GPU acceleration\n");
1128 r600_cp_fini(rdev);
75c81298 1129 r600_wb_fini(rdev);
655efd3d
JG		 1130 r600_irq_fini(rdev);
1131 radeon_irq_kms_fini(rdev);
75c81298 1132 rv770_pcie_gart_fini(rdev);
733289c2 1133 rdev->accel_working = false;
3ce0a23d 1134 }
733289c2 1135 if (rdev->accel_working) {
733289c2
JG		 1136 r = radeon_ib_pool_init(rdev);
1137 if (r) {
db96380e 1138 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 1139 rdev->accel_working = false;
db96380e
JG		 1140 } else {
1141 r = r600_ib_test(rdev);
1142 if (r) {
1143 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1144 rdev->accel_working = false;
1145 }
733289c2 1146 }
3ce0a23d
JG		 1147 }
1148 return 0;
1149}
1150
1151void rv770_fini(struct radeon_device *rdev)
1152{
1153 r600_blit_fini(rdev);
655efd3d
JG		 1154 r600_cp_fini(rdev);
1155 r600_wb_fini(rdev);
d8f60cfc
AD		 1156 r600_irq_fini(rdev);
1157 radeon_irq_kms_fini(rdev);
4aac0473 1158 rv770_pcie_gart_fini(rdev);
3ce0a23d
JG		 1159 radeon_gem_fini(rdev);
1160 radeon_fence_driver_fini(rdev);
1161 radeon_clocks_fini(rdev);
d0269ed8 1162 radeon_agp_fini(rdev);
4c788679 1163 radeon_bo_fini(rdev);
e7d40b9a 1164 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1165 kfree(rdev->bios);
1166 rdev->bios = NULL;
1167 radeon_dummy_page_fini(rdev);
771fe6b9 1168}
kernel source for telekom puls (alcatel/mediatek)