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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
28d52043 33#include <linux/vgaarb.h>
6a9ee8af 34#include <linux/vga_switcheroo.h>
771fe6b9
JG		 35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
b1e3a6d1
MD		 40/*
41 * Clear GPU surface registers.
42 */
3ce0a23d 43void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 44{
45 /* FIXME: check this out */
46 if (rdev->family < CHIP_R600) {
47 int i;
48
550e2d92
DA		 49 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
50 if (rdev->surface_regs[i].bo)
51 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
52 else
53 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 54 }
e024e110
DA		 55 /* enable surfaces */
56 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 57 }
58}
59
771fe6b9
JG		 60/*
61 * GPU scratch registers helpers function.
62 */
3ce0a23d 63void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 64{
65 int i;
66
67 /* FIXME: check this out */
68 if (rdev->family < CHIP_R300) {
69 rdev->scratch.num_reg = 5;
70 } else {
71 rdev->scratch.num_reg = 7;
72 }
73 for (i = 0; i < rdev->scratch.num_reg; i++) {
74 rdev->scratch.free[i] = true;
75 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
76 }
77}
78
79int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
80{
81 int i;
82
83 for (i = 0; i < rdev->scratch.num_reg; i++) {
84 if (rdev->scratch.free[i]) {
85 rdev->scratch.free[i] = false;
86 *reg = rdev->scratch.reg[i];
87 return 0;
88 }
89 }
90 return -EINVAL;
91}
92
93void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
94{
95 int i;
96
97 for (i = 0; i < rdev->scratch.num_reg; i++) {
98 if (rdev->scratch.reg[i] == reg) {
99 rdev->scratch.free[i] = true;
100 return;
101 }
102 }
103}
104
d594e46a
JG		 105/**
106 * radeon_vram_location - try to find VRAM location
107 * @rdev: radeon device structure holding all necessary informations
108 * @mc: memory controller structure holding memory informations
109 * @base: base address at which to put VRAM
110 *
111 * Function will place try to place VRAM at base address provided
112 * as parameter (which is so far either PCI aperture address or
113 * for IGP TOM base address).
114 *
115 * If there is not enough space to fit the unvisible VRAM in the 32bits
116 * address space then we limit the VRAM size to the aperture.
117 *
118 * If we are using AGP and if the AGP aperture doesn't allow us to have
119 * room for all the VRAM than we restrict the VRAM to the PCI aperture
120 * size and print a warning.
121 *
122 * This function will never fails, worst case are limiting VRAM.
123 *
124 * Note: GTT start, end, size should be initialized before calling this
125 * function on AGP platform.
126 *
127 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
128 * this shouldn't be a problem as we are using the PCI aperture as a reference.
129 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
130 * not IGP.
131 *
132 * Note: we use mc_vram_size as on some board we need to program the mc to
133 * cover the whole aperture even if VRAM size is inferior to aperture size
134 * Novell bug 204882 + along with lots of ubuntu ones
135 *
136 * Note: when limiting vram it's safe to overwritte real_vram_size because
137 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
138 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
139 * ones)
140 *
141 * Note: IGP TOM addr should be the same as the aperture addr, we don't
142 * explicitly check for that thought.
143 *
144 * FIXME: when reducing VRAM size align new size on power of 2.
771fe6b9 145 */
d594e46a 146void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
771fe6b9 147{
d594e46a
JG		 148 mc->vram_start = base;
149 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
150 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
151 mc->real_vram_size = mc->aper_size;
152 mc->mc_vram_size = mc->aper_size;
153 }
154 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
155 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
156 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
157 mc->real_vram_size = mc->aper_size;
158 mc->mc_vram_size = mc->aper_size;
159 }
160 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
161 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
162 mc->mc_vram_size >> 20, mc->vram_start,
163 mc->vram_end, mc->real_vram_size >> 20);
164}
771fe6b9 165
d594e46a
JG		 166/**
167 * radeon_gtt_location - try to find GTT location
168 * @rdev: radeon device structure holding all necessary informations
169 * @mc: memory controller structure holding memory informations
170 *
171 * Function will place try to place GTT before or after VRAM.
172 *
173 * If GTT size is bigger than space left then we ajust GTT size.
174 * Thus function will never fails.
175 *
176 * FIXME: when reducing GTT size align new size on power of 2.
177 */
178void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
179{
180 u64 size_af, size_bf;
181
182 size_af = 0xFFFFFFFF - mc->vram_end;
183 size_bf = mc->vram_start;
184 if (size_bf > size_af) {
185 if (mc->gtt_size > size_bf) {
186 dev_warn(rdev->dev, "limiting GTT\n");
187 mc->gtt_size = size_bf;
771fe6b9 188 }
d594e46a 189 mc->gtt_start = mc->vram_start - mc->gtt_size;
771fe6b9 190 } else {
d594e46a
JG		 191 if (mc->gtt_size > size_af) {
192 dev_warn(rdev->dev, "limiting GTT\n");
193 mc->gtt_size = size_af;
194 }
195 mc->gtt_start = mc->vram_end + 1;
771fe6b9 196 }
d594e46a
JG		 197 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
198 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
199 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
771fe6b9
JG		 200}
201
771fe6b9
JG		 202/*
203 * GPU helpers function.
204 */
9f022ddf 205bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 206{
207 uint32_t reg;
208
209 /* first check CRTCs */
bcc1c2a1
AD		 210 if (ASIC_IS_DCE4(rdev)) {
211 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
212 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
213 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
214 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
215 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
216 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
217 if (reg & EVERGREEN_CRTC_MASTER_EN)
218 return true;
219 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 220 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
221 RREG32(AVIVO_D2CRTC_CONTROL);
222 if (reg & AVIVO_CRTC_EN) {
223 return true;
224 }
225 } else {
226 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
227 RREG32(RADEON_CRTC2_GEN_CNTL);
228 if (reg & RADEON_CRTC_EN) {
229 return true;
230 }
231 }
232
233 /* then check MEM_SIZE, in case the crtcs are off */
234 if (rdev->family >= CHIP_R600)
235 reg = RREG32(R600_CONFIG_MEMSIZE);
236 else
237 reg = RREG32(RADEON_CONFIG_MEMSIZE);
238
239 if (reg)
240 return true;
241
242 return false;
243
244}
245
72542d77
DA		 246bool radeon_boot_test_post_card(struct radeon_device *rdev)
247{
248 if (radeon_card_posted(rdev))
249 return true;
250
251 if (rdev->bios) {
252 DRM_INFO("GPU not posted. posting now...\n");
253 if (rdev->is_atom_bios)
254 atom_asic_init(rdev->mode_info.atom_context);
255 else
256 radeon_combios_asic_init(rdev->ddev);
257 return true;
258 } else {
259 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
260 return false;
261 }
262}
263
3ce0a23d
JG		 264int radeon_dummy_page_init(struct radeon_device *rdev)
265{
82568565
DA		 266 if (rdev->dummy_page.page)
267 return 0;
3ce0a23d
JG		 268 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
269 if (rdev->dummy_page.page == NULL)
270 return -ENOMEM;
271 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
272 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
273 if (!rdev->dummy_page.addr) {
274 __free_page(rdev->dummy_page.page);
275 rdev->dummy_page.page = NULL;
276 return -ENOMEM;
277 }
278 return 0;
279}
280
281void radeon_dummy_page_fini(struct radeon_device *rdev)
282{
283 if (rdev->dummy_page.page == NULL)
284 return;
285 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
286 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
287 __free_page(rdev->dummy_page.page);
288 rdev->dummy_page.page = NULL;
289}
290
771fe6b9
JG		 291
292/*
293 * Registers accessors functions.
294 */
295uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
296{
297 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
298 BUG_ON(1);
299 return 0;
300}
301
302void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
303{
304 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
305 reg, v);
306 BUG_ON(1);
307}
308
309void radeon_register_accessor_init(struct radeon_device *rdev)
310{
771fe6b9
JG		 311 rdev->mc_rreg = &radeon_invalid_rreg;
312 rdev->mc_wreg = &radeon_invalid_wreg;
313 rdev->pll_rreg = &radeon_invalid_rreg;
314 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 315 rdev->pciep_rreg = &radeon_invalid_rreg;
316 rdev->pciep_wreg = &radeon_invalid_wreg;
317
318 /* Don't change order as we are overridding accessor. */
319 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 320 rdev->pcie_reg_mask = 0xff;
321 } else {
322 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 323 }
324 /* FIXME: not sure here */
325 if (rdev->family <= CHIP_R580) {
326 rdev->pll_rreg = &r100_pll_rreg;
327 rdev->pll_wreg = &r100_pll_wreg;
328 }
905b6822
JG		 329 if (rdev->family >= CHIP_R420) {
330 rdev->mc_rreg = &r420_mc_rreg;
331 rdev->mc_wreg = &r420_mc_wreg;
332 }
771fe6b9
JG		 333 if (rdev->family >= CHIP_RV515) {
334 rdev->mc_rreg = &rv515_mc_rreg;
335 rdev->mc_wreg = &rv515_mc_wreg;
336 }
337 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
338 rdev->mc_rreg = &rs400_mc_rreg;
339 rdev->mc_wreg = &rs400_mc_wreg;
340 }
341 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
342 rdev->mc_rreg = &rs690_mc_rreg;
343 rdev->mc_wreg = &rs690_mc_wreg;
344 }
345 if (rdev->family == CHIP_RS600) {
346 rdev->mc_rreg = &rs600_mc_rreg;
347 rdev->mc_wreg = &rs600_mc_wreg;
348 }
bcc1c2a1 349 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
771fe6b9
JG		 350 rdev->pciep_rreg = &r600_pciep_rreg;
351 rdev->pciep_wreg = &r600_pciep_wreg;
352 }
353}
354
355
356/*
357 * ASIC
358 */
359int radeon_asic_init(struct radeon_device *rdev)
360{
361 radeon_register_accessor_init(rdev);
362 switch (rdev->family) {
363 case CHIP_R100:
364 case CHIP_RV100:
365 case CHIP_RS100:
366 case CHIP_RV200:
367 case CHIP_RS200:
44ca7478
PN		 368 rdev->asic = &r100_asic;
369 break;
771fe6b9
JG		 370 case CHIP_R200:
371 case CHIP_RV250:
372 case CHIP_RS300:
373 case CHIP_RV280:
44ca7478 374 rdev->asic = &r200_asic;
771fe6b9
JG		 375 break;
376 case CHIP_R300:
377 case CHIP_R350:
378 case CHIP_RV350:
379 case CHIP_RV380:
d80eeb0f
PN		 380 if (rdev->flags & RADEON_IS_PCIE)
381 rdev->asic = &r300_asic_pcie;
382 else
383 rdev->asic = &r300_asic;
771fe6b9
JG		 384 break;
385 case CHIP_R420:
386 case CHIP_R423:
387 case CHIP_RV410:
388 rdev->asic = &r420_asic;
389 break;
390 case CHIP_RS400:
391 case CHIP_RS480:
392 rdev->asic = &rs400_asic;
393 break;
394 case CHIP_RS600:
395 rdev->asic = &rs600_asic;
396 break;
397 case CHIP_RS690:
398 case CHIP_RS740:
399 rdev->asic = &rs690_asic;
400 break;
401 case CHIP_RV515:
402 rdev->asic = &rv515_asic;
403 break;
404 case CHIP_R520:
405 case CHIP_RV530:
406 case CHIP_RV560:
407 case CHIP_RV570:
408 case CHIP_R580:
409 rdev->asic = &r520_asic;
410 break;
411 case CHIP_R600:
412 case CHIP_RV610:
413 case CHIP_RV630:
414 case CHIP_RV620:
415 case CHIP_RV635:
416 case CHIP_RV670:
417 case CHIP_RS780:
3ce0a23d
JG		 418 case CHIP_RS880:
419 rdev->asic = &r600_asic;
420 break;
771fe6b9
JG		 421 case CHIP_RV770:
422 case CHIP_RV730:
423 case CHIP_RV710:
3ce0a23d
JG		 424 case CHIP_RV740:
425 rdev->asic = &rv770_asic;
426 break;
bcc1c2a1
AD		 427 case CHIP_CEDAR:
428 case CHIP_REDWOOD:
429 case CHIP_JUNIPER:
430 case CHIP_CYPRESS:
431 case CHIP_HEMLOCK:
432 rdev->asic = &evergreen_asic;
433 break;
771fe6b9
JG		 434 default:
435 /* FIXME: not supported yet */
436 return -EINVAL;
437 }
5ea597f3
RM		 438
439 if (rdev->flags & RADEON_IS_IGP) {
440 rdev->asic->get_memory_clock = NULL;
441 rdev->asic->set_memory_clock = NULL;
442 }
443
771fe6b9
JG		 444 return 0;
445}
446
447
448/*
449 * Wrapper around modesetting bits.
450 */
451int radeon_clocks_init(struct radeon_device *rdev)
452{
453 int r;
454
771fe6b9
JG		 455 r = radeon_static_clocks_init(rdev->ddev);
456 if (r) {
457 return r;
458 }
459 DRM_INFO("Clocks initialized !\n");
460 return 0;
461}
462
463void radeon_clocks_fini(struct radeon_device *rdev)
464{
465}
466
467/* ATOM accessor methods */
468static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
469{
470 struct radeon_device *rdev = info->dev->dev_private;
471 uint32_t r;
472
473 r = rdev->pll_rreg(rdev, reg);
474 return r;
475}
476
477static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
478{
479 struct radeon_device *rdev = info->dev->dev_private;
480
481 rdev->pll_wreg(rdev, reg, val);
482}
483
484static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
485{
486 struct radeon_device *rdev = info->dev->dev_private;
487 uint32_t r;
488
489 r = rdev->mc_rreg(rdev, reg);
490 return r;
491}
492
493static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
494{
495 struct radeon_device *rdev = info->dev->dev_private;
496
497 rdev->mc_wreg(rdev, reg, val);
498}
499
500static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
501{
502 struct radeon_device *rdev = info->dev->dev_private;
503
504 WREG32(reg*4, val);
505}
506
507static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
508{
509 struct radeon_device *rdev = info->dev->dev_private;
510 uint32_t r;
511
512 r = RREG32(reg*4);
513 return r;
514}
515
771fe6b9
JG		 516int radeon_atombios_init(struct radeon_device *rdev)
517{
61c4b24b
MF		 518 struct card_info *atom_card_info =
519 kzalloc(sizeof(struct card_info), GFP_KERNEL);
520
521 if (!atom_card_info)
522 return -ENOMEM;
523
524 rdev->mode_info.atom_card_info = atom_card_info;
525 atom_card_info->dev = rdev->ddev;
526 atom_card_info->reg_read = cail_reg_read;
527 atom_card_info->reg_write = cail_reg_write;
528 atom_card_info->mc_read = cail_mc_read;
529 atom_card_info->mc_write = cail_mc_write;
530 atom_card_info->pll_read = cail_pll_read;
531 atom_card_info->pll_write = cail_pll_write;
532
533 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 534 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 535 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 536 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 537 return 0;
538}
539
540void radeon_atombios_fini(struct radeon_device *rdev)
541{
4a04a844
JG		 542 if (rdev->mode_info.atom_context) {
543 kfree(rdev->mode_info.atom_context->scratch);
544 kfree(rdev->mode_info.atom_context);
545 }
61c4b24b 546 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 547}
548
549int radeon_combios_init(struct radeon_device *rdev)
550{
551 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
552 return 0;
553}
554
555void radeon_combios_fini(struct radeon_device *rdev)
556{
557}
558
28d52043
DA		 559/* if we get transitioned to only one device, tak VGA back */
560static unsigned int radeon_vga_set_decode(void *cookie, bool state)
561{
562 struct radeon_device *rdev = cookie;
28d52043
DA		 563 radeon_vga_set_state(rdev, state);
564 if (state)
565 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
566 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
567 else
568 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
569}
c1176d6f 570
b574f251
JG		 571void radeon_agp_disable(struct radeon_device *rdev)
572{
573 rdev->flags &= ~RADEON_IS_AGP;
574 if (rdev->family >= CHIP_R600) {
575 DRM_INFO("Forcing AGP to PCIE mode\n");
576 rdev->flags |= RADEON_IS_PCIE;
577 } else if (rdev->family >= CHIP_RV515 ||
578 rdev->family == CHIP_RV380 ||
579 rdev->family == CHIP_RV410 ||
580 rdev->family == CHIP_R423) {
581 DRM_INFO("Forcing AGP to PCIE mode\n");
582 rdev->flags |= RADEON_IS_PCIE;
583 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
584 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
585 } else {
586 DRM_INFO("Forcing AGP to PCI mode\n");
587 rdev->flags |= RADEON_IS_PCI;
588 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
589 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
590 }
700a0cc0 591 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
b574f251 592}
771fe6b9 593
36421338
JG		 594void radeon_check_arguments(struct radeon_device *rdev)
595{
596 /* vramlimit must be a power of two */
597 switch (radeon_vram_limit) {
598 case 0:
599 case 4:
600 case 8:
601 case 16:
602 case 32:
603 case 64:
604 case 128:
605 case 256:
606 case 512:
607 case 1024:
608 case 2048:
609 case 4096:
610 break;
611 default:
612 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
613 radeon_vram_limit);
614 radeon_vram_limit = 0;
615 break;
616 }
617 radeon_vram_limit = radeon_vram_limit << 20;
618 /* gtt size must be power of two and greater or equal to 32M */
619 switch (radeon_gart_size) {
620 case 4:
621 case 8:
622 case 16:
623 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
624 radeon_gart_size);
625 radeon_gart_size = 512;
626 break;
627 case 32:
628 case 64:
629 case 128:
630 case 256:
631 case 512:
632 case 1024:
633 case 2048:
634 case 4096:
635 break;
636 default:
637 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
638 radeon_gart_size);
639 radeon_gart_size = 512;
640 break;
641 }
642 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
643 /* AGP mode can only be -1, 1, 2, 4, 8 */
644 switch (radeon_agpmode) {
645 case -1:
646 case 0:
647 case 1:
648 case 2:
649 case 4:
650 case 8:
651 break;
652 default:
653 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
654 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
655 radeon_agpmode = 0;
656 break;
657 }
658}
659
6a9ee8af
DA		 660static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
661{
662 struct drm_device *dev = pci_get_drvdata(pdev);
663 struct radeon_device *rdev = dev->dev_private;
664 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
665 if (state == VGA_SWITCHEROO_ON) {
666 printk(KERN_INFO "radeon: switched on\n");
667 /* don't suspend or resume card normally */
668 rdev->powered_down = false;
669 radeon_resume_kms(dev);
670 } else {
671 printk(KERN_INFO "radeon: switched off\n");
672 radeon_suspend_kms(dev, pmm);
673 /* don't suspend or resume card normally */
674 rdev->powered_down = true;
675 }
676}
677
678static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
679{
680 struct drm_device *dev = pci_get_drvdata(pdev);
681 bool can_switch;
682
683 spin_lock(&dev->count_lock);
684 can_switch = (dev->open_count == 0);
685 spin_unlock(&dev->count_lock);
686 return can_switch;
687}
688
689
771fe6b9
JG		 690int radeon_device_init(struct radeon_device *rdev,
691 struct drm_device *ddev,
692 struct pci_dev *pdev,
693 uint32_t flags)
694{
6cf8a3f5 695 int r;
ad49f501 696 int dma_bits;
771fe6b9
JG		 697
698 DRM_INFO("radeon: Initializing kernel modesetting.\n");
699 rdev->shutdown = false;
9f022ddf 700 rdev->dev = &pdev->dev;
771fe6b9
JG		 701 rdev->ddev = ddev;
702 rdev->pdev = pdev;
703 rdev->flags = flags;
704 rdev->family = flags & RADEON_FAMILY_MASK;
705 rdev->is_atom_bios = false;
706 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
707 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
708 rdev->gpu_lockup = false;
733289c2 709 rdev->accel_working = false;
771fe6b9
JG		 710 /* mutex initialization are all done here so we
711 * can recall function without having locking issues */
712 mutex_init(&rdev->cs_mutex);
713 mutex_init(&rdev->ib_pool.mutex);
714 mutex_init(&rdev->cp.mutex);
40bacf16 715 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 716 if (rdev->family >= CHIP_R600)
717 spin_lock_init(&rdev->ih.lock);
4c788679 718 mutex_init(&rdev->gem.mutex);
c913e23a 719 mutex_init(&rdev->pm.mutex);
771fe6b9 720 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 721 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 722 init_waitqueue_head(&rdev->irq.vblank_queue);
771fe6b9 723
d4877cf2
AD		 724 /* setup workqueue */
725 rdev->wq = create_workqueue("radeon");
726 if (rdev->wq == NULL)
727 return -ENOMEM;
728
4aac0473
JG		 729 /* Set asic functions */
730 r = radeon_asic_init(rdev);
36421338 731 if (r)
4aac0473 732 return r;
36421338 733 radeon_check_arguments(rdev);
4aac0473 734
30256a3f 735 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 736 radeon_agp_disable(rdev);
771fe6b9
JG		 737 }
738
ad49f501
DA		 739 /* set DMA mask + need_dma32 flags.
740 * PCIE - can handle 40-bits.
741 * IGP - can handle 40-bits (in theory)
742 * AGP - generally dma32 is safest
743 * PCI - only dma32
744 */
745 rdev->need_dma32 = false;
746 if (rdev->flags & RADEON_IS_AGP)
747 rdev->need_dma32 = true;
748 if (rdev->flags & RADEON_IS_PCI)
749 rdev->need_dma32 = true;
750
751 dma_bits = rdev->need_dma32 ? 32 : 40;
752 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 753 if (r) {
754 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
755 }
756
757 /* Registers mapping */
758 /* TODO: block userspace mapping of io register */
759 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
760 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
761 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
762 if (rdev->rmmio == NULL) {
763 return -ENOMEM;
764 }
765 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
766 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
767
28d52043 768 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 769 /* this will fail for cards that aren't VGA class devices, just
770 * ignore it */
771 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
6a9ee8af
DA		 772 vga_switcheroo_register_client(rdev->pdev,
773 radeon_switcheroo_set_state,
774 radeon_switcheroo_can_switch);
28d52043 775
3ce0a23d 776 r = radeon_init(rdev);
b574f251 777 if (r)
3ce0a23d 778 return r;
3ce0a23d 779
b574f251
JG		 780 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
781 /* Acceleration not working on AGP card try again
782 * with fallback to PCI or PCIE GART
783 */
1a029b76 784 radeon_gpu_reset(rdev);
b574f251
JG		 785 radeon_fini(rdev);
786 radeon_agp_disable(rdev);
787 r = radeon_init(rdev);
4aac0473
JG		 788 if (r)
789 return r;
771fe6b9 790 }
ecc0b326
MD		 791 if (radeon_testing) {
792 radeon_test_moves(rdev);
793 }
771fe6b9
JG		 794 if (radeon_benchmarking) {
795 radeon_benchmark(rdev);
796 }
6cf8a3f5 797 return 0;
771fe6b9
JG		 798}
799
800void radeon_device_fini(struct radeon_device *rdev)
801{
771fe6b9
JG		 802 DRM_INFO("radeon: finishing device.\n");
803 rdev->shutdown = true;
62a8ea3f 804 radeon_fini(rdev);
d4877cf2 805 destroy_workqueue(rdev->wq);
6a9ee8af 806 vga_switcheroo_unregister_client(rdev->pdev);
c1176d6f 807 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 808 iounmap(rdev->rmmio);
809 rdev->rmmio = NULL;
810}
811
812
813/*
814 * Suspend & resume.
815 */
816int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
817{
875c1866 818 struct radeon_device *rdev;
771fe6b9 819 struct drm_crtc *crtc;
4c788679 820 int r;
771fe6b9 821
875c1866 822 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 823 return -ENODEV;
824 }
825 if (state.event == PM_EVENT_PRETHAW) {
826 return 0;
827 }
875c1866
DJ		 828 rdev = dev->dev_private;
829
6a9ee8af
DA		 830 if (rdev->powered_down)
831 return 0;
771fe6b9
JG		 832 /* unpin the front buffers */
833 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
834 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 835 struct radeon_bo *robj;
771fe6b9
JG		 836
837 if (rfb == NULL || rfb->obj == NULL) {
838 continue;
839 }
840 robj = rfb->obj->driver_private;
4c788679
JG		 841 if (robj != rdev->fbdev_rbo) {
842 r = radeon_bo_reserve(robj, false);
843 if (unlikely(r == 0)) {
844 radeon_bo_unpin(robj);
845 radeon_bo_unreserve(robj);
846 }
771fe6b9
JG		 847 }
848 }
849 /* evict vram memory */
4c788679 850 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 851 /* wait for gpu to finish processing current batch */
852 radeon_fence_wait_last(rdev);
853
f657c2a7
YZ		 854 radeon_save_bios_scratch_regs(rdev);
855
62a8ea3f 856 radeon_suspend(rdev);
d4877cf2 857 radeon_hpd_fini(rdev);
771fe6b9 858 /* evict remaining vram memory */
4c788679 859 radeon_bo_evict_vram(rdev);
771fe6b9 860
771fe6b9
JG		 861 pci_save_state(dev->pdev);
862 if (state.event == PM_EVENT_SUSPEND) {
863 /* Shut down the device */
864 pci_disable_device(dev->pdev);
865 pci_set_power_state(dev->pdev, PCI_D3hot);
866 }
867 acquire_console_sem();
868 fb_set_suspend(rdev->fbdev_info, 1);
869 release_console_sem();
870 return 0;
871}
872
873int radeon_resume_kms(struct drm_device *dev)
874{
875 struct radeon_device *rdev = dev->dev_private;
771fe6b9 876
6a9ee8af
DA		 877 if (rdev->powered_down)
878 return 0;
879
771fe6b9
JG		 880 acquire_console_sem();
881 pci_set_power_state(dev->pdev, PCI_D0);
882 pci_restore_state(dev->pdev);
883 if (pci_enable_device(dev->pdev)) {
884 release_console_sem();
885 return -1;
886 }
887 pci_set_master(dev->pdev);
0ebf1717
DA		 888 /* resume AGP if in use */
889 radeon_agp_resume(rdev);
62a8ea3f 890 radeon_resume(rdev);
f657c2a7 891 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 892 fb_set_suspend(rdev->fbdev_info, 0);
893 release_console_sem();
894
d4877cf2
AD		 895 /* reset hpd state */
896 radeon_hpd_init(rdev);
771fe6b9
JG		 897 /* blat the mode back in */
898 drm_helper_resume_force_mode(dev);
899 return 0;
900}
901
902
903/*
904 * Debugfs
905 */
906struct radeon_debugfs {
907 struct drm_info_list *files;
908 unsigned num_files;
909};
910static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
911static unsigned _radeon_debugfs_count = 0;
912
913int radeon_debugfs_add_files(struct radeon_device *rdev,
914 struct drm_info_list *files,
915 unsigned nfiles)
916{
917 unsigned i;
918
919 for (i = 0; i < _radeon_debugfs_count; i++) {
920 if (_radeon_debugfs[i].files == files) {
921 /* Already registered */
922 return 0;
923 }
924 }
925 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
926 DRM_ERROR("Reached maximum number of debugfs files.\n");
927 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
928 return -EINVAL;
929 }
930 _radeon_debugfs[_radeon_debugfs_count].files = files;
931 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
932 _radeon_debugfs_count++;
933#if defined(CONFIG_DEBUG_FS)
934 drm_debugfs_create_files(files, nfiles,
935 rdev->ddev->control->debugfs_root,
936 rdev->ddev->control);
937 drm_debugfs_create_files(files, nfiles,
938 rdev->ddev->primary->debugfs_root,
939 rdev->ddev->primary);
940#endif
941 return 0;
942}
943
944#if defined(CONFIG_DEBUG_FS)
945int radeon_debugfs_init(struct drm_minor *minor)
946{
947 return 0;
948}
949
950void radeon_debugfs_cleanup(struct drm_minor *minor)
951{
952 unsigned i;
953
954 for (i = 0; i < _radeon_debugfs_count; i++) {
955 drm_debugfs_remove_files(_radeon_debugfs[i].files,
956 _radeon_debugfs[i].num_files, minor);
957 }
958}
959#endif
kernel source for telekom puls (alcatel/mediatek)