[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-tc3589x.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE };

#define CACHE_NR_REGS	4
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;
	struct irq_domain *domain;

	int irq_base;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct tc3589x_gpio, chip);
}

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return ret & mask;
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned pos = offset % 8;
	u8 data[] = {!!val << pos, 1 << pos};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
}

/**
 * tc3589x_gpio_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
 *
 * @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
 * @irq: index of the interrupt requested in the chip IRQs
 *
 * Useful for drivers to request their own IRQs.
 */
static int tc3589x_gpio_irq_get_virq(struct tc3589x_gpio *tc3589x_gpio,
				     int irq)
{
	if (!tc3589x_gpio)
		return -EINVAL;

	return irq_create_mapping(tc3589x_gpio->domain, irq);
}

static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);

	return tc3589x_gpio_irq_get_virq(tc3589x_gpio, offset);
}

static struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.direction_input	= tc3589x_gpio_direction_input,
	.get			= tc3589x_gpio_get,
	.direction_output	= tc3589x_gpio_direction_output,
	.set			= tc3589x_gpio_set,
	.to_irq			= tc3589x_gpio_to_irq,
	.can_sleep		= 1,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;
			int virq = tc3589x_gpio_irq_get_virq(tc3589x_gpio, line);

			handle_nested_irq(virq);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hwirq)
{
	struct tc3589x *tc3589x_gpio = d->host_data;

	irq_set_chip_data(virq, tc3589x_gpio);
	irq_set_chip_and_handler(virq, &tc3589x_gpio_irq_chip,
				handle_simple_irq);
	irq_set_nested_thread(virq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(virq, IRQF_VALID);
#else
	irq_set_noprobe(virq);
#endif

	return 0;
}

static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
{
#ifdef CONFIG_ARM
	set_irq_flags(virq, 0);
#endif
	irq_set_chip_and_handler(virq, NULL, NULL);
	irq_set_chip_data(virq, NULL);
}

static struct irq_domain_ops tc3589x_irq_ops = {
	.map    = tc3589x_gpio_irq_map,
	.unmap  = tc3589x_gpio_irq_unmap,
	.xlate  = irq_domain_xlate_twocell,
};

static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio,
				struct device_node *np)
{
	int base = tc3589x_gpio->irq_base;

	/*
	 * If this results in a linear domain, irq_create_mapping() will
	 * take care of allocating IRQ descriptors at runtime. When a base
	 * is provided, the IRQ descriptors will be allocated when the
	 * domain is instantiated.
	 */
	tc3589x_gpio->domain = irq_domain_add_simple(np,
			tc3589x_gpio->chip.ngpio, base, &tc3589x_irq_ops,
			tc3589x_gpio);
	if (!tc3589x_gpio->domain) {
		dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
		return -ENOSYS;
	}

	return 0;
}

static int tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct tc3589x_gpio_platform_data *pdata;
	struct device_node *np = pdev->dev.of_node;
	struct tc3589x_gpio *tc3589x_gpio;
	int ret;
	int irq;

	pdata = tc3589x->pdata->gpio;

	if (!(pdata || np)) {
		dev_err(&pdev->dev, "No platform data or Device Tree found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.dev = &pdev->dev;
	tc3589x_gpio->chip.base = (pdata) ? pdata->gpio_base : -1;

#ifdef CONFIG_OF_GPIO
	tc3589x_gpio->chip.of_node = np;
#endif

	tc3589x_gpio->irq_base = tc3589x->irq_base ?
		tc3589x->irq_base + TC3589x_INT_GPIO(0) : 0;

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		goto out_free;

	ret = tc3589x_gpio_irq_init(tc3589x_gpio, np);
	if (ret)
		goto out_free;

	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
				   "tc3589x-gpio", tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		goto out_free;
	}

	ret = gpiochip_add(&tc3589x_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata && pdata->setup)
		pdata->setup(tc3589x, tc3589x_gpio->chip.base);

	platform_set_drvdata(pdev, tc3589x_gpio);

	return 0;

out_freeirq:
	free_irq(irq, tc3589x_gpio);
out_free:
	kfree(tc3589x_gpio);
	return ret;
}

static int tc3589x_gpio_remove(struct platform_device *pdev)
{
	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata && pdata->remove)
		pdata->remove(tc3589x, tc3589x_gpio->chip.base);

	ret = gpiochip_remove(&tc3589x_gpio->chip);
	if (ret < 0) {
		dev_err(tc3589x_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	free_irq(irq, tc3589x_gpio);

	platform_set_drvdata(pdev, NULL);
	kfree(tc3589x_gpio);

	return 0;
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= tc3589x_gpio_probe,
	.remove		= tc3589x_gpio_remove,
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);

static void __exit tc3589x_gpio_exit(void)
{
	platform_driver_unregister(&tc3589x_gpio_driver);
}
module_exit(tc3589x_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("TC3589x GPIO driver");
MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");
Commit	Line	Data
d88b25be RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/slab.h>
	13	#include <linux/gpio.h>
3113e679	14	#include <linux/of.h>
d88b25be	15	#include <linux/irq.h>
efe4c949	16	#include <linux/irqdomain.h>
d88b25be	17	#include <linux/interrupt.h>
c6eda6c5	18	#include <linux/mfd/tc3589x.h>
d88b25be RV	19
	20	/*
	21	* These registers are modified under the irq bus lock and cached to avoid
	22	* unnecessary writes in bus_sync_unlock.
	23	*/
	24	enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
	25
	26	#define CACHE_NR_REGS 4
	27	#define CACHE_NR_BANKS 3
	28
20406ebf	29	struct tc3589x_gpio {
d88b25be	30	struct gpio_chip chip;
20406ebf	31	struct tc3589x *tc3589x;
d88b25be RV	32	struct device *dev;
d88b25be RV	33	struct mutex irq_lock;
efe4c949	34	struct irq_domain *domain;
d88b25be RV	35
	36	int irq_base;
	37
	38	/* Caches of interrupt control registers for bus_lock */
	39	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	41	};
	42
20406ebf	43	static inline struct tc3589x_gpio to_tc3589x_gpio(struct gpio_chip chip)
d88b25be	44	{
20406ebf	45	return container_of(chip, struct tc3589x_gpio, chip);
d88b25be RV	46	}
d88b25be RV	47
20406ebf	48	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
d88b25be	49	{
20406ebf SI	50	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	51	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	52	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	53	u8 mask = 1 << (offset % 8);
	54	int ret;
	55
20406ebf	56	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	57	if (ret < 0)
	58	return ret;
	59
	60	return ret & mask;
	61	}
	62
20406ebf	63	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
d88b25be	64	{
20406ebf SI	65	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	66	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	67	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
d88b25be RV	68	unsigned pos = offset % 8;
	69	u8 data[] = {!!val << pos, 1 << pos};
	70
20406ebf	71	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	72	}
d88b25be RV	73
20406ebf	74	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
d88b25be RV	75	unsigned offset, int val)
d88b25be RV	76	{
20406ebf SI	77	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	78	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	79	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	80	unsigned pos = offset % 8;
d88b25be RV	81
20406ebf	82	tc3589x_gpio_set(chip, offset, val);
d88b25be	83
20406ebf	84	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
d88b25be RV	85	}
d88b25be RV	86
20406ebf	87	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
d88b25be RV	88	unsigned offset)
d88b25be RV	89	{
20406ebf SI	90	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
	91	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	92	u8 reg = TC3589x_GPIODIR0 + offset / 8;
d88b25be RV	93	unsigned pos = offset % 8;
d88b25be RV	94
20406ebf	95	return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
d88b25be RV	96	}
d88b25be RV	97
efe4c949 LJ	98	/**
	99	* tc3589x_gpio_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
	100	*
	101	* @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
	102	* @irq: index of the interrupt requested in the chip IRQs
	103	*
	104	* Useful for drivers to request their own IRQs.
	105	*/
	106	static int tc3589x_gpio_irq_get_virq(struct tc3589x_gpio *tc3589x_gpio,
	107	int irq)
	108	{
	109	if (!tc3589x_gpio)
	110	return -EINVAL;
	111
	112	return irq_create_mapping(tc3589x_gpio->domain, irq);
	113	}
	114
20406ebf	115	static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
d88b25be	116	{
20406ebf	117	struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
d88b25be	118
efe4c949	119	return tc3589x_gpio_irq_get_virq(tc3589x_gpio, offset);
d88b25be RV	120	}
	121
	122	static struct gpio_chip template_chip = {
20406ebf	123	.label = "tc3589x",
d88b25be	124	.owner = THIS_MODULE,
20406ebf SI	125	.direction_input = tc3589x_gpio_direction_input,
	126	.get = tc3589x_gpio_get,
	127	.direction_output = tc3589x_gpio_direction_output,
	128	.set = tc3589x_gpio_set,
	129	.to_irq = tc3589x_gpio_to_irq,
d88b25be RV	130	.can_sleep = 1,
	131	};
	132
33fcc1b8	133	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	134	{
33fcc1b8	135	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	136	int offset = d->hwirq;
d88b25be RV	137	int regoffset = offset / 8;
	138	int mask = 1 << (offset % 8);
	139
	140	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	141	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	142	return 0;
	143	}
	144
20406ebf	145	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	146
d88b25be RV	147	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	148	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	149	else
20406ebf	150	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	151
d88b25be RV	152	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	153	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	154	else
20406ebf	155	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	156
	157	return 0;
	158	}
	159
33fcc1b8	160	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	161	{
33fcc1b8	162	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
d88b25be	163
20406ebf	164	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	165	}
d88b25be RV	166
33fcc1b8	167	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	168	{
33fcc1b8	169	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
20406ebf	170	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	171	static const u8 regmap[] = {
20406ebf SI	172	[REG_IBE] = TC3589x_GPIOIBE0,
	173	[REG_IEV] = TC3589x_GPIOIEV0,
	174	[REG_IS] = TC3589x_GPIOIS0,
	175	[REG_IE] = TC3589x_GPIOIE0,
d88b25be RV	176	};
	177	int i, j;
	178
	179	for (i = 0; i < CACHE_NR_REGS; i++) {
	180	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	181	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	182	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	183
	184	if (new == old)
	185	continue;
	186
20406ebf SI	187	tc3589x_gpio->oldregs[i][j] = new;
20406ebf SI	188	tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
d88b25be RV	189	}
	190	}
	191
20406ebf	192	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	193	}
d88b25be RV	194
33fcc1b8	195	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	196	{
33fcc1b8	197	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	198	int offset = d->hwirq;
d88b25be RV	199	int regoffset = offset / 8;
	200	int mask = 1 << (offset % 8);
	201
20406ebf	202	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d88b25be RV	203	}
d88b25be RV	204
33fcc1b8	205	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	206	{
33fcc1b8	207	struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
efe4c949	208	int offset = d->hwirq;
d88b25be RV	209	int regoffset = offset / 8;
	210	int mask = 1 << (offset % 8);
	211
20406ebf	212	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d88b25be RV	213	}
d88b25be RV	214
20406ebf SI	215	static struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf SI	216	.name = "tc3589x-gpio",
33fcc1b8 LB	217	.irq_bus_lock = tc3589x_gpio_irq_lock,
	218	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	219	.irq_mask = tc3589x_gpio_irq_mask,
	220	.irq_unmask = tc3589x_gpio_irq_unmask,
	221	.irq_set_type = tc3589x_gpio_irq_set_type,
d88b25be RV	222	};
d88b25be RV	223
20406ebf	224	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	225	{
20406ebf SI	226	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	227	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	228	u8 status[CACHE_NR_BANKS];
	229	int ret;
	230	int i;
	231
20406ebf	232	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	233	ARRAY_SIZE(status), status);
	234	if (ret < 0)
	235	return IRQ_NONE;
	236
	237	for (i = 0; i < ARRAY_SIZE(status); i++) {
	238	unsigned int stat = status[i];
	239	if (!stat)
	240	continue;
	241
	242	while (stat) {
	243	int bit = __ffs(stat);
	244	int line = i * 8 + bit;
efe4c949	245	int virq = tc3589x_gpio_irq_get_virq(tc3589x_gpio, line);
d88b25be	246
efe4c949	247	handle_nested_irq(virq);
d88b25be RV	248	stat &= ~(1 << bit);
	249	}
	250
20406ebf	251	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	252	}
	253
	254	return IRQ_HANDLED;
	255	}
	256
efe4c949 LJ	257	static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int virq,
efe4c949 LJ	258	irq_hw_number_t hwirq)
d88b25be	259	{
efe4c949	260	struct tc3589x *tc3589x_gpio = d->host_data;
d88b25be	261
efe4c949 LJ	262	irq_set_chip_data(virq, tc3589x_gpio);
	263	irq_set_chip_and_handler(virq, &tc3589x_gpio_irq_chip,
	264	handle_simple_irq);
	265	irq_set_nested_thread(virq, 1);
d88b25be	266	#ifdef CONFIG_ARM
efe4c949	267	set_irq_flags(virq, IRQF_VALID);
d88b25be	268	#else
efe4c949	269	irq_set_noprobe(virq);
d88b25be	270	#endif
d88b25be RV	271
	272	return 0;
	273	}
	274
efe4c949	275	static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
d88b25be	276	{
d88b25be	277	#ifdef CONFIG_ARM
efe4c949	278	set_irq_flags(virq, 0);
d88b25be	279	#endif
efe4c949 LJ	280	irq_set_chip_and_handler(virq, NULL, NULL);
	281	irq_set_chip_data(virq, NULL);
	282	}
	283
	284	static struct irq_domain_ops tc3589x_irq_ops = {
e90c636b LN	285	.map = tc3589x_gpio_irq_map,
	286	.unmap = tc3589x_gpio_irq_unmap,
	287	.xlate = irq_domain_xlate_twocell,
efe4c949 LJ	288	};
efe4c949 LJ	289
3113e679 LJ	290	static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio,
3113e679 LJ	291	struct device_node *np)
efe4c949 LJ	292	{
	293	int base = tc3589x_gpio->irq_base;
	294
a362605b LW	295	/*
	296	* If this results in a linear domain, irq_create_mapping() will
	297	* take care of allocating IRQ descriptors at runtime. When a base
	298	* is provided, the IRQ descriptors will be allocated when the
	299	* domain is instantiated.
	300	*/
	301	tc3589x_gpio->domain = irq_domain_add_simple(np,
	302	tc3589x_gpio->chip.ngpio, base, &tc3589x_irq_ops,
	303	tc3589x_gpio);
efe4c949 LJ	304	if (!tc3589x_gpio->domain) {
	305	dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
	306	return -ENOSYS;
	307	}
	308
	309	return 0;
d88b25be RV	310	}
d88b25be RV	311
3836309d	312	static int tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	313	{
20406ebf SI	314	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
20406ebf SI	315	struct tc3589x_gpio_platform_data *pdata;
3113e679	316	struct device_node *np = pdev->dev.of_node;
20406ebf	317	struct tc3589x_gpio *tc3589x_gpio;
d88b25be RV	318	int ret;
	319	int irq;
	320
20406ebf	321	pdata = tc3589x->pdata->gpio;
3113e679 LJ	322
	323	if (!(pdata \|\| np)) {
	324	dev_err(&pdev->dev, "No platform data or Device Tree found\n");
	325	return -EINVAL;
	326	}
d88b25be RV	327
	328	irq = platform_get_irq(pdev, 0);
	329	if (irq < 0)
	330	return irq;
	331
20406ebf SI	332	tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL);
20406ebf SI	333	if (!tc3589x_gpio)
d88b25be RV	334	return -ENOMEM;
d88b25be RV	335
20406ebf	336	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	337
20406ebf SI	338	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	339	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	340
20406ebf SI	341	tc3589x_gpio->chip = template_chip;
	342	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	343	tc3589x_gpio->chip.dev = &pdev->dev;
3113e679	344	tc3589x_gpio->chip.base = (pdata) ? pdata->gpio_base : -1;
d88b25be	345
3113e679	346	#ifdef CONFIG_OF_GPIO
e90c636b	347	tc3589x_gpio->chip.of_node = np;
3113e679	348	#endif
d88b25be	349
efe4c949 LJ	350	tc3589x_gpio->irq_base = tc3589x->irq_base ?
	351	tc3589x->irq_base + TC3589x_INT_GPIO(0) : 0;
	352
d88b25be	353	/* Bring the GPIO module out of reset */
20406ebf SI	354	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	355	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be RV	356	if (ret < 0)
	357	goto out_free;
	358
3113e679	359	ret = tc3589x_gpio_irq_init(tc3589x_gpio, np);
d88b25be RV	360	if (ret)
	361	goto out_free;
	362
20406ebf SI	363	ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT,
20406ebf SI	364	"tc3589x-gpio", tc3589x_gpio);
d88b25be RV	365	if (ret) {
d88b25be RV	366	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
efe4c949	367	goto out_free;
d88b25be RV	368	}
d88b25be RV	369
20406ebf	370	ret = gpiochip_add(&tc3589x_gpio->chip);
d88b25be RV	371	if (ret) {
	372	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	373	goto out_freeirq;
	374	}
	375
3113e679	376	if (pdata && pdata->setup)
20406ebf	377	pdata->setup(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	378
20406ebf	379	platform_set_drvdata(pdev, tc3589x_gpio);
d88b25be RV	380
	381	return 0;
	382
	383	out_freeirq:
20406ebf	384	free_irq(irq, tc3589x_gpio);
d88b25be	385	out_free:
20406ebf	386	kfree(tc3589x_gpio);
d88b25be RV	387	return ret;
	388	}
	389
206210ce	390	static int tc3589x_gpio_remove(struct platform_device *pdev)
d88b25be	391	{
20406ebf SI	392	struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
	393	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	394	struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio;
d88b25be RV	395	int irq = platform_get_irq(pdev, 0);
	396	int ret;
	397
3113e679	398	if (pdata && pdata->remove)
20406ebf	399	pdata->remove(tc3589x, tc3589x_gpio->chip.base);
f0a7a98d	400
20406ebf	401	ret = gpiochip_remove(&tc3589x_gpio->chip);
d88b25be	402	if (ret < 0) {
20406ebf	403	dev_err(tc3589x_gpio->dev,
d88b25be RV	404	"unable to remove gpiochip: %d\n", ret);
	405	return ret;
	406	}
	407
20406ebf	408	free_irq(irq, tc3589x_gpio);
d88b25be RV	409
d88b25be RV	410	platform_set_drvdata(pdev, NULL);
20406ebf	411	kfree(tc3589x_gpio);
d88b25be RV	412
	413	return 0;
	414	}
	415
20406ebf SI	416	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	417	.driver.name = "tc3589x-gpio",
d88b25be	418	.driver.owner = THIS_MODULE,
20406ebf	419	.probe = tc3589x_gpio_probe,
8283c4ff	420	.remove = tc3589x_gpio_remove,
d88b25be RV	421	};
d88b25be RV	422
20406ebf	423	static int __init tc3589x_gpio_init(void)
d88b25be	424	{
20406ebf	425	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	426	}
20406ebf	427	subsys_initcall(tc3589x_gpio_init);
d88b25be	428
20406ebf	429	static void __exit tc3589x_gpio_exit(void)
d88b25be	430	{
20406ebf	431	platform_driver_unregister(&tc3589x_gpio_driver);
d88b25be	432	}
20406ebf	433	module_exit(tc3589x_gpio_exit);
d88b25be RV	434
d88b25be RV	435	MODULE_LICENSE("GPL v2");
20406ebf	436	MODULE_DESCRIPTION("TC3589x GPIO driver");
d88b25be	437	MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");