[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

#define CACHE_NR_REGS	3
#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	struct irq_domain *domain;

	int irq_base;
	unsigned norequest_mask;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct stmpe_gpio, chip);
}

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);

	return irq_create_mapping(stmpe_gpio->domain, offset);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.to_irq			= stmpe_gpio_to_irq,
	.request		= stmpe_gpio_request,
	.can_sleep		= 1,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 doesn't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801)
		return 0;

	if (type == IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[] = {
		[REG_RE]	= STMPE_IDX_GPRER_LSB,
		[REG_FE]	= STMPE_IDX_GPFER_LSB,
		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 doesn't have RE and FE registers */
		if ((stmpe->partnum == STMPE801) &&
				(i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int virq = irq_find_mapping(stmpe_gpio->domain, line);

			handle_nested_irq(virq);
			stat &= ~(1 << bit);
		}

		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);

		/* Edge detect register is not present on 801 */
		if (stmpe->partnum != STMPE801)
			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
					+ i, status[i]);
	}

	return IRQ_HANDLED;
}

int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int virq,
		       irq_hw_number_t hwirq)
{
	struct stmpe_gpio *stmpe_gpio = d->host_data;

	if (!stmpe_gpio)
		return -EINVAL;

	irq_set_chip_data(hwirq, stmpe_gpio);
	irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip,
				 handle_simple_irq);
	irq_set_nested_thread(hwirq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(hwirq, IRQF_VALID);
#else
	irq_set_noprobe(hwirq);
#endif

	return 0;
}

void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
{
#ifdef CONFIG_ARM
	set_irq_flags(virq, 0);
#endif
	irq_set_chip_and_handler(virq, NULL, NULL);
	irq_set_chip_data(virq, NULL);
}

static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
	.unmap = stmpe_gpio_irq_unmap,
	.map = stmpe_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
		struct device_node *np)
{
	int base = 0;

	if (!np)
		base = stmpe_gpio->irq_base;

	stmpe_gpio->domain = irq_domain_add_simple(np,
				stmpe_gpio->chip.ngpio, base,
				&stmpe_gpio_irq_simple_ops, stmpe_gpio);
	if (!stmpe_gpio->domain) {
		dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
		return -ENOSYS;
	}

	return 0;
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio_platform_data *pdata;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq = 0;

	pdata = stmpe->pdata->gpio;

	irq = platform_get_irq(pdev, 0);

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.dev = &pdev->dev;
#ifdef CONFIG_OF
	stmpe_gpio->chip.of_node = np;
#endif
	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;

	if (pdata)
		stmpe_gpio->norequest_mask = pdata->norequest_mask;
	else if (np)
		of_property_read_u32(np, "st,norequest-mask",
				&stmpe_gpio->norequest_mask);

	if (irq >= 0)
		stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	else
		dev_info(&pdev->dev,
			"device configured in no-irq mode; "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	if (irq >= 0) {
		ret = stmpe_gpio_irq_init(stmpe_gpio, np);
		if (ret)
			goto out_disable;

		ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
				IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_disable;
		}
	}

	ret = gpiochip_add(&stmpe_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata && pdata->setup)
		pdata->setup(stmpe, stmpe_gpio->chip.base);

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_freeirq:
	if (irq >= 0)
		free_irq(irq, stmpe_gpio);
out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static int stmpe_gpio_remove(struct platform_device *pdev)
{
	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata && pdata->remove)
		pdata->remove(stmpe, stmpe_gpio->chip.base);

	ret = gpiochip_remove(&stmpe_gpio->chip);
	if (ret < 0) {
		dev_err(stmpe_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);

	if (irq >= 0)
		free_irq(irq, stmpe_gpio);

	platform_set_drvdata(pdev, NULL);
	kfree(stmpe_gpio);

	return 0;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver.name	= "stmpe-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= stmpe_gpio_probe,
	.remove		= stmpe_gpio_remove,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);

static void __exit stmpe_gpio_exit(void)
{
	platform_driver_unregister(&stmpe_gpio_driver);
}
module_exit(stmpe_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("STMPExxxx GPIO driver");
MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
	12	#include <linux/gpio.h>
	13	#include <linux/irq.h>
fc13d5a5	14	#include <linux/irqdomain.h>
03f822f5	15	#include <linux/interrupt.h>
86605cfe	16	#include <linux/of.h>
03f822f5 RV	17	#include <linux/mfd/stmpe.h>
	18
	19	/*
	20	* These registers are modified under the irq bus lock and cached to avoid
	21	* unnecessary writes in bus_sync_unlock.
	22	*/
	23	enum { REG_RE, REG_FE, REG_IE };
	24
	25	#define CACHE_NR_REGS 3
	26	#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
	27
	28	struct stmpe_gpio {
	29	struct gpio_chip chip;
	30	struct stmpe *stmpe;
	31	struct device *dev;
	32	struct mutex irq_lock;
fc13d5a5	33	struct irq_domain *domain;
03f822f5 RV	34
03f822f5 RV	35	int irq_base;
b8e9cf0b	36	unsigned norequest_mask;
03f822f5 RV	37
	38	/* Caches of interrupt control registers for bus_lock */
	39	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	41	};
	42
	43	static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	44	{
	45	return container_of(chip, struct stmpe_gpio, chip);
	46	}
	47
	48	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	49	{
	50	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	51	struct stmpe *stmpe = stmpe_gpio->stmpe;
	52	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	53	u8 mask = 1 << (offset % 8);
	54	int ret;
	55
	56	ret = stmpe_reg_read(stmpe, reg);
	57	if (ret < 0)
	58	return ret;
	59
7535b8be	60	return !!(ret & mask);
03f822f5 RV	61	}
	62
	63	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	64	{
	65	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	66	struct stmpe *stmpe = stmpe_gpio->stmpe;
	67	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	68	u8 reg = stmpe->regs[which] - (offset / 8);
	69	u8 mask = 1 << (offset % 8);
	70
cccdceb9 VK	71	/*
	72	* Some variants have single register for gpio set/clear functionality.
	73	* For them we need to write 0 to clear and 1 to set.
	74	*/
	75	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	76	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	77	else
	78	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	79	}
	80
	81	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	82	unsigned offset, int val)
	83	{
	84	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	85	struct stmpe *stmpe = stmpe_gpio->stmpe;
	86	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	87	u8 mask = 1 << (offset % 8);
	88
	89	stmpe_gpio_set(chip, offset, val);
	90
	91	return stmpe_set_bits(stmpe, reg, mask, mask);
	92	}
	93
	94	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	95	unsigned offset)
	96	{
	97	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	98	struct stmpe *stmpe = stmpe_gpio->stmpe;
	99	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	100	u8 mask = 1 << (offset % 8);
	101
	102	return stmpe_set_bits(stmpe, reg, mask, 0);
	103	}
	104
	105	static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	106	{
	107	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	108
fc13d5a5	109	return irq_create_mapping(stmpe_gpio->domain, offset);
03f822f5 RV	110	}
	111
	112	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	113	{
	114	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	115	struct stmpe *stmpe = stmpe_gpio->stmpe;
	116
b8e9cf0b WS	117	if (stmpe_gpio->norequest_mask & (1 << offset))
	118	return -EINVAL;
	119
03f822f5 RV	120	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	121	}
	122
	123	static struct gpio_chip template_chip = {
	124	.label = "stmpe",
	125	.owner = THIS_MODULE,
	126	.direction_input = stmpe_gpio_direction_input,
	127	.get = stmpe_gpio_get,
	128	.direction_output = stmpe_gpio_direction_output,
	129	.set = stmpe_gpio_set,
	130	.to_irq = stmpe_gpio_to_irq,
	131	.request = stmpe_gpio_request,
	132	.can_sleep = 1,
	133	};
	134
2a866f39	135	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	136	{
2a866f39	137	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	138	int offset = d->hwirq;
03f822f5 RV	139	int regoffset = offset / 8;
	140	int mask = 1 << (offset % 8);
	141
	142	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	143	return -EINVAL;
	144
cccdceb9 VK	145	/* STMPE801 doesn't have RE and FE registers */
	146	if (stmpe_gpio->stmpe->partnum == STMPE801)
	147	return 0;
	148
03f822f5 RV	149	if (type == IRQ_TYPE_EDGE_RISING)
	150	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	151	else
	152	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	153
	154	if (type == IRQ_TYPE_EDGE_FALLING)
	155	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	156	else
	157	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	158
	159	return 0;
	160	}
	161
2a866f39	162	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	163	{
2a866f39	164	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	165
	166	mutex_lock(&stmpe_gpio->irq_lock);
	167	}
	168
2a866f39	169	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	170	{
2a866f39	171	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	172	struct stmpe *stmpe = stmpe_gpio->stmpe;
	173	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	174	static const u8 regmap[] = {
	175	[REG_RE] = STMPE_IDX_GPRER_LSB,
	176	[REG_FE] = STMPE_IDX_GPFER_LSB,
	177	[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	178	};
	179	int i, j;
	180
	181	for (i = 0; i < CACHE_NR_REGS; i++) {
cccdceb9 VK	182	/* STMPE801 doesn't have RE and FE registers */
	183	if ((stmpe->partnum == STMPE801) &&
	184	(i != REG_IE))
	185	continue;
	186
03f822f5 RV	187	for (j = 0; j < num_banks; j++) {
	188	u8 old = stmpe_gpio->oldregs[i][j];
	189	u8 new = stmpe_gpio->regs[i][j];
	190
	191	if (new == old)
	192	continue;
	193
	194	stmpe_gpio->oldregs[i][j] = new;
	195	stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
	196	}
	197	}
	198
	199	mutex_unlock(&stmpe_gpio->irq_lock);
	200	}
	201
2a866f39	202	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	203	{
2a866f39	204	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	205	int offset = d->hwirq;
03f822f5 RV	206	int regoffset = offset / 8;
	207	int mask = 1 << (offset % 8);
	208
	209	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	210	}
	211
2a866f39	212	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	213	{
2a866f39	214	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	215	int offset = d->hwirq;
03f822f5 RV	216	int regoffset = offset / 8;
	217	int mask = 1 << (offset % 8);
	218
	219	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	220	}
	221
	222	static struct irq_chip stmpe_gpio_irq_chip = {
	223	.name = "stmpe-gpio",
2a866f39 LB	224	.irq_bus_lock = stmpe_gpio_irq_lock,
	225	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	226	.irq_mask = stmpe_gpio_irq_mask,
	227	.irq_unmask = stmpe_gpio_irq_unmask,
	228	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	229	};
	230
	231	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	232	{
	233	struct stmpe_gpio *stmpe_gpio = dev;
	234	struct stmpe *stmpe = stmpe_gpio->stmpe;
	235	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	236	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	237	u8 status[num_banks];
	238	int ret;
	239	int i;
	240
	241	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	242	if (ret < 0)
	243	return IRQ_NONE;
	244
	245	for (i = 0; i < num_banks; i++) {
	246	int bank = num_banks - i - 1;
	247	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	248	unsigned int stat = status[i];
	249
	250	stat &= enabled;
	251	if (!stat)
	252	continue;
	253
	254	while (stat) {
	255	int bit = __ffs(stat);
	256	int line = bank * 8 + bit;
fc13d5a5	257	int virq = irq_find_mapping(stmpe_gpio->domain, line);
03f822f5	258
fc13d5a5	259	handle_nested_irq(virq);
03f822f5 RV	260	stat &= ~(1 << bit);
	261	}
	262
	263	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
cccdceb9 VK	264
	265	/* Edge detect register is not present on 801 */
	266	if (stmpe->partnum != STMPE801)
	267	stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
	268	+ i, status[i]);
03f822f5 RV	269	}
	270
	271	return IRQ_HANDLED;
	272	}
	273
fc13d5a5 LJ	274	int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int virq,
fc13d5a5 LJ	275	irq_hw_number_t hwirq)
03f822f5	276	{
fc13d5a5 LJ	277	struct stmpe_gpio *stmpe_gpio = d->host_data;
	278
	279	if (!stmpe_gpio)
	280	return -EINVAL;
03f822f5	281
fc13d5a5 LJ	282	irq_set_chip_data(hwirq, stmpe_gpio);
	283	irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip,
	284	handle_simple_irq);
	285	irq_set_nested_thread(hwirq, 1);
03f822f5	286	#ifdef CONFIG_ARM
fc13d5a5	287	set_irq_flags(hwirq, IRQF_VALID);
03f822f5	288	#else
fc13d5a5	289	irq_set_noprobe(hwirq);
03f822f5	290	#endif
03f822f5 RV	291
	292	return 0;
	293	}
	294
fc13d5a5	295	void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
03f822f5	296	{
03f822f5	297	#ifdef CONFIG_ARM
fc13d5a5	298	set_irq_flags(virq, 0);
03f822f5	299	#endif
fc13d5a5 LJ	300	irq_set_chip_and_handler(virq, NULL, NULL);
	301	irq_set_chip_data(virq, NULL);
	302	}
	303
	304	static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
	305	.unmap = stmpe_gpio_irq_unmap,
	306	.map = stmpe_gpio_irq_map,
	307	.xlate = irq_domain_xlate_twocell,
	308	};
	309
9afd9b70 GF	310	static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
9afd9b70 GF	311	struct device_node *np)
fc13d5a5	312	{
9afd9b70	313	int base = 0;
fc13d5a5	314
9afd9b70 GF	315	if (!np)
	316	base = stmpe_gpio->irq_base;
	317
	318	stmpe_gpio->domain = irq_domain_add_simple(np,
fc13d5a5 LJ	319	stmpe_gpio->chip.ngpio, base,
	320	&stmpe_gpio_irq_simple_ops, stmpe_gpio);
	321	if (!stmpe_gpio->domain) {
	322	dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
	323	return -ENOSYS;
03f822f5	324	}
fc13d5a5 LJ	325
fc13d5a5 LJ	326	return 0;
03f822f5 RV	327	}
03f822f5 RV	328
3836309d	329	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	330	{
03f822f5 RV	331	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	332	struct device_node *np = pdev->dev.of_node;
03f822f5 RV	333	struct stmpe_gpio_platform_data *pdata;
	334	struct stmpe_gpio *stmpe_gpio;
	335	int ret;
38040c85	336	int irq = 0;
03f822f5 RV	337
03f822f5 RV	338	pdata = stmpe->pdata->gpio;
03f822f5 RV	339
03f822f5 RV	340	irq = platform_get_irq(pdev, 0);
03f822f5 RV	341
	342	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	343	if (!stmpe_gpio)
	344	return -ENOMEM;
	345
	346	mutex_init(&stmpe_gpio->irq_lock);
	347
	348	stmpe_gpio->dev = &pdev->dev;
	349	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	350	stmpe_gpio->chip = template_chip;
	351	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	352	stmpe_gpio->chip.dev = &pdev->dev;
9afd9b70 GF	353	#ifdef CONFIG_OF
	354	stmpe_gpio->chip.of_node = np;
	355	#endif
03f822f5 RV	356	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
03f822f5 RV	357
86605cfe VKS	358	if (pdata)
	359	stmpe_gpio->norequest_mask = pdata->norequest_mask;
	360	else if (np)
	361	of_property_read_u32(np, "st,norequest-mask",
	362	&stmpe_gpio->norequest_mask);
	363
38040c85 CB	364	if (irq >= 0)
	365	stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	366	else
	367	dev_info(&pdev->dev,
	368	"device configured in no-irq mode; "
	369	"irqs are not available\n");
03f822f5 RV	370
	371	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	372	if (ret)
02bf0749	373	goto out_free;
03f822f5	374
38040c85	375	if (irq >= 0) {
9afd9b70	376	ret = stmpe_gpio_irq_init(stmpe_gpio, np);
38040c85 CB	377	if (ret)
38040c85 CB	378	goto out_disable;
03f822f5	379
38040c85 CB	380	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
	381	IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
	382	if (ret) {
	383	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
fc13d5a5	384	goto out_disable;
38040c85	385	}
03f822f5 RV	386	}
	387
	388	ret = gpiochip_add(&stmpe_gpio->chip);
	389	if (ret) {
	390	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	391	goto out_freeirq;
	392	}
	393
	394	if (pdata && pdata->setup)
	395	pdata->setup(stmpe, stmpe_gpio->chip.base);
	396
	397	platform_set_drvdata(pdev, stmpe_gpio);
	398
	399	return 0;
	400
	401	out_freeirq:
38040c85 CB	402	if (irq >= 0)
38040c85 CB	403	free_irq(irq, stmpe_gpio);
02bf0749 VK	404	out_disable:
02bf0749 VK	405	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
03f822f5 RV	406	out_free:
	407	kfree(stmpe_gpio);
	408	return ret;
	409	}
	410
206210ce	411	static int stmpe_gpio_remove(struct platform_device *pdev)
03f822f5 RV	412	{
	413	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	414	struct stmpe *stmpe = stmpe_gpio->stmpe;
	415	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	416	int irq = platform_get_irq(pdev, 0);
	417	int ret;
	418
	419	if (pdata && pdata->remove)
	420	pdata->remove(stmpe, stmpe_gpio->chip.base);
	421
	422	ret = gpiochip_remove(&stmpe_gpio->chip);
	423	if (ret < 0) {
	424	dev_err(stmpe_gpio->dev,
	425	"unable to remove gpiochip: %d\n", ret);
	426	return ret;
	427	}
	428
	429	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	430
fc13d5a5	431	if (irq >= 0)
38040c85	432	free_irq(irq, stmpe_gpio);
fc13d5a5	433
03f822f5 RV	434	platform_set_drvdata(pdev, NULL);
	435	kfree(stmpe_gpio);
	436
	437	return 0;
	438	}
	439
	440	static struct platform_driver stmpe_gpio_driver = {
	441	.driver.name = "stmpe-gpio",
	442	.driver.owner = THIS_MODULE,
	443	.probe = stmpe_gpio_probe,
8283c4ff	444	.remove = stmpe_gpio_remove,
03f822f5 RV	445	};
	446
	447	static int __init stmpe_gpio_init(void)
	448	{
	449	return platform_driver_register(&stmpe_gpio_driver);
	450	}
	451	subsys_initcall(stmpe_gpio_init);
	452
	453	static void __exit stmpe_gpio_exit(void)
	454	{
	455	platform_driver_unregister(&stmpe_gpio_driver);
	456	}
	457	module_exit(stmpe_gpio_exit);
	458
	459	MODULE_LICENSE("GPL v2");
	460	MODULE_DESCRIPTION("STMPExxxx GPIO driver");
	461	MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");