[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-spear-spics.c

/*
 * SPEAr platform SPI chipselect abstraction over gpiolib
 *
 * Copyright (C) 2012 ST Microelectronics
 * Shiraz Hashim <shiraz.hashim@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/types.h>

/* maximum chipselects */
#define NUM_OF_GPIO	4

/*
 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
 * through system registers. This register lies outside spi (pl022)
 * address space into system registers.
 *
 * It provides control for spi chip select lines so that any chipselect
 * (out of 4 possible chipselects in pl022) can be made low to select
 * the particular slave.
 */

/**
 * struct spear_spics - represents spi chip select control
 * @base: base address
 * @perip_cfg: configuration register
 * @sw_enable_bit: bit to enable s/w control over chipselects
 * @cs_value_bit: bit to program high or low chipselect
 * @cs_enable_mask: mask to select bits required to select chipselect
 * @cs_enable_shift: bit pos of cs_enable_mask
 * @use_count: use count of a spi controller cs lines
 * @last_off: stores last offset caller of set_value()
 * @chip: gpio_chip abstraction
 */
struct spear_spics {
	void __iomem		*base;
	u32			perip_cfg;
	u32			sw_enable_bit;
	u32			cs_value_bit;
	u32			cs_enable_mask;
	u32			cs_enable_shift;
	unsigned long		use_count;
	int			last_off;
	struct gpio_chip	chip;
};

/* gpio framework specific routines */
static int spics_get_value(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
{
	struct spear_spics *spics = container_of(chip, struct spear_spics,
			chip);
	u32 tmp;

	/* select chip select from register */
	tmp = readl_relaxed(spics->base + spics->perip_cfg);
	if (spics->last_off != offset) {
		spics->last_off = offset;
		tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
		tmp |= offset << spics->cs_enable_shift;
	}

	/* toggle chip select line */
	tmp &= ~(0x1 << spics->cs_value_bit);
	tmp |= value << spics->cs_value_bit;
	writel_relaxed(tmp, spics->base + spics->perip_cfg);
}

static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
		int value)
{
	spics_set_value(chip, offset, value);
	return 0;
}

static int spics_request(struct gpio_chip *chip, unsigned offset)
{
	struct spear_spics *spics = container_of(chip, struct spear_spics,
			chip);
	u32 tmp;

	if (!spics->use_count++) {
		tmp = readl_relaxed(spics->base + spics->perip_cfg);
		tmp |= 0x1 << spics->sw_enable_bit;
		tmp |= 0x1 << spics->cs_value_bit;
		writel_relaxed(tmp, spics->base + spics->perip_cfg);
	}

	return 0;
}

static void spics_free(struct gpio_chip *chip, unsigned offset)
{
	struct spear_spics *spics = container_of(chip, struct spear_spics,
			chip);
	u32 tmp;

	if (!--spics->use_count) {
		tmp = readl_relaxed(spics->base + spics->perip_cfg);
		tmp &= ~(0x1 << spics->sw_enable_bit);
		writel_relaxed(tmp, spics->base + spics->perip_cfg);
	}
}

static int spics_gpio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spear_spics *spics;
	struct resource *res;
	int ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
		return -EBUSY;
	}

	spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
	if (!spics) {
		dev_err(&pdev->dev, "memory allocation fail\n");
		return -ENOMEM;
	}

	spics->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(spics->base))
		return PTR_ERR(spics->base);

	if (of_property_read_u32(np, "st-spics,peripcfg-reg",
				&spics->perip_cfg))
		goto err_dt_data;
	if (of_property_read_u32(np, "st-spics,sw-enable-bit",
				&spics->sw_enable_bit))
		goto err_dt_data;
	if (of_property_read_u32(np, "st-spics,cs-value-bit",
				&spics->cs_value_bit))
		goto err_dt_data;
	if (of_property_read_u32(np, "st-spics,cs-enable-mask",
				&spics->cs_enable_mask))
		goto err_dt_data;
	if (of_property_read_u32(np, "st-spics,cs-enable-shift",
				&spics->cs_enable_shift))
		goto err_dt_data;

	platform_set_drvdata(pdev, spics);

	spics->chip.ngpio = NUM_OF_GPIO;
	spics->chip.base = -1;
	spics->chip.request = spics_request;
	spics->chip.free = spics_free;
	spics->chip.direction_input = spics_direction_input;
	spics->chip.direction_output = spics_direction_output;
	spics->chip.get = spics_get_value;
	spics->chip.set = spics_set_value;
	spics->chip.label = dev_name(&pdev->dev);
	spics->chip.dev = &pdev->dev;
	spics->chip.owner = THIS_MODULE;
	spics->last_off = -1;

	ret = gpiochip_add(&spics->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpio chip\n");
		return ret;
	}

	dev_info(&pdev->dev, "spear spics registered\n");
	return 0;

err_dt_data:
	dev_err(&pdev->dev, "DT probe failed\n");
	return -EINVAL;
}

static const struct of_device_id spics_gpio_of_match[] = {
	{ .compatible = "st,spear-spics-gpio" },
	{}
};
MODULE_DEVICE_TABLE(of, spics_gpio_of_match);

static struct platform_driver spics_gpio_driver = {
	.probe = spics_gpio_probe,
	.driver = {
		.owner = THIS_MODULE,
		.name = "spear-spics-gpio",
		.of_match_table = spics_gpio_of_match,
	},
};

static int __init spics_gpio_init(void)
{
	return platform_driver_register(&spics_gpio_driver);
}
subsys_initcall(spics_gpio_init);

MODULE_AUTHOR("Shiraz Hashim <shiraz.hashim@st.com>");
MODULE_DESCRIPTION("ST Microlectronics SPEAr SPI Chip Select Abstraction");
MODULE_LICENSE("GPL");
Commit	Line	Data
b53bc281 SH	1	/*
	2	* SPEAr platform SPI chipselect abstraction over gpiolib
	3	*
	4	* Copyright (C) 2012 ST Microelectronics
	5	* Shiraz Hashim <shiraz.hashim@st.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
	12	#include <linux/err.h>
	13	#include <linux/gpio.h>
	14	#include <linux/io.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/types.h>
	19
	20	/* maximum chipselects */
	21	#define NUM_OF_GPIO 4
	22
	23	/*
	24	* Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
	25	* through system registers. This register lies outside spi (pl022)
	26	* address space into system registers.
	27	*
	28	* It provides control for spi chip select lines so that any chipselect
	29	* (out of 4 possible chipselects in pl022) can be made low to select
	30	* the particular slave.
	31	*/
	32
	33	/**
	34	* struct spear_spics - represents spi chip select control
	35	* @base: base address
	36	* @perip_cfg: configuration register
	37	* @sw_enable_bit: bit to enable s/w control over chipselects
	38	* @cs_value_bit: bit to program high or low chipselect
	39	* @cs_enable_mask: mask to select bits required to select chipselect
	40	* @cs_enable_shift: bit pos of cs_enable_mask
	41	* @use_count: use count of a spi controller cs lines
	42	* @last_off: stores last offset caller of set_value()
	43	* @chip: gpio_chip abstraction
	44	*/
	45	struct spear_spics {
	46	void __iomem *base;
	47	u32 perip_cfg;
	48	u32 sw_enable_bit;
	49	u32 cs_value_bit;
	50	u32 cs_enable_mask;
	51	u32 cs_enable_shift;
	52	unsigned long use_count;
	53	int last_off;
	54	struct gpio_chip chip;
	55	};
	56
	57	/* gpio framework specific routines */
	58	static int spics_get_value(struct gpio_chip *chip, unsigned offset)
	59	{
	60	return -ENXIO;
	61	}
	62
	63	static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
	64	{
65	struct spear_spics *spics = container_of(chip, struct spear_spics,
66	chip);
67	u32 tmp;
68
69	/* select chip select from register */
70	tmp = readl_relaxed(spics->base + spics->perip_cfg);
71	if (spics->last_off != offset) {
72	spics->last_off = offset;
73	tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
74	tmp \|= offset << spics->cs_enable_shift;
75	}
76
77	/* toggle chip select line */
78	tmp &= ~(0x1 << spics->cs_value_bit);
79	tmp \|= value << spics->cs_value_bit;
80	writel_relaxed(tmp, spics->base + spics->perip_cfg);
81	}
82
83	static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
84	{
85	return -ENXIO;
86	}
87
88	static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
89	int value)
90	{
91	spics_set_value(chip, offset, value);
92	return 0;
93	}
94
95	static int spics_request(struct gpio_chip *chip, unsigned offset)
96	{
97	struct spear_spics *spics = container_of(chip, struct spear_spics,
98	chip);
99	u32 tmp;
100
101	if (!spics->use_count++) {
102	tmp = readl_relaxed(spics->base + spics->perip_cfg);
103	tmp \|= 0x1 << spics->sw_enable_bit;
104	tmp \|= 0x1 << spics->cs_value_bit;
105	writel_relaxed(tmp, spics->base + spics->perip_cfg);
106	}
107
108	return 0;
109	}
110
111	static void spics_free(struct gpio_chip *chip, unsigned offset)
112	{
113	struct spear_spics *spics = container_of(chip, struct spear_spics,
114	chip);
115	u32 tmp;
116
117	if (!--spics->use_count) {
118	tmp = readl_relaxed(spics->base + spics->perip_cfg);
119	tmp &= ~(0x1 << spics->sw_enable_bit);
120	writel_relaxed(tmp, spics->base + spics->perip_cfg);
121	}
122	}
123
124	static int spics_gpio_probe(struct platform_device *pdev)
125	{
126	struct device_node *np = pdev->dev.of_node;
127	struct spear_spics *spics;
128	struct resource *res;
129	int ret;
130
131	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
132	if (!res) {
133	dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
134	return -EBUSY;
135	}
136
137	spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
138	if (!spics) {
139	dev_err(&pdev->dev, "memory allocation fail\n");
140	return -ENOMEM;
141	}
142
641d0342 TR	143	spics->base = devm_ioremap_resource(&pdev->dev, res);
	144	if (IS_ERR(spics->base))
	145	return PTR_ERR(spics->base);
b53bc281 SH	146
	147	if (of_property_read_u32(np, "st-spics,peripcfg-reg",
	148	&spics->perip_cfg))
	149	goto err_dt_data;
	150	if (of_property_read_u32(np, "st-spics,sw-enable-bit",
	151	&spics->sw_enable_bit))
	152	goto err_dt_data;
	153	if (of_property_read_u32(np, "st-spics,cs-value-bit",
	154	&spics->cs_value_bit))
	155	goto err_dt_data;
	156	if (of_property_read_u32(np, "st-spics,cs-enable-mask",
	157	&spics->cs_enable_mask))
	158	goto err_dt_data;
	159	if (of_property_read_u32(np, "st-spics,cs-enable-shift",
	160	&spics->cs_enable_shift))
	161	goto err_dt_data;
	162
	163	platform_set_drvdata(pdev, spics);
	164
	165	spics->chip.ngpio = NUM_OF_GPIO;
	166	spics->chip.base = -1;
	167	spics->chip.request = spics_request;
	168	spics->chip.free = spics_free;
	169	spics->chip.direction_input = spics_direction_input;
	170	spics->chip.direction_output = spics_direction_output;
	171	spics->chip.get = spics_get_value;
	172	spics->chip.set = spics_set_value;
	173	spics->chip.label = dev_name(&pdev->dev);
	174	spics->chip.dev = &pdev->dev;
	175	spics->chip.owner = THIS_MODULE;
	176	spics->last_off = -1;
	177
	178	ret = gpiochip_add(&spics->chip);
	179	if (ret) {
	180	dev_err(&pdev->dev, "unable to add gpio chip\n");
	181	return ret;
	182	}
	183
	184	dev_info(&pdev->dev, "spear spics registered\n");
	185	return 0;
	186
	187	err_dt_data:
	188	dev_err(&pdev->dev, "DT probe failed\n");
	189	return -EINVAL;
	190	}
	191
	192	static const struct of_device_id spics_gpio_of_match[] = {
	193	{ .compatible = "st,spear-spics-gpio" },
	194	{}
	195	};
	196	MODULE_DEVICE_TABLE(of, spics_gpio_of_match);
	197
	198	static struct platform_driver spics_gpio_driver = {
	199	.probe = spics_gpio_probe,
	200	.driver = {
	201	.owner = THIS_MODULE,
	202	.name = "spear-spics-gpio",
	203	.of_match_table = spics_gpio_of_match,
	204	},
	205	};
	206
	207	static int __init spics_gpio_init(void)
	208	{
	209	return platform_driver_register(&spics_gpio_driver);
210	}
211	subsys_initcall(spics_gpio_init);
212
213	MODULE_AUTHOR("Shiraz Hashim <shiraz.hashim@st.com>");
214	MODULE_DESCRIPTION("ST Microlectronics SPEAr SPI Chip Select Abstraction");
215	MODULE_LICENSE("GPL");