[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061_gpio {
	spinlock_t		lock;

	void __iomem		*base;
	struct irq_domain	*domain;
	struct gpio_chip	gc;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	/*
	 * Map back to global GPIO space and request muxing, the direction
	 * parameter does not matter for this controller.
	 */
	int gpio = chip->base + offset;

	return pinctrl_request_gpio(gpio);
}

static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	pinctrl_free_gpio(gpio);
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir &= ~(1 << offset);
	writeb(gpiodir, chip->base + GPIODIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir |= 1 << offset;
	writeb(gpiodir, chip->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return !!readb(chip->base + (1 << (offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
}

static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return irq_create_mapping(chip->domain, offset);
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readb(chip->base + GPIOIEV);

	gpiois = readb(chip->base + GPIOIS);
	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= 1 << offset;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= 1 << offset;
		else
			gpioiev &= ~(1 << offset);
	} else
		gpiois &= ~(1 << offset);
	writeb(gpiois, chip->base + GPIOIS);

	gpioibe = readb(chip->base + GPIOIBE);
	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		gpioibe |= 1 << offset;
	else {
		gpioibe &= ~(1 << offset);
		if (trigger & IRQ_TYPE_EDGE_RISING)
			gpioiev |= 1 << offset;
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
			gpioiev &= ~(1 << offset);
	}
	writeb(gpioibe, chip->base + GPIOIBE);

	writeb(gpioiev, chip->base + GPIOIEV);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(chip->base + GPIOMIS);
	writeb(pending, chip->base + GPIOIC);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(pl061_to_irq(&chip->gc, offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) & ~mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) | mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static struct irq_chip pl061_irqchip = {
	.name		= "pl061 gpio",
	.irq_mask	= pl061_irq_mask,
	.irq_unmask	= pl061_irq_unmask,
	.irq_set_type	= pl061_irq_type,
};

static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
			 irq_hw_number_t hw)
{
	struct pl061_gpio *chip = d->host_data;

	irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
				      "pl061");
	irq_set_chip_data(virq, chip);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops pl061_domain_ops = {
	.map	= pl061_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061_platform_data *pdata = dev->platform_data;
	struct pl061_gpio *chip;
	int ret, irq, i, irq_base;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	if (pdata) {
		chip->gc.base = pdata->gpio_base;
		irq_base = pdata->irq_base;
		if (irq_base <= 0)
			return -ENODEV;
	} else {
		chip->gc.base = -1;
		irq_base = 0;
	}

	if (!devm_request_mem_region(dev, adev->res.start,
				     resource_size(&adev->res), "pl061"))
		return -EBUSY;

	chip->base = devm_ioremap(dev, adev->res.start,
				  resource_size(&adev->res));
	if (!chip->base)
		return -ENOMEM;

	spin_lock_init(&chip->lock);

	chip->gc.request = pl061_gpio_request;
	chip->gc.free = pl061_gpio_free;
	chip->gc.direction_input = pl061_direction_input;
	chip->gc.direction_output = pl061_direction_output;
	chip->gc.get = pl061_get_value;
	chip->gc.set = pl061_set_value;
	chip->gc.to_irq = pl061_to_irq;
	chip->gc.ngpio = PL061_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.dev = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add(&chip->gc);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writeb(0, chip->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0)
		return -ENODEV;

	irq_set_chained_handler(irq, pl061_irq_handler);
	irq_set_handler_data(irq, chip);

	chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
					     irq_base, &pl061_domain_ops, chip);
	if (!chip->domain)
		return -ENODEV;

	for (i = 0; i < PL061_GPIO_NR; i++) {
		if (pdata) {
			if (pdata->directions & (1 << i))
				pl061_direction_output(&chip->gc, i,
						pdata->values & (1 << i));
			else
				pl061_direction_input(&chip->gc, i);
		}
	}

	amba_set_drvdata(adev, chip);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	chip->csave_regs.gpio_data = 0;
	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (1 << offset))
			chip->csave_regs.gpio_data |=
				pl061_get_value(&chip->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (1 << offset))
			pl061_direction_output(&chip->gc, offset,
					chip->csave_regs.gpio_data &
					(1 << offset));
		else
			pl061_direction_input(&chip->gc, offset);
	}

	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

MODULE_DEVICE_TABLE(amba, pl061_ids);

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
module_init(pl061_gpio_init);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("PL061 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859 BS	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	9	*
	10	* Data sheet: ARM DDI 0190B, September 2000
	11	*/
	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/module.h>
1e9c2859 BS	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
f1f70479	18	#include <linux/irqdomain.h>
de88cbb7	19	#include <linux/irqchip/chained_irq.h>
1e9c2859 BS	20	#include <linux/bitops.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/gpio.h>
	23	#include <linux/device.h>
	24	#include <linux/amba/bus.h>
	25	#include <linux/amba/pl061.h>
5a0e3ad6	26	#include <linux/slab.h>
39b70ee0	27	#include <linux/pinctrl/consumer.h>
e198a8de	28	#include <linux/pm.h>
1e9c2859 BS	29
	30	#define GPIODIR 0x400
	31	#define GPIOIS 0x404
	32	#define GPIOIBE 0x408
	33	#define GPIOIEV 0x40C
	34	#define GPIOIE 0x410
	35	#define GPIORIS 0x414
	36	#define GPIOMIS 0x418
	37	#define GPIOIC 0x41C
	38
	39	#define PL061_GPIO_NR 8
	40
e198a8de DS	41	#ifdef CONFIG_PM
	42	struct pl061_context_save_regs {
	43	u8 gpio_data;
	44	u8 gpio_dir;
	45	u8 gpio_is;
	46	u8 gpio_ibe;
	47	u8 gpio_iev;
	48	u8 gpio_ie;
	49	};
	50	#endif
1e9c2859	51
1e9c2859	52	struct pl061_gpio {
835c192f	53	spinlock_t lock;
1e9c2859 BS	54
1e9c2859 BS	55	void __iomem *base;
f1f70479	56	struct irq_domain *domain;
1e9c2859	57	struct gpio_chip gc;
e198a8de DS	58
	59	#ifdef CONFIG_PM
	60	struct pl061_context_save_regs csave_regs;
	61	#endif
1e9c2859 BS	62	};
1e9c2859 BS	63
39b70ee0 HZ	64	static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
	65	{
	66	/*
	67	* Map back to global GPIO space and request muxing, the direction
	68	* parameter does not matter for this controller.
	69	*/
	70	int gpio = chip->base + offset;
	71
	72	return pinctrl_request_gpio(gpio);
	73	}
	74
22ce4464 AL	75	static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
	76	{
	77	int gpio = chip->base + offset;
	78
	79	pinctrl_free_gpio(gpio);
	80	}
	81
1e9c2859 BS	82	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
	83	{
	84	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	85	unsigned long flags;
	86	unsigned char gpiodir;
	87
	88	if (offset >= gc->ngpio)
	89	return -EINVAL;
	90
	91	spin_lock_irqsave(&chip->lock, flags);
	92	gpiodir = readb(chip->base + GPIODIR);
	93	gpiodir &= ~(1 << offset);
	94	writeb(gpiodir, chip->base + GPIODIR);
	95	spin_unlock_irqrestore(&chip->lock, flags);
	96
	97	return 0;
	98	}
	99
	100	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	101	int value)
	102	{
	103	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	104	unsigned long flags;
	105	unsigned char gpiodir;
	106
	107	if (offset >= gc->ngpio)
	108	return -EINVAL;
	109
	110	spin_lock_irqsave(&chip->lock, flags);
	111	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	112	gpiodir = readb(chip->base + GPIODIR);
	113	gpiodir \|= 1 << offset;
	114	writeb(gpiodir, chip->base + GPIODIR);
64b997c5 VK	115
	116	/*
	117	* gpio value is set again, because pl061 doesn't allow to set value of
	118	* a gpio pin before configuring it in OUT mode.
	119	*/
	120	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
1e9c2859 BS	121	spin_unlock_irqrestore(&chip->lock, flags);
	122
	123	return 0;
	124	}
	125
	126	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	127	{
	128	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	129
	130	return !!readb(chip->base + (1 << (offset + 2)));
	131	}
	132
	133	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	134	{
	135	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	136
	137	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	138	}
	139
50efacf6 BS	140	static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
	141	{
	142	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	143
f1f70479	144	return irq_create_mapping(chip->domain, offset);
50efacf6 BS	145	}
50efacf6 BS	146
b2221869	147	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	148	{
f1f70479 HZ	149	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
f1f70479 HZ	150	int offset = irqd_to_hwirq(d);
1e9c2859 BS	151	unsigned long flags;
	152	u8 gpiois, gpioibe, gpioiev;
	153
c1cc9b97	154	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	155	return -EINVAL;
1e9c2859 BS	156
f1f70479	157	spin_lock_irqsave(&chip->lock, flags);
1e9c2859 BS	158
	159	gpioiev = readb(chip->base + GPIOIEV);
	160
	161	gpiois = readb(chip->base + GPIOIS);
	162	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
	163	gpiois \|= 1 << offset;
	164	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	165	gpioiev \|= 1 << offset;
	166	else
	167	gpioiev &= ~(1 << offset);
	168	} else
	169	gpiois &= ~(1 << offset);
	170	writeb(gpiois, chip->base + GPIOIS);
	171
	172	gpioibe = readb(chip->base + GPIOIBE);
	173	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	174	gpioibe \|= 1 << offset;
	175	else {
	176	gpioibe &= ~(1 << offset);
	177	if (trigger & IRQ_TYPE_EDGE_RISING)
	178	gpioiev \|= 1 << offset;
db7e1bc4	179	else if (trigger & IRQ_TYPE_EDGE_FALLING)
1e9c2859 BS	180	gpioiev &= ~(1 << offset);
	181	}
	182	writeb(gpioibe, chip->base + GPIOIBE);
	183
	184	writeb(gpioiev, chip->base + GPIOIEV);
	185
f1f70479	186	spin_unlock_irqrestore(&chip->lock, flags);
1e9c2859 BS	187
	188	return 0;
	189	}
	190
1e9c2859 BS	191	static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
1e9c2859 BS	192	{
2de0dbc5 RH	193	unsigned long pending;
	194	int offset;
	195	struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
dece904d	196	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	197
dece904d	198	chained_irq_enter(irqchip, desc);
1e9c2859	199
2de0dbc5 RH	200	pending = readb(chip->base + GPIOMIS);
	201	writeb(pending, chip->base + GPIOIC);
	202	if (pending) {
984b3f57	203	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
50efacf6	204	generic_handle_irq(pl061_to_irq(&chip->gc, offset));
1e9c2859	205	}
2de0dbc5	206
dece904d	207	chained_irq_exit(irqchip, desc);
1e9c2859 BS	208	}
1e9c2859 BS	209
f1f70479	210	static void pl061_irq_mask(struct irq_data *d)
3ab52475	211	{
f1f70479 HZ	212	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	213	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	214	u8 gpioie;
	215
	216	spin_lock(&chip->lock);
	217	gpioie = readb(chip->base + GPIOIE) & ~mask;
	218	writeb(gpioie, chip->base + GPIOIE);
	219	spin_unlock(&chip->lock);
	220	}
3ab52475	221
f1f70479 HZ	222	static void pl061_irq_unmask(struct irq_data *d)
	223	{
	224	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	225	u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
	226	u8 gpioie;
	227
	228	spin_lock(&chip->lock);
	229	gpioie = readb(chip->base + GPIOIE) \| mask;
	230	writeb(gpioie, chip->base + GPIOIE);
	231	spin_unlock(&chip->lock);
	232	}
	233
	234	static struct irq_chip pl061_irqchip = {
	235	.name = "pl061 gpio",
	236	.irq_mask = pl061_irq_mask,
	237	.irq_unmask = pl061_irq_unmask,
	238	.irq_set_type = pl061_irq_type,
	239	};
	240
	241	static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
	242	irq_hw_number_t hw)
	243	{
	244	struct pl061_gpio *chip = d->host_data;
3ab52475	245
f1f70479 HZ	246	irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
	247	"pl061");
	248	irq_set_chip_data(virq, chip);
	249	irq_set_irq_type(virq, IRQ_TYPE_NONE);
3ab52475	250
f1f70479	251	return 0;
1e9c2859 BS	252	}
1e9c2859 BS	253
f1f70479 HZ	254	static const struct irq_domain_ops pl061_domain_ops = {
	255	.map = pl061_irq_map,
	256	.xlate = irq_domain_xlate_twocell,
	257	};
	258
8944df72	259	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	260	{
8944df72 TK	261	struct device *dev = &adev->dev;
8944df72 TK	262	struct pl061_platform_data *pdata = dev->platform_data;
1e9c2859	263	struct pl061_gpio *chip;
f1f70479	264	int ret, irq, i, irq_base;
1e9c2859	265
8944df72	266	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1e9c2859 BS	267	if (chip == NULL)
	268	return -ENOMEM;
	269
76c05c8a RH	270	if (pdata) {
76c05c8a RH	271	chip->gc.base = pdata->gpio_base;
f1f70479 HZ	272	irq_base = pdata->irq_base;
	273	if (irq_base <= 0)
	274	return -ENODEV;
	275	} else {
76c05c8a	276	chip->gc.base = -1;
f1f70479 HZ	277	irq_base = 0;
f1f70479 HZ	278	}
76c05c8a	279
8944df72	280	if (!devm_request_mem_region(dev, adev->res.start,
f1f70479	281	resource_size(&adev->res), "pl061"))
8944df72	282	return -EBUSY;
1e9c2859	283
8944df72	284	chip->base = devm_ioremap(dev, adev->res.start,
f1f70479 HZ	285	resource_size(&adev->res));
f1f70479 HZ	286	if (!chip->base)
8944df72	287	return -ENOMEM;
1e9c2859 BS	288
1e9c2859 BS	289	spin_lock_init(&chip->lock);
1e9c2859	290
39b70ee0	291	chip->gc.request = pl061_gpio_request;
22ce4464	292	chip->gc.free = pl061_gpio_free;
1e9c2859 BS	293	chip->gc.direction_input = pl061_direction_input;
	294	chip->gc.direction_output = pl061_direction_output;
	295	chip->gc.get = pl061_get_value;
	296	chip->gc.set = pl061_set_value;
50efacf6	297	chip->gc.to_irq = pl061_to_irq;
1e9c2859	298	chip->gc.ngpio = PL061_GPIO_NR;
8944df72 TK	299	chip->gc.label = dev_name(dev);
8944df72 TK	300	chip->gc.dev = dev;
1e9c2859 BS	301	chip->gc.owner = THIS_MODULE;
1e9c2859 BS	302
1e9c2859 BS	303	ret = gpiochip_add(&chip->gc);
1e9c2859 BS	304	if (ret)
8944df72	305	return ret;
1e9c2859 BS	306
	307	/*
	308	* irq_chip support
	309	*/
1e9c2859	310	writeb(0, chip->base + GPIOIE); /* disable irqs */
8944df72 TK	311	irq = adev->irq[0];
	312	if (irq < 0)
	313	return -ENODEV;
	314
b51804bc	315	irq_set_chained_handler(irq, pl061_irq_handler);
2de0dbc5	316	irq_set_handler_data(irq, chip);
1e9c2859	317
52915b49 LW	318	chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
	319	irq_base, &pl061_domain_ops, chip);
	320	if (!chip->domain)
	321	return -ENODEV;
	322
1e9c2859	323	for (i = 0; i < PL061_GPIO_NR; i++) {
76c05c8a RH	324	if (pdata) {
	325	if (pdata->directions & (1 << i))
	326	pl061_direction_output(&chip->gc, i,
	327	pdata->values & (1 << i));
	328	else
	329	pl061_direction_input(&chip->gc, i);
	330	}
1e9c2859 BS	331	}
1e9c2859 BS	332
8944df72	333	amba_set_drvdata(adev, chip);
e198a8de	334
1e9c2859	335	return 0;
1e9c2859 BS	336	}
1e9c2859 BS	337
e198a8de DS	338	#ifdef CONFIG_PM
	339	static int pl061_suspend(struct device *dev)
	340	{
	341	struct pl061_gpio *chip = dev_get_drvdata(dev);
	342	int offset;
	343
	344	chip->csave_regs.gpio_data = 0;
	345	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	346	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	347	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	348	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	349	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
	350
	351	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
	352	if (chip->csave_regs.gpio_dir & (1 << offset))
	353	chip->csave_regs.gpio_data \|=
	354	pl061_get_value(&chip->gc, offset) << offset;
	355	}
	356
	357	return 0;
	358	}
	359
	360	static int pl061_resume(struct device *dev)
	361	{
	362	struct pl061_gpio *chip = dev_get_drvdata(dev);
	363	int offset;
	364
	365	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
	366	if (chip->csave_regs.gpio_dir & (1 << offset))
	367	pl061_direction_output(&chip->gc, offset,
	368	chip->csave_regs.gpio_data &
	369	(1 << offset));
	370	else
	371	pl061_direction_input(&chip->gc, offset);
	372	}
	373
	374	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	375	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	376	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	377	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
	378
	379	return 0;
	380	}
	381
6e33aced VK	382	static const struct dev_pm_ops pl061_dev_pm_ops = {
	383	.suspend = pl061_suspend,
	384	.resume = pl061_resume,
	385	.freeze = pl061_suspend,
	386	.restore = pl061_resume,
	387	};
e198a8de DS	388	#endif
e198a8de DS	389
2c39c9e1	390	static struct amba_id pl061_ids[] = {
1e9c2859 BS	391	{
	392	.id = 0x00041061,
	393	.mask = 0x000fffff,
	394	},
	395	{ 0, 0 },
	396	};
	397
955b678c DM	398	MODULE_DEVICE_TABLE(amba, pl061_ids);
955b678c DM	399
1e9c2859 BS	400	static struct amba_driver pl061_gpio_driver = {
	401	.drv = {
	402	.name = "pl061_gpio",
e198a8de DS	403	#ifdef CONFIG_PM
	404	.pm = &pl061_dev_pm_ops,
	405	#endif
1e9c2859 BS	406	},
	407	.id_table = pl061_ids,
	408	.probe = pl061_probe,
	409	};
	410
	411	static int __init pl061_gpio_init(void)
	412	{
	413	return amba_driver_register(&pl061_gpio_driver);
	414	}
5985d76c	415	module_init(pl061_gpio_init);
1e9c2859 BS	416
	417	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	418	MODULE_DESCRIPTION("PL061 GPIO driver");
	419	MODULE_LICENSE("GPL");