[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-mxs.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <mach/mxs.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(n)		((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
#define PINCTRL_DIN(n)		((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
#define PINCTRL_DOE(n)		((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
#define PINCTRL_PIN2IRQ(n)	((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
#define PINCTRL_IRQEN(n)	((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
#define PINCTRL_IRQLEV(n)	((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
#define PINCTRL_IRQPOL(n)	((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
#define PINCTRL_IRQSTAT(n)	((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	int irq_high;
	int virtual_irq_start;
	struct gpio_chip chip;
};

/* Note: This driver assumes 32 GPIOs are handled in one register */

static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
{
	writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
}

static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
				int enable)
{
	if (enable) {
		writel(1 << index,
			port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
		writel(1 << index,
			port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
	} else {
		writel(1 << index,
			port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
	}
}

static void mxs_gpio_ack_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	clear_gpio_irqstatus(port, gpio & 0x1f);
}

static void mxs_gpio_mask_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	set_gpio_irqenable(port, gpio & 0x1f, 0);
}

static void mxs_gpio_unmask_irq(struct irq_data *d)
{
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	u32 gpio = irq_to_gpio(d->irq);
	set_gpio_irqenable(port, gpio & 0x1f, 1);
}

static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 pin_mask = 1 << (gpio & 31);
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
	void __iomem *pin_addr;
	int edge;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
	if (edge & GPIO_INT_LEV_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	clear_gpio_irqstatus(port, gpio & 0x1f);

	return 0;
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_get_handler_data(irq);
	u32 gpio_irq_no_base = port->virtual_irq_start;

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
			readl(port->base + PINCTRL_IRQEN(port->id));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		generic_handle_irq(gpio_irq_no_base + irqoffset);
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	u32 gpio = irq_to_gpio(d->irq);
	u32 gpio_idx = gpio & 0x1f;
	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);

	if (enable) {
		if (port->irq_high && (gpio_idx >= 16))
			enable_irq_wake(port->irq_high);
		else
			enable_irq_wake(port->irq);
	} else {
		if (port->irq_high && (gpio_idx >= 16))
			disable_irq_wake(port->irq_high);
		else
			disable_irq_wake(port->irq);
	}

	return 0;
}

static struct irq_chip gpio_irq_chip = {
	.name = "mxs gpio",
	.irq_ack = mxs_gpio_ack_irq,
	.irq_mask = mxs_gpio_mask_irq,
	.irq_unmask = mxs_gpio_unmask_irq,
	.irq_set_type = mxs_gpio_set_irq_type,
	.irq_set_wake = mxs_gpio_set_wake_irq,
};

static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
				int dir)
{
	struct mxs_gpio_port *port =
		container_of(chip, struct mxs_gpio_port, chip);
	void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);

	if (dir)
		writel(1 << offset, pin_addr + MXS_SET);
	else
		writel(1 << offset, pin_addr + MXS_CLR);
}

static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct mxs_gpio_port *port =
		container_of(chip, struct mxs_gpio_port, chip);

	return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
}

static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct mxs_gpio_port *port =
		container_of(chip, struct mxs_gpio_port, chip);
	void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);

	if (value)
		writel(1 << offset, pin_addr + MXS_SET);
	else
		writel(1 << offset, pin_addr + MXS_CLR);
}

static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct mxs_gpio_port *port =
		container_of(chip, struct mxs_gpio_port, chip);

	return port->virtual_irq_start + offset;
}

static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	mxs_set_gpio_direction(chip, offset, 0);
	return 0;
}

static int mxs_gpio_direction_output(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	mxs_gpio_set(chip, offset, value);
	mxs_set_gpio_direction(chip, offset, 1);
	return 0;
}

static int __devinit mxs_gpio_probe(struct platform_device *pdev)
{
	static void __iomem *base;
	struct mxs_gpio_port *port;
	struct resource *iores = NULL;
	int err, i;

	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = pdev->id;
	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!iores) {
			err = -ENODEV;
			goto out_kfree;
		}

		if (!request_mem_region(iores->start, resource_size(iores),
					pdev->name)) {
			err = -EBUSY;
			goto out_kfree;
		}

		base = ioremap(iores->start, resource_size(iores));
		if (!base) {
			err = -ENOMEM;
			goto out_release_mem;
		}
	}
	port->base = base;

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0) {
		err = -EINVAL;
		goto out_iounmap;
	}

	/* disable the interrupt and clear the status */
	writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
	writel(0, port->base + PINCTRL_IRQEN(port->id));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);

	for (i = port->virtual_irq_start;
		i < port->virtual_irq_start + 32; i++) {
		irq_set_chip_and_handler(i, &gpio_irq_chip,
					 handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
		irq_set_chip_data(i, port);
	}

	/* setup one handler for each entry */
	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	irq_set_handler_data(port->irq, port);

	/* register gpio chip */
	port->chip.direction_input = mxs_gpio_direction_input;
	port->chip.direction_output = mxs_gpio_direction_output;
	port->chip.get = mxs_gpio_get;
	port->chip.set = mxs_gpio_set;
	port->chip.to_irq = mxs_gpio_to_irq;
	port->chip.base = port->id * 32;
	port->chip.ngpio = 32;

	err = gpiochip_add(&port->chip);
	if (err)
		goto out_iounmap;

	return 0;

out_iounmap:
	if (iores)
		iounmap(port->base);
out_release_mem:
	if (iores)
		release_mem_region(iores->start, resource_size(iores));
out_kfree:
	kfree(port);
	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.owner	= THIS_MODULE,
	},
	.probe		= mxs_gpio_probe,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
fba311fc SG	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
	23	#include <linux/init.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/gpio.h>
8d7cf837 SG	28	#include <linux/platform_device.h>
	29	#include <linux/slab.h>
	30	#include <mach/mxs.h>
fba311fc	31
8d7cf837 SG	32	#define MXS_SET 0x4
8d7cf837 SG	33	#define MXS_CLR 0x8
fba311fc SG	34
	35	#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
	36	#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
	37	#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
	38	#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
	39	#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
	40	#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
	41	#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
	42	#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
	43
	44	#define GPIO_INT_FALL_EDGE 0x0
	45	#define GPIO_INT_LOW_LEV 0x1
	46	#define GPIO_INT_RISE_EDGE 0x2
	47	#define GPIO_INT_HIGH_LEV 0x3
	48	#define GPIO_INT_LEV_MASK (1 << 0)
	49	#define GPIO_INT_POL_MASK (1 << 1)
	50
7b2fa570 GL	51	struct mxs_gpio_port {
	52	void __iomem *base;
	53	int id;
	54	int irq;
	55	int irq_high;
	56	int virtual_irq_start;
	57	struct gpio_chip chip;
	58	};
	59
fba311fc SG	60	/* Note: This driver assumes 32 GPIOs are handled in one register */
	61
	62	static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
	63	{
8d7cf837	64	writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
fba311fc SG	65	}
	66
	67	static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
	68	int enable)
	69	{
	70	if (enable) {
8d7cf837 SG	71	writel(1 << index,
	72	port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
	73	writel(1 << index,
	74	port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
fba311fc	75	} else {
8d7cf837 SG	76	writel(1 << index,
8d7cf837 SG	77	port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
fba311fc SG	78	}
	79	}
	80
bf0c1118	81	static void mxs_gpio_ack_irq(struct irq_data *d)
fba311fc	82	{
8d7cf837	83	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	84	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	85	clear_gpio_irqstatus(port, gpio & 0x1f);
fba311fc SG	86	}
fba311fc SG	87
bf0c1118	88	static void mxs_gpio_mask_irq(struct irq_data *d)
fba311fc	89	{
8d7cf837	90	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	91	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	92	set_gpio_irqenable(port, gpio & 0x1f, 0);
fba311fc SG	93	}
fba311fc SG	94
bf0c1118	95	static void mxs_gpio_unmask_irq(struct irq_data *d)
fba311fc	96	{
8d7cf837	97	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
bf0c1118	98	u32 gpio = irq_to_gpio(d->irq);
8d7cf837	99	set_gpio_irqenable(port, gpio & 0x1f, 1);
fba311fc SG	100	}
	101
	102	static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
	103
bf0c1118	104	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	105	{
bf0c1118	106	u32 gpio = irq_to_gpio(d->irq);
fba311fc	107	u32 pin_mask = 1 << (gpio & 31);
8d7cf837	108	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
fba311fc SG	109	void __iomem *pin_addr;
	110	int edge;
	111
	112	switch (type) {
	113	case IRQ_TYPE_EDGE_RISING:
	114	edge = GPIO_INT_RISE_EDGE;
	115	break;
	116	case IRQ_TYPE_EDGE_FALLING:
	117	edge = GPIO_INT_FALL_EDGE;
	118	break;
	119	case IRQ_TYPE_LEVEL_LOW:
	120	edge = GPIO_INT_LOW_LEV;
	121	break;
	122	case IRQ_TYPE_LEVEL_HIGH:
	123	edge = GPIO_INT_HIGH_LEV;
	124	break;
	125	default:
	126	return -EINVAL;
	127	}
	128
	129	/* set level or edge */
	130	pin_addr = port->base + PINCTRL_IRQLEV(port->id);
	131	if (edge & GPIO_INT_LEV_MASK)
8d7cf837	132	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	133	else
8d7cf837	134	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	135
	136	/* set polarity */
	137	pin_addr = port->base + PINCTRL_IRQPOL(port->id);
	138	if (edge & GPIO_INT_POL_MASK)
8d7cf837	139	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	140	else
8d7cf837	141	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	142
	143	clear_gpio_irqstatus(port, gpio & 0x1f);
	144
	145	return 0;
	146	}
	147
	148	/* MXS has one interrupt per gpio port */
	149	static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	150	{
	151	u32 irq_stat;
8d7cf837	152	struct mxs_gpio_port *port = irq_get_handler_data(irq);
fba311fc SG	153	u32 gpio_irq_no_base = port->virtual_irq_start;
fba311fc SG	154
1f6b5dd4 UKK	155	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	156
8d7cf837 SG	157	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
8d7cf837 SG	158	readl(port->base + PINCTRL_IRQEN(port->id));
fba311fc SG	159
	160	while (irq_stat != 0) {
	161	int irqoffset = fls(irq_stat) - 1;
	162	generic_handle_irq(gpio_irq_no_base + irqoffset);
	163	irq_stat &= ~(1 << irqoffset);
	164	}
	165	}
	166
	167	/*
	168	* Set interrupt number "irq" in the GPIO as a wake-up source.
	169	* While system is running, all registered GPIO interrupts need to have
	170	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	171	* need to have wake-up enabled.
	172	* @param irq interrupt source number
	173	* @param enable enable as wake-up if equal to non-zero
	174	* @return This function returns 0 on success.
	175	*/
bf0c1118	176	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	177	{
bf0c1118	178	u32 gpio = irq_to_gpio(d->irq);
fba311fc	179	u32 gpio_idx = gpio & 0x1f;
8d7cf837	180	struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
fba311fc SG	181
	182	if (enable) {
	183	if (port->irq_high && (gpio_idx >= 16))
	184	enable_irq_wake(port->irq_high);
	185	else
	186	enable_irq_wake(port->irq);
	187	} else {
	188	if (port->irq_high && (gpio_idx >= 16))
	189	disable_irq_wake(port->irq_high);
	190	else
	191	disable_irq_wake(port->irq);
	192	}
	193
	194	return 0;
	195	}
	196
	197	static struct irq_chip gpio_irq_chip = {
761b6d1a	198	.name = "mxs gpio",
bf0c1118 UKK	199	.irq_ack = mxs_gpio_ack_irq,
	200	.irq_mask = mxs_gpio_mask_irq,
	201	.irq_unmask = mxs_gpio_unmask_irq,
	202	.irq_set_type = mxs_gpio_set_irq_type,
	203	.irq_set_wake = mxs_gpio_set_wake_irq,
fba311fc SG	204	};
	205
	206	static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
	207	int dir)
	208	{
	209	struct mxs_gpio_port *port =
	210	container_of(chip, struct mxs_gpio_port, chip);
	211	void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
	212
	213	if (dir)
8d7cf837	214	writel(1 << offset, pin_addr + MXS_SET);
fba311fc	215	else
8d7cf837	216	writel(1 << offset, pin_addr + MXS_CLR);
fba311fc SG	217	}
	218
	219	static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
	220	{
	221	struct mxs_gpio_port *port =
	222	container_of(chip, struct mxs_gpio_port, chip);
	223
8d7cf837	224	return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
fba311fc SG	225	}
	226
	227	static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	228	{
	229	struct mxs_gpio_port *port =
	230	container_of(chip, struct mxs_gpio_port, chip);
	231	void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
	232
	233	if (value)
8d7cf837	234	writel(1 << offset, pin_addr + MXS_SET);
fba311fc	235	else
8d7cf837	236	writel(1 << offset, pin_addr + MXS_CLR);
fba311fc SG	237	}
	238
	239	static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	240	{
	241	struct mxs_gpio_port *port =
	242	container_of(chip, struct mxs_gpio_port, chip);
	243
	244	return port->virtual_irq_start + offset;
	245	}
	246
	247	static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	248	{
	249	mxs_set_gpio_direction(chip, offset, 0);
	250	return 0;
	251	}
	252
	253	static int mxs_gpio_direction_output(struct gpio_chip *chip,
	254	unsigned offset, int value)
	255	{
	256	mxs_gpio_set(chip, offset, value);
	257	mxs_set_gpio_direction(chip, offset, 1);
	258	return 0;
	259	}
	260
8d7cf837	261	static int __devinit mxs_gpio_probe(struct platform_device *pdev)
fba311fc	262	{
8d7cf837 SG	263	static void __iomem *base;
	264	struct mxs_gpio_port *port;
	265	struct resource *iores = NULL;
	266	int err, i;
	267
	268	port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
	269	if (!port)
	270	return -ENOMEM;
	271
	272	port->id = pdev->id;
	273	port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
	274
	275	/*
	276	* map memory region only once, as all the gpio ports
	277	* share the same one
	278	*/
	279	if (!base) {
	280	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	281	if (!iores) {
	282	err = -ENODEV;
	283	goto out_kfree;
	284	}
fba311fc	285
8d7cf837 SG	286	if (!request_mem_region(iores->start, resource_size(iores),
	287	pdev->name)) {
	288	err = -EBUSY;
	289	goto out_kfree;
	290	}
fba311fc	291
8d7cf837 SG	292	base = ioremap(iores->start, resource_size(iores));
	293	if (!base) {
	294	err = -ENOMEM;
	295	goto out_release_mem;
	296	}
	297	}
	298	port->base = base;
fba311fc	299
8d7cf837 SG	300	port->irq = platform_get_irq(pdev, 0);
	301	if (port->irq < 0) {
	302	err = -EINVAL;
	303	goto out_iounmap;
	304	}
fba311fc	305
8d7cf837 SG	306	/* disable the interrupt and clear the status */
	307	writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
	308	writel(0, port->base + PINCTRL_IRQEN(port->id));
fba311fc	309
8d7cf837 SG	310	/* clear address has to be used to clear IRQSTAT bits */
8d7cf837 SG	311	writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
fba311fc	312
8d7cf837 SG	313	for (i = port->virtual_irq_start;
	314	i < port->virtual_irq_start + 32; i++) {
	315	irq_set_chip_and_handler(i, &gpio_irq_chip,
	316	handle_level_irq);
	317	set_irq_flags(i, IRQF_VALID);
	318	irq_set_chip_data(i, port);
fba311fc SG	319	}
fba311fc SG	320
8d7cf837 SG	321	/* setup one handler for each entry */
	322	irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
	323	irq_set_handler_data(port->irq, port);
fba311fc	324
8d7cf837 SG	325	/* register gpio chip */
	326	port->chip.direction_input = mxs_gpio_direction_input;
	327	port->chip.direction_output = mxs_gpio_direction_output;
	328	port->chip.get = mxs_gpio_get;
	329	port->chip.set = mxs_gpio_set;
	330	port->chip.to_irq = mxs_gpio_to_irq;
	331	port->chip.base = port->id * 32;
	332	port->chip.ngpio = 32;
0e8b462d	333
8d7cf837 SG	334	err = gpiochip_add(&port->chip);
	335	if (err)
	336	goto out_iounmap;
fba311fc	337
8d7cf837	338	return 0;
ef19660b	339
8d7cf837 SG	340	out_iounmap:
	341	if (iores)
	342	iounmap(port->base);
	343	out_release_mem:
	344	if (iores)
	345	release_mem_region(iores->start, resource_size(iores));
	346	out_kfree:
	347	kfree(port);
	348	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
	349	return err;
ef19660b	350	}
8d7cf837 SG	351
	352	static struct platform_driver mxs_gpio_driver = {
	353	.driver = {
	354	.name = "gpio-mxs",
	355	.owner = THIS_MODULE,
	356	},
	357	.probe = mxs_gpio_probe,
fba311fc	358	};
ef19660b	359
8d7cf837	360	static int __init mxs_gpio_init(void)
ef19660b	361	{
8d7cf837	362	return platform_driver_register(&mxs_gpio_driver);
ef19660b	363	}
8d7cf837 SG	364	postcore_initcall(mxs_gpio_init);
	365
	366	MODULE_AUTHOR("Freescale Semiconductor, "
	367	"Daniel Mack <danielncaiaq.de>, "
	368	"Juergen Beisert <kernel@pengutronix.de>");
	369	MODULE_DESCRIPTION("Freescale MXS GPIO");
	370	MODULE_LICENSE("GPL");