[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-davinci.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/gpio.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <asm/mach/irq.h>

struct davinci_gpio_regs {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

#define chip2controller(chip)	\
	container_of(chip, struct davinci_gpio_controller, chip)

static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
static void __iomem *gpio_base;

static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
	void __iomem *ptr;

	if (gpio < 32 * 1)
		ptr = gpio_base + 0x10;
	else if (gpio < 32 * 2)
		ptr = gpio_base + 0x38;
	else if (gpio < 32 * 3)
		ptr = gpio_base + 0x60;
	else if (gpio < 32 * 4)
		ptr = gpio_base + 0x88;
	else if (gpio < 32 * 5)
		ptr = gpio_base + 0xb0;
	else
		ptr = NULL;
	return ptr;
}

static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
	struct davinci_gpio_regs __iomem *g;

	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);

	return g;
}

static int __init davinci_gpio_irq_setup(void);

/*--------------------------------------------------------------------------*/

/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;
	unsigned long flags;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock_irqsave(&d->lock, flags);
	temp = __raw_readl(&g->dir);
	if (out) {
		temp &= ~mask;
		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	__raw_writel(temp, &g->dir);
	spin_unlock_irqrestore(&d->lock, flags);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	return (1 << offset) & __raw_readl(&g->in_data);
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}

static int __init davinci_gpio_setup(void)
{
	int i, base;
	unsigned ngpio;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs *regs;

	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
		return 0;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = soc_info->gpio_num;
	if (ngpio == 0) {
		pr_err("GPIO setup:  how many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
		ngpio = DAVINCI_N_GPIO;

	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
	if (WARN_ON(!gpio_base))
		return -ENOMEM;

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

		spin_lock_init(&chips[i].lock);

		regs = gpio2regs(base);
		chips[i].regs = regs;
		chips[i].set_data = &regs->set_data;
		chips[i].clr_data = &regs->clr_data;
		chips[i].in_data = &regs->in_data;

		gpiochip_add(&chips[i].chip);
	}

	soc_info->gpio_ctlrs = chips;
	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);

	davinci_gpio_irq_setup();
	return 0;
}
pure_initcall(davinci_gpio_setup);

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);

	__raw_writel(mask, &g->clr_falling);
	__raw_writel(mask, &g->clr_rising);
}

static void gpio_irq_enable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);
	unsigned status = irqd_get_trigger_type(d);

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		__raw_writel(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		__raw_writel(mask, &g->set_rising);
}

static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= gpio_irq_enable,
	.irq_disable	= gpio_irq_disable,
	.irq_set_type	= gpio_irq_type,
	.flags		= IRQCHIP_SET_TYPE_MASKED,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct davinci_gpio_regs __iomem *g;
	u32 mask = 0xffff;
	struct davinci_gpio_controller *d;

	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
	g = (struct davinci_gpio_regs __iomem *)d->regs;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->irq_data.chip->irq_mask(&desc->irq_data);
	desc->irq_data.chip->irq_ack(&desc->irq_data);
	while (1) {
		u32		status;
		int		n;
		int		res;

		/* ack any irqs */
		status = __raw_readl(&g->intstat) & mask;
		if (!status)
			break;
		__raw_writel(status, &g->intstat);

		/* now demux them to the right lowlevel handler */
		n = d->irq_base;
		if (irq & 1) {
			n += 16;
			status >>= 16;
		}

		while (status) {
			res = ffs(status);
			n += res;
			generic_handle_irq(n - 1);
			status >>= res;
		}
	}
	desc->irq_data.chip->irq_unmask(&desc->irq_data);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);

	if (d->irq_base >= 0)
		return d->irq_base + offset;
	else
		return -ENODEV;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/* NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < soc_info->gpio_unbanked)
		return soc_info->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
{
	struct davinci_gpio_controller *d;
	struct davinci_gpio_regs __iomem *g;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	u32 mask;

	d = (struct davinci_gpio_controller *)data->handler_data;
	g = (struct davinci_gpio_regs __iomem *)d->regs;
	mask = __gpio_mask(data->irq - soc_info->gpio_irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int __init davinci_gpio_irq_setup(void)
{
	unsigned	gpio, irq, bank;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs	__iomem *g;

	ngpio = soc_info->gpio_num;

	bank_irq = soc_info->gpio_irq;
	if (bank_irq == 0) {
		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
		return -EINVAL;
	}

	clk = clk_get(NULL, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_prepare_enable(clk);

	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_base = soc_info->gpio_unbanked
			? -EINVAL
			: (soc_info->intc_irq_num + gpio);
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (soc_info->gpio_unbanked) {
		static struct irq_chip_type gpio_unbanked;

		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		gpio_unbanked = *container_of(irq_get_chip(irq),
					      struct irq_chip_type, chip);
		gpio_unbanked.chip.name = "GPIO-AINTC";
		gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2regs(0);
		__raw_writel(~0, &g->set_falling);
		__raw_writel(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
			irq_set_chip(irq, &gpio_unbanked.chip);
			irq_set_handler_data(irq, &chips[gpio / 32]);
			irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
			gpio < ngpio;
			bank++, bank_irq++) {
		unsigned		i;

		/* disabled by default, enabled only as needed */
		g = gpio2regs(gpio);
		__raw_writel(~0, &g->clr_falling);
		__raw_writel(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		irq_set_chained_handler(bank_irq, gpio_irq_handler);

		/*
		 * Each chip handles 32 gpios, and each irq bank consists of 16
		 * gpio irqs. Pass the irq bank's corresponding controller to
		 * the chained irq handler.
		 */
		irq_set_handler_data(bank_irq, &chips[gpio / 32]);

		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
			irq_set_chip(irq, &gpio_irqchip);
			irq_set_chip_data(irq, (__force void *)g);
			irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
			irq_set_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID);
		}

		binten |= BIT(bank);
	}

done:
	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	__raw_writel(binten, gpio_base + 0x08);

	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

	return 0;
}
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
2f8163ba	12	#include <linux/gpio.h>
3d9edf09 VB	13	#include <linux/errno.h>
3d9edf09 VB	14	#include <linux/kernel.h>
3d9edf09 VB	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
3d9edf09	18
3d9edf09 VB	19	#include <asm/mach/irq.h>
3d9edf09 VB	20
c12f415a CC	21	struct davinci_gpio_regs {
	22	u32 dir;
	23	u32 out_data;
	24	u32 set_data;
	25	u32 clr_data;
	26	u32 in_data;
	27	u32 set_rising;
	28	u32 clr_rising;
	29	u32 set_falling;
	30	u32 clr_falling;
	31	u32 intstat;
	32	};
	33
ba4a984e	34	#define chip2controller(chip) \
99e9e52d	35	container_of(chip, struct davinci_gpio_controller, chip)
ba4a984e	36
99e9e52d	37	static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
b8d44293	38	static void __iomem *gpio_base;
3d9edf09	39
99e9e52d	40	static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
3d9edf09	41	{
c12f415a	42	void __iomem *ptr;
c12f415a CC	43
c12f415a CC	44	if (gpio < 32 * 1)
b8d44293	45	ptr = gpio_base + 0x10;
c12f415a	46	else if (gpio < 32 * 2)
b8d44293	47	ptr = gpio_base + 0x38;
c12f415a	48	else if (gpio < 32 * 3)
b8d44293	49	ptr = gpio_base + 0x60;
c12f415a	50	else if (gpio < 32 * 4)
b8d44293	51	ptr = gpio_base + 0x88;
c12f415a	52	else if (gpio < 32 * 5)
b8d44293	53	ptr = gpio_base + 0xb0;
c12f415a CC	54	else
	55	ptr = NULL;
	56	return ptr;
3d9edf09 VB	57	}
3d9edf09 VB	58
99e9e52d	59	static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
21ce873d	60	{
99e9e52d	61	struct davinci_gpio_regs __iomem *g;
21ce873d	62
6845664a	63	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
21ce873d KH	64
	65	return g;
	66	}
	67
dc756026	68	static int __init davinci_gpio_irq_setup(void);
dce1115b DB	69
	70	/--------------------------------------------------------------------------/
	71
5b3a05ca	72	/* board setup code MUST setup pinmux and enable the GPIO clock. */
ba4a984e CC	73	static inline int __davinci_direction(struct gpio_chip *chip,
ba4a984e CC	74	unsigned offset, bool out, int value)
3d9edf09	75	{
99e9e52d CC	76	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	77	struct davinci_gpio_regs __iomem *g = d->regs;
b27b6d03	78	unsigned long flags;
dce1115b	79	u32 temp;
ba4a984e	80	u32 mask = 1 << offset;
3d9edf09	81
b27b6d03	82	spin_lock_irqsave(&d->lock, flags);
dce1115b	83	temp = __raw_readl(&g->dir);
ba4a984e CC	84	if (out) {
	85	temp &= ~mask;
	86	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	87	} else {
	88	temp \|= mask;
	89	}
dce1115b	90	__raw_writel(temp, &g->dir);
b27b6d03	91	spin_unlock_irqrestore(&d->lock, flags);
3d9edf09	92
dce1115b DB	93	return 0;
dce1115b DB	94	}
3d9edf09	95
ba4a984e CC	96	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	97	{
	98	return __davinci_direction(chip, offset, false, 0);
	99	}
	100
	101	static int
	102	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	103	{
	104	return __davinci_direction(chip, offset, true, value);
	105	}
	106
3d9edf09 VB	107	/*
	108	* Read the pin's value (works even if it's set up as output);
	109	* returns zero/nonzero.
	110	*
	111	* Note that changes are synched to the GPIO clock, so reading values back
	112	* right after you've set them may give old values.
	113	*/
dce1115b	114	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	115	{
99e9e52d CC	116	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	117	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	118
dce1115b	119	return (1 << offset) & __raw_readl(&g->in_data);
3d9edf09	120	}
3d9edf09	121
dce1115b DB	122	/*
	123	* Assuming the pin is muxed as a gpio output, set its output value.
	124	*/
	125	static void
	126	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	127	{
99e9e52d CC	128	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	129	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	130
dce1115b DB	131	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
	132	}
	133
	134	static int __init davinci_gpio_setup(void)
	135	{
	136	int i, base;
a994955c MG	137	unsigned ngpio;
a994955c MG	138	struct davinci_soc_info *soc_info = &davinci_soc_info;
c12f415a	139	struct davinci_gpio_regs *regs;
dce1115b	140
686b634a CC	141	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
	142	return 0;
	143
a994955c MG	144	/*
a994955c MG	145	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	146	* and "ngpio" is one more than the largest zero-based
	147	* bit index that's valid.
	148	*/
a994955c MG	149	ngpio = soc_info->gpio_num;
a994955c MG	150	if (ngpio == 0) {
474dad54 DB	151	pr_err("GPIO setup: how many GPIOs?\n");
	152	return -EINVAL;
	153	}
	154
	155	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
	156	ngpio = DAVINCI_N_GPIO;
	157
b8d44293 CC	158	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
	159	if (WARN_ON(!gpio_base))
	160	return -ENOMEM;
	161
474dad54	162	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	163	chips[i].chip.label = "DaVinci";
	164
	165	chips[i].chip.direction_input = davinci_direction_in;
	166	chips[i].chip.get = davinci_gpio_get;
	167	chips[i].chip.direction_output = davinci_direction_out;
	168	chips[i].chip.set = davinci_gpio_set;
	169
	170	chips[i].chip.base = base;
474dad54	171	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	172	if (chips[i].chip.ngpio > 32)
	173	chips[i].chip.ngpio = 32;
	174
b27b6d03 CC	175	spin_lock_init(&chips[i].lock);
b27b6d03 CC	176
c12f415a CC	177	regs = gpio2regs(base);
	178	chips[i].regs = regs;
	179	chips[i].set_data = &regs->set_data;
	180	chips[i].clr_data = &regs->clr_data;
	181	chips[i].in_data = &regs->in_data;
dce1115b DB	182
	183	gpiochip_add(&chips[i].chip);
	184	}
3d9edf09	185
c12f415a CC	186	soc_info->gpio_ctlrs = chips;
	187	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
	188
dc756026	189	davinci_gpio_irq_setup();
3d9edf09 VB	190	return 0;
3d9edf09 VB	191	}
dce1115b	192	pure_initcall(davinci_gpio_setup);
3d9edf09	193
dce1115b	194	/--------------------------------------------------------------------------/
3d9edf09 VB	195	/*
	196	* We expect irqs will normally be set up as input pins, but they can also be
	197	* used as output pins ... which is convenient for testing.
	198	*
474dad54	199	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	200	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	201	*
474dad54	202	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	203	* serve as EDMA event triggers.
	204	*/
	205
23265442	206	static void gpio_irq_disable(struct irq_data *d)
3d9edf09	207	{
23265442	208	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	209	u32 mask = (u32) irq_data_get_irq_handler_data(d);
3d9edf09 VB	210
	211	__raw_writel(mask, &g->clr_falling);
	212	__raw_writel(mask, &g->clr_rising);
	213	}
	214
23265442	215	static void gpio_irq_enable(struct irq_data *d)
3d9edf09	216	{
23265442	217	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	218	u32 mask = (u32) irq_data_get_irq_handler_data(d);
5093aec8	219	unsigned status = irqd_get_trigger_type(d);
3d9edf09	220
df4aab46 DB	221	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	222	if (!status)
	223	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	224
	225	if (status & IRQ_TYPE_EDGE_FALLING)
3d9edf09	226	__raw_writel(mask, &g->set_falling);
df4aab46	227	if (status & IRQ_TYPE_EDGE_RISING)
3d9edf09 VB	228	__raw_writel(mask, &g->set_rising);
	229	}
	230
23265442	231	static int gpio_irq_type(struct irq_data *d, unsigned trigger)
3d9edf09	232	{
3d9edf09 VB	233	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	234	return -EINVAL;
	235
3d9edf09 VB	236	return 0;
	237	}
	238
	239	static struct irq_chip gpio_irqchip = {
	240	.name = "GPIO",
23265442 LB	241	.irq_enable = gpio_irq_enable,
	242	.irq_disable = gpio_irq_disable,
	243	.irq_set_type = gpio_irq_type,
5093aec8	244	.flags = IRQCHIP_SET_TYPE_MASKED,
3d9edf09 VB	245	};
	246
	247	static void
	248	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	249	{
74164016	250	struct davinci_gpio_regs __iomem *g;
3d9edf09	251	u32 mask = 0xffff;
f299bb95	252	struct davinci_gpio_controller *d;
3d9edf09	253
f299bb95 IY	254	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
f299bb95 IY	255	g = (struct davinci_gpio_regs __iomem *)d->regs;
74164016	256
3d9edf09 VB	257	/* we only care about one bank */
	258	if (irq & 1)
	259	mask <<= 16;
	260
	261	/* temporarily mask (level sensitive) parent IRQ */
23265442 LB	262	desc->irq_data.chip->irq_mask(&desc->irq_data);
23265442 LB	263	desc->irq_data.chip->irq_ack(&desc->irq_data);
3d9edf09 VB	264	while (1) {
3d9edf09 VB	265	u32 status;
3d9edf09 VB	266	int n;
	267	int res;
	268
	269	/* ack any irqs */
	270	status = __raw_readl(&g->intstat) & mask;
	271	if (!status)
	272	break;
	273	__raw_writel(status, &g->intstat);
3d9edf09 VB	274
3d9edf09 VB	275	/* now demux them to the right lowlevel handler */
f299bb95 IY	276	n = d->irq_base;
	277	if (irq & 1) {
	278	n += 16;
	279	status >>= 16;
	280	}
	281
3d9edf09 VB	282	while (status) {
	283	res = ffs(status);
	284	n += res;
d8aa0251	285	generic_handle_irq(n - 1);
3d9edf09 VB	286	status >>= res;
	287	}
	288	}
23265442	289	desc->irq_data.chip->irq_unmask(&desc->irq_data);
3d9edf09 VB	290	/* now it may re-trigger */
	291	}
	292
7a36071e DB	293	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
7a36071e DB	294	{
99e9e52d	295	struct davinci_gpio_controller *d = chip2controller(chip);
7a36071e DB	296
	297	if (d->irq_base >= 0)
	298	return d->irq_base + offset;
	299	else
	300	return -ENODEV;
	301	}
	302
	303	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	304	{
	305	struct davinci_soc_info *soc_info = &davinci_soc_info;
	306
	307	/* NOTE: we assume for now that only irqs in the first gpio_chip
	308	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	309	*/
	310	if (offset < soc_info->gpio_unbanked)
	311	return soc_info->gpio_irq + offset;
	312	else
	313	return -ENODEV;
	314	}
	315
ab2dde99	316	static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
7a36071e	317	{
ab2dde99 SN	318	struct davinci_gpio_controller *d;
	319	struct davinci_gpio_regs __iomem *g;
	320	struct davinci_soc_info *soc_info = &davinci_soc_info;
	321	u32 mask;
	322
	323	d = (struct davinci_gpio_controller *)data->handler_data;
	324	g = (struct davinci_gpio_regs __iomem *)d->regs;
	325	mask = __gpio_mask(data->irq - soc_info->gpio_irq);
7a36071e DB	326
	327	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	328	return -EINVAL;
	329
	330	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	331	? &g->set_falling : &g->clr_falling);
	332	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	333	? &g->set_rising : &g->clr_rising);
	334
	335	return 0;
	336	}
	337
3d9edf09	338	/*
474dad54 DB	339	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	340	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	341	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	342	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	343	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	344	*/
	345
	346	static int __init davinci_gpio_irq_setup(void)
	347	{
	348	unsigned gpio, irq, bank;
	349	struct clk *clk;
474dad54	350	u32 binten = 0;
a994955c MG	351	unsigned ngpio, bank_irq;
a994955c MG	352	struct davinci_soc_info *soc_info = &davinci_soc_info;
99e9e52d	353	struct davinci_gpio_regs __iomem *g;
a994955c MG	354
a994955c MG	355	ngpio = soc_info->gpio_num;
474dad54	356
a994955c MG	357	bank_irq = soc_info->gpio_irq;
a994955c MG	358	if (bank_irq == 0) {
474dad54 DB	359	printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
	360	return -EINVAL;
	361	}
3d9edf09 VB	362
	363	clk = clk_get(NULL, "gpio");
	364	if (IS_ERR(clk)) {
	365	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	366	PTR_ERR(clk));
474dad54	367	return PTR_ERR(clk);
3d9edf09	368	}
ce6b658d	369	clk_prepare_enable(clk);
3d9edf09	370
7a36071e DB	371	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	372	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	373	* IRQs, while the others use banked IRQs, would need some setup
	374	* tweaks to recognize hardware which can do that.
	375	*/
	376	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	377	chips[bank].chip.to_irq = gpio_to_irq_banked;
	378	chips[bank].irq_base = soc_info->gpio_unbanked
	379	? -EINVAL
	380	: (soc_info->intc_irq_num + gpio);
	381	}
	382
	383	/*
	384	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	385	* controller only handling trigger modes. We currently assume no
	386	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	387	*/
	388	if (soc_info->gpio_unbanked) {
81b279d8	389	static struct irq_chip_type gpio_unbanked;
7a36071e DB	390
	391	/* pass "bank 0" GPIO IRQs to AINTC */
	392	chips[0].chip.to_irq = gpio_to_irq_unbanked;
	393	binten = BIT(0);
	394
	395	/* AINTC handles mask/unmask; GPIO handles triggering */
	396	irq = bank_irq;
81b279d8 SN	397	gpio_unbanked = *container_of(irq_get_chip(irq),
	398	struct irq_chip_type, chip);
	399	gpio_unbanked.chip.name = "GPIO-AINTC";
	400	gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
7a36071e DB	401
7a36071e DB	402	/* default trigger: both edges */
99e9e52d	403	g = gpio2regs(0);
7a36071e DB	404	__raw_writel(~0, &g->set_falling);
	405	__raw_writel(~0, &g->set_rising);
	406
	407	/* set the direct IRQs up to use that irqchip */
	408	for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
81b279d8	409	irq_set_chip(irq, &gpio_unbanked.chip);
ab2dde99	410	irq_set_handler_data(irq, &chips[gpio / 32]);
5093aec8	411	irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
7a36071e DB	412	}
	413
	414	goto done;
	415	}
	416
	417	/*
	418	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	419	* then chain through our own handler.
	420	*/
474dad54 DB	421	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
	422	gpio < ngpio;
	423	bank++, bank_irq++) {
3d9edf09 VB	424	unsigned i;
3d9edf09 VB	425
7a36071e	426	/* disabled by default, enabled only as needed */
99e9e52d	427	g = gpio2regs(gpio);
3d9edf09 VB	428	__raw_writel(~0, &g->clr_falling);
	429	__raw_writel(~0, &g->clr_rising);
	430
	431	/* set up all irqs in this bank */
6845664a	432	irq_set_chained_handler(bank_irq, gpio_irq_handler);
f299bb95 IY	433
	434	/*
	435	* Each chip handles 32 gpios, and each irq bank consists of 16
	436	* gpio irqs. Pass the irq bank's corresponding controller to
	437	* the chained irq handler.
	438	*/
	439	irq_set_handler_data(bank_irq, &chips[gpio / 32]);
3d9edf09	440
474dad54	441	for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
6845664a TG	442	irq_set_chip(irq, &gpio_irqchip);
	443	irq_set_chip_data(irq, (__force void *)g);
	444	irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
	445	irq_set_handler(irq, handle_simple_irq);
3d9edf09 VB	446	set_irq_flags(irq, IRQF_VALID);
3d9edf09 VB	447	}
474dad54 DB	448
474dad54 DB	449	binten \|= BIT(bank);
3d9edf09 VB	450	}
3d9edf09 VB	451
7a36071e	452	done:
3d9edf09 VB	453	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	454	* bits be set/cleared dynamically.
	455	*/
b8d44293	456	__raw_writel(binten, gpio_base + 0x08);
3d9edf09 VB	457
	458	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
	459
	460	return 0;
	461	}