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firewire: net: replacing deprecated __attribute__((packed)) with __packed
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
cf3e72fd 45
e8ca9702 46#include <asm/byteorder.h>
c26f0234 47#include <asm/page.h>
ee71c2f9 48#include <asm/system.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
a77754a7
KH		 57#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 70
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
a77754a7
KH		 80#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 84
7a39d8b8
CL		 85#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 93
32b46093
KH		 94struct ar_context {
95 struct fw_ohci *ohci;
7a39d8b8
CL		 96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
32b46093 100 void *pointer;
7a39d8b8 101 unsigned int last_buffer_index;
72e318e0 102 u32 regs;
ed568912
KH		 103 struct tasklet_struct tasklet;
104};
105
30200739
KH		 106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
fe5ca634
DM		 111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
30200739 124struct context {
373b2edd 125 struct fw_ohci *ohci;
30200739 126 u32 regs;
fe5ca634 127 int total_allocation;
386a4153 128 bool running;
82b662dc 129 bool flushing;
373b2edd 130
fe5ca634
DM		 131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
30200739
KH		 155
156 descriptor_callback_t callback;
157
373b2edd 158 struct tasklet_struct tasklet;
30200739 159};
30200739 160
a77754a7
KH		 161#define IT_HEADER_SY(v) ((v) << 0)
162#define IT_HEADER_TCODE(v) ((v) << 4)
163#define IT_HEADER_CHANNEL(v) ((v) << 8)
164#define IT_HEADER_TAG(v) ((v) << 14)
165#define IT_HEADER_SPEED(v) ((v) << 16)
166#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 167
168struct iso_context {
169 struct fw_iso_context base;
30200739 170 struct context context;
0642b657 171 int excess_bytes;
9b32d5f3
KH		 172 void *header;
173 size_t header_length;
dd23736e
ML		 174
175 u8 sync;
176 u8 tags;
ed568912
KH		 177};
178
179#define CONFIG_ROM_SIZE 1024
180
181struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
e636fe25 185 int node_id;
ed568912 186 int generation;
e09770db 187 int request_generation; /* for timestamping incoming requests */
4a635593 188 unsigned quirks;
a1a1132b 189 unsigned int pri_req_max;
a48777e0 190 u32 bus_time;
4ffb7a6a 191 bool is_root;
c8a94ded 192 bool csr_state_setclear_abdicate;
dd23736e
ML		 193 int n_ir;
194 int n_it;
c781c06d
KH		 195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
ed568912 199 spinlock_t lock;
ed568912 200
02d37bed
SR		 201 struct mutex phy_reg_mutex;
202
ec766a79
CL		 203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
ed568912
KH		 206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
f319b6a0
KH		 208 struct context at_request_ctx;
209 struct context at_response_ctx;
ed568912 210
f117a3e3 211 u32 it_context_support;
872e330e 212 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 213 struct iso_context *it_context_list;
872e330e 214 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 215 u32 ir_context_support;
872e330e 216 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 217 struct iso_context *ir_context_list;
872e330e
SR		 218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
ecb1cf9c
SR		 220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
ed568912
KH		 232};
233
95688e97 234static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 235{
236 return container_of(card, struct fw_ohci, card);
237}
238
295e3feb
KH		 239#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240#define IR_CONTEXT_BUFFER_FILL 0x80000000
241#define IR_CONTEXT_ISOCH_HEADER 0x40000000
242#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 245
246#define CONTEXT_RUN 0x8000
247#define CONTEXT_WAKE 0x1000
248#define CONTEXT_DEAD 0x0800
249#define CONTEXT_ACTIVE 0x0400
250
8b7b6afa 251#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 252#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
ed568912
KH		 255#define OHCI1394_REGISTER_SIZE 0x800
256#define OHCI_LOOP_COUNT 500
257#define OHCI1394_PCI_HCI_Control 0x40
258#define SELF_ID_BUF_SIZE 0x800
32b46093 259#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 260#define OHCI_VERSION_1_1 0x010010
0edeefd9 261
ed568912
KH		 262static char ohci_driver_name[] = KBUILD_MODNAME;
263
9993e0fe 264#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 265#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b
CL		 266#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
267
4a635593
SR		 268#define QUIRK_CYCLE_TIMER 1
269#define QUIRK_RESET_PACKET 2
270#define QUIRK_BE_HEADERS 4
925e7a65 271#define QUIRK_NO_1394A 8
262444ee 272#define QUIRK_NO_MSI 16
4a635593
SR		 273
274/* In case of multiple matches in ohci_quirks[], only the first one is used. */
275static const struct {
9993e0fe 276 unsigned short vendor, device, revision, flags;
4a635593 277} ohci_quirks[] = {
9993e0fe
SR		 278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
279 QUIRK_CYCLE_TIMER},
280
281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
282 QUIRK_BE_HEADERS},
283
284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
285 QUIRK_NO_MSI},
286
287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
288 QUIRK_NO_MSI},
289
290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER},
292
293 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
294 QUIRK_CYCLE_TIMER},
295
296 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
297 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
298
299 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_RESET_PACKET},
301
302 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
303 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 304};
305
3e9cc2f3
SR		 306/* This overrides anything that was found in ohci_quirks[]. */
307static int param_quirks;
308module_param_named(quirks, param_quirks, int, 0644);
309MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
310 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
311 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
312 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 313 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 314 ", disable MSI = " __stringify(QUIRK_NO_MSI)
3e9cc2f3
SR		 315 ")");
316
a007bb85 317#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 318#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 319#define OHCI_PARAM_DEBUG_IRQS 4
320#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 321
5da3dac8
SR		 322#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
323
ad3c0fe8
SR		 324static int param_debug;
325module_param_named(debug, param_debug, int, 0644);
326MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 327 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 328 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
329 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
330 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 331 ", or a combination, or all = -1)");
332
333static void log_irqs(u32 evt)
334{
a007bb85
SR		 335 if (likely(!(param_debug &
336 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
337 return;
338
339 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
340 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 341 return;
342
f117a3e3 343 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 344 evt & OHCI1394_selfIDComplete ? " selfID" : "",
345 evt & OHCI1394_RQPkt ? " AR_req" : "",
346 evt & OHCI1394_RSPkt ? " AR_resp" : "",
347 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
348 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
349 evt & OHCI1394_isochRx ? " IR" : "",
350 evt & OHCI1394_isochTx ? " IT" : "",
351 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
352 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 353 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 354 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 355 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 356 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 357 evt & OHCI1394_busReset ? " busReset" : "",
358 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
359 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
360 OHCI1394_respTxComplete | OHCI1394_isochRx |
361 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 362 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
363 OHCI1394_cycleInconsistent |
161b96e7 364 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 365 ? " ?" : "");
366}
367
368static const char *speed[] = {
369 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
370};
371static const char *power[] = {
372 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
373 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
374};
375static const char port[] = { '.', '-', 'p', 'c', };
376
377static char _p(u32 *s, int shift)
378{
379 return port[*s >> shift & 3];
380}
381
08ddb2f4 382static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
ad3c0fe8
SR		 383{
384 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
385 return;
386
161b96e7
SR		 387 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
388 self_id_count, generation, node_id);
ad3c0fe8
SR		 389
390 for (; self_id_count--; ++s)
391 if ((*s & 1 << 23) == 0)
161b96e7
SR		 392 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
393 "%s gc=%d %s %s%s%s\n",
394 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
395 speed[*s >> 14 & 3], *s >> 16 & 63,
396 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
397 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 398 else
161b96e7
SR		 399 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
400 *s, *s >> 24 & 63,
401 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
402 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 403}
404
405static const char *evts[] = {
406 [0x00] = "evt_no_status", [0x01] = "-reserved-",
407 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
408 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
409 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
410 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
411 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
412 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
413 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
414 [0x10] = "-reserved-", [0x11] = "ack_complete",
415 [0x12] = "ack_pending ", [0x13] = "-reserved-",
416 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
417 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
418 [0x18] = "-reserved-", [0x19] = "-reserved-",
419 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
420 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
421 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
422 [0x20] = "pending/cancelled",
423};
424static const char *tcodes[] = {
425 [0x0] = "QW req", [0x1] = "BW req",
426 [0x2] = "W resp", [0x3] = "-reserved-",
427 [0x4] = "QR req", [0x5] = "BR req",
428 [0x6] = "QR resp", [0x7] = "BR resp",
429 [0x8] = "cycle start", [0x9] = "Lk req",
430 [0xa] = "async stream packet", [0xb] = "Lk resp",
431 [0xc] = "-reserved-", [0xd] = "-reserved-",
432 [0xe] = "link internal", [0xf] = "-reserved-",
433};
ad3c0fe8
SR		 434
435static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
436{
437 int tcode = header[0] >> 4 & 0xf;
438 char specific[12];
439
440 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
441 return;
442
443 if (unlikely(evt >= ARRAY_SIZE(evts)))
444 evt = 0x1f;
445
08ddb2f4 446 if (evt == OHCI1394_evt_bus_reset) {
161b96e7
SR		 447 fw_notify("A%c evt_bus_reset, generation %d\n",
448 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 449 return;
450 }
451
ad3c0fe8
SR		 452 switch (tcode) {
453 case 0x0: case 0x6: case 0x8:
454 snprintf(specific, sizeof(specific), " = %08x",
455 be32_to_cpu((__force __be32)header[3]));
456 break;
457 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
458 snprintf(specific, sizeof(specific), " %x,%x",
459 header[3] >> 16, header[3] & 0xffff);
460 break;
461 default:
462 specific[0] = '\0';
463 }
464
465 switch (tcode) {
5b06db16 466 case 0xa:
161b96e7 467 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
ad3c0fe8 468 break;
5b06db16
CL		 469 case 0xe:
470 fw_notify("A%c %s, PHY %08x %08x\n",
471 dir, evts[evt], header[1], header[2]);
472 break;
ad3c0fe8 473 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
161b96e7
SR		 474 fw_notify("A%c spd %x tl %02x, "
475 "%04x -> %04x, %s, "
476 "%s, %04x%08x%s\n",
477 dir, speed, header[0] >> 10 & 0x3f,
478 header[1] >> 16, header[0] >> 16, evts[evt],
479 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 480 break;
481 default:
161b96e7
SR		 482 fw_notify("A%c spd %x tl %02x, "
483 "%04x -> %04x, %s, "
484 "%s%s\n",
485 dir, speed, header[0] >> 10 & 0x3f,
486 header[1] >> 16, header[0] >> 16, evts[evt],
487 tcodes[tcode], specific);
ad3c0fe8
SR		 488 }
489}
490
491#else
492
5da3dac8
SR		 493#define param_debug 0
494static inline void log_irqs(u32 evt) {}
495static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
496static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 497
498#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
499
95688e97 500static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 501{
502 writel(data, ohci->registers + offset);
503}
504
95688e97 505static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 506{
507 return readl(ohci->registers + offset);
508}
509
95688e97 510static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 511{
512 /* Do a dummy read to flush writes. */
513 reg_read(ohci, OHCI1394_Version);
514}
515
35d999b1 516static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 517{
4a96b4fc 518 u32 val;
35d999b1 519 int i;
ed568912
KH		 520
521 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 522 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 523 val = reg_read(ohci, OHCI1394_PhyControl);
524 if (val & OHCI1394_PhyControl_ReadDone)
525 return OHCI1394_PhyControl_ReadData(val);
526
153e3979
CL		 527 /*
528 * Try a few times without waiting. Sleeping is necessary
529 * only when the link/PHY interface is busy.
530 */
531 if (i >= 3)
532 msleep(1);
ed568912 533 }
35d999b1 534 fw_error("failed to read phy reg\n");
ed568912 535
35d999b1
SR		 536 return -EBUSY;
537}
4a96b4fc 538
35d999b1
SR		 539static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
540{
541 int i;
ed568912 542
ed568912 543 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 544 OHCI1394_PhyControl_Write(addr, val));
153e3979 545 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 546 val = reg_read(ohci, OHCI1394_PhyControl);
547 if (!(val & OHCI1394_PhyControl_WritePending))
548 return 0;
ed568912 549
153e3979
CL		 550 if (i >= 3)
551 msleep(1);
35d999b1
SR		 552 }
553 fw_error("failed to write phy reg\n");
554
555 return -EBUSY;
4a96b4fc
CL		 556}
557
02d37bed
SR		 558static int update_phy_reg(struct fw_ohci *ohci, int addr,
559 int clear_bits, int set_bits)
4a96b4fc 560{
02d37bed 561 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 562 if (ret < 0)
563 return ret;
4a96b4fc 564
e7014dad
CL		 565 /*
566 * The interrupt status bits are cleared by writing a one bit.
567 * Avoid clearing them unless explicitly requested in set_bits.
568 */
569 if (addr == 5)
570 clear_bits |= PHY_INT_STATUS_BITS;
571
35d999b1 572 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 573}
574
35d999b1 575static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 576{
35d999b1 577 int ret;
925e7a65 578
02d37bed 579 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 580 if (ret < 0)
581 return ret;
925e7a65 582
35d999b1 583 return read_phy_reg(ohci, addr);
ed568912
KH		 584}
585
02d37bed
SR		 586static int ohci_read_phy_reg(struct fw_card *card, int addr)
587{
588 struct fw_ohci *ohci = fw_ohci(card);
589 int ret;
590
591 mutex_lock(&ohci->phy_reg_mutex);
592 ret = read_phy_reg(ohci, addr);
593 mutex_unlock(&ohci->phy_reg_mutex);
594
595 return ret;
596}
597
598static int ohci_update_phy_reg(struct fw_card *card, int addr,
599 int clear_bits, int set_bits)
600{
601 struct fw_ohci *ohci = fw_ohci(card);
602 int ret;
603
604 mutex_lock(&ohci->phy_reg_mutex);
605 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
606 mutex_unlock(&ohci->phy_reg_mutex);
607
608 return ret;
ed568912
KH		 609}
610
7a39d8b8
CL		 611static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
612{
613 return page_private(ctx->pages[i]);
614}
615
616static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 617{
7a39d8b8 618 struct descriptor *d;
32b46093 619
7a39d8b8
CL		 620 d = &ctx->descriptors[index];
621 d->branch_address &= cpu_to_le32(~0xf);
622 d->res_count = cpu_to_le16(PAGE_SIZE);
623 d->transfer_status = 0;
32b46093 624
071595eb 625 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 626 d = &ctx->descriptors[ctx->last_buffer_index];
627 d->branch_address |= cpu_to_le32(1);
628
629 ctx->last_buffer_index = index;
32b46093 630
a77754a7 631 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
ed568912 632 flush_writes(ctx->ohci);
837596a6
CL		 633}
634
7a39d8b8 635static void ar_context_release(struct ar_context *ctx)
837596a6 636{
7a39d8b8 637 unsigned int i;
837596a6 638
7a39d8b8
CL		 639 if (ctx->buffer)
640 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 641
7a39d8b8
CL		 642 for (i = 0; i < AR_BUFFERS; i++)
643 if (ctx->pages[i]) {
644 dma_unmap_page(ctx->ohci->card.device,
645 ar_buffer_bus(ctx, i),
646 PAGE_SIZE, DMA_FROM_DEVICE);
647 __free_page(ctx->pages[i]);
648 }
ed568912
KH		 649}
650
7a39d8b8 651static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 652{
7a39d8b8
CL		 653 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
654 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
655 flush_writes(ctx->ohci);
a55709ba 656
7a39d8b8 657 fw_error("AR error: %s; DMA stopped\n", error_msg);
a55709ba 658 }
7a39d8b8
CL		 659 /* FIXME: restart? */
660}
661
662static inline unsigned int ar_next_buffer_index(unsigned int index)
663{
664 return (index + 1) % AR_BUFFERS;
665}
666
667static inline unsigned int ar_prev_buffer_index(unsigned int index)
668{
669 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
670}
671
672static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
673{
674 return ar_next_buffer_index(ctx->last_buffer_index);
675}
676
677/*
678 * We search for the buffer that contains the last AR packet DMA data written
679 * by the controller.
680 */
681static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
682 unsigned int *buffer_offset)
683{
684 unsigned int i, next_i, last = ctx->last_buffer_index;
685 __le16 res_count, next_res_count;
686
687 i = ar_first_buffer_index(ctx);
688 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
689
690 /* A buffer that is not yet completely filled must be the last one. */
691 while (i != last && res_count == 0) {
692
693 /* Peek at the next descriptor. */
694 next_i = ar_next_buffer_index(i);
695 rmb(); /* read descriptors in order */
696 next_res_count = ACCESS_ONCE(
697 ctx->descriptors[next_i].res_count);
698 /*
699 * If the next descriptor is still empty, we must stop at this
700 * descriptor.
701 */
702 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
703 /*
704 * The exception is when the DMA data for one packet is
705 * split over three buffers; in this case, the middle
706 * buffer's descriptor might be never updated by the
707 * controller and look still empty, and we have to peek
708 * at the third one.
709 */
710 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
711 next_i = ar_next_buffer_index(next_i);
712 rmb();
713 next_res_count = ACCESS_ONCE(
714 ctx->descriptors[next_i].res_count);
715 if (next_res_count != cpu_to_le16(PAGE_SIZE))
716 goto next_buffer_is_active;
717 }
718
719 break;
720 }
721
722next_buffer_is_active:
723 i = next_i;
724 res_count = next_res_count;
725 }
726
727 rmb(); /* read res_count before the DMA data */
728
729 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
730 if (*buffer_offset > PAGE_SIZE) {
731 *buffer_offset = 0;
732 ar_context_abort(ctx, "corrupted descriptor");
733 }
734
735 return i;
736}
737
738static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
739 unsigned int end_buffer_index,
740 unsigned int end_buffer_offset)
741{
742 unsigned int i;
743
744 i = ar_first_buffer_index(ctx);
745 while (i != end_buffer_index) {
746 dma_sync_single_for_cpu(ctx->ohci->card.device,
747 ar_buffer_bus(ctx, i),
748 PAGE_SIZE, DMA_FROM_DEVICE);
749 i = ar_next_buffer_index(i);
750 }
751 if (end_buffer_offset > 0)
752 dma_sync_single_for_cpu(ctx->ohci->card.device,
753 ar_buffer_bus(ctx, i),
754 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 755}
756
11bf20ad
SR		 757#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
758#define cond_le32_to_cpu(v) \
4a635593 759 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 760#else
761#define cond_le32_to_cpu(v) le32_to_cpu(v)
762#endif
763
32b46093 764static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 765{
ed568912 766 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 767 struct fw_packet p;
768 u32 status, length, tcode;
43286568 769 int evt;
2639a6fb 770
11bf20ad
SR		 771 p.header[0] = cond_le32_to_cpu(buffer[0]);
772 p.header[1] = cond_le32_to_cpu(buffer[1]);
773 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 774
775 tcode = (p.header[0] >> 4) & 0x0f;
776 switch (tcode) {
777 case TCODE_WRITE_QUADLET_REQUEST:
778 case TCODE_READ_QUADLET_RESPONSE:
32b46093 779 p.header[3] = (__force __u32) buffer[3];
2639a6fb 780 p.header_length = 16;
32b46093 781 p.payload_length = 0;
2639a6fb
KH		 782 break;
783
2639a6fb 784 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 785 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 786 p.header_length = 16;
787 p.payload_length = 0;
788 break;
789
790 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 791 case TCODE_READ_BLOCK_RESPONSE:
792 case TCODE_LOCK_REQUEST:
793 case TCODE_LOCK_RESPONSE:
11bf20ad 794 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 795 p.header_length = 16;
32b46093 796 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 797 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
798 ar_context_abort(ctx, "invalid packet length");
799 return NULL;
800 }
2639a6fb
KH		 801 break;
802
803 case TCODE_WRITE_RESPONSE:
804 case TCODE_READ_QUADLET_REQUEST:
32b46093 805 case OHCI_TCODE_PHY_PACKET:
2639a6fb 806 p.header_length = 12;
32b46093 807 p.payload_length = 0;
2639a6fb 808 break;
ccff9629
SR		 809
810 default:
7a39d8b8
CL		 811 ar_context_abort(ctx, "invalid tcode");
812 return NULL;
2639a6fb 813 }
ed568912 814
32b46093
KH		 815 p.payload = (void *) buffer + p.header_length;
816
817 /* FIXME: What to do about evt_* errors? */
818 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 819 status = cond_le32_to_cpu(buffer[length]);
43286568 820 evt = (status >> 16) & 0x1f;
32b46093 821
43286568 822 p.ack = evt - 16;
32b46093
KH		 823 p.speed = (status >> 21) & 0x7;
824 p.timestamp = status & 0xffff;
825 p.generation = ohci->request_generation;
ed568912 826
43286568 827 log_ar_at_event('R', p.speed, p.header, evt);
ad3c0fe8 828
c781c06d 829 /*
a4dc090b
SR		 830 * Several controllers, notably from NEC and VIA, forget to
831 * write ack_complete status at PHY packet reception.
832 */
833 if (evt == OHCI1394_evt_no_status &&
834 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
835 p.ack = ACK_COMPLETE;
836
837 /*
838 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 839 * the new generation number when a bus reset happens (see
840 * section 8.4.2.3). This helps us determine when a request
841 * was received and make sure we send the response in the same
842 * generation. We only need this for requests; for responses
843 * we use the unique tlabel for finding the matching
c781c06d 844 * request.
d34316a4
SR		 845 *
846 * Alas some chips sometimes emit bus reset packets with a
847 * wrong generation. We set the correct generation for these
848 * at a slightly incorrect time (in bus_reset_tasklet).
c781c06d 849 */
d34316a4 850 if (evt == OHCI1394_evt_bus_reset) {
4a635593 851 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 852 ohci->request_generation = (p.header[2] >> 16) & 0xff;
853 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 854 fw_core_handle_request(&ohci->card, &p);
d34316a4 855 } else {
2639a6fb 856 fw_core_handle_response(&ohci->card, &p);
d34316a4 857 }
ed568912 858
32b46093
KH		 859 return buffer + length + 1;
860}
ed568912 861
7a39d8b8
CL		 862static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
863{
864 void *next;
865
866 while (p < end) {
867 next = handle_ar_packet(ctx, p);
868 if (!next)
869 return p;
870 p = next;
871 }
872
873 return p;
874}
875
876static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
877{
878 unsigned int i;
879
880 i = ar_first_buffer_index(ctx);
881 while (i != end_buffer) {
882 dma_sync_single_for_device(ctx->ohci->card.device,
883 ar_buffer_bus(ctx, i),
884 PAGE_SIZE, DMA_FROM_DEVICE);
885 ar_context_link_page(ctx, i);
886 i = ar_next_buffer_index(i);
887 }
888}
889
32b46093
KH		 890static void ar_context_tasklet(unsigned long data)
891{
892 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 893 unsigned int end_buffer_index, end_buffer_offset;
894 void *p, *end;
32b46093 895
7a39d8b8
CL		 896 p = ctx->pointer;
897 if (!p)
898 return;
32b46093 899
7a39d8b8
CL		 900 end_buffer_index = ar_search_last_active_buffer(ctx,
901 &end_buffer_offset);
902 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
903 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 904
7a39d8b8 905 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 906 /*
7a39d8b8
CL		 907 * The filled part of the overall buffer wraps around; handle
908 * all packets up to the buffer end here. If the last packet
909 * wraps around, its tail will be visible after the buffer end
910 * because the buffer start pages are mapped there again.
c781c06d 911 */
7a39d8b8
CL		 912 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
913 p = handle_ar_packets(ctx, p, buffer_end);
914 if (p < buffer_end)
915 goto error;
916 /* adjust p to point back into the actual buffer */
917 p -= AR_BUFFERS * PAGE_SIZE;
918 }
32b46093 919
7a39d8b8
CL		 920 p = handle_ar_packets(ctx, p, end);
921 if (p != end) {
922 if (p > end)
923 ar_context_abort(ctx, "inconsistent descriptor");
924 goto error;
925 }
32b46093 926
7a39d8b8
CL		 927 ctx->pointer = p;
928 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 929
7a39d8b8 930 return;
a1f805e5 931
7a39d8b8
CL		 932error:
933 ctx->pointer = NULL;
ed568912
KH		 934}
935
ec766a79
CL		 936static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
937 unsigned int descriptors_offset, u32 regs)
ed568912 938{
7a39d8b8
CL		 939 unsigned int i;
940 dma_addr_t dma_addr;
941 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
942 struct descriptor *d;
ed568912 943
72e318e0
KH		 944 ctx->regs = regs;
945 ctx->ohci = ohci;
ed568912
KH		 946 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
947
7a39d8b8
CL		 948 for (i = 0; i < AR_BUFFERS; i++) {
949 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
950 if (!ctx->pages[i])
951 goto out_of_memory;
952 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
953 0, PAGE_SIZE, DMA_FROM_DEVICE);
954 if (dma_mapping_error(ohci->card.device, dma_addr)) {
955 __free_page(ctx->pages[i]);
956 ctx->pages[i] = NULL;
957 goto out_of_memory;
958 }
959 set_page_private(ctx->pages[i], dma_addr);
960 }
961
962 for (i = 0; i < AR_BUFFERS; i++)
963 pages[i] = ctx->pages[i];
964 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
965 pages[AR_BUFFERS + i] = ctx->pages[i];
966 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 967 -1, PAGE_KERNEL);
7a39d8b8
CL		 968 if (!ctx->buffer)
969 goto out_of_memory;
970
ec766a79
CL		 971 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
972 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 973
974 for (i = 0; i < AR_BUFFERS; i++) {
975 d = &ctx->descriptors[i];
976 d->req_count = cpu_to_le16(PAGE_SIZE);
977 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
978 DESCRIPTOR_STATUS |
979 DESCRIPTOR_BRANCH_ALWAYS);
980 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
981 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
982 ar_next_buffer_index(i) * sizeof(struct descriptor));
983 }
32b46093 984
2aef469a 985 return 0;
7a39d8b8
CL		 986
987out_of_memory:
988 ar_context_release(ctx);
989
990 return -ENOMEM;
2aef469a
KH		 991}
992
993static void ar_context_run(struct ar_context *ctx)
994{
7a39d8b8
CL		 995 unsigned int i;
996
997 for (i = 0; i < AR_BUFFERS; i++)
998 ar_context_link_page(ctx, i);
2aef469a 999
7a39d8b8 1000 ctx->pointer = ctx->buffer;
2aef469a 1001
7a39d8b8 1002 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1003 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
32b46093 1004 flush_writes(ctx->ohci);
ed568912 1005}
373b2edd 1006
53dca511 1007static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1008{
0ff8fbc6 1009 __le16 branch;
a186b4a6 1010
0ff8fbc6 1011 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1012
1013 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1014 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1015 return d;
1016 else
1017 return d + z - 1;
1018}
1019
30200739
KH		 1020static void context_tasklet(unsigned long data)
1021{
1022 struct context *ctx = (struct context *) data;
30200739
KH		 1023 struct descriptor *d, *last;
1024 u32 address;
1025 int z;
fe5ca634 1026 struct descriptor_buffer *desc;
30200739 1027
fe5ca634
DM		 1028 desc = list_entry(ctx->buffer_list.next,
1029 struct descriptor_buffer, list);
1030 last = ctx->last;
30200739 1031 while (last->branch_address != 0) {
fe5ca634 1032 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1033 address = le32_to_cpu(last->branch_address);
1034 z = address & 0xf;
fe5ca634
DM		 1035 address &= ~0xf;
1036
1037 /* If the branch address points to a buffer outside of the
1038 * current buffer, advance to the next buffer. */
1039 if (address < desc->buffer_bus ||
1040 address >= desc->buffer_bus + desc->used)
1041 desc = list_entry(desc->list.next,
1042 struct descriptor_buffer, list);
1043 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1044 last = find_branch_descriptor(d, z);
30200739
KH		 1045
1046 if (!ctx->callback(ctx, d, last))
1047 break;
1048
fe5ca634
DM		 1049 if (old_desc != desc) {
1050 /* If we've advanced to the next buffer, move the
1051 * previous buffer to the free list. */
1052 unsigned long flags;
1053 old_desc->used = 0;
1054 spin_lock_irqsave(&ctx->ohci->lock, flags);
1055 list_move_tail(&old_desc->list, &ctx->buffer_list);
1056 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1057 }
1058 ctx->last = last;
30200739
KH		 1059 }
1060}
1061
fe5ca634
DM		 1062/*
1063 * Allocate a new buffer and add it to the list of free buffers for this
1064 * context. Must be called with ohci->lock held.
1065 */
53dca511 1066static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1067{
1068 struct descriptor_buffer *desc;
f5101d58 1069 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1070 int offset;
1071
1072 /*
1073 * 16MB of descriptors should be far more than enough for any DMA
1074 * program. This will catch run-away userspace or DoS attacks.
1075 */
1076 if (ctx->total_allocation >= 16*1024*1024)
1077 return -ENOMEM;
1078
1079 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1080 &bus_addr, GFP_ATOMIC);
1081 if (!desc)
1082 return -ENOMEM;
1083
1084 offset = (void *)&desc->buffer - (void *)desc;
1085 desc->buffer_size = PAGE_SIZE - offset;
1086 desc->buffer_bus = bus_addr + offset;
1087 desc->used = 0;
1088
1089 list_add_tail(&desc->list, &ctx->buffer_list);
1090 ctx->total_allocation += PAGE_SIZE;
1091
1092 return 0;
1093}
1094
53dca511
SR		 1095static int context_init(struct context *ctx, struct fw_ohci *ohci,
1096 u32 regs, descriptor_callback_t callback)
30200739
KH		 1097{
1098 ctx->ohci = ohci;
1099 ctx->regs = regs;
fe5ca634
DM		 1100 ctx->total_allocation = 0;
1101
1102 INIT_LIST_HEAD(&ctx->buffer_list);
1103 if (context_add_buffer(ctx) < 0)
30200739
KH		 1104 return -ENOMEM;
1105
fe5ca634
DM		 1106 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1107 struct descriptor_buffer, list);
1108
30200739
KH		 1109 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1110 ctx->callback = callback;
1111
c781c06d
KH		 1112 /*
1113 * We put a dummy descriptor in the buffer that has a NULL
30200739 1114 * branch address and looks like it's been sent. That way we
fe5ca634 1115 * have a descriptor to append DMA programs to.
c781c06d 1116 */
fe5ca634
DM		 1117 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1118 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1119 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1120 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1121 ctx->last = ctx->buffer_tail->buffer;
1122 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1123
1124 return 0;
1125}
1126
53dca511 1127static void context_release(struct context *ctx)
30200739
KH		 1128{
1129 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1130 struct descriptor_buffer *desc, *tmp;
30200739 1131
fe5ca634
DM		 1132 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1133 dma_free_coherent(card->device, PAGE_SIZE, desc,
1134 desc->buffer_bus -
1135 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1136}
1137
fe5ca634 1138/* Must be called with ohci->lock held */
53dca511
SR		 1139static struct descriptor *context_get_descriptors(struct context *ctx,
1140 int z, dma_addr_t *d_bus)
30200739 1141{
fe5ca634
DM		 1142 struct descriptor *d = NULL;
1143 struct descriptor_buffer *desc = ctx->buffer_tail;
1144
1145 if (z * sizeof(*d) > desc->buffer_size)
1146 return NULL;
1147
1148 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1149 /* No room for the descriptor in this buffer, so advance to the
1150 * next one. */
30200739 1151
fe5ca634
DM		 1152 if (desc->list.next == &ctx->buffer_list) {
1153 /* If there is no free buffer next in the list,
1154 * allocate one. */
1155 if (context_add_buffer(ctx) < 0)
1156 return NULL;
1157 }
1158 desc = list_entry(desc->list.next,
1159 struct descriptor_buffer, list);
1160 ctx->buffer_tail = desc;
1161 }
30200739 1162
fe5ca634 1163 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1164 memset(d, 0, z * sizeof(*d));
fe5ca634 1165 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1166
1167 return d;
1168}
1169
295e3feb 1170static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1171{
1172 struct fw_ohci *ohci = ctx->ohci;
1173
a77754a7 1174 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1175 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1176 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1177 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1178 ctx->running = true;
30200739
KH		 1179 flush_writes(ohci);
1180}
1181
1182static void context_append(struct context *ctx,
1183 struct descriptor *d, int z, int extra)
1184{
1185 dma_addr_t d_bus;
fe5ca634 1186 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1187
fe5ca634 1188 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1189
fe5ca634 1190 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1191
1192 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1193 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1194 ctx->prev = find_branch_descriptor(d, z);
30200739
KH		 1195}
1196
1197static void context_stop(struct context *ctx)
1198{
1199 u32 reg;
b8295668 1200 int i;
30200739 1201
a77754a7 1202 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1203 ctx->running = false;
b8295668 1204 flush_writes(ctx->ohci);
30200739 1205
b8295668 1206 for (i = 0; i < 10; i++) {
a77754a7 1207 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
b8295668 1208 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1209 return;
b8295668 1210
b980f5a2 1211 mdelay(1);
b8295668 1212 }
b0068549 1213 fw_error("Error: DMA context still active (0x%08x)\n", reg);
30200739 1214}
ed568912 1215
f319b6a0 1216struct driver_data {
da28947e 1217 u8 inline_data[8];
f319b6a0
KH		 1218 struct fw_packet *packet;
1219};
ed568912 1220
c781c06d
KH		 1221/*
1222 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1223 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1224 * generation handling and locking around packet queue manipulation.
1225 */
53dca511
SR		 1226static int at_context_queue_packet(struct context *ctx,
1227 struct fw_packet *packet)
ed568912 1228{
ed568912 1229 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1230 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1231 struct driver_data *driver_data;
1232 struct descriptor *d, *last;
1233 __le32 *header;
ed568912
KH		 1234 int z, tcode;
1235
f319b6a0
KH		 1236 d = context_get_descriptors(ctx, 4, &d_bus);
1237 if (d == NULL) {
1238 packet->ack = RCODE_SEND_ERROR;
1239 return -1;
ed568912
KH		 1240 }
1241
a77754a7 1242 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1243 d[0].res_count = cpu_to_le16(packet->timestamp);
1244
c781c06d
KH		 1245 /*
1246 * The DMA format for asyncronous link packets is different
ed568912 1247 * from the IEEE1394 layout, so shift the fields around
5b06db16 1248 * accordingly.
c781c06d 1249 */
f319b6a0 1250
5b06db16 1251 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1252 header = (__le32 *) &d[1];
5b06db16
CL		 1253 switch (tcode) {
1254 case TCODE_WRITE_QUADLET_REQUEST:
1255 case TCODE_WRITE_BLOCK_REQUEST:
1256 case TCODE_WRITE_RESPONSE:
1257 case TCODE_READ_QUADLET_REQUEST:
1258 case TCODE_READ_BLOCK_REQUEST:
1259 case TCODE_READ_QUADLET_RESPONSE:
1260 case TCODE_READ_BLOCK_RESPONSE:
1261 case TCODE_LOCK_REQUEST:
1262 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1263 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1264 (packet->speed << 16));
1265 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1266 (packet->header[0] & 0xffff0000));
1267 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1268
ed568912 1269 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1270 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1271 else
f319b6a0
KH		 1272 header[3] = (__force __le32) packet->header[3];
1273
1274 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1275 break;
1276
5b06db16 1277 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1278 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1279 (packet->speed << 16));
5b06db16
CL		 1280 header[1] = cpu_to_le32(packet->header[1]);
1281 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1282 d[0].req_count = cpu_to_le16(12);
cc550216 1283
5b06db16 1284 if (is_ping_packet(&packet->header[1]))
cc550216 1285 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1286 break;
1287
5b06db16 1288 case TCODE_STREAM_DATA:
f8c2287c
JF		 1289 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1290 (packet->speed << 16));
1291 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1292 d[0].req_count = cpu_to_le16(8);
1293 break;
1294
1295 default:
1296 /* BUG(); */
1297 packet->ack = RCODE_SEND_ERROR;
1298 return -1;
ed568912
KH		 1299 }
1300
da28947e 1301 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1302 driver_data = (struct driver_data *) &d[3];
1303 driver_data->packet = packet;
20d11673 1304 packet->driver_data = driver_data;
a186b4a6 1305
f319b6a0 1306 if (packet->payload_length > 0) {
da28947e
CL		 1307 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1308 payload_bus = dma_map_single(ohci->card.device,
1309 packet->payload,
1310 packet->payload_length,
1311 DMA_TO_DEVICE);
1312 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1313 packet->ack = RCODE_SEND_ERROR;
1314 return -1;
1315 }
1316 packet->payload_bus = payload_bus;
1317 packet->payload_mapped = true;
1318 } else {
1319 memcpy(driver_data->inline_data, packet->payload,
1320 packet->payload_length);
1321 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1322 }
1323
1324 d[2].req_count = cpu_to_le16(packet->payload_length);
1325 d[2].data_address = cpu_to_le32(payload_bus);
1326 last = &d[2];
1327 z = 3;
ed568912 1328 } else {
f319b6a0
KH		 1329 last = &d[0];
1330 z = 2;
ed568912 1331 }
ed568912 1332
a77754a7
KH		 1333 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1334 DESCRIPTOR_IRQ_ALWAYS |
1335 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1336
b6258fc1
SR		 1337 /* FIXME: Document how the locking works. */
1338 if (ohci->generation != packet->generation) {
19593ffd 1339 if (packet->payload_mapped)
ab88ca48
SR		 1340 dma_unmap_single(ohci->card.device, payload_bus,
1341 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1342 packet->ack = RCODE_GENERATION;
1343 return -1;
1344 }
1345
1346 context_append(ctx, d, z, 4 - z);
ed568912 1347
13882a82
CL		 1348 if (ctx->running) {
1349 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1350 flush_writes(ohci);
1351 } else {
f319b6a0 1352 context_run(ctx, 0);
13882a82 1353 }
f319b6a0
KH		 1354
1355 return 0;
ed568912
KH		 1356}
1357
82b662dc
CL		 1358static void at_context_flush(struct context *ctx)
1359{
1360 tasklet_disable(&ctx->tasklet);
1361
1362 ctx->flushing = true;
1363 context_tasklet((unsigned long)ctx);
1364 ctx->flushing = false;
1365
1366 tasklet_enable(&ctx->tasklet);
1367}
1368
f319b6a0
KH		 1369static int handle_at_packet(struct context *context,
1370 struct descriptor *d,
1371 struct descriptor *last)
ed568912 1372{
f319b6a0 1373 struct driver_data *driver_data;
ed568912 1374 struct fw_packet *packet;
f319b6a0 1375 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1376 int evt;
1377
82b662dc 1378 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1379 /* This descriptor isn't done yet, stop iteration. */
1380 return 0;
ed568912 1381
f319b6a0
KH		 1382 driver_data = (struct driver_data *) &d[3];
1383 packet = driver_data->packet;
1384 if (packet == NULL)
1385 /* This packet was cancelled, just continue. */
1386 return 1;
730c32f5 1387
19593ffd 1388 if (packet->payload_mapped)
1d1dc5e8 1389 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1390 packet->payload_length, DMA_TO_DEVICE);
ed568912 1391
f319b6a0
KH		 1392 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1393 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1394
ad3c0fe8
SR		 1395 log_ar_at_event('T', packet->speed, packet->header, evt);
1396
f319b6a0
KH		 1397 switch (evt) {
1398 case OHCI1394_evt_timeout:
1399 /* Async response transmit timed out. */
1400 packet->ack = RCODE_CANCELLED;
1401 break;
ed568912 1402
f319b6a0 1403 case OHCI1394_evt_flushed:
c781c06d
KH		 1404 /*
1405 * The packet was flushed should give same error as
1406 * when we try to use a stale generation count.
1407 */
f319b6a0
KH		 1408 packet->ack = RCODE_GENERATION;
1409 break;
ed568912 1410
f319b6a0 1411 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1412 if (context->flushing)
1413 packet->ack = RCODE_GENERATION;
1414 else {
1415 /*
1416 * Using a valid (current) generation count, but the
1417 * node is not on the bus or not sending acks.
1418 */
1419 packet->ack = RCODE_NO_ACK;
1420 }
f319b6a0 1421 break;
ed568912 1422
f319b6a0
KH		 1423 case ACK_COMPLETE + 0x10:
1424 case ACK_PENDING + 0x10:
1425 case ACK_BUSY_X + 0x10:
1426 case ACK_BUSY_A + 0x10:
1427 case ACK_BUSY_B + 0x10:
1428 case ACK_DATA_ERROR + 0x10:
1429 case ACK_TYPE_ERROR + 0x10:
1430 packet->ack = evt - 0x10;
1431 break;
ed568912 1432
82b662dc
CL		 1433 case OHCI1394_evt_no_status:
1434 if (context->flushing) {
1435 packet->ack = RCODE_GENERATION;
1436 break;
1437 }
1438 /* fall through */
1439
f319b6a0
KH		 1440 default:
1441 packet->ack = RCODE_SEND_ERROR;
1442 break;
1443 }
ed568912 1444
f319b6a0 1445 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1446
f319b6a0 1447 return 1;
ed568912
KH		 1448}
1449
a77754a7
KH		 1450#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1451#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1452#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1453#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1454#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1455
53dca511
SR		 1456static void handle_local_rom(struct fw_ohci *ohci,
1457 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1458{
1459 struct fw_packet response;
1460 int tcode, length, i;
1461
a77754a7 1462 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1463 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1464 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1465 else
1466 length = 4;
1467
1468 i = csr - CSR_CONFIG_ROM;
1469 if (i + length > CONFIG_ROM_SIZE) {
1470 fw_fill_response(&response, packet->header,
1471 RCODE_ADDRESS_ERROR, NULL, 0);
1472 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1473 fw_fill_response(&response, packet->header,
1474 RCODE_TYPE_ERROR, NULL, 0);
1475 } else {
1476 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1477 (void *) ohci->config_rom + i, length);
1478 }
1479
1480 fw_core_handle_response(&ohci->card, &response);
1481}
1482
53dca511
SR		 1483static void handle_local_lock(struct fw_ohci *ohci,
1484 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1485{
1486 struct fw_packet response;
e1393667 1487 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1488 __be32 *payload, lock_old;
1489 u32 lock_arg, lock_data;
1490
a77754a7
KH		 1491 tcode = HEADER_GET_TCODE(packet->header[0]);
1492 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1493 payload = packet->payload;
a77754a7 1494 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1495
1496 if (tcode == TCODE_LOCK_REQUEST &&
1497 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1498 lock_arg = be32_to_cpu(payload[0]);
1499 lock_data = be32_to_cpu(payload[1]);
1500 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1501 lock_arg = 0;
1502 lock_data = 0;
1503 } else {
1504 fw_fill_response(&response, packet->header,
1505 RCODE_TYPE_ERROR, NULL, 0);
1506 goto out;
1507 }
1508
1509 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1510 reg_write(ohci, OHCI1394_CSRData, lock_data);
1511 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1512 reg_write(ohci, OHCI1394_CSRControl, sel);
1513
e1393667
CL		 1514 for (try = 0; try < 20; try++)
1515 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1516 lock_old = cpu_to_be32(reg_read(ohci,
1517 OHCI1394_CSRData));
1518 fw_fill_response(&response, packet->header,
1519 RCODE_COMPLETE,
1520 &lock_old, sizeof(lock_old));
1521 goto out;
1522 }
1523
1524 fw_error("swap not done (CSR lock timeout)\n");
1525 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1526
93c4cceb
KH		 1527 out:
1528 fw_core_handle_response(&ohci->card, &response);
1529}
1530
53dca511 1531static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1532{
2608203d 1533 u64 offset, csr;
93c4cceb 1534
473d28c7
KH		 1535 if (ctx == &ctx->ohci->at_request_ctx) {
1536 packet->ack = ACK_PENDING;
1537 packet->callback(packet, &ctx->ohci->card, packet->ack);
1538 }
93c4cceb
KH		 1539
1540 offset =
1541 ((unsigned long long)
a77754a7 1542 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1543 packet->header[2];
1544 csr = offset - CSR_REGISTER_BASE;
1545
1546 /* Handle config rom reads. */
1547 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1548 handle_local_rom(ctx->ohci, packet, csr);
1549 else switch (csr) {
1550 case CSR_BUS_MANAGER_ID:
1551 case CSR_BANDWIDTH_AVAILABLE:
1552 case CSR_CHANNELS_AVAILABLE_HI:
1553 case CSR_CHANNELS_AVAILABLE_LO:
1554 handle_local_lock(ctx->ohci, packet, csr);
1555 break;
1556 default:
1557 if (ctx == &ctx->ohci->at_request_ctx)
1558 fw_core_handle_request(&ctx->ohci->card, packet);
1559 else
1560 fw_core_handle_response(&ctx->ohci->card, packet);
1561 break;
1562 }
473d28c7
KH		 1563
1564 if (ctx == &ctx->ohci->at_response_ctx) {
1565 packet->ack = ACK_COMPLETE;
1566 packet->callback(packet, &ctx->ohci->card, packet->ack);
1567 }
93c4cceb 1568}
e636fe25 1569
53dca511 1570static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1571{
ed568912 1572 unsigned long flags;
2dbd7d7e 1573 int ret;
ed568912
KH		 1574
1575 spin_lock_irqsave(&ctx->ohci->lock, flags);
1576
a77754a7 1577 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1578 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1579 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1580 handle_local_request(ctx, packet);
1581 return;
e636fe25 1582 }
ed568912 1583
2dbd7d7e 1584 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1585 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1586
2dbd7d7e 1587 if (ret < 0)
f319b6a0 1588 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1589
ed568912
KH		 1590}
1591
f117a3e3
CL		 1592static void detect_dead_context(struct fw_ohci *ohci,
1593 const char *name, unsigned int regs)
1594{
1595 u32 ctl;
1596
1597 ctl = reg_read(ohci, CONTROL_SET(regs));
1598 if (ctl & CONTEXT_DEAD) {
1599#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1600 fw_error("DMA context %s has stopped, error code: %s\n",
1601 name, evts[ctl & 0x1f]);
1602#else
1603 fw_error("DMA context %s has stopped, error code: %#x\n",
1604 name, ctl & 0x1f);
1605#endif
1606 }
1607}
1608
1609static void handle_dead_contexts(struct fw_ohci *ohci)
1610{
1611 unsigned int i;
1612 char name[8];
1613
1614 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1615 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1616 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1617 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1618 for (i = 0; i < 32; ++i) {
1619 if (!(ohci->it_context_support & (1 << i)))
1620 continue;
1621 sprintf(name, "IT%u", i);
1622 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1623 }
1624 for (i = 0; i < 32; ++i) {
1625 if (!(ohci->ir_context_support & (1 << i)))
1626 continue;
1627 sprintf(name, "IR%u", i);
1628 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1629 }
1630 /* TODO: maybe try to flush and restart the dead contexts */
1631}
1632
a48777e0
CL		 1633static u32 cycle_timer_ticks(u32 cycle_timer)
1634{
1635 u32 ticks;
1636
1637 ticks = cycle_timer & 0xfff;
1638 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1639 ticks += (3072 * 8000) * (cycle_timer >> 25);
1640
1641 return ticks;
1642}
1643
1644/*
1645 * Some controllers exhibit one or more of the following bugs when updating the
1646 * iso cycle timer register:
1647 * - When the lowest six bits are wrapping around to zero, a read that happens
1648 * at the same time will return garbage in the lowest ten bits.
1649 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1650 * not incremented for about 60 ns.
1651 * - Occasionally, the entire register reads zero.
1652 *
1653 * To catch these, we read the register three times and ensure that the
1654 * difference between each two consecutive reads is approximately the same, i.e.
1655 * less than twice the other. Furthermore, any negative difference indicates an
1656 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1657 * execute, so we have enough precision to compute the ratio of the differences.)
1658 */
1659static u32 get_cycle_time(struct fw_ohci *ohci)
1660{
1661 u32 c0, c1, c2;
1662 u32 t0, t1, t2;
1663 s32 diff01, diff12;
1664 int i;
1665
1666 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1667
1668 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1669 i = 0;
1670 c1 = c2;
1671 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1672 do {
1673 c0 = c1;
1674 c1 = c2;
1675 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1676 t0 = cycle_timer_ticks(c0);
1677 t1 = cycle_timer_ticks(c1);
1678 t2 = cycle_timer_ticks(c2);
1679 diff01 = t1 - t0;
1680 diff12 = t2 - t1;
1681 } while ((diff01 <= 0 || diff12 <= 0 ||
1682 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1683 && i++ < 20);
1684 }
1685
1686 return c2;
1687}
1688
1689/*
1690 * This function has to be called at least every 64 seconds. The bus_time
1691 * field stores not only the upper 25 bits of the BUS_TIME register but also
1692 * the most significant bit of the cycle timer in bit 6 so that we can detect
1693 * changes in this bit.
1694 */
1695static u32 update_bus_time(struct fw_ohci *ohci)
1696{
1697 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1698
1699 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1700 ohci->bus_time += 0x40;
1701
1702 return ohci->bus_time | cycle_time_seconds;
1703}
1704
ed568912
KH		 1705static void bus_reset_tasklet(unsigned long data)
1706{
1707 struct fw_ohci *ohci = (struct fw_ohci *)data;
e636fe25 1708 int self_id_count, i, j, reg;
ed568912
KH		 1709 int generation, new_generation;
1710 unsigned long flags;
4eaff7d6
SR		 1711 void *free_rom = NULL;
1712 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1713 bool is_new_root;
ed568912
KH		 1714
1715 reg = reg_read(ohci, OHCI1394_NodeID);
1716 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 1717 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH		 1718 return;
1719 }
02ff8f8e
SR		 1720 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1721 fw_notify("malconfigured bus\n");
1722 return;
1723 }
1724 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1725 OHCI1394_NodeID_nodeNumber);
ed568912 1726
4ffb7a6a
CL		 1727 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1728 if (!(ohci->is_root && is_new_root))
1729 reg_write(ohci, OHCI1394_LinkControlSet,
1730 OHCI1394_LinkControl_cycleMaster);
1731 ohci->is_root = is_new_root;
1732
c8a9a498
SR		 1733 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1734 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1735 fw_notify("inconsistent self IDs\n");
1736 return;
1737 }
c781c06d
KH		 1738 /*
1739 * The count in the SelfIDCount register is the number of
ed568912
KH		 1740 * bytes in the self ID receive buffer. Since we also receive
1741 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1742 * bit extra to get the actual number of self IDs.
1743 */
928ec5f1
SR		 1744 self_id_count = (reg >> 3) & 0xff;
1745 if (self_id_count == 0 || self_id_count > 252) {
016bf3df
SR		 1746 fw_notify("inconsistent self IDs\n");
1747 return;
1748 }
11bf20ad 1749 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1750 rmb();
ed568912
KH		 1751
1752 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498
SR		 1753 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1754 fw_notify("inconsistent self IDs\n");
1755 return;
1756 }
11bf20ad
SR		 1757 ohci->self_id_buffer[j] =
1758 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1759 }
ee71c2f9 1760 rmb();
ed568912 1761
c781c06d
KH		 1762 /*
1763 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1764 * problem we face is that a new bus reset can start while we
1765 * read out the self IDs from the DMA buffer. If this happens,
1766 * the DMA buffer will be overwritten with new self IDs and we
1767 * will read out inconsistent data. The OHCI specification
1768 * (section 11.2) recommends a technique similar to
1769 * linux/seqlock.h, where we remember the generation of the
1770 * self IDs in the buffer before reading them out and compare
1771 * it to the current generation after reading them out. If
1772 * the two generations match we know we have a consistent set
c781c06d
KH		 1773 * of self IDs.
1774 */
ed568912
KH		 1775
1776 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1777 if (new_generation != generation) {
1778 fw_notify("recursive bus reset detected, "
1779 "discarding self ids\n");
1780 return;
1781 }
1782
1783 /* FIXME: Document how the locking works. */
1784 spin_lock_irqsave(&ohci->lock, flags);
1785
82b662dc 1786 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1787 context_stop(&ohci->at_request_ctx);
1788 context_stop(&ohci->at_response_ctx);
82b662dc
CL		 1789
1790 spin_unlock_irqrestore(&ohci->lock, flags);
1791
78dec56d
SR		 1792 /*
1793 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1794 * packets in the AT queues and software needs to drain them.
1795 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1796 */
82b662dc
CL		 1797 at_context_flush(&ohci->at_request_ctx);
1798 at_context_flush(&ohci->at_response_ctx);
1799
1800 spin_lock_irqsave(&ohci->lock, flags);
1801
1802 ohci->generation = generation;
ed568912
KH		 1803 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1804
4a635593 1805 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1806 ohci->request_generation = generation;
1807
c781c06d
KH		 1808 /*
1809 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1810 * have to do it under the spinlock also. If a new config rom
1811 * was set up before this reset, the old one is now no longer
1812 * in use and we can free it. Update the config rom pointers
1813 * to point to the current config rom and clear the
88393161 1814 * next_config_rom pointer so a new update can take place.
c781c06d 1815 */
ed568912
KH		 1816
1817 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1818 if (ohci->next_config_rom != ohci->config_rom) {
1819 free_rom = ohci->config_rom;
1820 free_rom_bus = ohci->config_rom_bus;
1821 }
ed568912
KH		 1822 ohci->config_rom = ohci->next_config_rom;
1823 ohci->config_rom_bus = ohci->next_config_rom_bus;
1824 ohci->next_config_rom = NULL;
1825
c781c06d
KH		 1826 /*
1827 * Restore config_rom image and manually update
ed568912
KH		 1828 * config_rom registers. Writing the header quadlet
1829 * will indicate that the config rom is ready, so we
c781c06d
KH		 1830 * do that last.
1831 */
ed568912
KH		 1832 reg_write(ohci, OHCI1394_BusOptions,
1833 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1834 ohci->config_rom[0] = ohci->next_header;
1835 reg_write(ohci, OHCI1394_ConfigROMhdr,
1836 be32_to_cpu(ohci->next_header));
ed568912
KH		 1837 }
1838
080de8c2
SR		 1839#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1840 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1841 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1842#endif
1843
ed568912
KH		 1844 spin_unlock_irqrestore(&ohci->lock, flags);
1845
4eaff7d6
SR		 1846 if (free_rom)
1847 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1848 free_rom, free_rom_bus);
1849
08ddb2f4
SR		 1850 log_selfids(ohci->node_id, generation,
1851 self_id_count, ohci->self_id_buffer);
ad3c0fe8 1852
e636fe25 1853 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 1854 self_id_count, ohci->self_id_buffer,
1855 ohci->csr_state_setclear_abdicate);
1856 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 1857}
1858
1859static irqreturn_t irq_handler(int irq, void *data)
1860{
1861 struct fw_ohci *ohci = data;
168cf9af 1862 u32 event, iso_event;
ed568912
KH		 1863 int i;
1864
1865 event = reg_read(ohci, OHCI1394_IntEventClear);
1866
a515958d 1867 if (!event || !~event)
ed568912
KH		 1868 return IRQ_NONE;
1869
8327b37b
CL		 1870 /*
1871 * busReset and postedWriteErr must not be cleared yet
1872 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1873 */
1874 reg_write(ohci, OHCI1394_IntEventClear,
1875 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
ad3c0fe8 1876 log_irqs(event);
ed568912
KH		 1877
1878 if (event & OHCI1394_selfIDComplete)
1879 tasklet_schedule(&ohci->bus_reset_tasklet);
1880
1881 if (event & OHCI1394_RQPkt)
1882 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1883
1884 if (event & OHCI1394_RSPkt)
1885 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1886
1887 if (event & OHCI1394_reqTxComplete)
1888 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1889
1890 if (event & OHCI1394_respTxComplete)
1891 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1892
2dd5bed5
CL		 1893 if (event & OHCI1394_isochRx) {
1894 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1895 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1896
1897 while (iso_event) {
1898 i = ffs(iso_event) - 1;
1899 tasklet_schedule(
1900 &ohci->ir_context_list[i].context.tasklet);
1901 iso_event &= ~(1 << i);
1902 }
ed568912
KH		 1903 }
1904
2dd5bed5
CL		 1905 if (event & OHCI1394_isochTx) {
1906 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1907 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 1908
2dd5bed5
CL		 1909 while (iso_event) {
1910 i = ffs(iso_event) - 1;
1911 tasklet_schedule(
1912 &ohci->it_context_list[i].context.tasklet);
1913 iso_event &= ~(1 << i);
1914 }
ed568912
KH		 1915 }
1916
75f7832e
JW		 1917 if (unlikely(event & OHCI1394_regAccessFail))
1918 fw_error("Register access failure - "
1919 "please notify linux1394-devel@lists.sf.net\n");
1920
8327b37b
CL		 1921 if (unlikely(event & OHCI1394_postedWriteErr)) {
1922 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1923 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1924 reg_write(ohci, OHCI1394_IntEventClear,
1925 OHCI1394_postedWriteErr);
e524f616 1926 fw_error("PCI posted write error\n");
8327b37b 1927 }
e524f616 1928
bb9f2206
SR		 1929 if (unlikely(event & OHCI1394_cycleTooLong)) {
1930 if (printk_ratelimit())
1931 fw_notify("isochronous cycle too long\n");
1932 reg_write(ohci, OHCI1394_LinkControlSet,
1933 OHCI1394_LinkControl_cycleMaster);
1934 }
1935
5ed1f321
JF		 1936 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1937 /*
1938 * We need to clear this event bit in order to make
1939 * cycleMatch isochronous I/O work. In theory we should
1940 * stop active cycleMatch iso contexts now and restart
1941 * them at least two cycles later. (FIXME?)
1942 */
1943 if (printk_ratelimit())
1944 fw_notify("isochronous cycle inconsistent\n");
1945 }
1946
f117a3e3
CL		 1947 if (unlikely(event & OHCI1394_unrecoverableError))
1948 handle_dead_contexts(ohci);
1949
a48777e0
CL		 1950 if (event & OHCI1394_cycle64Seconds) {
1951 spin_lock(&ohci->lock);
1952 update_bus_time(ohci);
1953 spin_unlock(&ohci->lock);
e597e989
CL		 1954 } else
1955 flush_writes(ohci);
a48777e0 1956
ed568912
KH		 1957 return IRQ_HANDLED;
1958}
1959
2aef469a
KH		 1960static int software_reset(struct fw_ohci *ohci)
1961{
1962 int i;
1963
1964 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1965
1966 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1967 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1968 OHCI1394_HCControl_softReset) == 0)
1969 return 0;
1970 msleep(1);
1971 }
1972
1973 return -EBUSY;
1974}
1975
8e85973e
SR		 1976static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1977{
1978 size_t size = length * 4;
1979
1980 memcpy(dest, src, size);
1981 if (size < CONFIG_ROM_SIZE)
1982 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1983}
1984
925e7a65
CL		 1985static int configure_1394a_enhancements(struct fw_ohci *ohci)
1986{
1987 bool enable_1394a;
35d999b1 1988 int ret, clear, set, offset;
925e7a65
CL		 1989
1990 /* Check if the driver should configure link and PHY. */
1991 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1992 OHCI1394_HCControl_programPhyEnable))
1993 return 0;
1994
1995 /* Paranoia: check whether the PHY supports 1394a, too. */
1996 enable_1394a = false;
35d999b1
SR		 1997 ret = read_phy_reg(ohci, 2);
1998 if (ret < 0)
1999 return ret;
2000 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2001 ret = read_paged_phy_reg(ohci, 1, 8);
2002 if (ret < 0)
2003 return ret;
2004 if (ret >= 1)
925e7a65
CL		 2005 enable_1394a = true;
2006 }
2007
2008 if (ohci->quirks & QUIRK_NO_1394A)
2009 enable_1394a = false;
2010
2011 /* Configure PHY and link consistently. */
2012 if (enable_1394a) {
2013 clear = 0;
2014 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2015 } else {
2016 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2017 set = 0;
2018 }
02d37bed 2019 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2020 if (ret < 0)
2021 return ret;
925e7a65
CL		 2022
2023 if (enable_1394a)
2024 offset = OHCI1394_HCControlSet;
2025 else
2026 offset = OHCI1394_HCControlClear;
2027 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2028
2029 /* Clean up: configuration has been taken care of. */
2030 reg_write(ohci, OHCI1394_HCControlClear,
2031 OHCI1394_HCControl_programPhyEnable);
2032
2033 return 0;
2034}
2035
8e85973e
SR		 2036static int ohci_enable(struct fw_card *card,
2037 const __be32 *config_rom, size_t length)
ed568912
KH		 2038{
2039 struct fw_ohci *ohci = fw_ohci(card);
2040 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 2041 u32 lps, seconds, version, irqs;
35d999b1 2042 int i, ret;
ed568912 2043
2aef469a
KH		 2044 if (software_reset(ohci)) {
2045 fw_error("Failed to reset ohci card.\n");
2046 return -EBUSY;
2047 }
2048
2049 /*
2050 * Now enable LPS, which we need in order to start accessing
2051 * most of the registers. In fact, on some cards (ALI M5251),
2052 * accessing registers in the SClk domain without LPS enabled
2053 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2054 * full link enabled. However, with some cards (well, at least
2055 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2056 */
2057 reg_write(ohci, OHCI1394_HCControlSet,
2058 OHCI1394_HCControl_LPS |
2059 OHCI1394_HCControl_postedWriteEnable);
2060 flush_writes(ohci);
02214724
JW		 2061
2062 for (lps = 0, i = 0; !lps && i < 3; i++) {
2063 msleep(50);
2064 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2065 OHCI1394_HCControl_LPS;
2066 }
2067
2068 if (!lps) {
2069 fw_error("Failed to set Link Power Status\n");
2070 return -EIO;
2071 }
2aef469a
KH		 2072
2073 reg_write(ohci, OHCI1394_HCControlClear,
2074 OHCI1394_HCControl_noByteSwapData);
2075
affc9c24 2076 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2077 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2078 OHCI1394_LinkControl_cycleTimerEnable |
2079 OHCI1394_LinkControl_cycleMaster);
2080
2081 reg_write(ohci, OHCI1394_ATRetries,
2082 OHCI1394_MAX_AT_REQ_RETRIES |
2083 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2084 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2085 (200 << 16));
2aef469a 2086
a48777e0
CL		 2087 seconds = lower_32_bits(get_seconds());
2088 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2089 ohci->bus_time = seconds & ~0x3f;
2090
e91b2787
CL		 2091 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2092 if (version >= OHCI_VERSION_1_1) {
2093 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2094 0xfffffffe);
db3c9cc1 2095 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2096 }
2097
a1a1132b
CL		 2098 /* Get implemented bits of the priority arbitration request counter. */
2099 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2100 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2101 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2102 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2103
2aef469a
KH		 2104 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2105 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2106 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2107
35d999b1
SR		 2108 ret = configure_1394a_enhancements(ohci);
2109 if (ret < 0)
2110 return ret;
925e7a65 2111
2aef469a 2112 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2113 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2114 if (ret < 0)
2115 return ret;
2aef469a 2116
c781c06d
KH		 2117 /*
2118 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2119 * update mechanism described below in ohci_set_config_rom()
2120 * is not active. We have to update ConfigRomHeader and
2121 * BusOptions manually, and the write to ConfigROMmap takes
2122 * effect immediately. We tie this to the enabling of the
2123 * link, so we have a valid config rom before enabling - the
2124 * OHCI requires that ConfigROMhdr and BusOptions have valid
2125 * values before enabling.
2126 *
2127 * However, when the ConfigROMmap is written, some controllers
2128 * always read back quadlets 0 and 2 from the config rom to
2129 * the ConfigRomHeader and BusOptions registers on bus reset.
2130 * They shouldn't do that in this initial case where the link
2131 * isn't enabled. This means we have to use the same
2132 * workaround here, setting the bus header to 0 and then write
2133 * the right values in the bus reset tasklet.
2134 */
2135
0bd243c4
KH		 2136 if (config_rom) {
2137 ohci->next_config_rom =
2138 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2139 &ohci->next_config_rom_bus,
2140 GFP_KERNEL);
2141 if (ohci->next_config_rom == NULL)
2142 return -ENOMEM;
ed568912 2143
8e85973e 2144 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2145 } else {
2146 /*
2147 * In the suspend case, config_rom is NULL, which
2148 * means that we just reuse the old config rom.
2149 */
2150 ohci->next_config_rom = ohci->config_rom;
2151 ohci->next_config_rom_bus = ohci->config_rom_bus;
2152 }
ed568912 2153
8e85973e 2154 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2155 ohci->next_config_rom[0] = 0;
2156 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2157 reg_write(ohci, OHCI1394_BusOptions,
2158 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2159 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2160
2161 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2162
262444ee
CL		 2163 if (!(ohci->quirks & QUIRK_NO_MSI))
2164 pci_enable_msi(dev);
ed568912 2165 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2166 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2167 ohci_driver_name, ohci)) {
2168 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2169 pci_disable_msi(dev);
ed568912
KH		 2170 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2171 ohci->config_rom, ohci->config_rom_bus);
2172 return -EIO;
2173 }
2174
148c7866
SR		 2175 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2176 OHCI1394_RQPkt | OHCI1394_RSPkt |
2177 OHCI1394_isochTx | OHCI1394_isochRx |
2178 OHCI1394_postedWriteErr |
2179 OHCI1394_selfIDComplete |
2180 OHCI1394_regAccessFail |
a48777e0 2181 OHCI1394_cycle64Seconds |
f117a3e3
CL		 2182 OHCI1394_cycleInconsistent |
2183 OHCI1394_unrecoverableError |
2184 OHCI1394_cycleTooLong |
148c7866
SR		 2185 OHCI1394_masterIntEnable;
2186 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2187 irqs |= OHCI1394_busReset;
2188 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2189
ed568912
KH		 2190 reg_write(ohci, OHCI1394_HCControlSet,
2191 OHCI1394_HCControl_linkEnable |
2192 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2193
2194 reg_write(ohci, OHCI1394_LinkControlSet,
2195 OHCI1394_LinkControl_rcvSelfID |
2196 OHCI1394_LinkControl_rcvPhyPkt);
2197
2198 ar_context_run(&ohci->ar_request_ctx);
2199 ar_context_run(&ohci->ar_response_ctx); /* also flushes writes */
ed568912 2200
02d37bed
SR		 2201 /* We are ready to go, reset bus to finish initialization. */
2202 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2203
2204 return 0;
2205}
2206
53dca511 2207static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2208 const __be32 *config_rom, size_t length)
ed568912
KH		 2209{
2210 struct fw_ohci *ohci;
2211 unsigned long flags;
ed568912 2212 __be32 *next_config_rom;
f5101d58 2213 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2214
2215 ohci = fw_ohci(card);
2216
c781c06d
KH		 2217 /*
2218 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2219 * mechanism is a bit tricky, but easy enough to use. See
2220 * section 5.5.6 in the OHCI specification.
2221 *
2222 * The OHCI controller caches the new config rom address in a
2223 * shadow register (ConfigROMmapNext) and needs a bus reset
2224 * for the changes to take place. When the bus reset is
2225 * detected, the controller loads the new values for the
2226 * ConfigRomHeader and BusOptions registers from the specified
2227 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2228 * shadow register. All automatically and atomically.
2229 *
2230 * Now, there's a twist to this story. The automatic load of
2231 * ConfigRomHeader and BusOptions doesn't honor the
2232 * noByteSwapData bit, so with a be32 config rom, the
2233 * controller will load be32 values in to these registers
2234 * during the atomic update, even on litte endian
2235 * architectures. The workaround we use is to put a 0 in the
2236 * header quadlet; 0 is endian agnostic and means that the
2237 * config rom isn't ready yet. In the bus reset tasklet we
2238 * then set up the real values for the two registers.
2239 *
2240 * We use ohci->lock to avoid racing with the code that sets
2241 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2242 */
2243
2244 next_config_rom =
2245 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2246 &next_config_rom_bus, GFP_KERNEL);
2247 if (next_config_rom == NULL)
2248 return -ENOMEM;
2249
2250 spin_lock_irqsave(&ohci->lock, flags);
2251
2e053a27
B		 2252 /*
2253 * If there is not an already pending config_rom update,
2254 * push our new allocation into the ohci->next_config_rom
2255 * and then mark the local variable as null so that we
2256 * won't deallocate the new buffer.
2257 *
2258 * OTOH, if there is a pending config_rom update, just
2259 * use that buffer with the new config_rom data, and
2260 * let this routine free the unused DMA allocation.
2261 */
2262
ed568912
KH		 2263 if (ohci->next_config_rom == NULL) {
2264 ohci->next_config_rom = next_config_rom;
2265 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2266 next_config_rom = NULL;
2267 }
ed568912 2268
2e053a27 2269 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2270
2e053a27
B		 2271 ohci->next_header = config_rom[0];
2272 ohci->next_config_rom[0] = 0;
ed568912 2273
2e053a27 2274 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912
KH		 2275
2276 spin_unlock_irqrestore(&ohci->lock, flags);
2277
2e053a27
B		 2278 /* If we didn't use the DMA allocation, delete it. */
2279 if (next_config_rom != NULL)
2280 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2281 next_config_rom, next_config_rom_bus);
2282
c781c06d
KH		 2283 /*
2284 * Now initiate a bus reset to have the changes take
ed568912
KH		 2285 * effect. We clean up the old config rom memory and DMA
2286 * mappings in the bus reset tasklet, since the OHCI
2287 * controller could need to access it before the bus reset
c781c06d
KH		 2288 * takes effect.
2289 */
ed568912 2290
2e053a27
B		 2291 fw_schedule_bus_reset(&ohci->card, true, true);
2292
2293 return 0;
ed568912
KH		 2294}
2295
2296static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2297{
2298 struct fw_ohci *ohci = fw_ohci(card);
2299
2300 at_context_transmit(&ohci->at_request_ctx, packet);
2301}
2302
2303static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2304{
2305 struct fw_ohci *ohci = fw_ohci(card);
2306
2307 at_context_transmit(&ohci->at_response_ctx, packet);
2308}
2309
730c32f5
KH		 2310static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2311{
2312 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2313 struct context *ctx = &ohci->at_request_ctx;
2314 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2315 int ret = -ENOENT;
730c32f5 2316
f319b6a0 2317 tasklet_disable(&ctx->tasklet);
730c32f5 2318
f319b6a0
KH		 2319 if (packet->ack != 0)
2320 goto out;
730c32f5 2321
19593ffd 2322 if (packet->payload_mapped)
1d1dc5e8
SR		 2323 dma_unmap_single(ohci->card.device, packet->payload_bus,
2324 packet->payload_length, DMA_TO_DEVICE);
2325
ad3c0fe8 2326 log_ar_at_event('T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2327 driver_data->packet = NULL;
2328 packet->ack = RCODE_CANCELLED;
2329 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2330 ret = 0;
f319b6a0
KH		 2331 out:
2332 tasklet_enable(&ctx->tasklet);
730c32f5 2333
2dbd7d7e 2334 return ret;
730c32f5
KH		 2335}
2336
53dca511
SR		 2337static int ohci_enable_phys_dma(struct fw_card *card,
2338 int node_id, int generation)
ed568912 2339{
080de8c2
SR		 2340#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2341 return 0;
2342#else
ed568912
KH		 2343 struct fw_ohci *ohci = fw_ohci(card);
2344 unsigned long flags;
2dbd7d7e 2345 int n, ret = 0;
ed568912 2346
c781c06d
KH		 2347 /*
2348 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2349 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2350 */
ed568912
KH		 2351
2352 spin_lock_irqsave(&ohci->lock, flags);
2353
2354 if (ohci->generation != generation) {
2dbd7d7e 2355 ret = -ESTALE;
ed568912
KH		 2356 goto out;
2357 }
2358
c781c06d
KH		 2359 /*
2360 * Note, if the node ID contains a non-local bus ID, physical DMA is
2361 * enabled for _all_ nodes on remote buses.
2362 */
907293d7
SR		 2363
2364 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2365 if (n < 32)
2366 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2367 else
2368 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2369
ed568912 2370 flush_writes(ohci);
ed568912 2371 out:
6cad95fe 2372 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2373
2374 return ret;
080de8c2 2375#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2376}
373b2edd 2377
0fcff4e3 2378static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2379{
60d32970 2380 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2381 unsigned long flags;
2382 u32 value;
60d32970
CL		 2383
2384 switch (csr_offset) {
4ffb7a6a
CL		 2385 case CSR_STATE_CLEAR:
2386 case CSR_STATE_SET:
4ffb7a6a
CL		 2387 if (ohci->is_root &&
2388 (reg_read(ohci, OHCI1394_LinkControlSet) &
2389 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2390 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2391 else
c8a94ded
SR		 2392 value = 0;
2393 if (ohci->csr_state_setclear_abdicate)
2394 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2395
c8a94ded 2396 return value;
4a9bde9b 2397
506f1a31
CL		 2398 case CSR_NODE_IDS:
2399 return reg_read(ohci, OHCI1394_NodeID) << 16;
2400
60d32970
CL		 2401 case CSR_CYCLE_TIME:
2402 return get_cycle_time(ohci);
2403
a48777e0
CL		 2404 case CSR_BUS_TIME:
2405 /*
2406 * We might be called just after the cycle timer has wrapped
2407 * around but just before the cycle64Seconds handler, so we
2408 * better check here, too, if the bus time needs to be updated.
2409 */
2410 spin_lock_irqsave(&ohci->lock, flags);
2411 value = update_bus_time(ohci);
2412 spin_unlock_irqrestore(&ohci->lock, flags);
2413 return value;
2414
27a2329f
CL		 2415 case CSR_BUSY_TIMEOUT:
2416 value = reg_read(ohci, OHCI1394_ATRetries);
2417 return (value >> 4) & 0x0ffff00f;
2418
a1a1132b
CL		 2419 case CSR_PRIORITY_BUDGET:
2420 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2421 (ohci->pri_req_max << 8);
2422
60d32970
CL		 2423 default:
2424 WARN_ON(1);
2425 return 0;
2426 }
b677532b
CL		 2427}
2428
0fcff4e3 2429static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2430{
2431 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2432 unsigned long flags;
d60d7f1d 2433
506f1a31 2434 switch (csr_offset) {
4ffb7a6a 2435 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2436 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2437 reg_write(ohci, OHCI1394_LinkControlClear,
2438 OHCI1394_LinkControl_cycleMaster);
2439 flush_writes(ohci);
2440 }
c8a94ded
SR		 2441 if (value & CSR_STATE_BIT_ABDICATE)
2442 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2443 break;
4a9bde9b 2444
4ffb7a6a
CL		 2445 case CSR_STATE_SET:
2446 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2447 reg_write(ohci, OHCI1394_LinkControlSet,
2448 OHCI1394_LinkControl_cycleMaster);
2449 flush_writes(ohci);
2450 }
c8a94ded
SR		 2451 if (value & CSR_STATE_BIT_ABDICATE)
2452 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2453 break;
d60d7f1d 2454
506f1a31
CL		 2455 case CSR_NODE_IDS:
2456 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2457 flush_writes(ohci);
2458 break;
2459
9ab5071c
CL		 2460 case CSR_CYCLE_TIME:
2461 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2462 reg_write(ohci, OHCI1394_IntEventSet,
2463 OHCI1394_cycleInconsistent);
2464 flush_writes(ohci);
2465 break;
2466
a48777e0
CL		 2467 case CSR_BUS_TIME:
2468 spin_lock_irqsave(&ohci->lock, flags);
2469 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2470 spin_unlock_irqrestore(&ohci->lock, flags);
2471 break;
2472
27a2329f
CL		 2473 case CSR_BUSY_TIMEOUT:
2474 value = (value & 0xf) | ((value & 0xf) << 4) |
2475 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2476 reg_write(ohci, OHCI1394_ATRetries, value);
2477 flush_writes(ohci);
2478 break;
2479
a1a1132b
CL		 2480 case CSR_PRIORITY_BUDGET:
2481 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2482 flush_writes(ohci);
2483 break;
2484
506f1a31
CL		 2485 default:
2486 WARN_ON(1);
2487 break;
2488 }
d60d7f1d
KH		 2489}
2490
1aa292bb
DM		 2491static void copy_iso_headers(struct iso_context *ctx, void *p)
2492{
2493 int i = ctx->header_length;
2494
2495 if (i + ctx->base.header_size > PAGE_SIZE)
2496 return;
2497
2498 /*
2499 * The iso header is byteswapped to little endian by
2500 * the controller, but the remaining header quadlets
2501 * are big endian. We want to present all the headers
2502 * as big endian, so we have to swap the first quadlet.
2503 */
2504 if (ctx->base.header_size > 0)
2505 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2506 if (ctx->base.header_size > 4)
2507 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2508 if (ctx->base.header_size > 8)
2509 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2510 ctx->header_length += ctx->base.header_size;
2511}
2512
a186b4a6
JW		 2513static int handle_ir_packet_per_buffer(struct context *context,
2514 struct descriptor *d,
2515 struct descriptor *last)
2516{
2517 struct iso_context *ctx =
2518 container_of(context, struct iso_context, context);
bcee893c 2519 struct descriptor *pd;
a186b4a6 2520 __le32 *ir_header;
bcee893c 2521 void *p;
a186b4a6 2522
872e330e 2523 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2524 if (pd->transfer_status)
2525 break;
bcee893c 2526 if (pd > last)
a186b4a6
JW		 2527 /* Descriptor(s) not done yet, stop iteration */
2528 return 0;
2529
1aa292bb
DM		 2530 p = last + 1;
2531 copy_iso_headers(ctx, p);
a186b4a6 2532
bcee893c
DM		 2533 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2534 ir_header = (__le32 *) p;
872e330e
SR		 2535 ctx->base.callback.sc(&ctx->base,
2536 le32_to_cpu(ir_header[0]) & 0xffff,
2537 ctx->header_length, ctx->header,
2538 ctx->base.callback_data);
a186b4a6
JW		 2539 ctx->header_length = 0;
2540 }
2541
a186b4a6
JW		 2542 return 1;
2543}
2544
872e330e
SR		 2545/* d == last because each descriptor block is only a single descriptor. */
2546static int handle_ir_buffer_fill(struct context *context,
2547 struct descriptor *d,
2548 struct descriptor *last)
2549{
2550 struct iso_context *ctx =
2551 container_of(context, struct iso_context, context);
2552
2553 if (!last->transfer_status)
2554 /* Descriptor(s) not done yet, stop iteration */
2555 return 0;
2556
2557 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2558 ctx->base.callback.mc(&ctx->base,
2559 le32_to_cpu(last->data_address) +
2560 le16_to_cpu(last->req_count) -
2561 le16_to_cpu(last->res_count),
2562 ctx->base.callback_data);
2563
2564 return 1;
2565}
2566
30200739
KH		 2567static int handle_it_packet(struct context *context,
2568 struct descriptor *d,
2569 struct descriptor *last)
ed568912 2570{
30200739
KH		 2571 struct iso_context *ctx =
2572 container_of(context, struct iso_context, context);
31769cef
JF		 2573 int i;
2574 struct descriptor *pd;
373b2edd 2575
31769cef
JF		 2576 for (pd = d; pd <= last; pd++)
2577 if (pd->transfer_status)
2578 break;
2579 if (pd > last)
2580 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2581 return 0;
2582
31769cef
JF		 2583 i = ctx->header_length;
2584 if (i + 4 < PAGE_SIZE) {
2585 /* Present this value as big-endian to match the receive code */
2586 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2587 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2588 le16_to_cpu(pd->res_count));
2589 ctx->header_length += 4;
2590 }
2591 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2592 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2593 ctx->header_length, ctx->header,
2594 ctx->base.callback_data);
31769cef
JF		 2595 ctx->header_length = 0;
2596 }
30200739 2597 return 1;
ed568912
KH		 2598}
2599
872e330e
SR		 2600static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2601{
2602 u32 hi = channels >> 32, lo = channels;
2603
2604 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2605 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2606 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2607 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2608 mmiowb();
2609 ohci->mc_channels = channels;
2610}
2611
53dca511 2612static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2613 int type, int channel, size_t header_size)
ed568912
KH		 2614{
2615 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2616 struct iso_context *uninitialized_var(ctx);
2617 descriptor_callback_t uninitialized_var(callback);
2618 u64 *uninitialized_var(channels);
2619 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2620 unsigned long flags;
872e330e 2621 int index, ret = -EBUSY;
ed568912 2622
872e330e 2623 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2624
872e330e
SR		 2625 switch (type) {
2626 case FW_ISO_CONTEXT_TRANSMIT:
2627 mask = &ohci->it_context_mask;
30200739 2628 callback = handle_it_packet;
872e330e
SR		 2629 index = ffs(*mask) - 1;
2630 if (index >= 0) {
2631 *mask &= ~(1 << index);
2632 regs = OHCI1394_IsoXmitContextBase(index);
2633 ctx = &ohci->it_context_list[index];
2634 }
2635 break;
2636
2637 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2638 channels = &ohci->ir_context_channels;
872e330e 2639 mask = &ohci->ir_context_mask;
6498ba04 2640 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2641 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2642 if (index >= 0) {
2643 *channels &= ~(1ULL << channel);
2644 *mask &= ~(1 << index);
2645 regs = OHCI1394_IsoRcvContextBase(index);
2646 ctx = &ohci->ir_context_list[index];
2647 }
2648 break;
ed568912 2649
872e330e
SR		 2650 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2651 mask = &ohci->ir_context_mask;
2652 callback = handle_ir_buffer_fill;
2653 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2654 if (index >= 0) {
2655 ohci->mc_allocated = true;
2656 *mask &= ~(1 << index);
2657 regs = OHCI1394_IsoRcvContextBase(index);
2658 ctx = &ohci->ir_context_list[index];
2659 }
2660 break;
2661
2662 default:
2663 index = -1;
2664 ret = -ENOSYS;
4817ed24 2665 }
872e330e 2666
ed568912
KH		 2667 spin_unlock_irqrestore(&ohci->lock, flags);
2668
2669 if (index < 0)
872e330e 2670 return ERR_PTR(ret);
373b2edd 2671
2d826cc5 2672 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2673 ctx->header_length = 0;
2674 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2675 if (ctx->header == NULL) {
2676 ret = -ENOMEM;
9b32d5f3 2677 goto out;
872e330e 2678 }
2dbd7d7e
SR		 2679 ret = context_init(&ctx->context, ohci, regs, callback);
2680 if (ret < 0)
9b32d5f3 2681 goto out_with_header;
ed568912 2682
872e330e
SR		 2683 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2684 set_multichannel_mask(ohci, 0);
2685
ed568912 2686 return &ctx->base;
9b32d5f3
KH		 2687
2688 out_with_header:
2689 free_page((unsigned long)ctx->header);
2690 out:
2691 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2692
2693 switch (type) {
2694 case FW_ISO_CONTEXT_RECEIVE:
2695 *channels |= 1ULL << channel;
2696 break;
2697
2698 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2699 ohci->mc_allocated = false;
2700 break;
2701 }
9b32d5f3 2702 *mask |= 1 << index;
872e330e 2703
9b32d5f3
KH		 2704 spin_unlock_irqrestore(&ohci->lock, flags);
2705
2dbd7d7e 2706 return ERR_PTR(ret);
ed568912
KH		 2707}
2708
eb0306ea
KH		 2709static int ohci_start_iso(struct fw_iso_context *base,
2710 s32 cycle, u32 sync, u32 tags)
ed568912 2711{
373b2edd 2712 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2713 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2714 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2715 int index;
2716
44b74d90
CL		 2717 /* the controller cannot start without any queued packets */
2718 if (ctx->context.last->branch_address == 0)
2719 return -ENODATA;
2720
872e330e
SR		 2721 switch (ctx->base.type) {
2722 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2723 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2724 match = 0;
2725 if (cycle >= 0)
2726 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2727 (cycle & 0x7fff) << 16;
21efb3cf 2728
295e3feb
KH		 2729 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2730 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2731 context_run(&ctx->context, match);
872e330e
SR		 2732 break;
2733
2734 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2735 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2736 /* fall through */
2737 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 2738 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 2739 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2740 if (cycle >= 0) {
2741 match |= (cycle & 0x07fff) << 12;
2742 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2743 }
ed568912 2744
295e3feb
KH		 2745 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2746 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 2747 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 2748 context_run(&ctx->context, control);
dd23736e
ML		 2749
2750 ctx->sync = sync;
2751 ctx->tags = tags;
2752
872e330e 2753 break;
295e3feb 2754 }
ed568912
KH		 2755
2756 return 0;
2757}
2758
b8295668
KH		 2759static int ohci_stop_iso(struct fw_iso_context *base)
2760{
2761 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2762 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 2763 int index;
2764
872e330e
SR		 2765 switch (ctx->base.type) {
2766 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 2767 index = ctx - ohci->it_context_list;
2768 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 2769 break;
2770
2771 case FW_ISO_CONTEXT_RECEIVE:
2772 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 2773 index = ctx - ohci->ir_context_list;
2774 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 2775 break;
b8295668
KH		 2776 }
2777 flush_writes(ohci);
2778 context_stop(&ctx->context);
e81cbebd 2779 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 2780
2781 return 0;
2782}
2783
ed568912
KH		 2784static void ohci_free_iso_context(struct fw_iso_context *base)
2785{
2786 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2787 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 2788 unsigned long flags;
2789 int index;
2790
b8295668
KH		 2791 ohci_stop_iso(base);
2792 context_release(&ctx->context);
9b32d5f3 2793 free_page((unsigned long)ctx->header);
b8295668 2794
ed568912
KH		 2795 spin_lock_irqsave(&ohci->lock, flags);
2796
872e330e
SR		 2797 switch (base->type) {
2798 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 2799 index = ctx - ohci->it_context_list;
ed568912 2800 ohci->it_context_mask |= 1 << index;
872e330e
SR		 2801 break;
2802
2803 case FW_ISO_CONTEXT_RECEIVE:
ed568912 2804 index = ctx - ohci->ir_context_list;
ed568912 2805 ohci->ir_context_mask |= 1 << index;
4817ed24 2806 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 2807 break;
2808
2809 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2810 index = ctx - ohci->ir_context_list;
2811 ohci->ir_context_mask |= 1 << index;
2812 ohci->ir_context_channels |= ohci->mc_channels;
2813 ohci->mc_channels = 0;
2814 ohci->mc_allocated = false;
2815 break;
ed568912 2816 }
ed568912
KH		 2817
2818 spin_unlock_irqrestore(&ohci->lock, flags);
2819}
2820
872e330e
SR		 2821static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2822{
2823 struct fw_ohci *ohci = fw_ohci(base->card);
2824 unsigned long flags;
2825 int ret;
2826
2827 switch (base->type) {
2828 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2829
2830 spin_lock_irqsave(&ohci->lock, flags);
2831
2832 /* Don't allow multichannel to grab other contexts' channels. */
2833 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2834 *channels = ohci->ir_context_channels;
2835 ret = -EBUSY;
2836 } else {
2837 set_multichannel_mask(ohci, *channels);
2838 ret = 0;
2839 }
2840
2841 spin_unlock_irqrestore(&ohci->lock, flags);
2842
2843 break;
2844 default:
2845 ret = -EINVAL;
2846 }
2847
2848 return ret;
2849}
2850
dd23736e
ML		 2851#ifdef CONFIG_PM
2852static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2853{
2854 int i;
2855 struct iso_context *ctx;
2856
2857 for (i = 0 ; i < ohci->n_ir ; i++) {
2858 ctx = &ohci->ir_context_list[i];
693a50b5 2859 if (ctx->context.running)
dd23736e
ML		 2860 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2861 }
2862
2863 for (i = 0 ; i < ohci->n_it ; i++) {
2864 ctx = &ohci->it_context_list[i];
693a50b5 2865 if (ctx->context.running)
dd23736e
ML		 2866 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2867 }
2868}
2869#endif
2870
872e330e
SR		 2871static int queue_iso_transmit(struct iso_context *ctx,
2872 struct fw_iso_packet *packet,
2873 struct fw_iso_buffer *buffer,
2874 unsigned long payload)
ed568912 2875{
30200739 2876 struct descriptor *d, *last, *pd;
ed568912
KH		 2877 struct fw_iso_packet *p;
2878 __le32 *header;
9aad8125 2879 dma_addr_t d_bus, page_bus;
ed568912
KH		 2880 u32 z, header_z, payload_z, irq;
2881 u32 payload_index, payload_end_index, next_page_index;
30200739 2882 int page, end_page, i, length, offset;
ed568912 2883
ed568912 2884 p = packet;
9aad8125 2885 payload_index = payload;
ed568912
KH		 2886
2887 if (p->skip)
2888 z = 1;
2889 else
2890 z = 2;
2891 if (p->header_length > 0)
2892 z++;
2893
2894 /* Determine the first page the payload isn't contained in. */
2895 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2896 if (p->payload_length > 0)
2897 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2898 else
2899 payload_z = 0;
2900
2901 z += payload_z;
2902
2903 /* Get header size in number of descriptors. */
2d826cc5 2904 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 2905
30200739
KH		 2906 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2907 if (d == NULL)
2908 return -ENOMEM;
ed568912
KH		 2909
2910 if (!p->skip) {
a77754a7 2911 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 2912 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 2913 /*
2914 * Link the skip address to this descriptor itself. This causes
2915 * a context to skip a cycle whenever lost cycles or FIFO
2916 * overruns occur, without dropping the data. The application
2917 * should then decide whether this is an error condition or not.
2918 * FIXME: Make the context's cycle-lost behaviour configurable?
2919 */
2920 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 2921
2922 header = (__le32 *) &d[1];
a77754a7
KH		 2923 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2924 IT_HEADER_TAG(p->tag) |
2925 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2926 IT_HEADER_CHANNEL(ctx->base.channel) |
2927 IT_HEADER_SPEED(ctx->base.speed));
ed568912 2928 header[1] =
a77754a7 2929 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 2930 p->payload_length));
2931 }
2932
2933 if (p->header_length > 0) {
2934 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 2935 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 2936 memcpy(&d[z], p->header, p->header_length);
2937 }
2938
2939 pd = d + z - payload_z;
2940 payload_end_index = payload_index + p->payload_length;
2941 for (i = 0; i < payload_z; i++) {
2942 page = payload_index >> PAGE_SHIFT;
2943 offset = payload_index & ~PAGE_MASK;
2944 next_page_index = (page + 1) << PAGE_SHIFT;
2945 length =
2946 min(next_page_index, payload_end_index) - payload_index;
2947 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 2948
2949 page_bus = page_private(buffer->pages[page]);
2950 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912
KH		 2951
2952 payload_index += length;
2953 }
2954
ed568912 2955 if (p->interrupt)
a77754a7 2956 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 2957 else
a77754a7 2958 irq = DESCRIPTOR_NO_IRQ;
ed568912 2959
30200739 2960 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 2961 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2962 DESCRIPTOR_STATUS |
2963 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 2964 irq);
ed568912 2965
30200739 2966 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 2967
2968 return 0;
2969}
373b2edd 2970
872e330e
SR		 2971static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2972 struct fw_iso_packet *packet,
2973 struct fw_iso_buffer *buffer,
2974 unsigned long payload)
a186b4a6 2975{
8c0c0cc2 2976 struct descriptor *d, *pd;
a186b4a6
JW		 2977 dma_addr_t d_bus, page_bus;
2978 u32 z, header_z, rest;
bcee893c
DM		 2979 int i, j, length;
2980 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 2981
2982 /*
1aa292bb
DM		 2983 * The OHCI controller puts the isochronous header and trailer in the
2984 * buffer, so we need at least 8 bytes.
a186b4a6 2985 */
872e330e 2986 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 2987 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 2988
2989 /* Get header size in number of descriptors. */
2990 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2991 page = payload >> PAGE_SHIFT;
2992 offset = payload & ~PAGE_MASK;
872e330e 2993 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 2994
2995 for (i = 0; i < packet_count; i++) {
2996 /* d points to the header descriptor */
bcee893c 2997 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 2998 d = context_get_descriptors(&ctx->context,
bcee893c 2999 z + header_z, &d_bus);
a186b4a6
JW		 3000 if (d == NULL)
3001 return -ENOMEM;
3002
bcee893c
DM		 3003 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3004 DESCRIPTOR_INPUT_MORE);
872e330e 3005 if (packet->skip && i == 0)
bcee893c 3006 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3007 d->req_count = cpu_to_le16(header_size);
3008 d->res_count = d->req_count;
bcee893c 3009 d->transfer_status = 0;
a186b4a6
JW		 3010 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3011
bcee893c 3012 rest = payload_per_buffer;
8c0c0cc2 3013 pd = d;
bcee893c 3014 for (j = 1; j < z; j++) {
8c0c0cc2 3015 pd++;
bcee893c
DM		 3016 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3017 DESCRIPTOR_INPUT_MORE);
3018
3019 if (offset + rest < PAGE_SIZE)
3020 length = rest;
3021 else
3022 length = PAGE_SIZE - offset;
3023 pd->req_count = cpu_to_le16(length);
3024 pd->res_count = pd->req_count;
3025 pd->transfer_status = 0;
3026
3027 page_bus = page_private(buffer->pages[page]);
3028 pd->data_address = cpu_to_le32(page_bus + offset);
3029
3030 offset = (offset + length) & ~PAGE_MASK;
3031 rest -= length;
3032 if (offset == 0)
3033 page++;
3034 }
a186b4a6
JW		 3035 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3036 DESCRIPTOR_INPUT_LAST |
3037 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3038 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3039 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3040
a186b4a6
JW		 3041 context_append(&ctx->context, d, z, header_z);
3042 }
3043
3044 return 0;
3045}
3046
872e330e
SR		 3047static int queue_iso_buffer_fill(struct iso_context *ctx,
3048 struct fw_iso_packet *packet,
3049 struct fw_iso_buffer *buffer,
3050 unsigned long payload)
3051{
3052 struct descriptor *d;
3053 dma_addr_t d_bus, page_bus;
3054 int page, offset, rest, z, i, length;
3055
3056 page = payload >> PAGE_SHIFT;
3057 offset = payload & ~PAGE_MASK;
3058 rest = packet->payload_length;
3059
3060 /* We need one descriptor for each page in the buffer. */
3061 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3062
3063 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3064 return -EFAULT;
3065
3066 for (i = 0; i < z; i++) {
3067 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3068 if (d == NULL)
3069 return -ENOMEM;
3070
3071 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3072 DESCRIPTOR_BRANCH_ALWAYS);
3073 if (packet->skip && i == 0)
3074 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3075 if (packet->interrupt && i == z - 1)
3076 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3077
3078 if (offset + rest < PAGE_SIZE)
3079 length = rest;
3080 else
3081 length = PAGE_SIZE - offset;
3082 d->req_count = cpu_to_le16(length);
3083 d->res_count = d->req_count;
3084 d->transfer_status = 0;
3085
3086 page_bus = page_private(buffer->pages[page]);
3087 d->data_address = cpu_to_le32(page_bus + offset);
3088
3089 rest -= length;
3090 offset = 0;
3091 page++;
3092
3093 context_append(&ctx->context, d, 1, 0);
3094 }
3095
3096 return 0;
3097}
3098
53dca511
SR		 3099static int ohci_queue_iso(struct fw_iso_context *base,
3100 struct fw_iso_packet *packet,
3101 struct fw_iso_buffer *buffer,
3102 unsigned long payload)
295e3feb 3103{
e364cf4e 3104 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3105 unsigned long flags;
872e330e 3106 int ret = -ENOSYS;
e364cf4e 3107
fe5ca634 3108 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3109 switch (base->type) {
3110 case FW_ISO_CONTEXT_TRANSMIT:
3111 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3112 break;
3113 case FW_ISO_CONTEXT_RECEIVE:
3114 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3115 break;
3116 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3117 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3118 break;
3119 }
fe5ca634
DM		 3120 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3121
2dbd7d7e 3122 return ret;
295e3feb
KH		 3123}
3124
13882a82
CL		 3125static void ohci_flush_queue_iso(struct fw_iso_context *base)
3126{
3127 struct context *ctx =
3128 &container_of(base, struct iso_context, base)->context;
3129
3130 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3131 flush_writes(ctx->ohci);
3132}
3133
21ebcd12 3134static const struct fw_card_driver ohci_driver = {
ed568912 3135 .enable = ohci_enable,
02d37bed 3136 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3137 .update_phy_reg = ohci_update_phy_reg,
3138 .set_config_rom = ohci_set_config_rom,
3139 .send_request = ohci_send_request,
3140 .send_response = ohci_send_response,
730c32f5 3141 .cancel_packet = ohci_cancel_packet,
ed568912 3142 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3143 .read_csr = ohci_read_csr,
3144 .write_csr = ohci_write_csr,
ed568912
KH		 3145
3146 .allocate_iso_context = ohci_allocate_iso_context,
3147 .free_iso_context = ohci_free_iso_context,
872e330e 3148 .set_iso_channels = ohci_set_iso_channels,
ed568912 3149 .queue_iso = ohci_queue_iso,
13882a82 3150 .flush_queue_iso = ohci_flush_queue_iso,
69cdb726 3151 .start_iso = ohci_start_iso,
b8295668 3152 .stop_iso = ohci_stop_iso,
ed568912
KH		 3153};
3154
ea8d006b 3155#ifdef CONFIG_PPC_PMAC
5da3dac8 3156static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3157{
ea8d006b
SR		 3158 if (machine_is(powermac)) {
3159 struct device_node *ofn = pci_device_to_OF_node(dev);
3160
3161 if (ofn) {
3162 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3163 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3164 }
3165 }
2ed0f181
SR		 3166}
3167
5da3dac8 3168static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3169{
3170 if (machine_is(powermac)) {
3171 struct device_node *ofn = pci_device_to_OF_node(dev);
3172
3173 if (ofn) {
3174 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3175 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3176 }
3177 }
3178}
3179#else
5da3dac8
SR		 3180static inline void pmac_ohci_on(struct pci_dev *dev) {}
3181static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3182#endif /* CONFIG_PPC_PMAC */
3183
53dca511
SR		 3184static int __devinit pci_probe(struct pci_dev *dev,
3185 const struct pci_device_id *ent)
2ed0f181
SR		 3186{
3187 struct fw_ohci *ohci;
aa0170ff 3188 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3189 u64 guid;
dd23736e 3190 int i, err;
2ed0f181
SR		 3191 size_t size;
3192
2d826cc5 3193 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3194 if (ohci == NULL) {
7007a076
SR		 3195 err = -ENOMEM;
3196 goto fail;
ed568912
KH		 3197 }
3198
3199 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3200
5da3dac8 3201 pmac_ohci_on(dev);
130d5496 3202
d79406dd
KH		 3203 err = pci_enable_device(dev);
3204 if (err) {
7007a076 3205 fw_error("Failed to enable OHCI hardware\n");
bd7dee63 3206 goto fail_free;
ed568912
KH		 3207 }
3208
3209 pci_set_master(dev);
3210 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3211 pci_set_drvdata(dev, ohci);
3212
3213 spin_lock_init(&ohci->lock);
02d37bed 3214 mutex_init(&ohci->phy_reg_mutex);
ed568912
KH		 3215
3216 tasklet_init(&ohci->bus_reset_tasklet,
3217 bus_reset_tasklet, (unsigned long)ohci);
3218
d79406dd
KH		 3219 err = pci_request_region(dev, 0, ohci_driver_name);
3220 if (err) {
ed568912 3221 fw_error("MMIO resource unavailable\n");
d79406dd 3222 goto fail_disable;
ed568912
KH		 3223 }
3224
3225 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3226 if (ohci->registers == NULL) {
3227 fw_error("Failed to remap registers\n");
d79406dd
KH		 3228 err = -ENXIO;
3229 goto fail_iomem;
ed568912
KH		 3230 }
3231
4a635593 3232 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3233 if ((ohci_quirks[i].vendor == dev->vendor) &&
3234 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3235 ohci_quirks[i].device == dev->device) &&
3236 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3237 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3238 ohci->quirks = ohci_quirks[i].flags;
3239 break;
3240 }
3e9cc2f3
SR		 3241 if (param_quirks)
3242 ohci->quirks = param_quirks;
b677532b 3243
ec766a79
CL		 3244 /*
3245 * Because dma_alloc_coherent() allocates at least one page,
3246 * we save space by using a common buffer for the AR request/
3247 * response descriptors and the self IDs buffer.
3248 */
3249 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3250 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3251 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3252 PAGE_SIZE,
3253 &ohci->misc_buffer_bus,
3254 GFP_KERNEL);
3255 if (!ohci->misc_buffer) {
3256 err = -ENOMEM;
3257 goto fail_iounmap;
3258 }
3259
3260 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3261 OHCI1394_AsReqRcvContextControlSet);
3262 if (err < 0)
ec766a79 3263 goto fail_misc_buf;
ed568912 3264
ec766a79 3265 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3266 OHCI1394_AsRspRcvContextControlSet);
3267 if (err < 0)
3268 goto fail_arreq_ctx;
ed568912 3269
c088ab30
CL		 3270 err = context_init(&ohci->at_request_ctx, ohci,
3271 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3272 if (err < 0)
3273 goto fail_arrsp_ctx;
ed568912 3274
c088ab30
CL		 3275 err = context_init(&ohci->at_response_ctx, ohci,
3276 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3277 if (err < 0)
3278 goto fail_atreq_ctx;
ed568912 3279
ed568912 3280 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3281 ohci->ir_context_channels = ~0ULL;
f117a3e3 3282 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3283 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3284 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3285 ohci->n_ir = hweight32(ohci->ir_context_mask);
3286 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3287 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3288
3289 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3290 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3291 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3292 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3293 ohci->n_it = hweight32(ohci->it_context_mask);
3294 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3295 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3296
3297 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3298 err = -ENOMEM;
7007a076 3299 goto fail_contexts;
ed568912
KH		 3300 }
3301
ec766a79
CL		 3302 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3303 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3304
ed568912
KH		 3305 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3306 max_receive = (bus_options >> 12) & 0xf;
3307 link_speed = bus_options & 0x7;
3308 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3309 reg_read(ohci, OHCI1394_GUIDLo);
3310
d79406dd 3311 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3312 if (err)
ec766a79 3313 goto fail_contexts;
ed568912 3314
6fdb2ee2
SR		 3315 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3316 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3317 "%d IR + %d IT contexts, quirks 0x%x\n",
3318 dev_name(&dev->dev), version >> 16, version & 0xff,
dd23736e 3319 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3320
ed568912 3321 return 0;
d79406dd 3322
7007a076 3323 fail_contexts:
d79406dd 3324 kfree(ohci->ir_context_list);
7007a076
SR		 3325 kfree(ohci->it_context_list);
3326 context_release(&ohci->at_response_ctx);
c088ab30 3327 fail_atreq_ctx:
7007a076 3328 context_release(&ohci->at_request_ctx);
c088ab30 3329 fail_arrsp_ctx:
7007a076 3330 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3331 fail_arreq_ctx:
7007a076 3332 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3333 fail_misc_buf:
3334 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3335 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3336 fail_iounmap:
d79406dd
KH		 3337 pci_iounmap(dev, ohci->registers);
3338 fail_iomem:
3339 pci_release_region(dev, 0);
3340 fail_disable:
3341 pci_disable_device(dev);
bd7dee63 3342 fail_free:
d838d2c0 3343 kfree(ohci);
5da3dac8 3344 pmac_ohci_off(dev);
7007a076
SR		 3345 fail:
3346 if (err == -ENOMEM)
3347 fw_error("Out of memory\n");
d79406dd
KH		 3348
3349 return err;
ed568912
KH		 3350}
3351
3352static void pci_remove(struct pci_dev *dev)
3353{
3354 struct fw_ohci *ohci;
3355
3356 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3357 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3358 flush_writes(ohci);
ed568912
KH		 3359 fw_core_remove_card(&ohci->card);
3360
c781c06d
KH		 3361 /*
3362 * FIXME: Fail all pending packets here, now that the upper
3363 * layers can't queue any more.
3364 */
ed568912
KH		 3365
3366 software_reset(ohci);
3367 free_irq(dev->irq, ohci);
a55709ba
JF		 3368
3369 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3370 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3371 ohci->next_config_rom, ohci->next_config_rom_bus);
3372 if (ohci->config_rom)
3373 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3374 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3375 ar_context_release(&ohci->ar_request_ctx);
3376 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3377 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3378 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3379 context_release(&ohci->at_request_ctx);
3380 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3381 kfree(ohci->it_context_list);
3382 kfree(ohci->ir_context_list);
262444ee 3383 pci_disable_msi(dev);
d79406dd
KH		 3384 pci_iounmap(dev, ohci->registers);
3385 pci_release_region(dev, 0);
3386 pci_disable_device(dev);
d838d2c0 3387 kfree(ohci);
5da3dac8 3388 pmac_ohci_off(dev);
ea8d006b 3389
ed568912
KH		 3390 fw_notify("Removed fw-ohci device.\n");
3391}
3392
2aef469a 3393#ifdef CONFIG_PM
2ed0f181 3394static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3395{
2ed0f181 3396 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3397 int err;
3398
3399 software_reset(ohci);
2ed0f181 3400 free_irq(dev->irq, ohci);
262444ee 3401 pci_disable_msi(dev);
2ed0f181 3402 err = pci_save_state(dev);
2aef469a 3403 if (err) {
8a8cea27 3404 fw_error("pci_save_state failed\n");
2aef469a
KH		 3405 return err;
3406 }
2ed0f181 3407 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428
SR		 3408 if (err)
3409 fw_error("pci_set_power_state failed with %d\n", err);
5da3dac8 3410 pmac_ohci_off(dev);
ea8d006b 3411
2aef469a
KH		 3412 return 0;
3413}
3414
2ed0f181 3415static int pci_resume(struct pci_dev *dev)
2aef469a 3416{
2ed0f181 3417 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3418 int err;
3419
5da3dac8 3420 pmac_ohci_on(dev);
2ed0f181
SR		 3421 pci_set_power_state(dev, PCI_D0);
3422 pci_restore_state(dev);
3423 err = pci_enable_device(dev);
2aef469a 3424 if (err) {
8a8cea27 3425 fw_error("pci_enable_device failed\n");
2aef469a
KH		 3426 return err;
3427 }
3428
8662b6b0
ML		 3429 /* Some systems don't setup GUID register on resume from ram */
3430 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3431 !reg_read(ohci, OHCI1394_GUIDHi)) {
3432 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3433 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3434 }
3435
dd23736e 3436 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3437 if (err)
3438 return err;
3439
3440 ohci_resume_iso_dma(ohci);
693a50b5 3441
dd23736e 3442 return 0;
2aef469a
KH		 3443}
3444#endif
3445
a67483d2 3446static const struct pci_device_id pci_table[] = {
ed568912
KH		 3447 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3448 { }
3449};
3450
3451MODULE_DEVICE_TABLE(pci, pci_table);
3452
3453static struct pci_driver fw_ohci_pci_driver = {
3454 .name = ohci_driver_name,
3455 .id_table = pci_table,
3456 .probe = pci_probe,
3457 .remove = pci_remove,
2aef469a
KH		 3458#ifdef CONFIG_PM
3459 .resume = pci_resume,
3460 .suspend = pci_suspend,
3461#endif
ed568912
KH		 3462};
3463
3464MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3465MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3466MODULE_LICENSE("GPL");
3467
1e4c7b0d
OH		 3468/* Provide a module alias so root-on-sbp2 initrds don't break. */
3469#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3470MODULE_ALIAS("ohci1394");
3471#endif
3472
ed568912
KH		 3473static int __init fw_ohci_init(void)
3474{
3475 return pci_register_driver(&fw_ohci_pci_driver);
3476}
3477
3478static void __exit fw_ohci_cleanup(void)
3479{
3480 pci_unregister_driver(&fw_ohci_pci_driver);
3481}
3482
3483module_init(fw_ohci_init);
3484module_exit(fw_ohci_cleanup);
kernel source for telekom puls (alcatel/mediatek)