Merge branch 'for_linus' of git://cavan.codon.org.uk/platform-drivers-x86
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / firewire / core-iso.c
CommitLineData
c781c06d 1/*
b1bda4cd
JFSR
2 * Isochronous I/O functionality:
3 * - Isochronous DMA context management
4 * - Isochronous bus resource management (channels, bandwidth), client side
3038e353 5 *
3038e353
KH
6 * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
3038e353 23#include <linux/dma-mapping.h>
b1bda4cd 24#include <linux/errno.h>
77c9a5da 25#include <linux/firewire.h>
b1bda4cd
JFSR
26#include <linux/firewire-constants.h>
27#include <linux/kernel.h>
3038e353 28#include <linux/mm.h>
5a0e3ad6 29#include <linux/slab.h>
b1bda4cd
JFSR
30#include <linux/spinlock.h>
31#include <linux/vmalloc.h>
823467e5 32#include <linux/export.h>
3038e353 33
e8ca9702
SR
34#include <asm/byteorder.h>
35
77c9a5da 36#include "core.h"
b1bda4cd
JFSR
37
38/*
39 * Isochronous DMA context management
40 */
3038e353 41
0b6c4857 42int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count)
3038e353 43{
0b6c4857 44 int i;
9aad8125 45
0b6c4857
SR
46 buffer->page_count = 0;
47 buffer->page_count_mapped = 0;
9aad8125
KH
48 buffer->pages = kmalloc(page_count * sizeof(buffer->pages[0]),
49 GFP_KERNEL);
50 if (buffer->pages == NULL)
0b6c4857 51 return -ENOMEM;
9aad8125 52
0b6c4857 53 for (i = 0; i < page_count; i++) {
68be3fa1 54 buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
9aad8125 55 if (buffer->pages[i] == NULL)
0b6c4857
SR
56 break;
57 }
58 buffer->page_count = i;
59 if (i < page_count) {
60 fw_iso_buffer_destroy(buffer, NULL);
61 return -ENOMEM;
62 }
373b2edd 63
0b6c4857
SR
64 return 0;
65}
66
67int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card,
68 enum dma_data_direction direction)
69{
70 dma_addr_t address;
71 int i;
72
73 buffer->direction = direction;
74
75 for (i = 0; i < buffer->page_count; i++) {
9aad8125
KH
76 address = dma_map_page(card->device, buffer->pages[i],
77 0, PAGE_SIZE, direction);
0b6c4857
SR
78 if (dma_mapping_error(card->device, address))
79 break;
80
9aad8125 81 set_page_private(buffer->pages[i], address);
3038e353 82 }
0b6c4857
SR
83 buffer->page_count_mapped = i;
84 if (i < buffer->page_count)
85 return -ENOMEM;
3038e353
KH
86
87 return 0;
0b6c4857 88}
82eff9db 89
0b6c4857
SR
90int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
91 int page_count, enum dma_data_direction direction)
92{
93 int ret;
94
95 ret = fw_iso_buffer_alloc(buffer, page_count);
96 if (ret < 0)
97 return ret;
e1eff7a3 98
0b6c4857
SR
99 ret = fw_iso_buffer_map_dma(buffer, card, direction);
100 if (ret < 0)
101 fw_iso_buffer_destroy(buffer, card);
102
103 return ret;
9aad8125 104}
c76acec6 105EXPORT_SYMBOL(fw_iso_buffer_init);
9aad8125 106
0b6c4857
SR
107int fw_iso_buffer_map_vma(struct fw_iso_buffer *buffer,
108 struct vm_area_struct *vma)
9aad8125
KH
109{
110 unsigned long uaddr;
e1eff7a3 111 int i, err;
9aad8125
KH
112
113 uaddr = vma->vm_start;
114 for (i = 0; i < buffer->page_count; i++) {
e1eff7a3
SR
115 err = vm_insert_page(vma, uaddr, buffer->pages[i]);
116 if (err)
117 return err;
118
9aad8125
KH
119 uaddr += PAGE_SIZE;
120 }
121
122 return 0;
3038e353
KH
123}
124
9aad8125
KH
125void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer,
126 struct fw_card *card)
3038e353
KH
127{
128 int i;
9aad8125 129 dma_addr_t address;
3038e353 130
0b6c4857 131 for (i = 0; i < buffer->page_count_mapped; i++) {
9aad8125
KH
132 address = page_private(buffer->pages[i]);
133 dma_unmap_page(card->device, address,
29ad14cd 134 PAGE_SIZE, buffer->direction);
9aad8125 135 }
0b6c4857
SR
136 for (i = 0; i < buffer->page_count; i++)
137 __free_page(buffer->pages[i]);
3038e353 138
9aad8125
KH
139 kfree(buffer->pages);
140 buffer->pages = NULL;
0b6c4857
SR
141 buffer->page_count = 0;
142 buffer->page_count_mapped = 0;
3038e353 143}
c76acec6 144EXPORT_SYMBOL(fw_iso_buffer_destroy);
3038e353 145
872e330e
SR
146/* Convert DMA address to offset into virtually contiguous buffer. */
147size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed)
148{
9d23f9e9 149 size_t i;
872e330e
SR
150 dma_addr_t address;
151 ssize_t offset;
152
153 for (i = 0; i < buffer->page_count; i++) {
154 address = page_private(buffer->pages[i]);
155 offset = (ssize_t)completed - (ssize_t)address;
156 if (offset > 0 && offset <= PAGE_SIZE)
157 return (i << PAGE_SHIFT) + offset;
158 }
159
160 return 0;
161}
162
53dca511
SR
163struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
164 int type, int channel, int speed, size_t header_size,
165 fw_iso_callback_t callback, void *callback_data)
3038e353
KH
166{
167 struct fw_iso_context *ctx;
3038e353 168
4817ed24
SR
169 ctx = card->driver->allocate_iso_context(card,
170 type, channel, header_size);
3038e353
KH
171 if (IS_ERR(ctx))
172 return ctx;
173
174 ctx->card = card;
175 ctx->type = type;
21efb3cf
KH
176 ctx->channel = channel;
177 ctx->speed = speed;
295e3feb 178 ctx->header_size = header_size;
872e330e 179 ctx->callback.sc = callback;
3038e353
KH
180 ctx->callback_data = callback_data;
181
3038e353
KH
182 return ctx;
183}
c76acec6 184EXPORT_SYMBOL(fw_iso_context_create);
3038e353
KH
185
186void fw_iso_context_destroy(struct fw_iso_context *ctx)
187{
872e330e 188 ctx->card->driver->free_iso_context(ctx);
3038e353 189}
c76acec6 190EXPORT_SYMBOL(fw_iso_context_destroy);
3038e353 191
53dca511
SR
192int fw_iso_context_start(struct fw_iso_context *ctx,
193 int cycle, int sync, int tags)
3038e353 194{
eb0306ea 195 return ctx->card->driver->start_iso(ctx, cycle, sync, tags);
3038e353 196}
c76acec6 197EXPORT_SYMBOL(fw_iso_context_start);
3038e353 198
872e330e
SR
199int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels)
200{
201 return ctx->card->driver->set_iso_channels(ctx, channels);
202}
203
53dca511
SR
204int fw_iso_context_queue(struct fw_iso_context *ctx,
205 struct fw_iso_packet *packet,
206 struct fw_iso_buffer *buffer,
207 unsigned long payload)
3038e353 208{
872e330e 209 return ctx->card->driver->queue_iso(ctx, packet, buffer, payload);
3038e353 210}
c76acec6 211EXPORT_SYMBOL(fw_iso_context_queue);
b8295668 212
13882a82
CL
213void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
214{
215 ctx->card->driver->flush_queue_iso(ctx);
216}
217EXPORT_SYMBOL(fw_iso_context_queue_flush);
218
d1bbd209
CL
219int fw_iso_context_flush_completions(struct fw_iso_context *ctx)
220{
221 return ctx->card->driver->flush_iso_completions(ctx);
222}
223EXPORT_SYMBOL(fw_iso_context_flush_completions);
224
53dca511 225int fw_iso_context_stop(struct fw_iso_context *ctx)
b8295668
KH
226{
227 return ctx->card->driver->stop_iso(ctx);
228}
c76acec6 229EXPORT_SYMBOL(fw_iso_context_stop);
b1bda4cd
JFSR
230
231/*
232 * Isochronous bus resource management (channels, bandwidth), client side
233 */
234
235static int manage_bandwidth(struct fw_card *card, int irm_id, int generation,
f30e6d3e 236 int bandwidth, bool allocate)
b1bda4cd 237{
b1bda4cd 238 int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0;
f30e6d3e 239 __be32 data[2];
b1bda4cd
JFSR
240
241 /*
242 * On a 1394a IRM with low contention, try < 1 is enough.
243 * On a 1394-1995 IRM, we need at least try < 2.
244 * Let's just do try < 5.
245 */
246 for (try = 0; try < 5; try++) {
247 new = allocate ? old - bandwidth : old + bandwidth;
248 if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL)
d6372b6e 249 return -EBUSY;
b1bda4cd
JFSR
250
251 data[0] = cpu_to_be32(old);
252 data[1] = cpu_to_be32(new);
253 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
254 irm_id, generation, SCODE_100,
255 CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
1821bc19 256 data, 8)) {
b1bda4cd
JFSR
257 case RCODE_GENERATION:
258 /* A generation change frees all bandwidth. */
259 return allocate ? -EAGAIN : bandwidth;
260
261 case RCODE_COMPLETE:
262 if (be32_to_cpup(data) == old)
263 return bandwidth;
264
265 old = be32_to_cpup(data);
266 /* Fall through. */
267 }
268 }
269
270 return -EIO;
271}
272
273static int manage_channel(struct fw_card *card, int irm_id, int generation,
f30e6d3e 274 u32 channels_mask, u64 offset, bool allocate)
b1bda4cd 275{
5aaffc65 276 __be32 bit, all, old;
f30e6d3e 277 __be32 data[2];
5aaffc65 278 int channel, ret = -EIO, retry = 5;
b1bda4cd 279
5d9cb7d2
SR
280 old = all = allocate ? cpu_to_be32(~0) : 0;
281
5aaffc65
CL
282 for (channel = 0; channel < 32; channel++) {
283 if (!(channels_mask & 1 << channel))
b1bda4cd
JFSR
284 continue;
285
d6372b6e
CL
286 ret = -EBUSY;
287
5aaffc65
CL
288 bit = cpu_to_be32(1 << (31 - channel));
289 if ((old & bit) != (all & bit))
b1bda4cd
JFSR
290 continue;
291
292 data[0] = old;
5aaffc65 293 data[1] = old ^ bit;
b1bda4cd
JFSR
294 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
295 irm_id, generation, SCODE_100,
1821bc19 296 offset, data, 8)) {
b1bda4cd
JFSR
297 case RCODE_GENERATION:
298 /* A generation change frees all channels. */
5aaffc65 299 return allocate ? -EAGAIN : channel;
b1bda4cd
JFSR
300
301 case RCODE_COMPLETE:
302 if (data[0] == old)
5aaffc65 303 return channel;
b1bda4cd
JFSR
304
305 old = data[0];
306
307 /* Is the IRM 1394a-2000 compliant? */
5aaffc65 308 if ((data[0] & bit) == (data[1] & bit))
b1bda4cd
JFSR
309 continue;
310
311 /* 1394-1995 IRM, fall through to retry. */
312 default:
3a1f0a0e
CL
313 if (retry) {
314 retry--;
5aaffc65 315 channel--;
d6372b6e
CL
316 } else {
317 ret = -EIO;
3a1f0a0e 318 }
b1bda4cd
JFSR
319 }
320 }
321
d6372b6e 322 return ret;
b1bda4cd
JFSR
323}
324
325static void deallocate_channel(struct fw_card *card, int irm_id,
f30e6d3e 326 int generation, int channel)
b1bda4cd 327{
5d9cb7d2 328 u32 mask;
b1bda4cd
JFSR
329 u64 offset;
330
5d9cb7d2 331 mask = channel < 32 ? 1 << channel : 1 << (channel - 32);
b1bda4cd
JFSR
332 offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
333 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
334
f30e6d3e 335 manage_channel(card, irm_id, generation, mask, offset, false);
b1bda4cd
JFSR
336}
337
338/**
656b7afd 339 * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth
b1bda4cd
JFSR
340 *
341 * In parameters: card, generation, channels_mask, bandwidth, allocate
342 * Out parameters: channel, bandwidth
343 * This function blocks (sleeps) during communication with the IRM.
5d9cb7d2 344 *
b1bda4cd 345 * Allocates or deallocates at most one channel out of channels_mask.
5d9cb7d2
SR
346 * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
347 * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for
348 * channel 0 and LSB for channel 63.)
349 * Allocates or deallocates as many bandwidth allocation units as specified.
b1bda4cd
JFSR
350 *
351 * Returns channel < 0 if no channel was allocated or deallocated.
352 * Returns bandwidth = 0 if no bandwidth was allocated or deallocated.
353 *
354 * If generation is stale, deallocations succeed but allocations fail with
355 * channel = -EAGAIN.
356 *
5d9cb7d2 357 * If channel allocation fails, no bandwidth will be allocated either.
b1bda4cd 358 * If bandwidth allocation fails, no channel will be allocated either.
5d9cb7d2
SR
359 * But deallocations of channel and bandwidth are tried independently
360 * of each other's success.
b1bda4cd
JFSR
361 */
362void fw_iso_resource_manage(struct fw_card *card, int generation,
363 u64 channels_mask, int *channel, int *bandwidth,
f30e6d3e 364 bool allocate)
b1bda4cd 365{
5d9cb7d2
SR
366 u32 channels_hi = channels_mask; /* channels 31...0 */
367 u32 channels_lo = channels_mask >> 32; /* channels 63...32 */
b1bda4cd
JFSR
368 int irm_id, ret, c = -EINVAL;
369
370 spin_lock_irq(&card->lock);
371 irm_id = card->irm_node->node_id;
372 spin_unlock_irq(&card->lock);
373
374 if (channels_hi)
375 c = manage_channel(card, irm_id, generation, channels_hi,
6fdc0370 376 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
f30e6d3e 377 allocate);
b1bda4cd
JFSR
378 if (channels_lo && c < 0) {
379 c = manage_channel(card, irm_id, generation, channels_lo,
6fdc0370 380 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
f30e6d3e 381 allocate);
b1bda4cd
JFSR
382 if (c >= 0)
383 c += 32;
384 }
385 *channel = c;
386
5d9cb7d2 387 if (allocate && channels_mask != 0 && c < 0)
b1bda4cd
JFSR
388 *bandwidth = 0;
389
390 if (*bandwidth == 0)
391 return;
392
f30e6d3e 393 ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate);
b1bda4cd
JFSR
394 if (ret < 0)
395 *bandwidth = 0;
396
cf36df6b
CL
397 if (allocate && ret < 0) {
398 if (c >= 0)
f30e6d3e 399 deallocate_channel(card, irm_id, generation, c);
b1bda4cd
JFSR
400 *channel = ret;
401 }
402}
31ef9134 403EXPORT_SYMBOL(fw_iso_resource_manage);