Commit | Line | Data |
---|---|---|
b70ef010 | 1 | #include <linux/module.h> |
888ab8e6 BP |
2 | #include <linux/slab.h> |
3 | ||
47ca08a4 | 4 | #include "mce_amd.h" |
b52401ce | 5 | |
888ab8e6 BP |
6 | static struct amd_decoder_ops *fam_ops; |
7 | ||
2be64bfa | 8 | static u8 xec_mask = 0xf; |
5ce88f6e BP |
9 | static u8 nb_err_cpumask = 0xf; |
10 | ||
549d042d | 11 | static bool report_gart_errors; |
b0b07a2b | 12 | static void (*nb_bus_decoder)(int node_id, struct mce *m); |
549d042d BP |
13 | |
14 | void amd_report_gart_errors(bool v) | |
15 | { | |
16 | report_gart_errors = v; | |
17 | } | |
18 | EXPORT_SYMBOL_GPL(amd_report_gart_errors); | |
19 | ||
b0b07a2b | 20 | void amd_register_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
21 | { |
22 | nb_bus_decoder = f; | |
23 | } | |
24 | EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); | |
25 | ||
b0b07a2b | 26 | void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
27 | { |
28 | if (nb_bus_decoder) { | |
29 | WARN_ON(nb_bus_decoder != f); | |
30 | ||
31 | nb_bus_decoder = NULL; | |
32 | } | |
33 | } | |
34 | EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |
35 | ||
b52401ce DT |
36 | /* |
37 | * string representation for the different MCA reported error types, see F3x48 | |
38 | * or MSR0000_0411. | |
39 | */ | |
6337583d BP |
40 | |
41 | /* transaction type */ | |
0f08669e | 42 | static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
b52401ce | 43 | |
6337583d | 44 | /* cache level */ |
0f08669e | 45 | static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
b52401ce | 46 | |
6337583d | 47 | /* memory transaction type */ |
0f08669e | 48 | static const char * const rrrr_msgs[] = { |
6337583d | 49 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
b52401ce DT |
50 | }; |
51 | ||
6337583d | 52 | /* participating processor */ |
ebe2aea8 | 53 | const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
b70ef010 | 54 | EXPORT_SYMBOL_GPL(pp_msgs); |
b52401ce | 55 | |
6337583d | 56 | /* request timeout */ |
0f08669e | 57 | static const char * const to_msgs[] = { "no timeout", "timed out" }; |
b52401ce | 58 | |
6337583d | 59 | /* memory or i/o */ |
0f08669e | 60 | static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
b52401ce | 61 | |
980eec8b | 62 | /* internal error type */ |
0f08669e | 63 | static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; |
980eec8b | 64 | |
f05c41a9 | 65 | static const char * const f15h_mc1_mce_desc[] = { |
86039cd4 BP |
66 | "UC during a demand linefill from L2", |
67 | "Parity error during data load from IC", | |
68 | "Parity error for IC valid bit", | |
69 | "Main tag parity error", | |
70 | "Parity error in prediction queue", | |
71 | "PFB data/address parity error", | |
72 | "Parity error in the branch status reg", | |
73 | "PFB promotion address error", | |
74 | "Tag error during probe/victimization", | |
75 | "Parity error for IC probe tag valid bit", | |
76 | "PFB non-cacheable bit parity error", | |
77 | "PFB valid bit parity error", /* xec = 0xd */ | |
6c1173a6 | 78 | "Microcode Patch Buffer", /* xec = 010 */ |
86039cd4 BP |
79 | "uop queue", |
80 | "insn buffer", | |
81 | "predecode buffer", | |
82 | "fetch address FIFO" | |
83 | }; | |
84 | ||
f05c41a9 | 85 | static const char * const f15h_mc2_mce_desc[] = { |
70fdb494 BP |
86 | "Fill ECC error on data fills", /* xec = 0x4 */ |
87 | "Fill parity error on insn fills", | |
88 | "Prefetcher request FIFO parity error", | |
89 | "PRQ address parity error", | |
90 | "PRQ data parity error", | |
91 | "WCC Tag ECC error", | |
92 | "WCC Data ECC error", | |
93 | "WCB Data parity error", | |
b64a99c1 | 94 | "VB Data ECC or parity error", |
70fdb494 BP |
95 | "L2 Tag ECC error", /* xec = 0x10 */ |
96 | "Hard L2 Tag ECC error", | |
97 | "Multiple hits on L2 tag", | |
98 | "XAB parity error", | |
99 | "PRB address parity error" | |
100 | }; | |
101 | ||
f05c41a9 | 102 | static const char * const mc4_mce_desc[] = { |
68782673 BP |
103 | "DRAM ECC error detected on the NB", |
104 | "CRC error detected on HT link", | |
105 | "Link-defined sync error packets detected on HT link", | |
106 | "HT Master abort", | |
107 | "HT Target abort", | |
108 | "Invalid GART PTE entry during GART table walk", | |
109 | "Unsupported atomic RMW received from an IO link", | |
110 | "Watchdog timeout due to lack of progress", | |
111 | "DRAM ECC error detected on the NB", | |
112 | "SVM DMA Exclusion Vector error", | |
113 | "HT data error detected on link", | |
114 | "Protocol error (link, L3, probe filter)", | |
115 | "NB internal arrays parity error", | |
116 | "DRAM addr/ctl signals parity error", | |
117 | "IO link transmission error", | |
118 | "L3 data cache ECC error", /* xec = 0x1c */ | |
119 | "L3 cache tag error", | |
120 | "L3 LRU parity bits error", | |
121 | "ECC Error in the Probe Filter directory" | |
122 | }; | |
123 | ||
f05c41a9 | 124 | static const char * const mc5_mce_desc[] = { |
8259a7e5 BP |
125 | "CPU Watchdog timer expire", |
126 | "Wakeup array dest tag", | |
127 | "AG payload array", | |
128 | "EX payload array", | |
129 | "IDRF array", | |
130 | "Retire dispatch queue", | |
131 | "Mapper checkpoint array", | |
132 | "Physical register file EX0 port", | |
133 | "Physical register file EX1 port", | |
134 | "Physical register file AG0 port", | |
135 | "Physical register file AG1 port", | |
136 | "Flag register file", | |
ae615b4b | 137 | "DE error occurred" |
8259a7e5 BP |
138 | }; |
139 | ||
f05c41a9 | 140 | static bool f12h_mc0_mce(u16 ec, u8 xec) |
51966241 | 141 | { |
888ab8e6 | 142 | bool ret = false; |
51966241 | 143 | |
888ab8e6 | 144 | if (MEM_ERROR(ec)) { |
62452882 | 145 | u8 ll = LL(ec); |
888ab8e6 | 146 | ret = true; |
51966241 | 147 | |
888ab8e6 BP |
148 | if (ll == LL_L2) |
149 | pr_cont("during L1 linefill from L2.\n"); | |
150 | else if (ll == LL_L1) | |
62452882 | 151 | pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); |
888ab8e6 BP |
152 | else |
153 | ret = false; | |
154 | } | |
155 | return ret; | |
156 | } | |
51966241 | 157 | |
f05c41a9 | 158 | static bool f10h_mc0_mce(u16 ec, u8 xec) |
9be0bb10 | 159 | { |
62452882 | 160 | if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { |
9be0bb10 BP |
161 | pr_cont("during data scrub.\n"); |
162 | return true; | |
163 | } | |
f05c41a9 | 164 | return f12h_mc0_mce(ec, xec); |
9be0bb10 BP |
165 | } |
166 | ||
f05c41a9 | 167 | static bool k8_mc0_mce(u16 ec, u8 xec) |
888ab8e6 BP |
168 | { |
169 | if (BUS_ERROR(ec)) { | |
170 | pr_cont("during system linefill.\n"); | |
171 | return true; | |
172 | } | |
51966241 | 173 | |
f05c41a9 | 174 | return f10h_mc0_mce(ec, xec); |
888ab8e6 BP |
175 | } |
176 | ||
980eec8b | 177 | static bool cat_mc0_mce(u16 ec, u8 xec) |
888ab8e6 | 178 | { |
62452882 | 179 | u8 r4 = R4(ec); |
888ab8e6 BP |
180 | bool ret = true; |
181 | ||
182 | if (MEM_ERROR(ec)) { | |
183 | ||
62452882 | 184 | if (TT(ec) != TT_DATA || LL(ec) != LL_L1) |
888ab8e6 BP |
185 | return false; |
186 | ||
187 | switch (r4) { | |
188 | case R4_DRD: | |
189 | case R4_DWR: | |
190 | pr_cont("Data/Tag parity error due to %s.\n", | |
191 | (r4 == R4_DRD ? "load/hw prf" : "store")); | |
192 | break; | |
193 | case R4_EVICT: | |
194 | pr_cont("Copyback parity error on a tag miss.\n"); | |
195 | break; | |
196 | case R4_SNOOP: | |
197 | pr_cont("Tag parity error during snoop.\n"); | |
198 | break; | |
199 | default: | |
200 | ret = false; | |
201 | } | |
202 | } else if (BUS_ERROR(ec)) { | |
203 | ||
62452882 | 204 | if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) |
888ab8e6 BP |
205 | return false; |
206 | ||
207 | pr_cont("System read data error on a "); | |
208 | ||
209 | switch (r4) { | |
210 | case R4_RD: | |
211 | pr_cont("TLB reload.\n"); | |
212 | break; | |
213 | case R4_DWR: | |
214 | pr_cont("store.\n"); | |
215 | break; | |
216 | case R4_DRD: | |
217 | pr_cont("load.\n"); | |
218 | break; | |
219 | default: | |
220 | ret = false; | |
221 | } | |
222 | } else { | |
223 | ret = false; | |
224 | } | |
225 | ||
226 | return ret; | |
227 | } | |
228 | ||
f05c41a9 | 229 | static bool f15h_mc0_mce(u16 ec, u8 xec) |
25a4f8b0 BP |
230 | { |
231 | bool ret = true; | |
232 | ||
233 | if (MEM_ERROR(ec)) { | |
234 | ||
235 | switch (xec) { | |
236 | case 0x0: | |
237 | pr_cont("Data Array access error.\n"); | |
238 | break; | |
239 | ||
240 | case 0x1: | |
241 | pr_cont("UC error during a linefill from L2/NB.\n"); | |
242 | break; | |
243 | ||
244 | case 0x2: | |
245 | case 0x11: | |
246 | pr_cont("STQ access error.\n"); | |
247 | break; | |
248 | ||
249 | case 0x3: | |
250 | pr_cont("SCB access error.\n"); | |
251 | break; | |
252 | ||
253 | case 0x10: | |
254 | pr_cont("Tag error.\n"); | |
255 | break; | |
256 | ||
257 | case 0x12: | |
258 | pr_cont("LDQ access error.\n"); | |
259 | break; | |
260 | ||
261 | default: | |
262 | ret = false; | |
263 | } | |
264 | } else if (BUS_ERROR(ec)) { | |
265 | ||
266 | if (!xec) | |
344f0a06 | 267 | pr_cont("System Read Data Error.\n"); |
25a4f8b0 | 268 | else |
344f0a06 | 269 | pr_cont(" Internal error condition type %d.\n", xec); |
25a4f8b0 BP |
270 | } else |
271 | ret = false; | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
f05c41a9 | 276 | static void decode_mc0_mce(struct mce *m) |
888ab8e6 | 277 | { |
62452882 BP |
278 | u16 ec = EC(m->status); |
279 | u8 xec = XEC(m->status, xec_mask); | |
888ab8e6 | 280 | |
f05c41a9 | 281 | pr_emerg(HW_ERR "MC0 Error: "); |
888ab8e6 BP |
282 | |
283 | /* TLB error signatures are the same across families */ | |
284 | if (TLB_ERROR(ec)) { | |
62452882 | 285 | if (TT(ec) == TT_DATA) { |
888ab8e6 | 286 | pr_cont("%s TLB %s.\n", LL_MSG(ec), |
25a4f8b0 BP |
287 | ((xec == 2) ? "locked miss" |
288 | : (xec ? "multimatch" : "parity"))); | |
888ab8e6 BP |
289 | return; |
290 | } | |
f05c41a9 | 291 | } else if (fam_ops->mc0_mce(ec, xec)) |
25a4f8b0 BP |
292 | ; |
293 | else | |
f05c41a9 | 294 | pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); |
51966241 BP |
295 | } |
296 | ||
f05c41a9 | 297 | static bool k8_mc1_mce(u16 ec, u8 xec) |
ab5535e7 | 298 | { |
62452882 | 299 | u8 ll = LL(ec); |
dd53bce4 | 300 | bool ret = true; |
ab5535e7 | 301 | |
dd53bce4 BP |
302 | if (!MEM_ERROR(ec)) |
303 | return false; | |
ab5535e7 | 304 | |
dd53bce4 BP |
305 | if (ll == 0x2) |
306 | pr_cont("during a linefill from L2.\n"); | |
307 | else if (ll == 0x1) { | |
62452882 | 308 | switch (R4(ec)) { |
dd53bce4 BP |
309 | case R4_IRD: |
310 | pr_cont("Parity error during data load.\n"); | |
311 | break; | |
ab5535e7 | 312 | |
dd53bce4 BP |
313 | case R4_EVICT: |
314 | pr_cont("Copyback Parity/Victim error.\n"); | |
315 | break; | |
316 | ||
317 | case R4_SNOOP: | |
318 | pr_cont("Tag Snoop error.\n"); | |
319 | break; | |
320 | ||
321 | default: | |
322 | ret = false; | |
323 | break; | |
324 | } | |
ab5535e7 | 325 | } else |
dd53bce4 | 326 | ret = false; |
ab5535e7 | 327 | |
dd53bce4 BP |
328 | return ret; |
329 | } | |
330 | ||
980eec8b | 331 | static bool cat_mc1_mce(u16 ec, u8 xec) |
dd53bce4 | 332 | { |
62452882 | 333 | u8 r4 = R4(ec); |
dd53bce4 | 334 | bool ret = true; |
ab5535e7 | 335 | |
980eec8b JS |
336 | if (!MEM_ERROR(ec)) |
337 | return false; | |
338 | ||
339 | if (TT(ec) != TT_INSTR) | |
340 | return false; | |
341 | ||
342 | if (r4 == R4_IRD) | |
343 | pr_cont("Data/tag array parity error for a tag hit.\n"); | |
344 | else if (r4 == R4_SNOOP) | |
345 | pr_cont("Tag error during snoop/victimization.\n"); | |
346 | else if (xec == 0x0) | |
347 | pr_cont("Tag parity error from victim castout.\n"); | |
348 | else if (xec == 0x2) | |
349 | pr_cont("Microcode patch RAM parity error.\n"); | |
350 | else | |
351 | ret = false; | |
dd53bce4 | 352 | |
dd53bce4 BP |
353 | return ret; |
354 | } | |
355 | ||
f05c41a9 | 356 | static bool f15h_mc1_mce(u16 ec, u8 xec) |
86039cd4 BP |
357 | { |
358 | bool ret = true; | |
359 | ||
360 | if (!MEM_ERROR(ec)) | |
361 | return false; | |
362 | ||
363 | switch (xec) { | |
364 | case 0x0 ... 0xa: | |
f05c41a9 | 365 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); |
86039cd4 BP |
366 | break; |
367 | ||
368 | case 0xd: | |
f05c41a9 | 369 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); |
86039cd4 BP |
370 | break; |
371 | ||
6c1173a6 | 372 | case 0x10: |
f05c41a9 | 373 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); |
6c1173a6 BP |
374 | break; |
375 | ||
376 | case 0x11 ... 0x14: | |
f05c41a9 | 377 | pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); |
86039cd4 BP |
378 | break; |
379 | ||
380 | default: | |
381 | ret = false; | |
382 | } | |
383 | return ret; | |
384 | } | |
385 | ||
f05c41a9 | 386 | static void decode_mc1_mce(struct mce *m) |
dd53bce4 | 387 | { |
62452882 BP |
388 | u16 ec = EC(m->status); |
389 | u8 xec = XEC(m->status, xec_mask); | |
dd53bce4 | 390 | |
f05c41a9 | 391 | pr_emerg(HW_ERR "MC1 Error: "); |
dd53bce4 BP |
392 | |
393 | if (TLB_ERROR(ec)) | |
394 | pr_cont("%s TLB %s.\n", LL_MSG(ec), | |
395 | (xec ? "multimatch" : "parity error")); | |
396 | else if (BUS_ERROR(ec)) { | |
525906bc | 397 | bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); |
dd53bce4 BP |
398 | |
399 | pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); | |
f05c41a9 | 400 | } else if (fam_ops->mc1_mce(ec, xec)) |
dd53bce4 BP |
401 | ; |
402 | else | |
f05c41a9 | 403 | pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); |
ab5535e7 BP |
404 | } |
405 | ||
4a73d3de | 406 | static bool k8_mc2_mce(u16 ec, u8 xec) |
56cad2d6 | 407 | { |
4a73d3de | 408 | bool ret = true; |
56cad2d6 BP |
409 | |
410 | if (xec == 0x1) | |
411 | pr_cont(" in the write data buffers.\n"); | |
412 | else if (xec == 0x3) | |
413 | pr_cont(" in the victim data buffers.\n"); | |
414 | else if (xec == 0x2 && MEM_ERROR(ec)) | |
62452882 | 415 | pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); |
56cad2d6 BP |
416 | else if (xec == 0x0) { |
417 | if (TLB_ERROR(ec)) | |
418 | pr_cont(": %s error in a Page Descriptor Cache or " | |
419 | "Guest TLB.\n", TT_MSG(ec)); | |
420 | else if (BUS_ERROR(ec)) | |
421 | pr_cont(": %s/ECC error in data read from NB: %s.\n", | |
62452882 | 422 | R4_MSG(ec), PP_MSG(ec)); |
56cad2d6 | 423 | else if (MEM_ERROR(ec)) { |
62452882 | 424 | u8 r4 = R4(ec); |
56cad2d6 | 425 | |
62452882 | 426 | if (r4 >= 0x7) |
56cad2d6 | 427 | pr_cont(": %s error during data copyback.\n", |
62452882 BP |
428 | R4_MSG(ec)); |
429 | else if (r4 <= 0x1) | |
56cad2d6 | 430 | pr_cont(": %s parity/ECC error during data " |
62452882 | 431 | "access from L2.\n", R4_MSG(ec)); |
56cad2d6 | 432 | else |
4a73d3de | 433 | ret = false; |
56cad2d6 | 434 | } else |
4a73d3de | 435 | ret = false; |
56cad2d6 | 436 | } else |
4a73d3de | 437 | ret = false; |
56cad2d6 | 438 | |
4a73d3de | 439 | return ret; |
56cad2d6 BP |
440 | } |
441 | ||
4a73d3de | 442 | static bool f15h_mc2_mce(u16 ec, u8 xec) |
70fdb494 | 443 | { |
4a73d3de | 444 | bool ret = true; |
70fdb494 BP |
445 | |
446 | if (TLB_ERROR(ec)) { | |
447 | if (xec == 0x0) | |
448 | pr_cont("Data parity TLB read error.\n"); | |
449 | else if (xec == 0x1) | |
450 | pr_cont("Poison data provided for TLB fill.\n"); | |
451 | else | |
4a73d3de | 452 | ret = false; |
70fdb494 BP |
453 | } else if (BUS_ERROR(ec)) { |
454 | if (xec > 2) | |
4a73d3de | 455 | ret = false; |
70fdb494 BP |
456 | |
457 | pr_cont("Error during attempted NB data read.\n"); | |
458 | } else if (MEM_ERROR(ec)) { | |
459 | switch (xec) { | |
460 | case 0x4 ... 0xc: | |
f05c41a9 | 461 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); |
70fdb494 BP |
462 | break; |
463 | ||
464 | case 0x10 ... 0x14: | |
f05c41a9 | 465 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); |
70fdb494 BP |
466 | break; |
467 | ||
468 | default: | |
4a73d3de | 469 | ret = false; |
70fdb494 BP |
470 | } |
471 | } | |
472 | ||
4a73d3de JS |
473 | return ret; |
474 | } | |
475 | ||
980eec8b JS |
476 | static bool f16h_mc2_mce(u16 ec, u8 xec) |
477 | { | |
478 | u8 r4 = R4(ec); | |
479 | ||
480 | if (!MEM_ERROR(ec)) | |
481 | return false; | |
482 | ||
483 | switch (xec) { | |
484 | case 0x04 ... 0x05: | |
485 | pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); | |
486 | break; | |
487 | ||
488 | case 0x09 ... 0x0b: | |
489 | case 0x0d ... 0x0f: | |
490 | pr_cont("ECC error in L2 tag (%s).\n", | |
491 | ((r4 == R4_GEN) ? "BankReq" : | |
492 | ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); | |
493 | break; | |
494 | ||
495 | case 0x10 ... 0x19: | |
496 | case 0x1b: | |
497 | pr_cont("ECC error in L2 data array (%s).\n", | |
498 | (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : | |
499 | ((r4 == R4_GEN) ? "Attr" : | |
500 | ((r4 == R4_EVICT) ? "Vict" : "Fill")))); | |
501 | break; | |
502 | ||
503 | case 0x1c ... 0x1d: | |
504 | case 0x1f: | |
505 | pr_cont("Parity error in L2 attribute bits (%s).\n", | |
506 | ((r4 == R4_RD) ? "Hit" : | |
507 | ((r4 == R4_GEN) ? "Attr" : "Fill"))); | |
508 | break; | |
509 | ||
510 | default: | |
511 | return false; | |
512 | } | |
513 | ||
514 | return true; | |
515 | } | |
516 | ||
4a73d3de JS |
517 | static void decode_mc2_mce(struct mce *m) |
518 | { | |
519 | u16 ec = EC(m->status); | |
520 | u8 xec = XEC(m->status, xec_mask); | |
70fdb494 | 521 | |
4a73d3de JS |
522 | pr_emerg(HW_ERR "MC2 Error: "); |
523 | ||
524 | if (!fam_ops->mc2_mce(ec, xec)) | |
525 | pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); | |
70fdb494 BP |
526 | } |
527 | ||
f05c41a9 | 528 | static void decode_mc3_mce(struct mce *m) |
f9350efd | 529 | { |
62452882 BP |
530 | u16 ec = EC(m->status); |
531 | u8 xec = XEC(m->status, xec_mask); | |
ded50623 | 532 | |
b18434ca | 533 | if (boot_cpu_data.x86 >= 0x14) { |
f05c41a9 | 534 | pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," |
ded50623 BP |
535 | " please report on LKML.\n"); |
536 | return; | |
537 | } | |
f9350efd | 538 | |
f05c41a9 | 539 | pr_emerg(HW_ERR "MC3 Error"); |
f9350efd BP |
540 | |
541 | if (xec == 0x0) { | |
62452882 | 542 | u8 r4 = R4(ec); |
f9350efd | 543 | |
ded50623 | 544 | if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) |
f05c41a9 | 545 | goto wrong_mc3_mce; |
f9350efd | 546 | |
62452882 | 547 | pr_cont(" during %s.\n", R4_MSG(ec)); |
ded50623 | 548 | } else |
f05c41a9 | 549 | goto wrong_mc3_mce; |
ded50623 | 550 | |
f9350efd BP |
551 | return; |
552 | ||
f05c41a9 BP |
553 | wrong_mc3_mce: |
554 | pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); | |
f9350efd BP |
555 | } |
556 | ||
f05c41a9 | 557 | static void decode_mc4_mce(struct mce *m) |
5ce88f6e | 558 | { |
68782673 BP |
559 | struct cpuinfo_x86 *c = &boot_cpu_data; |
560 | int node_id = amd_get_nb_id(m->extcpu); | |
561 | u16 ec = EC(m->status); | |
562 | u8 xec = XEC(m->status, 0x1f); | |
563 | u8 offset = 0; | |
5ce88f6e | 564 | |
f05c41a9 | 565 | pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); |
5ce88f6e | 566 | |
68782673 BP |
567 | switch (xec) { |
568 | case 0x0 ... 0xe: | |
5ce88f6e | 569 | |
68782673 BP |
570 | /* special handling for DRAM ECCs */ |
571 | if (xec == 0x0 || xec == 0x8) { | |
572 | /* no ECCs on F11h */ | |
573 | if (c->x86 == 0x11) | |
f05c41a9 | 574 | goto wrong_mc4_mce; |
5ce88f6e | 575 | |
f05c41a9 | 576 | pr_cont("%s.\n", mc4_mce_desc[xec]); |
5ce88f6e | 577 | |
68782673 BP |
578 | if (nb_bus_decoder) |
579 | nb_bus_decoder(node_id, m); | |
580 | return; | |
581 | } | |
5ce88f6e BP |
582 | break; |
583 | ||
584 | case 0xf: | |
585 | if (TLB_ERROR(ec)) | |
586 | pr_cont("GART Table Walk data error.\n"); | |
587 | else if (BUS_ERROR(ec)) | |
588 | pr_cont("DMA Exclusion Vector Table Walk error.\n"); | |
589 | else | |
f05c41a9 | 590 | goto wrong_mc4_mce; |
68782673 | 591 | return; |
5ce88f6e | 592 | |
05cd667d | 593 | case 0x19: |
980eec8b | 594 | if (boot_cpu_data.x86 == 0x15 || boot_cpu_data.x86 == 0x16) |
05cd667d BP |
595 | pr_cont("Compute Unit Data Error.\n"); |
596 | else | |
f05c41a9 | 597 | goto wrong_mc4_mce; |
68782673 | 598 | return; |
05cd667d | 599 | |
5ce88f6e | 600 | case 0x1c ... 0x1f: |
68782673 | 601 | offset = 13; |
5ce88f6e BP |
602 | break; |
603 | ||
604 | default: | |
f05c41a9 | 605 | goto wrong_mc4_mce; |
68782673 | 606 | } |
5ce88f6e | 607 | |
f05c41a9 | 608 | pr_cont("%s.\n", mc4_mce_desc[xec - offset]); |
5ce88f6e BP |
609 | return; |
610 | ||
f05c41a9 BP |
611 | wrong_mc4_mce: |
612 | pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); | |
d93cc222 | 613 | } |
d93cc222 | 614 | |
f05c41a9 | 615 | static void decode_mc5_mce(struct mce *m) |
53bd5fed | 616 | { |
8259a7e5 | 617 | struct cpuinfo_x86 *c = &boot_cpu_data; |
62452882 | 618 | u8 xec = XEC(m->status, xec_mask); |
8259a7e5 BP |
619 | |
620 | if (c->x86 == 0xf || c->x86 == 0x11) | |
f05c41a9 | 621 | goto wrong_mc5_mce; |
fe4ea262 | 622 | |
f05c41a9 | 623 | pr_emerg(HW_ERR "MC5 Error: "); |
8259a7e5 BP |
624 | |
625 | if (xec == 0x0 || xec == 0xc) | |
f05c41a9 | 626 | pr_cont("%s.\n", mc5_mce_desc[xec]); |
8259a7e5 | 627 | else if (xec < 0xd) |
f05c41a9 | 628 | pr_cont("%s parity error.\n", mc5_mce_desc[xec]); |
8259a7e5 | 629 | else |
f05c41a9 | 630 | goto wrong_mc5_mce; |
8259a7e5 BP |
631 | |
632 | return; | |
fe4ea262 | 633 | |
f05c41a9 BP |
634 | wrong_mc5_mce: |
635 | pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); | |
53bd5fed BP |
636 | } |
637 | ||
f05c41a9 | 638 | static void decode_mc6_mce(struct mce *m) |
b8f85c47 | 639 | { |
62452882 | 640 | u8 xec = XEC(m->status, xec_mask); |
b8f85c47 | 641 | |
f05c41a9 | 642 | pr_emerg(HW_ERR "MC6 Error: "); |
b8f85c47 BP |
643 | |
644 | switch (xec) { | |
645 | case 0x1: | |
646 | pr_cont("Free List"); | |
647 | break; | |
648 | ||
649 | case 0x2: | |
650 | pr_cont("Physical Register File"); | |
651 | break; | |
652 | ||
653 | case 0x3: | |
654 | pr_cont("Retire Queue"); | |
655 | break; | |
656 | ||
657 | case 0x4: | |
658 | pr_cont("Scheduler table"); | |
659 | break; | |
660 | ||
661 | case 0x5: | |
662 | pr_cont("Status Register File"); | |
663 | break; | |
664 | ||
665 | default: | |
f05c41a9 | 666 | goto wrong_mc6_mce; |
b8f85c47 BP |
667 | break; |
668 | } | |
669 | ||
670 | pr_cont(" parity error.\n"); | |
671 | ||
672 | return; | |
673 | ||
f05c41a9 BP |
674 | wrong_mc6_mce: |
675 | pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); | |
b8f85c47 BP |
676 | } |
677 | ||
6337583d | 678 | static inline void amd_decode_err_code(u16 ec) |
d93cc222 | 679 | { |
980eec8b JS |
680 | if (INT_ERROR(ec)) { |
681 | pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); | |
682 | return; | |
683 | } | |
fa7ae8cc BP |
684 | |
685 | pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); | |
686 | ||
687 | if (BUS_ERROR(ec)) | |
688 | pr_cont(", mem/io: %s", II_MSG(ec)); | |
689 | else | |
690 | pr_cont(", tx: %s", TT_MSG(ec)); | |
691 | ||
692 | if (MEM_ERROR(ec) || BUS_ERROR(ec)) { | |
693 | pr_cont(", mem-tx: %s", R4_MSG(ec)); | |
694 | ||
695 | if (BUS_ERROR(ec)) | |
696 | pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); | |
697 | } | |
698 | ||
699 | pr_cont("\n"); | |
549d042d | 700 | } |
549d042d | 701 | |
5ce88f6e BP |
702 | /* |
703 | * Filter out unwanted MCE signatures here. | |
704 | */ | |
705 | static bool amd_filter_mce(struct mce *m) | |
706 | { | |
707 | u8 xec = (m->status >> 16) & 0x1f; | |
708 | ||
709 | /* | |
710 | * NB GART TLB error reporting is disabled by default. | |
711 | */ | |
712 | if (m->bank == 4 && xec == 0x5 && !report_gart_errors) | |
713 | return true; | |
714 | ||
715 | return false; | |
716 | } | |
717 | ||
d5c6770d BP |
718 | static const char *decode_error_status(struct mce *m) |
719 | { | |
720 | if (m->status & MCI_STATUS_UC) { | |
721 | if (m->status & MCI_STATUS_PCC) | |
722 | return "System Fatal error."; | |
723 | if (m->mcgstatus & MCG_STATUS_RIPV) | |
724 | return "Uncorrected, software restartable error."; | |
725 | return "Uncorrected, software containable error."; | |
726 | } | |
727 | ||
728 | if (m->status & MCI_STATUS_DEFERRED) | |
729 | return "Deferred error."; | |
730 | ||
731 | return "Corrected error, no action required."; | |
732 | } | |
733 | ||
9cdeb404 | 734 | int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) |
549d042d | 735 | { |
fb253195 | 736 | struct mce *m = (struct mce *)data; |
f89f8388 | 737 | struct cpuinfo_x86 *c = &cpu_data(m->extcpu); |
b0b07a2b | 738 | int ecc; |
549d042d | 739 | |
5ce88f6e BP |
740 | if (amd_filter_mce(m)) |
741 | return NOTIFY_STOP; | |
742 | ||
51966241 BP |
743 | switch (m->bank) { |
744 | case 0: | |
f05c41a9 | 745 | decode_mc0_mce(m); |
51966241 | 746 | break; |
d93cc222 | 747 | |
ab5535e7 | 748 | case 1: |
f05c41a9 | 749 | decode_mc1_mce(m); |
ab5535e7 BP |
750 | break; |
751 | ||
56cad2d6 | 752 | case 2: |
4a73d3de | 753 | decode_mc2_mce(m); |
56cad2d6 BP |
754 | break; |
755 | ||
f9350efd | 756 | case 3: |
f05c41a9 | 757 | decode_mc3_mce(m); |
f9350efd BP |
758 | break; |
759 | ||
51966241 | 760 | case 4: |
f05c41a9 | 761 | decode_mc4_mce(m); |
51966241 BP |
762 | break; |
763 | ||
53bd5fed | 764 | case 5: |
f05c41a9 | 765 | decode_mc5_mce(m); |
53bd5fed BP |
766 | break; |
767 | ||
b8f85c47 | 768 | case 6: |
f05c41a9 | 769 | decode_mc6_mce(m); |
b8f85c47 BP |
770 | break; |
771 | ||
51966241 BP |
772 | default: |
773 | break; | |
b69b29de | 774 | } |
51966241 | 775 | |
d5c6770d BP |
776 | pr_emerg(HW_ERR "Error Status: %s\n", decode_error_status(m)); |
777 | ||
d824c771 BP |
778 | pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", |
779 | m->extcpu, | |
780 | c->x86, c->x86_model, c->x86_mask, | |
781 | m->bank, | |
782 | ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), | |
783 | ((m->status & MCI_STATUS_UC) ? "UE" : "CE"), | |
784 | ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), | |
785 | ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"), | |
786 | ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-")); | |
787 | ||
980eec8b | 788 | if (c->x86 == 0x15 || c->x86 == 0x16) |
d824c771 | 789 | pr_cont("|%s|%s", |
d5c6770d BP |
790 | ((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"), |
791 | ((m->status & MCI_STATUS_POISON) ? "Poison" : "-")); | |
d824c771 BP |
792 | |
793 | /* do the two bits[14:13] together */ | |
794 | ecc = (m->status >> 45) & 0x3; | |
795 | if (ecc) | |
796 | pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); | |
797 | ||
798 | pr_cont("]: 0x%016llx\n", m->status); | |
799 | ||
800 | if (m->status & MCI_STATUS_ADDRV) | |
801 | pr_emerg(HW_ERR "MC%d_ADDR: 0x%016llx\n", m->bank, m->addr); | |
802 | ||
51966241 | 803 | amd_decode_err_code(m->status & 0xffff); |
fb253195 BP |
804 | |
805 | return NOTIFY_STOP; | |
549d042d | 806 | } |
9cdeb404 | 807 | EXPORT_SYMBOL_GPL(amd_decode_mce); |
f436f8bb | 808 | |
fb253195 BP |
809 | static struct notifier_block amd_mce_dec_nb = { |
810 | .notifier_call = amd_decode_mce, | |
811 | }; | |
812 | ||
f436f8bb IM |
813 | static int __init mce_amd_init(void) |
814 | { | |
bad11e03 BP |
815 | struct cpuinfo_x86 *c = &boot_cpu_data; |
816 | ||
817 | if (c->x86_vendor != X86_VENDOR_AMD) | |
e045c291 BP |
818 | return 0; |
819 | ||
980eec8b | 820 | if (c->x86 < 0xf || c->x86 > 0x16) |
e045c291 BP |
821 | return 0; |
822 | ||
888ab8e6 BP |
823 | fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); |
824 | if (!fam_ops) | |
825 | return -ENOMEM; | |
826 | ||
bad11e03 | 827 | switch (c->x86) { |
888ab8e6 | 828 | case 0xf: |
f05c41a9 BP |
829 | fam_ops->mc0_mce = k8_mc0_mce; |
830 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 831 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
832 | break; |
833 | ||
834 | case 0x10: | |
f05c41a9 BP |
835 | fam_ops->mc0_mce = f10h_mc0_mce; |
836 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 837 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
838 | break; |
839 | ||
f0157b3a | 840 | case 0x11: |
f05c41a9 BP |
841 | fam_ops->mc0_mce = k8_mc0_mce; |
842 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 843 | fam_ops->mc2_mce = k8_mc2_mce; |
f0157b3a BP |
844 | break; |
845 | ||
9be0bb10 | 846 | case 0x12: |
f05c41a9 BP |
847 | fam_ops->mc0_mce = f12h_mc0_mce; |
848 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 849 | fam_ops->mc2_mce = k8_mc2_mce; |
9be0bb10 BP |
850 | break; |
851 | ||
888ab8e6 | 852 | case 0x14: |
5ce88f6e | 853 | nb_err_cpumask = 0x3; |
980eec8b JS |
854 | fam_ops->mc0_mce = cat_mc0_mce; |
855 | fam_ops->mc1_mce = cat_mc1_mce; | |
4a73d3de | 856 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
857 | break; |
858 | ||
2be64bfa BP |
859 | case 0x15: |
860 | xec_mask = 0x1f; | |
f05c41a9 BP |
861 | fam_ops->mc0_mce = f15h_mc0_mce; |
862 | fam_ops->mc1_mce = f15h_mc1_mce; | |
4a73d3de | 863 | fam_ops->mc2_mce = f15h_mc2_mce; |
2be64bfa BP |
864 | break; |
865 | ||
980eec8b JS |
866 | case 0x16: |
867 | xec_mask = 0x1f; | |
868 | fam_ops->mc0_mce = cat_mc0_mce; | |
869 | fam_ops->mc1_mce = cat_mc1_mce; | |
870 | fam_ops->mc2_mce = f16h_mc2_mce; | |
871 | break; | |
872 | ||
888ab8e6 | 873 | default: |
ec3e82d6 | 874 | printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); |
888ab8e6 BP |
875 | kfree(fam_ops); |
876 | return -EINVAL; | |
877 | } | |
878 | ||
9530d608 BP |
879 | pr_info("MCE: In-kernel MCE decoding enabled.\n"); |
880 | ||
3653ada5 | 881 | mce_register_decode_chain(&amd_mce_dec_nb); |
f436f8bb IM |
882 | |
883 | return 0; | |
884 | } | |
885 | early_initcall(mce_amd_init); | |
0d18b2e3 BP |
886 | |
887 | #ifdef MODULE | |
888 | static void __exit mce_amd_exit(void) | |
889 | { | |
3653ada5 | 890 | mce_unregister_decode_chain(&amd_mce_dec_nb); |
888ab8e6 | 891 | kfree(fam_ops); |
0d18b2e3 BP |
892 | } |
893 | ||
894 | MODULE_DESCRIPTION("AMD MCE decoder"); | |
895 | MODULE_ALIAS("edac-mce-amd"); | |
896 | MODULE_LICENSE("GPL"); | |
897 | module_exit(mce_amd_exit); | |
898 | #endif |