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dmaengine: move last completed cookie into generic dma_chan structure
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / timb_dma.c
CommitLineData
de5d4453
RR		 1/*
2 * timb_dma.c timberdale FPGA DMA driver
3 * Copyright (c) 2010 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA DMA engine
21 */
22
23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
6a3cd3ea 30#include <linux/slab.h>
de5d4453
RR		 31
32#include <linux/timb_dma.h>
33
34#define DRIVER_NAME "timb-dma"
35
36/* Global DMA registers */
37#define TIMBDMA_ACR 0x34
38#define TIMBDMA_32BIT_ADDR 0x01
39
40#define TIMBDMA_ISR 0x080000
41#define TIMBDMA_IPR 0x080004
42#define TIMBDMA_IER 0x080008
43
44/* Channel specific registers */
45/* RX instances base addresses are 0x00, 0x40, 0x80 ...
46 * TX instances base addresses are 0x18, 0x58, 0x98 ...
47 */
48#define TIMBDMA_INSTANCE_OFFSET 0x40
49#define TIMBDMA_INSTANCE_TX_OFFSET 0x18
50
51/* RX registers, relative the instance base */
52#define TIMBDMA_OFFS_RX_DHAR 0x00
53#define TIMBDMA_OFFS_RX_DLAR 0x04
54#define TIMBDMA_OFFS_RX_LR 0x0C
55#define TIMBDMA_OFFS_RX_BLR 0x10
56#define TIMBDMA_OFFS_RX_ER 0x14
57#define TIMBDMA_RX_EN 0x01
58/* bytes per Row, video specific register
59 * which is placed after the TX registers...
60 */
61#define TIMBDMA_OFFS_RX_BPRR 0x30
62
63/* TX registers, relative the instance base */
64#define TIMBDMA_OFFS_TX_DHAR 0x00
65#define TIMBDMA_OFFS_TX_DLAR 0x04
66#define TIMBDMA_OFFS_TX_BLR 0x0C
67#define TIMBDMA_OFFS_TX_LR 0x14
68
69
70#define TIMB_DMA_DESC_SIZE 8
71
72struct timb_dma_desc {
73 struct list_head desc_node;
74 struct dma_async_tx_descriptor txd;
75 u8 *desc_list;
76 unsigned int desc_list_len;
77 bool interrupt;
78};
79
80struct timb_dma_chan {
81 struct dma_chan chan;
82 void __iomem *membase;
0f65169b
RR		 83 spinlock_t lock; /* Used to protect data structures,
84 especially the lists and descriptors,
85 from races between the tasklet and calls
86 from above */
de5d4453
RR		 87 bool ongoing;
88 struct list_head active_list;
89 struct list_head queue;
90 struct list_head free_list;
91 unsigned int bytes_per_line;
db8196df 92 enum dma_transfer_direction direction;
de5d4453
RR		 93 unsigned int descs; /* Descriptors to allocate */
94 unsigned int desc_elems; /* number of elems per descriptor */
95};
96
97struct timb_dma {
98 struct dma_device dma;
99 void __iomem *membase;
100 struct tasklet_struct tasklet;
101 struct timb_dma_chan channels[0];
102};
103
104static struct device *chan2dev(struct dma_chan *chan)
105{
106 return &chan->dev->device;
107}
108static struct device *chan2dmadev(struct dma_chan *chan)
109{
110 return chan2dev(chan)->parent->parent;
111}
112
113static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan)
114{
115 int id = td_chan->chan.chan_id;
116 return (struct timb_dma *)((u8 *)td_chan -
117 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
118}
119
120/* Must be called with the spinlock held */
121static void __td_enable_chan_irq(struct timb_dma_chan *td_chan)
122{
123 int id = td_chan->chan.chan_id;
124 struct timb_dma *td = tdchantotd(td_chan);
125 u32 ier;
126
127 /* enable interrupt for this channel */
128 ier = ioread32(td->membase + TIMBDMA_IER);
129 ier |= 1 << id;
130 dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id,
131 ier);
132 iowrite32(ier, td->membase + TIMBDMA_IER);
133}
134
135/* Should be called with the spinlock held */
136static bool __td_dma_done_ack(struct timb_dma_chan *td_chan)
137{
138 int id = td_chan->chan.chan_id;
139 struct timb_dma *td = (struct timb_dma *)((u8 *)td_chan -
140 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
141 u32 isr;
142 bool done = false;
143
144 dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td);
145
146 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id);
147 if (isr) {
148 iowrite32(isr, td->membase + TIMBDMA_ISR);
149 done = true;
150 }
151
152 return done;
153}
154
155static void __td_unmap_desc(struct timb_dma_chan *td_chan, const u8 *dma_desc,
156 bool single)
157{
158 dma_addr_t addr;
159 int len;
160
161 addr = (dma_desc[7] << 24) | (dma_desc[6] << 16) | (dma_desc[5] << 8) |
162 dma_desc[4];
163
164 len = (dma_desc[3] << 8) | dma_desc[2];
165
166 if (single)
167 dma_unmap_single(chan2dev(&td_chan->chan), addr, len,
d5613947 168 DMA_TO_DEVICE);
de5d4453
RR		 169 else
170 dma_unmap_page(chan2dev(&td_chan->chan), addr, len,
d5613947 171 DMA_TO_DEVICE);
de5d4453
RR		 172}
173
174static void __td_unmap_descs(struct timb_dma_desc *td_desc, bool single)
175{
176 struct timb_dma_chan *td_chan = container_of(td_desc->txd.chan,
177 struct timb_dma_chan, chan);
178 u8 *descs;
179
180 for (descs = td_desc->desc_list; ; descs += TIMB_DMA_DESC_SIZE) {
181 __td_unmap_desc(td_chan, descs, single);
182 if (descs[0] & 0x02)
183 break;
184 }
185}
186
187static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc,
188 struct scatterlist *sg, bool last)
189{
4be929be 190 if (sg_dma_len(sg) > USHRT_MAX) {
de5d4453
RR		 191 dev_err(chan2dev(&td_chan->chan), "Too big sg element\n");
192 return -EINVAL;
193 }
194
195 /* length must be word aligned */
196 if (sg_dma_len(sg) % sizeof(u32)) {
197 dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n",
198 sg_dma_len(sg));
199 return -EINVAL;
200 }
201
efcc2898
DC		 202 dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n",
203 dma_desc, (unsigned long long)sg_dma_address(sg));
de5d4453
RR		 204
205 dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff;
206 dma_desc[6] = (sg_dma_address(sg) >> 16) & 0xff;
207 dma_desc[5] = (sg_dma_address(sg) >> 8) & 0xff;
208 dma_desc[4] = (sg_dma_address(sg) >> 0) & 0xff;
209
210 dma_desc[3] = (sg_dma_len(sg) >> 8) & 0xff;
211 dma_desc[2] = (sg_dma_len(sg) >> 0) & 0xff;
212
213 dma_desc[1] = 0x00;
214 dma_desc[0] = 0x21 | (last ? 0x02 : 0); /* tran, valid */
215
216 return 0;
217}
218
219/* Must be called with the spinlock held */
220static void __td_start_dma(struct timb_dma_chan *td_chan)
221{
222 struct timb_dma_desc *td_desc;
223
224 if (td_chan->ongoing) {
225 dev_err(chan2dev(&td_chan->chan),
226 "Transfer already ongoing\n");
227 return;
228 }
229
230 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
231 desc_node);
232
233 dev_dbg(chan2dev(&td_chan->chan),
234 "td_chan: %p, chan: %d, membase: %p\n",
235 td_chan, td_chan->chan.chan_id, td_chan->membase);
236
db8196df 237 if (td_chan->direction == DMA_DEV_TO_MEM) {
de5d4453
RR		 238
239 /* descriptor address */
240 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
241 iowrite32(td_desc->txd.phys, td_chan->membase +
242 TIMBDMA_OFFS_RX_DLAR);
243 /* Bytes per line */
244 iowrite32(td_chan->bytes_per_line, td_chan->membase +
245 TIMBDMA_OFFS_RX_BPRR);
246 /* enable RX */
247 iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER);
248 } else {
249 /* address high */
250 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR);
251 iowrite32(td_desc->txd.phys, td_chan->membase +
252 TIMBDMA_OFFS_TX_DLAR);
253 }
254
255 td_chan->ongoing = true;
256
257 if (td_desc->interrupt)
258 __td_enable_chan_irq(td_chan);
259}
260
261static void __td_finish(struct timb_dma_chan *td_chan)
262{
263 dma_async_tx_callback callback;
264 void *param;
265 struct dma_async_tx_descriptor *txd;
266 struct timb_dma_desc *td_desc;
267
268 /* can happen if the descriptor is canceled */
269 if (list_empty(&td_chan->active_list))
270 return;
271
272 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
273 desc_node);
274 txd = &td_desc->txd;
275
276 dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n",
277 txd->cookie);
278
279 /* make sure to stop the transfer */
db8196df 280 if (td_chan->direction == DMA_DEV_TO_MEM)
de5d4453
RR		 281 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
282/* Currently no support for stopping DMA transfers
283 else
284 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
285*/
4d4e58de 286 td_chan->chan.completed_cookie = txd->cookie;
de5d4453
RR		 287 td_chan->ongoing = false;
288
289 callback = txd->callback;
290 param = txd->callback_param;
291
292 list_move(&td_desc->desc_node, &td_chan->free_list);
293
294 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
295 __td_unmap_descs(td_desc,
296 txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE);
297
298 /*
299 * The API requires that no submissions are done from a
300 * callback, so we don't need to drop the lock here
301 */
302 if (callback)
303 callback(param);
304}
305
306static u32 __td_ier_mask(struct timb_dma *td)
307{
308 int i;
309 u32 ret = 0;
310
311 for (i = 0; i < td->dma.chancnt; i++) {
312 struct timb_dma_chan *td_chan = td->channels + i;
313 if (td_chan->ongoing) {
314 struct timb_dma_desc *td_desc =
315 list_entry(td_chan->active_list.next,
316 struct timb_dma_desc, desc_node);
317 if (td_desc->interrupt)
318 ret |= 1 << i;
319 }
320 }
321
322 return ret;
323}
324
325static void __td_start_next(struct timb_dma_chan *td_chan)
326{
327 struct timb_dma_desc *td_desc;
328
329 BUG_ON(list_empty(&td_chan->queue));
330 BUG_ON(td_chan->ongoing);
331
332 td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc,
333 desc_node);
334
335 dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n",
336 __func__, td_desc->txd.cookie);
337
338 list_move(&td_desc->desc_node, &td_chan->active_list);
339 __td_start_dma(td_chan);
340}
341
342static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
343{
344 struct timb_dma_desc *td_desc = container_of(txd, struct timb_dma_desc,
345 txd);
346 struct timb_dma_chan *td_chan = container_of(txd->chan,
347 struct timb_dma_chan, chan);
348 dma_cookie_t cookie;
349
350 spin_lock_bh(&td_chan->lock);
351
352 cookie = txd->chan->cookie;
353 if (++cookie < 0)
354 cookie = 1;
355 txd->chan->cookie = cookie;
356 txd->cookie = cookie;
357
358 if (list_empty(&td_chan->active_list)) {
359 dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
360 txd->cookie);
361 list_add_tail(&td_desc->desc_node, &td_chan->active_list);
362 __td_start_dma(td_chan);
363 } else {
364 dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n",
365 txd->cookie);
366
367 list_add_tail(&td_desc->desc_node, &td_chan->queue);
368 }
369
370 spin_unlock_bh(&td_chan->lock);
371
372 return cookie;
373}
374
375static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
376{
377 struct dma_chan *chan = &td_chan->chan;
378 struct timb_dma_desc *td_desc;
379 int err;
380
381 td_desc = kzalloc(sizeof(struct timb_dma_desc), GFP_KERNEL);
382 if (!td_desc) {
383 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
48568005 384 goto out;
de5d4453
RR		 385 }
386
387 td_desc->desc_list_len = td_chan->desc_elems * TIMB_DMA_DESC_SIZE;
388
389 td_desc->desc_list = kzalloc(td_desc->desc_list_len, GFP_KERNEL);
390 if (!td_desc->desc_list) {
391 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
392 goto err;
393 }
394
395 dma_async_tx_descriptor_init(&td_desc->txd, chan);
396 td_desc->txd.tx_submit = td_tx_submit;
397 td_desc->txd.flags = DMA_CTRL_ACK;
398
399 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
d5613947 400 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE);
de5d4453
RR		 401
402 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
403 if (err) {
404 dev_err(chan2dev(chan), "DMA mapping error: %d\n", err);
405 goto err;
406 }
407
408 return td_desc;
409err:
410 kfree(td_desc->desc_list);
411 kfree(td_desc);
48568005 412out:
de5d4453
RR		 413 return NULL;
414
415}
416
417static void td_free_desc(struct timb_dma_desc *td_desc)
418{
419 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
420 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
d5613947 421 td_desc->desc_list_len, DMA_TO_DEVICE);
de5d4453
RR		 422
423 kfree(td_desc->desc_list);
424 kfree(td_desc);
425}
426
427static void td_desc_put(struct timb_dma_chan *td_chan,
428 struct timb_dma_desc *td_desc)
429{
430 dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc);
431
432 spin_lock_bh(&td_chan->lock);
433 list_add(&td_desc->desc_node, &td_chan->free_list);
434 spin_unlock_bh(&td_chan->lock);
435}
436
437static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan)
438{
439 struct timb_dma_desc *td_desc, *_td_desc;
440 struct timb_dma_desc *ret = NULL;
441
442 spin_lock_bh(&td_chan->lock);
443 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->free_list,
444 desc_node) {
445 if (async_tx_test_ack(&td_desc->txd)) {
446 list_del(&td_desc->desc_node);
447 ret = td_desc;
448 break;
449 }
450 dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n",
451 td_desc);
452 }
453 spin_unlock_bh(&td_chan->lock);
454
455 return ret;
456}
457
458static int td_alloc_chan_resources(struct dma_chan *chan)
459{
460 struct timb_dma_chan *td_chan =
461 container_of(chan, struct timb_dma_chan, chan);
462 int i;
463
464 dev_dbg(chan2dev(chan), "%s: entry\n", __func__);
465
466 BUG_ON(!list_empty(&td_chan->free_list));
467 for (i = 0; i < td_chan->descs; i++) {
468 struct timb_dma_desc *td_desc = td_alloc_init_desc(td_chan);
469 if (!td_desc) {
470 if (i)
471 break;
472 else {
473 dev_err(chan2dev(chan),
474 "Couldnt allocate any descriptors\n");
475 return -ENOMEM;
476 }
477 }
478
479 td_desc_put(td_chan, td_desc);
480 }
481
482 spin_lock_bh(&td_chan->lock);
4d4e58de 483 chan->completed_cookie = 1;
de5d4453
RR		 484 chan->cookie = 1;
485 spin_unlock_bh(&td_chan->lock);
486
487 return 0;
488}
489
490static void td_free_chan_resources(struct dma_chan *chan)
491{
492 struct timb_dma_chan *td_chan =
493 container_of(chan, struct timb_dma_chan, chan);
494 struct timb_dma_desc *td_desc, *_td_desc;
495 LIST_HEAD(list);
496
497 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
498
499 /* check that all descriptors are free */
500 BUG_ON(!list_empty(&td_chan->active_list));
501 BUG_ON(!list_empty(&td_chan->queue));
502
503 spin_lock_bh(&td_chan->lock);
504 list_splice_init(&td_chan->free_list, &list);
505 spin_unlock_bh(&td_chan->lock);
506
507 list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) {
508 dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__,
509 td_desc);
510 td_free_desc(td_desc);
511 }
512}
513
07934481
LW		 514static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
515 struct dma_tx_state *txstate)
de5d4453
RR		 516{
517 struct timb_dma_chan *td_chan =
518 container_of(chan, struct timb_dma_chan, chan);
519 dma_cookie_t last_used;
520 dma_cookie_t last_complete;
521 int ret;
522
523 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
524
4d4e58de 525 last_complete = chan->completed_cookie;
de5d4453
RR		 526 last_used = chan->cookie;
527
528 ret = dma_async_is_complete(cookie, last_complete, last_used);
529
bca34692 530 dma_set_tx_state(txstate, last_complete, last_used, 0);
de5d4453
RR		 531
532 dev_dbg(chan2dev(chan),
533 "%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
534 __func__, ret, last_complete, last_used);
535
536 return ret;
537}
538
539static void td_issue_pending(struct dma_chan *chan)
540{
541 struct timb_dma_chan *td_chan =
542 container_of(chan, struct timb_dma_chan, chan);
543
544 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
545 spin_lock_bh(&td_chan->lock);
546
547 if (!list_empty(&td_chan->active_list))
548 /* transfer ongoing */
549 if (__td_dma_done_ack(td_chan))
550 __td_finish(td_chan);
551
552 if (list_empty(&td_chan->active_list) && !list_empty(&td_chan->queue))
553 __td_start_next(td_chan);
554
555 spin_unlock_bh(&td_chan->lock);
556}
557
558static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
559 struct scatterlist *sgl, unsigned int sg_len,
db8196df 560 enum dma_transfer_direction direction, unsigned long flags)
de5d4453
RR		 561{
562 struct timb_dma_chan *td_chan =
563 container_of(chan, struct timb_dma_chan, chan);
564 struct timb_dma_desc *td_desc;
565 struct scatterlist *sg;
566 unsigned int i;
567 unsigned int desc_usage = 0;
568
569 if (!sgl || !sg_len) {
570 dev_err(chan2dev(chan), "%s: No SG list\n", __func__);
571 return NULL;
572 }
573
574 /* even channels are for RX, odd for TX */
575 if (td_chan->direction != direction) {
576 dev_err(chan2dev(chan),
577 "Requesting channel in wrong direction\n");
578 return NULL;
579 }
580
581 td_desc = td_desc_get(td_chan);
582 if (!td_desc) {
583 dev_err(chan2dev(chan), "Not enough descriptors available\n");
584 return NULL;
585 }
586
587 td_desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0;
588
589 for_each_sg(sgl, sg, sg_len, i) {
590 int err;
591 if (desc_usage > td_desc->desc_list_len) {
592 dev_err(chan2dev(chan), "No descriptor space\n");
593 return NULL;
594 }
595
596 err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg,
597 i == (sg_len - 1));
598 if (err) {
599 dev_err(chan2dev(chan), "Failed to update desc: %d\n",
600 err);
601 td_desc_put(td_chan, td_desc);
602 return NULL;
603 }
604 desc_usage += TIMB_DMA_DESC_SIZE;
605 }
606
607 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
db8196df 608 td_desc->desc_list_len, DMA_MEM_TO_DEV);
de5d4453
RR		 609
610 return &td_desc->txd;
611}
612
05827630
LW		 613static int td_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
614 unsigned long arg)
de5d4453
RR		 615{
616 struct timb_dma_chan *td_chan =
617 container_of(chan, struct timb_dma_chan, chan);
618 struct timb_dma_desc *td_desc, *_td_desc;
619
620 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
621
c3635c78
LW		 622 if (cmd != DMA_TERMINATE_ALL)
623 return -ENXIO;
624
de5d4453
RR		 625 /* first the easy part, put the queue into the free list */
626 spin_lock_bh(&td_chan->lock);
627 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->queue,
628 desc_node)
629 list_move(&td_desc->desc_node, &td_chan->free_list);
630
ae0e47f0 631 /* now tear down the running */
de5d4453
RR		 632 __td_finish(td_chan);
633 spin_unlock_bh(&td_chan->lock);
c3635c78
LW		 634
635 return 0;
de5d4453
RR		 636}
637
638static void td_tasklet(unsigned long data)
639{
640 struct timb_dma *td = (struct timb_dma *)data;
641 u32 isr;
642 u32 ipr;
643 u32 ier;
644 int i;
645
646 isr = ioread32(td->membase + TIMBDMA_ISR);
647 ipr = isr & __td_ier_mask(td);
648
649 /* ack the interrupts */
650 iowrite32(ipr, td->membase + TIMBDMA_ISR);
651
652 for (i = 0; i < td->dma.chancnt; i++)
653 if (ipr & (1 << i)) {
654 struct timb_dma_chan *td_chan = td->channels + i;
655 spin_lock(&td_chan->lock);
656 __td_finish(td_chan);
657 if (!list_empty(&td_chan->queue))
658 __td_start_next(td_chan);
659 spin_unlock(&td_chan->lock);
660 }
661
662 ier = __td_ier_mask(td);
663 iowrite32(ier, td->membase + TIMBDMA_IER);
664}
665
666
667static irqreturn_t td_irq(int irq, void *devid)
668{
669 struct timb_dma *td = devid;
670 u32 ipr = ioread32(td->membase + TIMBDMA_IPR);
671
672 if (ipr) {
673 /* disable interrupts, will be re-enabled in tasklet */
674 iowrite32(0, td->membase + TIMBDMA_IER);
675
676 tasklet_schedule(&td->tasklet);
677
678 return IRQ_HANDLED;
679 } else
680 return IRQ_NONE;
681}
682
683
684static int __devinit td_probe(struct platform_device *pdev)
685{
3271d382 686 struct timb_dma_platform_data *pdata = pdev->dev.platform_data;
de5d4453
RR		 687 struct timb_dma *td;
688 struct resource *iomem;
689 int irq;
690 int err;
691 int i;
692
693 if (!pdata) {
694 dev_err(&pdev->dev, "No platform data\n");
695 return -EINVAL;
696 }
697
698 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 if (!iomem)
700 return -EINVAL;
701
702 irq = platform_get_irq(pdev, 0);
703 if (irq < 0)
704 return irq;
705
706 if (!request_mem_region(iomem->start, resource_size(iomem),
707 DRIVER_NAME))
708 return -EBUSY;
709
710 td = kzalloc(sizeof(struct timb_dma) +
711 sizeof(struct timb_dma_chan) * pdata->nr_channels, GFP_KERNEL);
712 if (!td) {
713 err = -ENOMEM;
714 goto err_release_region;
715 }
716
717 dev_dbg(&pdev->dev, "Allocated TD: %p\n", td);
718
719 td->membase = ioremap(iomem->start, resource_size(iomem));
720 if (!td->membase) {
721 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
722 err = -ENOMEM;
723 goto err_free_mem;
724 }
725
726 /* 32bit addressing */
727 iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR);
728
729 /* disable and clear any interrupts */
730 iowrite32(0x0, td->membase + TIMBDMA_IER);
731 iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR);
732
733 tasklet_init(&td->tasklet, td_tasklet, (unsigned long)td);
734
735 err = request_irq(irq, td_irq, IRQF_SHARED, DRIVER_NAME, td);
736 if (err) {
737 dev_err(&pdev->dev, "Failed to request IRQ\n");
738 goto err_tasklet_kill;
739 }
740
741 td->dma.device_alloc_chan_resources = td_alloc_chan_resources;
742 td->dma.device_free_chan_resources = td_free_chan_resources;
07934481 743 td->dma.device_tx_status = td_tx_status;
de5d4453
RR		 744 td->dma.device_issue_pending = td_issue_pending;
745
746 dma_cap_set(DMA_SLAVE, td->dma.cap_mask);
747 dma_cap_set(DMA_PRIVATE, td->dma.cap_mask);
748 td->dma.device_prep_slave_sg = td_prep_slave_sg;
c3635c78 749 td->dma.device_control = td_control;
de5d4453
RR		 750
751 td->dma.dev = &pdev->dev;
752
753 INIT_LIST_HEAD(&td->dma.channels);
754
46389470 755 for (i = 0; i < pdata->nr_channels; i++) {
de5d4453
RR		 756 struct timb_dma_chan *td_chan = &td->channels[i];
757 struct timb_dma_platform_data_channel *pchan =
758 pdata->channels + i;
759
760 /* even channels are RX, odd are TX */
9cb047d4 761 if ((i % 2) == pchan->rx) {
de5d4453
RR		 762 dev_err(&pdev->dev, "Wrong channel configuration\n");
763 err = -EINVAL;
f80befe0 764 goto err_free_irq;
de5d4453
RR		 765 }
766
767 td_chan->chan.device = &td->dma;
768 td_chan->chan.cookie = 1;
de5d4453
RR		 769 spin_lock_init(&td_chan->lock);
770 INIT_LIST_HEAD(&td_chan->active_list);
771 INIT_LIST_HEAD(&td_chan->queue);
772 INIT_LIST_HEAD(&td_chan->free_list);
773
774 td_chan->descs = pchan->descriptors;
775 td_chan->desc_elems = pchan->descriptor_elements;
776 td_chan->bytes_per_line = pchan->bytes_per_line;
db8196df
VK		 777 td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
778 DMA_MEM_TO_DEV;
de5d4453
RR		 779
780 td_chan->membase = td->membase +
781 (i / 2) * TIMBDMA_INSTANCE_OFFSET +
782 (pchan->rx ? 0 : TIMBDMA_INSTANCE_TX_OFFSET);
783
784 dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n",
785 i, td_chan->membase);
786
787 list_add_tail(&td_chan->chan.device_node, &td->dma.channels);
788 }
789
790 err = dma_async_device_register(&td->dma);
791 if (err) {
792 dev_err(&pdev->dev, "Failed to register async device\n");
793 goto err_free_irq;
794 }
795
796 platform_set_drvdata(pdev, td);
797
798 dev_dbg(&pdev->dev, "Probe result: %d\n", err);
799 return err;
800
801err_free_irq:
802 free_irq(irq, td);
803err_tasklet_kill:
804 tasklet_kill(&td->tasklet);
805 iounmap(td->membase);
806err_free_mem:
807 kfree(td);
808err_release_region:
809 release_mem_region(iomem->start, resource_size(iomem));
810
811 return err;
812
813}
814
815static int __devexit td_remove(struct platform_device *pdev)
816{
817 struct timb_dma *td = platform_get_drvdata(pdev);
818 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 int irq = platform_get_irq(pdev, 0);
820
821 dma_async_device_unregister(&td->dma);
822 free_irq(irq, td);
823 tasklet_kill(&td->tasklet);
824 iounmap(td->membase);
825 kfree(td);
826 release_mem_region(iomem->start, resource_size(iomem));
827
828 platform_set_drvdata(pdev, NULL);
829
830 dev_dbg(&pdev->dev, "Removed...\n");
831 return 0;
832}
833
834static struct platform_driver td_driver = {
835 .driver = {
836 .name = DRIVER_NAME,
837 .owner = THIS_MODULE,
838 },
839 .probe = td_probe,
840 .remove = __exit_p(td_remove),
841};
842
c94e9105 843module_platform_driver(td_driver);
de5d4453
RR		 844
845MODULE_LICENSE("GPL v2");
846MODULE_DESCRIPTION("Timberdale DMA controller driver");
847MODULE_AUTHOR("Pelagicore AB <info@pelagicore.com>");
848MODULE_ALIAS("platform:"DRIVER_NAME);
kernel source for telekom puls (alcatel/mediatek)