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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / tegra20-apb-dma.c
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ec8a1586
LD		 1/*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
7331205a 24#include <linux/err.h>
ec8a1586
LD		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/mm.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/platform_device.h>
3065c194 33#include <linux/pm.h>
ec8a1586
LD		 34#include <linux/pm_runtime.h>
35#include <linux/slab.h>
61fd290d 36#include <linux/clk/tegra.h>
ec8a1586 37
ec8a1586
LD		 38#include "dmaengine.h"
39
40#define TEGRA_APBDMA_GENERAL 0x0
41#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
42
43#define TEGRA_APBDMA_CONTROL 0x010
44#define TEGRA_APBDMA_IRQ_MASK 0x01c
45#define TEGRA_APBDMA_IRQ_MASK_SET 0x020
46
47/* CSR register */
48#define TEGRA_APBDMA_CHAN_CSR 0x00
49#define TEGRA_APBDMA_CSR_ENB BIT(31)
50#define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
51#define TEGRA_APBDMA_CSR_HOLD BIT(29)
52#define TEGRA_APBDMA_CSR_DIR BIT(28)
53#define TEGRA_APBDMA_CSR_ONCE BIT(27)
54#define TEGRA_APBDMA_CSR_FLOW BIT(21)
55#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
56#define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
57
58/* STATUS register */
59#define TEGRA_APBDMA_CHAN_STATUS 0x004
60#define TEGRA_APBDMA_STATUS_BUSY BIT(31)
61#define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
62#define TEGRA_APBDMA_STATUS_HALT BIT(29)
63#define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
64#define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
65#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
66
1b140908
LD		 67#define TEGRA_APBDMA_CHAN_CSRE 0x00C
68#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
69
ec8a1586
LD		 70/* AHB memory address */
71#define TEGRA_APBDMA_CHAN_AHBPTR 0x010
72
73/* AHB sequence register */
74#define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
75#define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
76#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
77#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
78#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
79#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
80#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
81#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
82#define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
83#define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
84#define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
85#define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
86#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
87#define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
88
89/* APB address */
90#define TEGRA_APBDMA_CHAN_APBPTR 0x018
91
92/* APB sequence register */
93#define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
94#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
95#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
96#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
97#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
98#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
99#define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
100#define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
101
102/*
103 * If any burst is in flight and DMA paused then this is the time to complete
104 * on-flight burst and update DMA status register.
105 */
106#define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
107
108/* Channel base address offset from APBDMA base address */
109#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
110
111/* DMA channel register space size */
112#define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE 0x20
113
114struct tegra_dma;
115
116/*
117 * tegra_dma_chip_data Tegra chip specific DMA data
118 * @nr_channels: Number of channels available in the controller.
119 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
1b140908 120 * @support_channel_pause: Support channel wise pause of dma.
ec8a1586
LD		 121 */
122struct tegra_dma_chip_data {
123 int nr_channels;
124 int max_dma_count;
1b140908 125 bool support_channel_pause;
ec8a1586
LD		 126};
127
128/* DMA channel registers */
129struct tegra_dma_channel_regs {
130 unsigned long csr;
131 unsigned long ahb_ptr;
132 unsigned long apb_ptr;
133 unsigned long ahb_seq;
134 unsigned long apb_seq;
135};
136
137/*
138 * tegra_dma_sg_req: Dma request details to configure hardware. This
139 * contains the details for one transfer to configure DMA hw.
140 * The client's request for data transfer can be broken into multiple
141 * sub-transfer as per requester details and hw support.
142 * This sub transfer get added in the list of transfer and point to Tegra
143 * DMA descriptor which manages the transfer details.
144 */
145struct tegra_dma_sg_req {
146 struct tegra_dma_channel_regs ch_regs;
147 int req_len;
148 bool configured;
149 bool last_sg;
150 bool half_done;
151 struct list_head node;
152 struct tegra_dma_desc *dma_desc;
153};
154
155/*
156 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
157 * This descriptor keep track of transfer status, callbacks and request
158 * counts etc.
159 */
160struct tegra_dma_desc {
161 struct dma_async_tx_descriptor txd;
162 int bytes_requested;
163 int bytes_transferred;
164 enum dma_status dma_status;
165 struct list_head node;
166 struct list_head tx_list;
167 struct list_head cb_node;
168 int cb_count;
169};
170
171struct tegra_dma_channel;
172
173typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
174 bool to_terminate);
175
176/* tegra_dma_channel: Channel specific information */
177struct tegra_dma_channel {
178 struct dma_chan dma_chan;
d0fc9054 179 char name[30];
ec8a1586
LD		 180 bool config_init;
181 int id;
182 int irq;
183 unsigned long chan_base_offset;
184 spinlock_t lock;
185 bool busy;
186 struct tegra_dma *tdma;
187 bool cyclic;
188
189 /* Different lists for managing the requests */
190 struct list_head free_sg_req;
191 struct list_head pending_sg_req;
192 struct list_head free_dma_desc;
193 struct list_head cb_desc;
194
195 /* ISR handler and tasklet for bottom half of isr handling */
196 dma_isr_handler isr_handler;
197 struct tasklet_struct tasklet;
198 dma_async_tx_callback callback;
199 void *callback_param;
200
201 /* Channel-slave specific configuration */
202 struct dma_slave_config dma_sconfig;
3065c194 203 struct tegra_dma_channel_regs channel_reg;
ec8a1586
LD		 204};
205
206/* tegra_dma: Tegra DMA specific information */
207struct tegra_dma {
208 struct dma_device dma_dev;
209 struct device *dev;
210 struct clk *dma_clk;
211 spinlock_t global_lock;
212 void __iomem *base_addr;
83a1ef2e 213 const struct tegra_dma_chip_data *chip_data;
ec8a1586
LD		 214
215 /* Some register need to be cache before suspend */
216 u32 reg_gen;
217
218 /* Last member of the structure */
219 struct tegra_dma_channel channels[0];
220};
221
222static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
223{
224 writel(val, tdma->base_addr + reg);
225}
226
227static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
228{
229 return readl(tdma->base_addr + reg);
230}
231
232static inline void tdc_write(struct tegra_dma_channel *tdc,
233 u32 reg, u32 val)
234{
235 writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
236}
237
238static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
239{
240 return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
241}
242
243static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
244{
245 return container_of(dc, struct tegra_dma_channel, dma_chan);
246}
247
248static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
249 struct dma_async_tx_descriptor *td)
250{
251 return container_of(td, struct tegra_dma_desc, txd);
252}
253
254static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
255{
256 return &tdc->dma_chan.dev->device;
257}
258
259static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
260static int tegra_dma_runtime_suspend(struct device *dev);
261static int tegra_dma_runtime_resume(struct device *dev);
262
263/* Get DMA desc from free list, if not there then allocate it. */
264static struct tegra_dma_desc *tegra_dma_desc_get(
265 struct tegra_dma_channel *tdc)
266{
267 struct tegra_dma_desc *dma_desc;
268 unsigned long flags;
269
270 spin_lock_irqsave(&tdc->lock, flags);
271
272 /* Do not allocate if desc are waiting for ack */
273 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
274 if (async_tx_test_ack(&dma_desc->txd)) {
275 list_del(&dma_desc->node);
276 spin_unlock_irqrestore(&tdc->lock, flags);
b9bb37f5 277 dma_desc->txd.flags = 0;
ec8a1586
LD		 278 return dma_desc;
279 }
280 }
281
282 spin_unlock_irqrestore(&tdc->lock, flags);
283
284 /* Allocate DMA desc */
285 dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
286 if (!dma_desc) {
287 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
288 return NULL;
289 }
290
291 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
292 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
293 dma_desc->txd.flags = 0;
294 return dma_desc;
295}
296
297static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
298 struct tegra_dma_desc *dma_desc)
299{
300 unsigned long flags;
301
302 spin_lock_irqsave(&tdc->lock, flags);
303 if (!list_empty(&dma_desc->tx_list))
304 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
305 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
306 spin_unlock_irqrestore(&tdc->lock, flags);
307}
308
309static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
310 struct tegra_dma_channel *tdc)
311{
312 struct tegra_dma_sg_req *sg_req = NULL;
313 unsigned long flags;
314
315 spin_lock_irqsave(&tdc->lock, flags);
316 if (!list_empty(&tdc->free_sg_req)) {
317 sg_req = list_first_entry(&tdc->free_sg_req,
318 typeof(*sg_req), node);
319 list_del(&sg_req->node);
320 spin_unlock_irqrestore(&tdc->lock, flags);
321 return sg_req;
322 }
323 spin_unlock_irqrestore(&tdc->lock, flags);
324
325 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
326 if (!sg_req)
327 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
328 return sg_req;
329}
330
331static int tegra_dma_slave_config(struct dma_chan *dc,
332 struct dma_slave_config *sconfig)
333{
334 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
335
336 if (!list_empty(&tdc->pending_sg_req)) {
337 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
338 return -EBUSY;
339 }
340
341 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
342 tdc->config_init = true;
343 return 0;
344}
345
346static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
347 bool wait_for_burst_complete)
348{
349 struct tegra_dma *tdma = tdc->tdma;
350
351 spin_lock(&tdma->global_lock);
352 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
353 if (wait_for_burst_complete)
354 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
355}
356
357static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
358{
359 struct tegra_dma *tdma = tdc->tdma;
360
361 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
362 spin_unlock(&tdma->global_lock);
363}
364
1b140908
LD		 365static void tegra_dma_pause(struct tegra_dma_channel *tdc,
366 bool wait_for_burst_complete)
367{
368 struct tegra_dma *tdma = tdc->tdma;
369
370 if (tdma->chip_data->support_channel_pause) {
371 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
372 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
373 if (wait_for_burst_complete)
374 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
375 } else {
376 tegra_dma_global_pause(tdc, wait_for_burst_complete);
377 }
378}
379
380static void tegra_dma_resume(struct tegra_dma_channel *tdc)
381{
382 struct tegra_dma *tdma = tdc->tdma;
383
384 if (tdma->chip_data->support_channel_pause) {
385 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
386 } else {
387 tegra_dma_global_resume(tdc);
388 }
389}
390
ec8a1586
LD		 391static void tegra_dma_stop(struct tegra_dma_channel *tdc)
392{
393 u32 csr;
394 u32 status;
395
396 /* Disable interrupts */
397 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
398 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
399 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
400
401 /* Disable DMA */
402 csr &= ~TEGRA_APBDMA_CSR_ENB;
403 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
404
405 /* Clear interrupt status if it is there */
406 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
407 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
408 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
409 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
410 }
411 tdc->busy = false;
412}
413
414static void tegra_dma_start(struct tegra_dma_channel *tdc,
415 struct tegra_dma_sg_req *sg_req)
416{
417 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
418
419 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
420 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
421 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
422 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
423 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
424
425 /* Start DMA */
426 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
427 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
428}
429
430static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
431 struct tegra_dma_sg_req *nsg_req)
432{
433 unsigned long status;
434
435 /*
436 * The DMA controller reloads the new configuration for next transfer
437 * after last burst of current transfer completes.
438 * If there is no IEC status then this makes sure that last burst
439 * has not be completed. There may be case that last burst is on
440 * flight and so it can complete but because DMA is paused, it
441 * will not generates interrupt as well as not reload the new
442 * configuration.
443 * If there is already IEC status then interrupt handler need to
444 * load new configuration.
445 */
1b140908 446 tegra_dma_pause(tdc, false);
ec8a1586
LD		 447 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
448
449 /*
450 * If interrupt is pending then do nothing as the ISR will handle
451 * the programing for new request.
452 */
453 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
454 dev_err(tdc2dev(tdc),
455 "Skipping new configuration as interrupt is pending\n");
1b140908 456 tegra_dma_resume(tdc);
ec8a1586
LD		 457 return;
458 }
459
460 /* Safe to program new configuration */
461 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
462 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
463 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
464 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
465 nsg_req->configured = true;
466
1b140908 467 tegra_dma_resume(tdc);
ec8a1586
LD		 468}
469
470static void tdc_start_head_req(struct tegra_dma_channel *tdc)
471{
472 struct tegra_dma_sg_req *sg_req;
473
474 if (list_empty(&tdc->pending_sg_req))
475 return;
476
477 sg_req = list_first_entry(&tdc->pending_sg_req,
478 typeof(*sg_req), node);
479 tegra_dma_start(tdc, sg_req);
480 sg_req->configured = true;
481 tdc->busy = true;
482}
483
484static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
485{
486 struct tegra_dma_sg_req *hsgreq;
487 struct tegra_dma_sg_req *hnsgreq;
488
489 if (list_empty(&tdc->pending_sg_req))
490 return;
491
492 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
493 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
494 hnsgreq = list_first_entry(&hsgreq->node,
495 typeof(*hnsgreq), node);
496 tegra_dma_configure_for_next(tdc, hnsgreq);
497 }
498}
499
500static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
501 struct tegra_dma_sg_req *sg_req, unsigned long status)
502{
503 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
504}
505
506static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
507{
508 struct tegra_dma_sg_req *sgreq;
509 struct tegra_dma_desc *dma_desc;
510
511 while (!list_empty(&tdc->pending_sg_req)) {
512 sgreq = list_first_entry(&tdc->pending_sg_req,
513 typeof(*sgreq), node);
2cc44e63 514 list_move_tail(&sgreq->node, &tdc->free_sg_req);
ec8a1586
LD		 515 if (sgreq->last_sg) {
516 dma_desc = sgreq->dma_desc;
517 dma_desc->dma_status = DMA_ERROR;
518 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
519
520 /* Add in cb list if it is not there. */
521 if (!dma_desc->cb_count)
522 list_add_tail(&dma_desc->cb_node,
523 &tdc->cb_desc);
524 dma_desc->cb_count++;
525 }
526 }
527 tdc->isr_handler = NULL;
528}
529
530static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
531 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
532{
533 struct tegra_dma_sg_req *hsgreq = NULL;
534
535 if (list_empty(&tdc->pending_sg_req)) {
536 dev_err(tdc2dev(tdc), "Dma is running without req\n");
537 tegra_dma_stop(tdc);
538 return false;
539 }
540
541 /*
542 * Check that head req on list should be in flight.
543 * If it is not in flight then abort transfer as
544 * looping of transfer can not continue.
545 */
546 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
547 if (!hsgreq->configured) {
548 tegra_dma_stop(tdc);
549 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
550 tegra_dma_abort_all(tdc);
551 return false;
552 }
553
554 /* Configure next request */
555 if (!to_terminate)
556 tdc_configure_next_head_desc(tdc);
557 return true;
558}
559
560static void handle_once_dma_done(struct tegra_dma_channel *tdc,
561 bool to_terminate)
562{
563 struct tegra_dma_sg_req *sgreq;
564 struct tegra_dma_desc *dma_desc;
565
566 tdc->busy = false;
567 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
568 dma_desc = sgreq->dma_desc;
569 dma_desc->bytes_transferred += sgreq->req_len;
570
571 list_del(&sgreq->node);
572 if (sgreq->last_sg) {
573 dma_desc->dma_status = DMA_SUCCESS;
574 dma_cookie_complete(&dma_desc->txd);
575 if (!dma_desc->cb_count)
576 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
577 dma_desc->cb_count++;
578 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
579 }
580 list_add_tail(&sgreq->node, &tdc->free_sg_req);
581
582 /* Do not start DMA if it is going to be terminate */
583 if (to_terminate || list_empty(&tdc->pending_sg_req))
584 return;
585
586 tdc_start_head_req(tdc);
587 return;
588}
589
590static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
591 bool to_terminate)
592{
593 struct tegra_dma_sg_req *sgreq;
594 struct tegra_dma_desc *dma_desc;
595 bool st;
596
597 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
598 dma_desc = sgreq->dma_desc;
599 dma_desc->bytes_transferred += sgreq->req_len;
600
601 /* Callback need to be call */
602 if (!dma_desc->cb_count)
603 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
604 dma_desc->cb_count++;
605
606 /* If not last req then put at end of pending list */
607 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
2cc44e63 608 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
ec8a1586
LD		 609 sgreq->configured = false;
610 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
611 if (!st)
612 dma_desc->dma_status = DMA_ERROR;
613 }
614 return;
615}
616
617static void tegra_dma_tasklet(unsigned long data)
618{
619 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
620 dma_async_tx_callback callback = NULL;
621 void *callback_param = NULL;
622 struct tegra_dma_desc *dma_desc;
623 unsigned long flags;
624 int cb_count;
625
626 spin_lock_irqsave(&tdc->lock, flags);
627 while (!list_empty(&tdc->cb_desc)) {
628 dma_desc = list_first_entry(&tdc->cb_desc,
629 typeof(*dma_desc), cb_node);
630 list_del(&dma_desc->cb_node);
631 callback = dma_desc->txd.callback;
632 callback_param = dma_desc->txd.callback_param;
633 cb_count = dma_desc->cb_count;
634 dma_desc->cb_count = 0;
635 spin_unlock_irqrestore(&tdc->lock, flags);
636 while (cb_count-- && callback)
637 callback(callback_param);
638 spin_lock_irqsave(&tdc->lock, flags);
639 }
640 spin_unlock_irqrestore(&tdc->lock, flags);
641}
642
643static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
644{
645 struct tegra_dma_channel *tdc = dev_id;
646 unsigned long status;
647 unsigned long flags;
648
649 spin_lock_irqsave(&tdc->lock, flags);
650
651 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
652 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
653 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
654 tdc->isr_handler(tdc, false);
655 tasklet_schedule(&tdc->tasklet);
656 spin_unlock_irqrestore(&tdc->lock, flags);
657 return IRQ_HANDLED;
658 }
659
660 spin_unlock_irqrestore(&tdc->lock, flags);
661 dev_info(tdc2dev(tdc),
662 "Interrupt already served status 0x%08lx\n", status);
663 return IRQ_NONE;
664}
665
666static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
667{
668 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
669 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
670 unsigned long flags;
671 dma_cookie_t cookie;
672
673 spin_lock_irqsave(&tdc->lock, flags);
674 dma_desc->dma_status = DMA_IN_PROGRESS;
675 cookie = dma_cookie_assign(&dma_desc->txd);
676 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
677 spin_unlock_irqrestore(&tdc->lock, flags);
678 return cookie;
679}
680
681static void tegra_dma_issue_pending(struct dma_chan *dc)
682{
683 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
684 unsigned long flags;
685
686 spin_lock_irqsave(&tdc->lock, flags);
687 if (list_empty(&tdc->pending_sg_req)) {
688 dev_err(tdc2dev(tdc), "No DMA request\n");
689 goto end;
690 }
691 if (!tdc->busy) {
692 tdc_start_head_req(tdc);
693
694 /* Continuous single mode: Configure next req */
695 if (tdc->cyclic) {
696 /*
697 * Wait for 1 burst time for configure DMA for
698 * next transfer.
699 */
700 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
701 tdc_configure_next_head_desc(tdc);
702 }
703 }
704end:
705 spin_unlock_irqrestore(&tdc->lock, flags);
706 return;
707}
708
709static void tegra_dma_terminate_all(struct dma_chan *dc)
710{
711 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
712 struct tegra_dma_sg_req *sgreq;
713 struct tegra_dma_desc *dma_desc;
714 unsigned long flags;
715 unsigned long status;
716 bool was_busy;
717
718 spin_lock_irqsave(&tdc->lock, flags);
719 if (list_empty(&tdc->pending_sg_req)) {
720 spin_unlock_irqrestore(&tdc->lock, flags);
721 return;
722 }
723
724 if (!tdc->busy)
725 goto skip_dma_stop;
726
727 /* Pause DMA before checking the queue status */
1b140908 728 tegra_dma_pause(tdc, true);
ec8a1586
LD		 729
730 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
731 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
732 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
733 tdc->isr_handler(tdc, true);
734 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
735 }
736
737 was_busy = tdc->busy;
738 tegra_dma_stop(tdc);
739
740 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
741 sgreq = list_first_entry(&tdc->pending_sg_req,
742 typeof(*sgreq), node);
743 sgreq->dma_desc->bytes_transferred +=
744 get_current_xferred_count(tdc, sgreq, status);
745 }
1b140908 746 tegra_dma_resume(tdc);
ec8a1586
LD		 747
748skip_dma_stop:
749 tegra_dma_abort_all(tdc);
750
751 while (!list_empty(&tdc->cb_desc)) {
752 dma_desc = list_first_entry(&tdc->cb_desc,
753 typeof(*dma_desc), cb_node);
754 list_del(&dma_desc->cb_node);
755 dma_desc->cb_count = 0;
756 }
757 spin_unlock_irqrestore(&tdc->lock, flags);
758}
759
760static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
761 dma_cookie_t cookie, struct dma_tx_state *txstate)
762{
763 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
764 struct tegra_dma_desc *dma_desc;
765 struct tegra_dma_sg_req *sg_req;
766 enum dma_status ret;
767 unsigned long flags;
4a46ba36 768 unsigned int residual;
ec8a1586
LD		 769
770 spin_lock_irqsave(&tdc->lock, flags);
771
772 ret = dma_cookie_status(dc, cookie, txstate);
773 if (ret == DMA_SUCCESS) {
ec8a1586
LD		 774 spin_unlock_irqrestore(&tdc->lock, flags);
775 return ret;
776 }
777
778 /* Check on wait_ack desc status */
779 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
780 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 781 residual = dma_desc->bytes_requested -
782 (dma_desc->bytes_transferred %
783 dma_desc->bytes_requested);
784 dma_set_residue(txstate, residual);
ec8a1586
LD		 785 ret = dma_desc->dma_status;
786 spin_unlock_irqrestore(&tdc->lock, flags);
787 return ret;
788 }
789 }
790
791 /* Check in pending list */
792 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
793 dma_desc = sg_req->dma_desc;
794 if (dma_desc->txd.cookie == cookie) {
4a46ba36
LD		 795 residual = dma_desc->bytes_requested -
796 (dma_desc->bytes_transferred %
797 dma_desc->bytes_requested);
798 dma_set_residue(txstate, residual);
ec8a1586
LD		 799 ret = dma_desc->dma_status;
800 spin_unlock_irqrestore(&tdc->lock, flags);
801 return ret;
802 }
803 }
804
805 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
806 spin_unlock_irqrestore(&tdc->lock, flags);
807 return ret;
808}
809
810static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
811 unsigned long arg)
812{
813 switch (cmd) {
814 case DMA_SLAVE_CONFIG:
815 return tegra_dma_slave_config(dc,
816 (struct dma_slave_config *)arg);
817
818 case DMA_TERMINATE_ALL:
819 tegra_dma_terminate_all(dc);
820 return 0;
821
822 default:
823 break;
824 }
825
826 return -ENXIO;
827}
828
829static inline int get_bus_width(struct tegra_dma_channel *tdc,
830 enum dma_slave_buswidth slave_bw)
831{
832 switch (slave_bw) {
833 case DMA_SLAVE_BUSWIDTH_1_BYTE:
834 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
835 case DMA_SLAVE_BUSWIDTH_2_BYTES:
836 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
837 case DMA_SLAVE_BUSWIDTH_4_BYTES:
838 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
839 case DMA_SLAVE_BUSWIDTH_8_BYTES:
840 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
841 default:
842 dev_warn(tdc2dev(tdc),
843 "slave bw is not supported, using 32bits\n");
844 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
845 }
846}
847
848static inline int get_burst_size(struct tegra_dma_channel *tdc,
849 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
850{
851 int burst_byte;
852 int burst_ahb_width;
853
854 /*
855 * burst_size from client is in terms of the bus_width.
856 * convert them into AHB memory width which is 4 byte.
857 */
858 burst_byte = burst_size * slave_bw;
859 burst_ahb_width = burst_byte / 4;
860
861 /* If burst size is 0 then calculate the burst size based on length */
862 if (!burst_ahb_width) {
863 if (len & 0xF)
864 return TEGRA_APBDMA_AHBSEQ_BURST_1;
865 else if ((len >> 4) & 0x1)
866 return TEGRA_APBDMA_AHBSEQ_BURST_4;
867 else
868 return TEGRA_APBDMA_AHBSEQ_BURST_8;
869 }
870 if (burst_ahb_width < 4)
871 return TEGRA_APBDMA_AHBSEQ_BURST_1;
872 else if (burst_ahb_width < 8)
873 return TEGRA_APBDMA_AHBSEQ_BURST_4;
874 else
875 return TEGRA_APBDMA_AHBSEQ_BURST_8;
876}
877
878static int get_transfer_param(struct tegra_dma_channel *tdc,
879 enum dma_transfer_direction direction, unsigned long *apb_addr,
880 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
881 enum dma_slave_buswidth *slave_bw)
882{
883
884 switch (direction) {
885 case DMA_MEM_TO_DEV:
886 *apb_addr = tdc->dma_sconfig.dst_addr;
887 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
888 *burst_size = tdc->dma_sconfig.dst_maxburst;
889 *slave_bw = tdc->dma_sconfig.dst_addr_width;
890 *csr = TEGRA_APBDMA_CSR_DIR;
891 return 0;
892
893 case DMA_DEV_TO_MEM:
894 *apb_addr = tdc->dma_sconfig.src_addr;
895 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
896 *burst_size = tdc->dma_sconfig.src_maxburst;
897 *slave_bw = tdc->dma_sconfig.src_addr_width;
898 *csr = 0;
899 return 0;
900
901 default:
902 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
903 return -EINVAL;
904 }
905 return -EINVAL;
906}
907
908static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
909 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
910 enum dma_transfer_direction direction, unsigned long flags,
911 void *context)
912{
913 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
914 struct tegra_dma_desc *dma_desc;
915 unsigned int i;
916 struct scatterlist *sg;
917 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
918 struct list_head req_list;
919 struct tegra_dma_sg_req *sg_req = NULL;
920 u32 burst_size;
921 enum dma_slave_buswidth slave_bw;
922 int ret;
923
924 if (!tdc->config_init) {
925 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
926 return NULL;
927 }
928 if (sg_len < 1) {
929 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
930 return NULL;
931 }
932
933 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
934 &burst_size, &slave_bw);
935 if (ret < 0)
936 return NULL;
937
938 INIT_LIST_HEAD(&req_list);
939
940 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
941 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
942 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
943 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
944
945 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
946 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
947 if (flags & DMA_PREP_INTERRUPT)
948 csr |= TEGRA_APBDMA_CSR_IE_EOC;
949
950 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
951
952 dma_desc = tegra_dma_desc_get(tdc);
953 if (!dma_desc) {
954 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
955 return NULL;
956 }
957 INIT_LIST_HEAD(&dma_desc->tx_list);
958 INIT_LIST_HEAD(&dma_desc->cb_node);
959 dma_desc->cb_count = 0;
960 dma_desc->bytes_requested = 0;
961 dma_desc->bytes_transferred = 0;
962 dma_desc->dma_status = DMA_IN_PROGRESS;
963
964 /* Make transfer requests */
965 for_each_sg(sgl, sg, sg_len, i) {
966 u32 len, mem;
967
597c8549 968 mem = sg_dma_address(sg);
ec8a1586
LD		 969 len = sg_dma_len(sg);
970
971 if ((len & 3) || (mem & 3) ||
972 (len > tdc->tdma->chip_data->max_dma_count)) {
973 dev_err(tdc2dev(tdc),
974 "Dma length/memory address is not supported\n");
975 tegra_dma_desc_put(tdc, dma_desc);
976 return NULL;
977 }
978
979 sg_req = tegra_dma_sg_req_get(tdc);
980 if (!sg_req) {
981 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
982 tegra_dma_desc_put(tdc, dma_desc);
983 return NULL;
984 }
985
986 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
987 dma_desc->bytes_requested += len;
988
989 sg_req->ch_regs.apb_ptr = apb_ptr;
990 sg_req->ch_regs.ahb_ptr = mem;
991 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
992 sg_req->ch_regs.apb_seq = apb_seq;
993 sg_req->ch_regs.ahb_seq = ahb_seq;
994 sg_req->configured = false;
995 sg_req->last_sg = false;
996 sg_req->dma_desc = dma_desc;
997 sg_req->req_len = len;
998
999 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1000 }
1001 sg_req->last_sg = true;
1002 if (flags & DMA_CTRL_ACK)
1003 dma_desc->txd.flags = DMA_CTRL_ACK;
1004
1005 /*
1006 * Make sure that mode should not be conflicting with currently
1007 * configured mode.
1008 */
1009 if (!tdc->isr_handler) {
1010 tdc->isr_handler = handle_once_dma_done;
1011 tdc->cyclic = false;
1012 } else {
1013 if (tdc->cyclic) {
1014 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1015 tegra_dma_desc_put(tdc, dma_desc);
1016 return NULL;
1017 }
1018 }
1019
1020 return &dma_desc->txd;
1021}
1022
1023struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1024 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1025 size_t period_len, enum dma_transfer_direction direction,
ec8b5e48 1026 unsigned long flags, void *context)
ec8a1586
LD		 1027{
1028 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1029 struct tegra_dma_desc *dma_desc = NULL;
1030 struct tegra_dma_sg_req *sg_req = NULL;
1031 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1032 int len;
1033 size_t remain_len;
1034 dma_addr_t mem = buf_addr;
1035 u32 burst_size;
1036 enum dma_slave_buswidth slave_bw;
1037 int ret;
1038
1039 if (!buf_len || !period_len) {
1040 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1041 return NULL;
1042 }
1043
1044 if (!tdc->config_init) {
1045 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1046 return NULL;
1047 }
1048
1049 /*
1050 * We allow to take more number of requests till DMA is
1051 * not started. The driver will loop over all requests.
1052 * Once DMA is started then new requests can be queued only after
1053 * terminating the DMA.
1054 */
1055 if (tdc->busy) {
1056 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1057 return NULL;
1058 }
1059
1060 /*
1061 * We only support cycle transfer when buf_len is multiple of
1062 * period_len.
1063 */
1064 if (buf_len % period_len) {
1065 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1066 return NULL;
1067 }
1068
1069 len = period_len;
1070 if ((len & 3) || (buf_addr & 3) ||
1071 (len > tdc->tdma->chip_data->max_dma_count)) {
1072 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1073 return NULL;
1074 }
1075
1076 ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1077 &burst_size, &slave_bw);
1078 if (ret < 0)
1079 return NULL;
1080
1081
1082 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1083 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1084 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1085 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1086
b9bb37f5
LD		 1087 csr |= TEGRA_APBDMA_CSR_FLOW;
1088 if (flags & DMA_PREP_INTERRUPT)
1089 csr |= TEGRA_APBDMA_CSR_IE_EOC;
ec8a1586
LD		 1090 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1091
1092 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1093
1094 dma_desc = tegra_dma_desc_get(tdc);
1095 if (!dma_desc) {
1096 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1097 return NULL;
1098 }
1099
1100 INIT_LIST_HEAD(&dma_desc->tx_list);
1101 INIT_LIST_HEAD(&dma_desc->cb_node);
1102 dma_desc->cb_count = 0;
1103
1104 dma_desc->bytes_transferred = 0;
1105 dma_desc->bytes_requested = buf_len;
1106 remain_len = buf_len;
1107
1108 /* Split transfer equal to period size */
1109 while (remain_len) {
1110 sg_req = tegra_dma_sg_req_get(tdc);
1111 if (!sg_req) {
1112 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1113 tegra_dma_desc_put(tdc, dma_desc);
1114 return NULL;
1115 }
1116
1117 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1118 sg_req->ch_regs.apb_ptr = apb_ptr;
1119 sg_req->ch_regs.ahb_ptr = mem;
1120 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1121 sg_req->ch_regs.apb_seq = apb_seq;
1122 sg_req->ch_regs.ahb_seq = ahb_seq;
1123 sg_req->configured = false;
1124 sg_req->half_done = false;
1125 sg_req->last_sg = false;
1126 sg_req->dma_desc = dma_desc;
1127 sg_req->req_len = len;
1128
1129 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1130 remain_len -= len;
1131 mem += len;
1132 }
1133 sg_req->last_sg = true;
b9bb37f5
LD		 1134 if (flags & DMA_CTRL_ACK)
1135 dma_desc->txd.flags = DMA_CTRL_ACK;
ec8a1586
LD		 1136
1137 /*
1138 * Make sure that mode should not be conflicting with currently
1139 * configured mode.
1140 */
1141 if (!tdc->isr_handler) {
1142 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1143 tdc->cyclic = true;
1144 } else {
1145 if (!tdc->cyclic) {
1146 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1147 tegra_dma_desc_put(tdc, dma_desc);
1148 return NULL;
1149 }
1150 }
1151
1152 return &dma_desc->txd;
1153}
1154
1155static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1156{
1157 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306
LD		 1158 struct tegra_dma *tdma = tdc->tdma;
1159 int ret;
ec8a1586
LD		 1160
1161 dma_cookie_init(&tdc->dma_chan);
1162 tdc->config_init = false;
ffc49306
LD		 1163 ret = clk_prepare_enable(tdma->dma_clk);
1164 if (ret < 0)
1165 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1166 return ret;
ec8a1586
LD		 1167}
1168
1169static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1170{
1171 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
ffc49306 1172 struct tegra_dma *tdma = tdc->tdma;
ec8a1586
LD		 1173
1174 struct tegra_dma_desc *dma_desc;
1175 struct tegra_dma_sg_req *sg_req;
1176 struct list_head dma_desc_list;
1177 struct list_head sg_req_list;
1178 unsigned long flags;
1179
1180 INIT_LIST_HEAD(&dma_desc_list);
1181 INIT_LIST_HEAD(&sg_req_list);
1182
1183 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1184
1185 if (tdc->busy)
1186 tegra_dma_terminate_all(dc);
1187
1188 spin_lock_irqsave(&tdc->lock, flags);
1189 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1190 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1191 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1192 INIT_LIST_HEAD(&tdc->cb_desc);
1193 tdc->config_init = false;
1194 spin_unlock_irqrestore(&tdc->lock, flags);
1195
1196 while (!list_empty(&dma_desc_list)) {
1197 dma_desc = list_first_entry(&dma_desc_list,
1198 typeof(*dma_desc), node);
1199 list_del(&dma_desc->node);
1200 kfree(dma_desc);
1201 }
1202
1203 while (!list_empty(&sg_req_list)) {
1204 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1205 list_del(&sg_req->node);
1206 kfree(sg_req);
1207 }
ffc49306 1208 clk_disable_unprepare(tdma->dma_clk);
ec8a1586
LD		 1209}
1210
1211/* Tegra20 specific DMA controller information */
75f21631 1212static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
ec8a1586
LD		 1213 .nr_channels = 16,
1214 .max_dma_count = 1024UL * 64,
1b140908 1215 .support_channel_pause = false,
ec8a1586
LD		 1216};
1217
ec8a1586 1218/* Tegra30 specific DMA controller information */
75f21631 1219static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
ec8a1586
LD		 1220 .nr_channels = 32,
1221 .max_dma_count = 1024UL * 64,
1b140908 1222 .support_channel_pause = false,
ec8a1586
LD		 1223};
1224
5ea7caf3
LD		 1225/* Tegra114 specific DMA controller information */
1226static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1227 .nr_channels = 32,
1228 .max_dma_count = 1024UL * 64,
1229 .support_channel_pause = true,
1230};
1231
1232
4bf27b8b 1233static const struct of_device_id tegra_dma_of_match[] = {
ec8a1586 1234 {
5ea7caf3
LD		 1235 .compatible = "nvidia,tegra114-apbdma",
1236 .data = &tegra114_dma_chip_data,
1237 }, {
cd9092c6 1238 .compatible = "nvidia,tegra30-apbdma",
ec8a1586
LD		 1239 .data = &tegra30_dma_chip_data,
1240 }, {
cd9092c6 1241 .compatible = "nvidia,tegra20-apbdma",
ec8a1586
LD		 1242 .data = &tegra20_dma_chip_data,
1243 }, {
1244 },
1245};
1246MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
ec8a1586 1247
463a1f8b 1248static int tegra_dma_probe(struct platform_device *pdev)
ec8a1586
LD		 1249{
1250 struct resource *res;
1251 struct tegra_dma *tdma;
1252 int ret;
1253 int i;
83a1ef2e 1254 const struct tegra_dma_chip_data *cdata = NULL;
dc7badba 1255 const struct of_device_id *match;
ec8a1586 1256
dc7badba
SW		 1257 match = of_match_device(tegra_dma_of_match, &pdev->dev);
1258 if (!match) {
1259 dev_err(&pdev->dev, "Error: No device match found\n");
1260 return -ENODEV;
ec8a1586 1261 }
dc7badba 1262 cdata = match->data;
ec8a1586
LD		 1263
1264 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1265 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1266 if (!tdma) {
1267 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1268 return -ENOMEM;
1269 }
1270
1271 tdma->dev = &pdev->dev;
1272 tdma->chip_data = cdata;
1273 platform_set_drvdata(pdev, tdma);
1274
1275 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7331205a
TR		 1276 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1277 if (IS_ERR(tdma->base_addr))
1278 return PTR_ERR(tdma->base_addr);
ec8a1586
LD		 1279
1280 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1281 if (IS_ERR(tdma->dma_clk)) {
1282 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1283 return PTR_ERR(tdma->dma_clk);
1284 }
1285
1286 spin_lock_init(&tdma->global_lock);
1287
1288 pm_runtime_enable(&pdev->dev);
1289 if (!pm_runtime_enabled(&pdev->dev)) {
1290 ret = tegra_dma_runtime_resume(&pdev->dev);
1291 if (ret) {
1292 dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1293 ret);
1294 goto err_pm_disable;
1295 }
1296 }
1297
ffc49306
LD		 1298 /* Enable clock before accessing registers */
1299 ret = clk_prepare_enable(tdma->dma_clk);
1300 if (ret < 0) {
1301 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1302 goto err_pm_disable;
1303 }
1304
ec8a1586
LD		 1305 /* Reset DMA controller */
1306 tegra_periph_reset_assert(tdma->dma_clk);
1307 udelay(2);
1308 tegra_periph_reset_deassert(tdma->dma_clk);
1309
1310 /* Enable global DMA registers */
1311 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1312 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1313 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1314
ffc49306
LD		 1315 clk_disable_unprepare(tdma->dma_clk);
1316
ec8a1586
LD		 1317 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1318 for (i = 0; i < cdata->nr_channels; i++) {
1319 struct tegra_dma_channel *tdc = &tdma->channels[i];
ec8a1586
LD		 1320
1321 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1322 i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1323
1324 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1325 if (!res) {
1326 ret = -EINVAL;
1327 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1328 goto err_irq;
1329 }
1330 tdc->irq = res->start;
d0fc9054 1331 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
ec8a1586 1332 ret = devm_request_irq(&pdev->dev, tdc->irq,
d0fc9054 1333 tegra_dma_isr, 0, tdc->name, tdc);
ec8a1586
LD		 1334 if (ret) {
1335 dev_err(&pdev->dev,
1336 "request_irq failed with err %d channel %d\n",
1337 i, ret);
1338 goto err_irq;
1339 }
1340
1341 tdc->dma_chan.device = &tdma->dma_dev;
1342 dma_cookie_init(&tdc->dma_chan);
1343 list_add_tail(&tdc->dma_chan.device_node,
1344 &tdma->dma_dev.channels);
1345 tdc->tdma = tdma;
1346 tdc->id = i;
1347
1348 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1349 (unsigned long)tdc);
1350 spin_lock_init(&tdc->lock);
1351
1352 INIT_LIST_HEAD(&tdc->pending_sg_req);
1353 INIT_LIST_HEAD(&tdc->free_sg_req);
1354 INIT_LIST_HEAD(&tdc->free_dma_desc);
1355 INIT_LIST_HEAD(&tdc->cb_desc);
1356 }
1357
1358 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1359 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
46fb3f8e
LD		 1360 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1361
ec8a1586
LD		 1362 tdma->dma_dev.dev = &pdev->dev;
1363 tdma->dma_dev.device_alloc_chan_resources =
1364 tegra_dma_alloc_chan_resources;
1365 tdma->dma_dev.device_free_chan_resources =
1366 tegra_dma_free_chan_resources;
1367 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1368 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1369 tdma->dma_dev.device_control = tegra_dma_device_control;
1370 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1371 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1372
1373 ret = dma_async_device_register(&tdma->dma_dev);
1374 if (ret < 0) {
1375 dev_err(&pdev->dev,
1376 "Tegra20 APB DMA driver registration failed %d\n", ret);
1377 goto err_irq;
1378 }
1379
1380 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1381 cdata->nr_channels);
1382 return 0;
1383
1384err_irq:
1385 while (--i >= 0) {
1386 struct tegra_dma_channel *tdc = &tdma->channels[i];
1387 tasklet_kill(&tdc->tasklet);
1388 }
1389
1390err_pm_disable:
1391 pm_runtime_disable(&pdev->dev);
1392 if (!pm_runtime_status_suspended(&pdev->dev))
1393 tegra_dma_runtime_suspend(&pdev->dev);
1394 return ret;
1395}
1396
4bf27b8b 1397static int tegra_dma_remove(struct platform_device *pdev)
ec8a1586
LD		 1398{
1399 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1400 int i;
1401 struct tegra_dma_channel *tdc;
1402
1403 dma_async_device_unregister(&tdma->dma_dev);
1404
1405 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1406 tdc = &tdma->channels[i];
1407 tasklet_kill(&tdc->tasklet);
1408 }
1409
1410 pm_runtime_disable(&pdev->dev);
1411 if (!pm_runtime_status_suspended(&pdev->dev))
1412 tegra_dma_runtime_suspend(&pdev->dev);
1413
1414 return 0;
1415}
1416
1417static int tegra_dma_runtime_suspend(struct device *dev)
1418{
1419 struct platform_device *pdev = to_platform_device(dev);
1420 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1421
56482ec0 1422 clk_disable_unprepare(tdma->dma_clk);
ec8a1586
LD		 1423 return 0;
1424}
1425
1426static int tegra_dma_runtime_resume(struct device *dev)
1427{
1428 struct platform_device *pdev = to_platform_device(dev);
1429 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1430 int ret;
1431
56482ec0 1432 ret = clk_prepare_enable(tdma->dma_clk);
ec8a1586
LD		 1433 if (ret < 0) {
1434 dev_err(dev, "clk_enable failed: %d\n", ret);
1435 return ret;
1436 }
1437 return 0;
1438}
1439
3065c194
LD		 1440#ifdef CONFIG_PM_SLEEP
1441static int tegra_dma_pm_suspend(struct device *dev)
1442{
1443 struct tegra_dma *tdma = dev_get_drvdata(dev);
1444 int i;
1445 int ret;
1446
1447 /* Enable clock before accessing register */
1448 ret = tegra_dma_runtime_resume(dev);
1449 if (ret < 0)
1450 return ret;
1451
1452 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1453 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1454 struct tegra_dma_channel *tdc = &tdma->channels[i];
1455 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1456
1457 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1458 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1459 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1460 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1461 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1462 }
1463
1464 /* Disable clock */
1465 tegra_dma_runtime_suspend(dev);
1466 return 0;
1467}
1468
1469static int tegra_dma_pm_resume(struct device *dev)
1470{
1471 struct tegra_dma *tdma = dev_get_drvdata(dev);
1472 int i;
1473 int ret;
1474
1475 /* Enable clock before accessing register */
1476 ret = tegra_dma_runtime_resume(dev);
1477 if (ret < 0)
1478 return ret;
1479
1480 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1481 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1482 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1483
1484 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1485 struct tegra_dma_channel *tdc = &tdma->channels[i];
1486 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1487
1488 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1489 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1490 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1491 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1492 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1493 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1494 }
1495
1496 /* Disable clock */
1497 tegra_dma_runtime_suspend(dev);
1498 return 0;
1499}
1500#endif
1501
4bf27b8b 1502static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
ec8a1586
LD		 1503#ifdef CONFIG_PM_RUNTIME
1504 .runtime_suspend = tegra_dma_runtime_suspend,
1505 .runtime_resume = tegra_dma_runtime_resume,
1506#endif
3065c194 1507 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
ec8a1586
LD		 1508};
1509
1510static struct platform_driver tegra_dmac_driver = {
1511 .driver = {
cd9092c6 1512 .name = "tegra-apbdma",
ec8a1586
LD		 1513 .owner = THIS_MODULE,
1514 .pm = &tegra_dma_dev_pm_ops,
dc7badba 1515 .of_match_table = tegra_dma_of_match,
ec8a1586
LD		 1516 },
1517 .probe = tegra_dma_probe,
a7d6e3ec 1518 .remove = tegra_dma_remove,
ec8a1586
LD		 1519};
1520
1521module_platform_driver(tegra_dmac_driver);
1522
1523MODULE_ALIAS("platform:tegra20-apbdma");
1524MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1525MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1526MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)