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fix mali API_VERSION grep
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / coh901318.c
CommitLineData
61f135b9
LW		 1/*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/kernel.h> /* printk() */
13#include <linux/fs.h> /* everything... */
b7f080cf 14#include <linux/scatterlist.h>
61f135b9
LW		 15#include <linux/slab.h> /* kmalloc() */
16#include <linux/dmaengine.h>
17#include <linux/platform_device.h>
18#include <linux/device.h>
19#include <linux/irqreturn.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/uaccess.h>
23#include <linux/debugfs.h>
9f575d97 24#include <linux/platform_data/dma-coh901318.h>
61f135b9 25
2b9277ad 26#include "coh901318.h"
d2ebfb33 27#include "dmaengine.h"
61f135b9 28
03b5357c
LW		 29#define COH901318_MOD32_MASK (0x1F)
30#define COH901318_WORD_MASK (0xFFFFFFFF)
31/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
32#define COH901318_INT_STATUS1 (0x0000)
33#define COH901318_INT_STATUS2 (0x0004)
34/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
35#define COH901318_TC_INT_STATUS1 (0x0008)
36#define COH901318_TC_INT_STATUS2 (0x000C)
37/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
38#define COH901318_TC_INT_CLEAR1 (0x0010)
39#define COH901318_TC_INT_CLEAR2 (0x0014)
40/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
41#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
42#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
43/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
44#define COH901318_BE_INT_STATUS1 (0x0020)
45#define COH901318_BE_INT_STATUS2 (0x0024)
46/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
47#define COH901318_BE_INT_CLEAR1 (0x0028)
48#define COH901318_BE_INT_CLEAR2 (0x002C)
49/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
50#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
51#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
52
53/*
54 * CX_CFG - Channel Configuration Registers 32bit (R/W)
55 */
56#define COH901318_CX_CFG (0x0100)
57#define COH901318_CX_CFG_SPACING (0x04)
58/* Channel enable activates tha dma job */
59#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
60#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
61/* Request Mode */
62#define COH901318_CX_CFG_RM_MASK (0x00000006)
63#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
64#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
65#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
66#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
67#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
68/* Linked channel request field. RM must == 11 */
69#define COH901318_CX_CFG_LCRF_SHIFT 3
70#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
71#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
72/* Terminal Counter Interrupt Request Mask */
73#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
74#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
75/* Bus Error interrupt Mask */
76#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
77#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
78
79/*
80 * CX_STAT - Channel Status Registers 32bit (R/-)
81 */
82#define COH901318_CX_STAT (0x0200)
83#define COH901318_CX_STAT_SPACING (0x04)
84#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
85#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
86#define COH901318_CX_STAT_ACTIVE (0x00000002)
87#define COH901318_CX_STAT_ENABLED (0x00000001)
88
89/*
90 * CX_CTRL - Channel Control Registers 32bit (R/W)
91 */
92#define COH901318_CX_CTRL (0x0400)
93#define COH901318_CX_CTRL_SPACING (0x10)
94/* Transfer Count Enable */
95#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
96#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
97/* Transfer Count Value 0 - 4095 */
98#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
99/* Burst count */
100#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
101#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
102#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
103#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
104#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
105#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
106#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
107#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
108#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
109/* Source bus size */
110#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
111#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
112#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
113#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
114/* Source address increment */
115#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
116#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
117/* Destination Bus Size */
118#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
119#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
120#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
121#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
122/* Destination address increment */
123#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
124#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
125/* Master Mode (Master2 is only connected to MSL) */
126#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
127#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
128#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
129#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
130#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
131/* Terminal Count flag to PER enable */
132#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
133#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
134/* Terminal Count flags to CPU enable */
135#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
136#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
137/* Hand shake to peripheral */
138#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
139#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
140#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
141#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
142/* DMA mode */
143#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
144#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
145#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
147/* Primary Request Data Destination */
148#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
149#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
150#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
151
152/*
153 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
154 */
155#define COH901318_CX_SRC_ADDR (0x0404)
156#define COH901318_CX_SRC_ADDR_SPACING (0x10)
157
158/*
159 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
160 */
161#define COH901318_CX_DST_ADDR (0x0408)
162#define COH901318_CX_DST_ADDR_SPACING (0x10)
163
164/*
165 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
166 */
167#define COH901318_CX_LNK_ADDR (0x040C)
168#define COH901318_CX_LNK_ADDR_SPACING (0x10)
169#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
170
171/**
172 * struct coh901318_params - parameters for DMAC configuration
173 * @config: DMA config register
174 * @ctrl_lli_last: DMA control register for the last lli in the list
175 * @ctrl_lli: DMA control register for an lli
176 * @ctrl_lli_chained: DMA control register for a chained lli
177 */
178struct coh901318_params {
179 u32 config;
180 u32 ctrl_lli_last;
181 u32 ctrl_lli;
182 u32 ctrl_lli_chained;
183};
184
185/**
186 * struct coh_dma_channel - dma channel base
187 * @name: ascii name of dma channel
188 * @number: channel id number
189 * @desc_nbr_max: number of preallocated descriptors
190 * @priority_high: prio of channel, 0 low otherwise high.
191 * @param: configuration parameters
192 */
193struct coh_dma_channel {
194 const char name[32];
195 const int number;
196 const int desc_nbr_max;
197 const int priority_high;
198 const struct coh901318_params param;
199};
200
03b5357c
LW		 201/**
202 * struct powersave - DMA power save structure
203 * @lock: lock protecting data in this struct
204 * @started_channels: bit mask indicating active dma channels
205 */
206struct powersave {
207 spinlock_t lock;
208 u64 started_channels;
209};
210
24dbcd8a
LW		 211/* points out all dma slave channels.
212 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
213 * Select all channels from A to B, end of list is marked with -1,-1
214 */
215static int dma_slave_channels[] = {
216 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
217 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
218
219/* points out all dma memcpy channels. */
220static int dma_memcpy_channels[] = {
221 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
222
24dbcd8a
LW		 223#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
224 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
225 COH901318_CX_CFG_LCR_DISABLE | \
226 COH901318_CX_CFG_TC_IRQ_ENABLE | \
227 COH901318_CX_CFG_BE_IRQ_ENABLE)
228#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
229 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
230 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
231 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
232 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
233 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
234 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
235 COH901318_CX_CTRL_TCP_DISABLE | \
236 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
237 COH901318_CX_CTRL_HSP_DISABLE | \
238 COH901318_CX_CTRL_HSS_DISABLE | \
239 COH901318_CX_CTRL_DDMA_LEGACY | \
240 COH901318_CX_CTRL_PRDD_SOURCE)
241#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
242 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
243 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
244 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
245 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
246 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
247 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
248 COH901318_CX_CTRL_TCP_DISABLE | \
249 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
250 COH901318_CX_CTRL_HSP_DISABLE | \
251 COH901318_CX_CTRL_HSS_DISABLE | \
252 COH901318_CX_CTRL_DDMA_LEGACY | \
253 COH901318_CX_CTRL_PRDD_SOURCE)
254#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
255 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
256 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
257 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
258 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
259 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
260 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
261 COH901318_CX_CTRL_TCP_DISABLE | \
262 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
263 COH901318_CX_CTRL_HSP_DISABLE | \
264 COH901318_CX_CTRL_HSS_DISABLE | \
265 COH901318_CX_CTRL_DDMA_LEGACY | \
266 COH901318_CX_CTRL_PRDD_SOURCE)
267
268const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
269 {
270 .number = U300_DMA_MSL_TX_0,
271 .name = "MSL TX 0",
272 .priority_high = 0,
24dbcd8a
LW		 273 },
274 {
275 .number = U300_DMA_MSL_TX_1,
276 .name = "MSL TX 1",
277 .priority_high = 0,
24dbcd8a
LW		 278 .param.config = COH901318_CX_CFG_CH_DISABLE |
279 COH901318_CX_CFG_LCR_DISABLE |
280 COH901318_CX_CFG_TC_IRQ_ENABLE |
281 COH901318_CX_CFG_BE_IRQ_ENABLE,
282 .param.ctrl_lli_chained = 0 |
283 COH901318_CX_CTRL_TC_ENABLE |
284 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
285 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
286 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
287 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
288 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
289 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
290 COH901318_CX_CTRL_TCP_DISABLE |
291 COH901318_CX_CTRL_TC_IRQ_DISABLE |
292 COH901318_CX_CTRL_HSP_ENABLE |
293 COH901318_CX_CTRL_HSS_DISABLE |
294 COH901318_CX_CTRL_DDMA_LEGACY |
295 COH901318_CX_CTRL_PRDD_SOURCE,
296 .param.ctrl_lli = 0 |
297 COH901318_CX_CTRL_TC_ENABLE |
298 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
299 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
300 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
301 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
302 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
303 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
304 COH901318_CX_CTRL_TCP_ENABLE |
305 COH901318_CX_CTRL_TC_IRQ_DISABLE |
306 COH901318_CX_CTRL_HSP_ENABLE |
307 COH901318_CX_CTRL_HSS_DISABLE |
308 COH901318_CX_CTRL_DDMA_LEGACY |
309 COH901318_CX_CTRL_PRDD_SOURCE,
310 .param.ctrl_lli_last = 0 |
311 COH901318_CX_CTRL_TC_ENABLE |
312 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
313 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
314 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
315 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
316 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
317 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
318 COH901318_CX_CTRL_TCP_ENABLE |
319 COH901318_CX_CTRL_TC_IRQ_ENABLE |
320 COH901318_CX_CTRL_HSP_ENABLE |
321 COH901318_CX_CTRL_HSS_DISABLE |
322 COH901318_CX_CTRL_DDMA_LEGACY |
323 COH901318_CX_CTRL_PRDD_SOURCE,
324 },
325 {
326 .number = U300_DMA_MSL_TX_2,
327 .name = "MSL TX 2",
328 .priority_high = 0,
24dbcd8a
LW		 329 .param.config = COH901318_CX_CFG_CH_DISABLE |
330 COH901318_CX_CFG_LCR_DISABLE |
331 COH901318_CX_CFG_TC_IRQ_ENABLE |
332 COH901318_CX_CFG_BE_IRQ_ENABLE,
333 .param.ctrl_lli_chained = 0 |
334 COH901318_CX_CTRL_TC_ENABLE |
335 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
336 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
337 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
338 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
339 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
340 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
341 COH901318_CX_CTRL_TCP_DISABLE |
342 COH901318_CX_CTRL_TC_IRQ_DISABLE |
343 COH901318_CX_CTRL_HSP_ENABLE |
344 COH901318_CX_CTRL_HSS_DISABLE |
345 COH901318_CX_CTRL_DDMA_LEGACY |
346 COH901318_CX_CTRL_PRDD_SOURCE,
347 .param.ctrl_lli = 0 |
348 COH901318_CX_CTRL_TC_ENABLE |
349 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
350 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
351 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
352 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
353 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
354 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
355 COH901318_CX_CTRL_TCP_ENABLE |
356 COH901318_CX_CTRL_TC_IRQ_DISABLE |
357 COH901318_CX_CTRL_HSP_ENABLE |
358 COH901318_CX_CTRL_HSS_DISABLE |
359 COH901318_CX_CTRL_DDMA_LEGACY |
360 COH901318_CX_CTRL_PRDD_SOURCE,
361 .param.ctrl_lli_last = 0 |
362 COH901318_CX_CTRL_TC_ENABLE |
363 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
364 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
365 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
366 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
367 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
368 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
369 COH901318_CX_CTRL_TCP_ENABLE |
370 COH901318_CX_CTRL_TC_IRQ_ENABLE |
371 COH901318_CX_CTRL_HSP_ENABLE |
372 COH901318_CX_CTRL_HSS_DISABLE |
373 COH901318_CX_CTRL_DDMA_LEGACY |
374 COH901318_CX_CTRL_PRDD_SOURCE,
375 .desc_nbr_max = 10,
376 },
377 {
378 .number = U300_DMA_MSL_TX_3,
379 .name = "MSL TX 3",
380 .priority_high = 0,
24dbcd8a
LW		 381 .param.config = COH901318_CX_CFG_CH_DISABLE |
382 COH901318_CX_CFG_LCR_DISABLE |
383 COH901318_CX_CFG_TC_IRQ_ENABLE |
384 COH901318_CX_CFG_BE_IRQ_ENABLE,
385 .param.ctrl_lli_chained = 0 |
386 COH901318_CX_CTRL_TC_ENABLE |
387 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
388 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
389 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
390 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
391 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
392 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
393 COH901318_CX_CTRL_TCP_DISABLE |
394 COH901318_CX_CTRL_TC_IRQ_DISABLE |
395 COH901318_CX_CTRL_HSP_ENABLE |
396 COH901318_CX_CTRL_HSS_DISABLE |
397 COH901318_CX_CTRL_DDMA_LEGACY |
398 COH901318_CX_CTRL_PRDD_SOURCE,
399 .param.ctrl_lli = 0 |
400 COH901318_CX_CTRL_TC_ENABLE |
401 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
402 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
403 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
404 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
405 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
406 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
407 COH901318_CX_CTRL_TCP_ENABLE |
408 COH901318_CX_CTRL_TC_IRQ_DISABLE |
409 COH901318_CX_CTRL_HSP_ENABLE |
410 COH901318_CX_CTRL_HSS_DISABLE |
411 COH901318_CX_CTRL_DDMA_LEGACY |
412 COH901318_CX_CTRL_PRDD_SOURCE,
413 .param.ctrl_lli_last = 0 |
414 COH901318_CX_CTRL_TC_ENABLE |
415 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
416 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
417 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
418 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
419 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
420 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
421 COH901318_CX_CTRL_TCP_ENABLE |
422 COH901318_CX_CTRL_TC_IRQ_ENABLE |
423 COH901318_CX_CTRL_HSP_ENABLE |
424 COH901318_CX_CTRL_HSS_DISABLE |
425 COH901318_CX_CTRL_DDMA_LEGACY |
426 COH901318_CX_CTRL_PRDD_SOURCE,
427 },
428 {
429 .number = U300_DMA_MSL_TX_4,
430 .name = "MSL TX 4",
431 .priority_high = 0,
24dbcd8a
LW		 432 .param.config = COH901318_CX_CFG_CH_DISABLE |
433 COH901318_CX_CFG_LCR_DISABLE |
434 COH901318_CX_CFG_TC_IRQ_ENABLE |
435 COH901318_CX_CFG_BE_IRQ_ENABLE,
436 .param.ctrl_lli_chained = 0 |
437 COH901318_CX_CTRL_TC_ENABLE |
438 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
439 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
440 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
441 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
442 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
443 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
444 COH901318_CX_CTRL_TCP_DISABLE |
445 COH901318_CX_CTRL_TC_IRQ_DISABLE |
446 COH901318_CX_CTRL_HSP_ENABLE |
447 COH901318_CX_CTRL_HSS_DISABLE |
448 COH901318_CX_CTRL_DDMA_LEGACY |
449 COH901318_CX_CTRL_PRDD_SOURCE,
450 .param.ctrl_lli = 0 |
451 COH901318_CX_CTRL_TC_ENABLE |
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
456 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
457 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
458 COH901318_CX_CTRL_TCP_ENABLE |
459 COH901318_CX_CTRL_TC_IRQ_DISABLE |
460 COH901318_CX_CTRL_HSP_ENABLE |
461 COH901318_CX_CTRL_HSS_DISABLE |
462 COH901318_CX_CTRL_DDMA_LEGACY |
463 COH901318_CX_CTRL_PRDD_SOURCE,
464 .param.ctrl_lli_last = 0 |
465 COH901318_CX_CTRL_TC_ENABLE |
466 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
467 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
468 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
469 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
470 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
471 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
472 COH901318_CX_CTRL_TCP_ENABLE |
473 COH901318_CX_CTRL_TC_IRQ_ENABLE |
474 COH901318_CX_CTRL_HSP_ENABLE |
475 COH901318_CX_CTRL_HSS_DISABLE |
476 COH901318_CX_CTRL_DDMA_LEGACY |
477 COH901318_CX_CTRL_PRDD_SOURCE,
478 },
479 {
480 .number = U300_DMA_MSL_TX_5,
481 .name = "MSL TX 5",
482 .priority_high = 0,
24dbcd8a
LW		 483 },
484 {
485 .number = U300_DMA_MSL_TX_6,
486 .name = "MSL TX 6",
487 .priority_high = 0,
24dbcd8a
LW		 488 },
489 {
490 .number = U300_DMA_MSL_RX_0,
491 .name = "MSL RX 0",
492 .priority_high = 0,
24dbcd8a
LW		 493 },
494 {
495 .number = U300_DMA_MSL_RX_1,
496 .name = "MSL RX 1",
497 .priority_high = 0,
24dbcd8a
LW		 498 .param.config = COH901318_CX_CFG_CH_DISABLE |
499 COH901318_CX_CFG_LCR_DISABLE |
500 COH901318_CX_CFG_TC_IRQ_ENABLE |
501 COH901318_CX_CFG_BE_IRQ_ENABLE,
502 .param.ctrl_lli_chained = 0 |
503 COH901318_CX_CTRL_TC_ENABLE |
504 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
505 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
506 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
507 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
508 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
509 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
510 COH901318_CX_CTRL_TCP_DISABLE |
511 COH901318_CX_CTRL_TC_IRQ_DISABLE |
512 COH901318_CX_CTRL_HSP_ENABLE |
513 COH901318_CX_CTRL_HSS_DISABLE |
514 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
515 COH901318_CX_CTRL_PRDD_DEST,
516 .param.ctrl_lli = 0,
517 .param.ctrl_lli_last = 0 |
518 COH901318_CX_CTRL_TC_ENABLE |
519 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
520 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
521 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
522 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
523 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
524 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
525 COH901318_CX_CTRL_TCP_DISABLE |
526 COH901318_CX_CTRL_TC_IRQ_ENABLE |
527 COH901318_CX_CTRL_HSP_ENABLE |
528 COH901318_CX_CTRL_HSS_DISABLE |
529 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
530 COH901318_CX_CTRL_PRDD_DEST,
531 },
532 {
533 .number = U300_DMA_MSL_RX_2,
534 .name = "MSL RX 2",
535 .priority_high = 0,
24dbcd8a
LW		 536 .param.config = COH901318_CX_CFG_CH_DISABLE |
537 COH901318_CX_CFG_LCR_DISABLE |
538 COH901318_CX_CFG_TC_IRQ_ENABLE |
539 COH901318_CX_CFG_BE_IRQ_ENABLE,
540 .param.ctrl_lli_chained = 0 |
541 COH901318_CX_CTRL_TC_ENABLE |
542 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
543 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
544 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
545 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
546 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
547 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
548 COH901318_CX_CTRL_TCP_DISABLE |
549 COH901318_CX_CTRL_TC_IRQ_DISABLE |
550 COH901318_CX_CTRL_HSP_ENABLE |
551 COH901318_CX_CTRL_HSS_DISABLE |
552 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
553 COH901318_CX_CTRL_PRDD_DEST,
554 .param.ctrl_lli = 0 |
555 COH901318_CX_CTRL_TC_ENABLE |
556 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
557 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
558 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
559 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
560 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
561 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
562 COH901318_CX_CTRL_TCP_DISABLE |
563 COH901318_CX_CTRL_TC_IRQ_ENABLE |
564 COH901318_CX_CTRL_HSP_ENABLE |
565 COH901318_CX_CTRL_HSS_DISABLE |
566 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
567 COH901318_CX_CTRL_PRDD_DEST,
568 .param.ctrl_lli_last = 0 |
569 COH901318_CX_CTRL_TC_ENABLE |
570 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
571 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
572 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
573 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
574 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
575 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
576 COH901318_CX_CTRL_TCP_DISABLE |
577 COH901318_CX_CTRL_TC_IRQ_ENABLE |
578 COH901318_CX_CTRL_HSP_ENABLE |
579 COH901318_CX_CTRL_HSS_DISABLE |
580 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
581 COH901318_CX_CTRL_PRDD_DEST,
582 },
583 {
584 .number = U300_DMA_MSL_RX_3,
585 .name = "MSL RX 3",
586 .priority_high = 0,
24dbcd8a
LW		 587 .param.config = COH901318_CX_CFG_CH_DISABLE |
588 COH901318_CX_CFG_LCR_DISABLE |
589 COH901318_CX_CFG_TC_IRQ_ENABLE |
590 COH901318_CX_CFG_BE_IRQ_ENABLE,
591 .param.ctrl_lli_chained = 0 |
592 COH901318_CX_CTRL_TC_ENABLE |
593 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
594 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
595 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
596 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
597 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
598 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
599 COH901318_CX_CTRL_TCP_DISABLE |
600 COH901318_CX_CTRL_TC_IRQ_DISABLE |
601 COH901318_CX_CTRL_HSP_ENABLE |
602 COH901318_CX_CTRL_HSS_DISABLE |
603 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
604 COH901318_CX_CTRL_PRDD_DEST,
605 .param.ctrl_lli = 0 |
606 COH901318_CX_CTRL_TC_ENABLE |
607 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
608 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
609 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
610 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
611 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
612 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
613 COH901318_CX_CTRL_TCP_DISABLE |
614 COH901318_CX_CTRL_TC_IRQ_ENABLE |
615 COH901318_CX_CTRL_HSP_ENABLE |
616 COH901318_CX_CTRL_HSS_DISABLE |
617 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
618 COH901318_CX_CTRL_PRDD_DEST,
619 .param.ctrl_lli_last = 0 |
620 COH901318_CX_CTRL_TC_ENABLE |
621 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
622 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
623 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
624 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
625 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
626 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
627 COH901318_CX_CTRL_TCP_DISABLE |
628 COH901318_CX_CTRL_TC_IRQ_ENABLE |
629 COH901318_CX_CTRL_HSP_ENABLE |
630 COH901318_CX_CTRL_HSS_DISABLE |
631 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
632 COH901318_CX_CTRL_PRDD_DEST,
633 },
634 {
635 .number = U300_DMA_MSL_RX_4,
636 .name = "MSL RX 4",
637 .priority_high = 0,
24dbcd8a
LW		 638 .param.config = COH901318_CX_CFG_CH_DISABLE |
639 COH901318_CX_CFG_LCR_DISABLE |
640 COH901318_CX_CFG_TC_IRQ_ENABLE |
641 COH901318_CX_CFG_BE_IRQ_ENABLE,
642 .param.ctrl_lli_chained = 0 |
643 COH901318_CX_CTRL_TC_ENABLE |
644 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
645 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
646 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
647 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
648 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
649 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
650 COH901318_CX_CTRL_TCP_DISABLE |
651 COH901318_CX_CTRL_TC_IRQ_DISABLE |
652 COH901318_CX_CTRL_HSP_ENABLE |
653 COH901318_CX_CTRL_HSS_DISABLE |
654 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
655 COH901318_CX_CTRL_PRDD_DEST,
656 .param.ctrl_lli = 0 |
657 COH901318_CX_CTRL_TC_ENABLE |
658 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
659 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
661 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
662 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
663 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
664 COH901318_CX_CTRL_TCP_DISABLE |
665 COH901318_CX_CTRL_TC_IRQ_ENABLE |
666 COH901318_CX_CTRL_HSP_ENABLE |
667 COH901318_CX_CTRL_HSS_DISABLE |
668 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
669 COH901318_CX_CTRL_PRDD_DEST,
670 .param.ctrl_lli_last = 0 |
671 COH901318_CX_CTRL_TC_ENABLE |
672 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
673 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
674 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
675 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
676 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
677 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
678 COH901318_CX_CTRL_TCP_DISABLE |
679 COH901318_CX_CTRL_TC_IRQ_ENABLE |
680 COH901318_CX_CTRL_HSP_ENABLE |
681 COH901318_CX_CTRL_HSS_DISABLE |
682 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
683 COH901318_CX_CTRL_PRDD_DEST,
684 },
685 {
686 .number = U300_DMA_MSL_RX_5,
687 .name = "MSL RX 5",
688 .priority_high = 0,
24dbcd8a
LW		 689 .param.config = COH901318_CX_CFG_CH_DISABLE |
690 COH901318_CX_CFG_LCR_DISABLE |
691 COH901318_CX_CFG_TC_IRQ_ENABLE |
692 COH901318_CX_CFG_BE_IRQ_ENABLE,
693 .param.ctrl_lli_chained = 0 |
694 COH901318_CX_CTRL_TC_ENABLE |
695 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
696 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
697 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
698 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
699 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
700 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
701 COH901318_CX_CTRL_TCP_DISABLE |
702 COH901318_CX_CTRL_TC_IRQ_DISABLE |
703 COH901318_CX_CTRL_HSP_ENABLE |
704 COH901318_CX_CTRL_HSS_DISABLE |
705 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
706 COH901318_CX_CTRL_PRDD_DEST,
707 .param.ctrl_lli = 0 |
708 COH901318_CX_CTRL_TC_ENABLE |
709 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
710 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
711 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
712 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
713 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
714 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
715 COH901318_CX_CTRL_TCP_DISABLE |
716 COH901318_CX_CTRL_TC_IRQ_ENABLE |
717 COH901318_CX_CTRL_HSP_ENABLE |
718 COH901318_CX_CTRL_HSS_DISABLE |
719 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
720 COH901318_CX_CTRL_PRDD_DEST,
721 .param.ctrl_lli_last = 0 |
722 COH901318_CX_CTRL_TC_ENABLE |
723 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
724 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
725 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
726 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
728 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
729 COH901318_CX_CTRL_TCP_DISABLE |
730 COH901318_CX_CTRL_TC_IRQ_ENABLE |
731 COH901318_CX_CTRL_HSP_ENABLE |
732 COH901318_CX_CTRL_HSS_DISABLE |
733 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
734 COH901318_CX_CTRL_PRDD_DEST,
735 },
736 {
737 .number = U300_DMA_MSL_RX_6,
738 .name = "MSL RX 6",
739 .priority_high = 0,
24dbcd8a
LW		 740 },
741 /*
742 * Don't set up device address, burst count or size of src
743 * or dst bus for this peripheral - handled by PrimeCell
744 * DMA extension.
745 */
746 {
747 .number = U300_DMA_MMCSD_RX_TX,
748 .name = "MMCSD RX TX",
749 .priority_high = 0,
750 .param.config = COH901318_CX_CFG_CH_DISABLE |
751 COH901318_CX_CFG_LCR_DISABLE |
752 COH901318_CX_CFG_TC_IRQ_ENABLE |
753 COH901318_CX_CFG_BE_IRQ_ENABLE,
754 .param.ctrl_lli_chained = 0 |
755 COH901318_CX_CTRL_TC_ENABLE |
756 COH901318_CX_CTRL_MASTER_MODE_M1RW |
757 COH901318_CX_CTRL_TCP_ENABLE |
758 COH901318_CX_CTRL_TC_IRQ_DISABLE |
759 COH901318_CX_CTRL_HSP_ENABLE |
760 COH901318_CX_CTRL_HSS_DISABLE |
761 COH901318_CX_CTRL_DDMA_LEGACY,
762 .param.ctrl_lli = 0 |
763 COH901318_CX_CTRL_TC_ENABLE |
764 COH901318_CX_CTRL_MASTER_MODE_M1RW |
765 COH901318_CX_CTRL_TCP_ENABLE |
766 COH901318_CX_CTRL_TC_IRQ_DISABLE |
767 COH901318_CX_CTRL_HSP_ENABLE |
768 COH901318_CX_CTRL_HSS_DISABLE |
769 COH901318_CX_CTRL_DDMA_LEGACY,
770 .param.ctrl_lli_last = 0 |
771 COH901318_CX_CTRL_TC_ENABLE |
772 COH901318_CX_CTRL_MASTER_MODE_M1RW |
773 COH901318_CX_CTRL_TCP_DISABLE |
774 COH901318_CX_CTRL_TC_IRQ_ENABLE |
775 COH901318_CX_CTRL_HSP_ENABLE |
776 COH901318_CX_CTRL_HSS_DISABLE |
777 COH901318_CX_CTRL_DDMA_LEGACY,
778
779 },
780 {
781 .number = U300_DMA_MSPRO_TX,
782 .name = "MSPRO TX",
783 .priority_high = 0,
784 },
785 {
786 .number = U300_DMA_MSPRO_RX,
787 .name = "MSPRO RX",
788 .priority_high = 0,
789 },
790 /*
791 * Don't set up device address, burst count or size of src
792 * or dst bus for this peripheral - handled by PrimeCell
793 * DMA extension.
794 */
795 {
796 .number = U300_DMA_UART0_TX,
797 .name = "UART0 TX",
798 .priority_high = 0,
799 .param.config = COH901318_CX_CFG_CH_DISABLE |
800 COH901318_CX_CFG_LCR_DISABLE |
801 COH901318_CX_CFG_TC_IRQ_ENABLE |
802 COH901318_CX_CFG_BE_IRQ_ENABLE,
803 .param.ctrl_lli_chained = 0 |
804 COH901318_CX_CTRL_TC_ENABLE |
805 COH901318_CX_CTRL_MASTER_MODE_M1RW |
806 COH901318_CX_CTRL_TCP_ENABLE |
807 COH901318_CX_CTRL_TC_IRQ_DISABLE |
808 COH901318_CX_CTRL_HSP_ENABLE |
809 COH901318_CX_CTRL_HSS_DISABLE |
810 COH901318_CX_CTRL_DDMA_LEGACY,
811 .param.ctrl_lli = 0 |
812 COH901318_CX_CTRL_TC_ENABLE |
813 COH901318_CX_CTRL_MASTER_MODE_M1RW |
814 COH901318_CX_CTRL_TCP_ENABLE |
815 COH901318_CX_CTRL_TC_IRQ_ENABLE |
816 COH901318_CX_CTRL_HSP_ENABLE |
817 COH901318_CX_CTRL_HSS_DISABLE |
818 COH901318_CX_CTRL_DDMA_LEGACY,
819 .param.ctrl_lli_last = 0 |
820 COH901318_CX_CTRL_TC_ENABLE |
821 COH901318_CX_CTRL_MASTER_MODE_M1RW |
822 COH901318_CX_CTRL_TCP_ENABLE |
823 COH901318_CX_CTRL_TC_IRQ_ENABLE |
824 COH901318_CX_CTRL_HSP_ENABLE |
825 COH901318_CX_CTRL_HSS_DISABLE |
826 COH901318_CX_CTRL_DDMA_LEGACY,
827 },
828 {
829 .number = U300_DMA_UART0_RX,
830 .name = "UART0 RX",
831 .priority_high = 0,
832 .param.config = COH901318_CX_CFG_CH_DISABLE |
833 COH901318_CX_CFG_LCR_DISABLE |
834 COH901318_CX_CFG_TC_IRQ_ENABLE |
835 COH901318_CX_CFG_BE_IRQ_ENABLE,
836 .param.ctrl_lli_chained = 0 |
837 COH901318_CX_CTRL_TC_ENABLE |
838 COH901318_CX_CTRL_MASTER_MODE_M1RW |
839 COH901318_CX_CTRL_TCP_ENABLE |
840 COH901318_CX_CTRL_TC_IRQ_DISABLE |
841 COH901318_CX_CTRL_HSP_ENABLE |
842 COH901318_CX_CTRL_HSS_DISABLE |
843 COH901318_CX_CTRL_DDMA_LEGACY,
844 .param.ctrl_lli = 0 |
845 COH901318_CX_CTRL_TC_ENABLE |
846 COH901318_CX_CTRL_MASTER_MODE_M1RW |
847 COH901318_CX_CTRL_TCP_ENABLE |
848 COH901318_CX_CTRL_TC_IRQ_ENABLE |
849 COH901318_CX_CTRL_HSP_ENABLE |
850 COH901318_CX_CTRL_HSS_DISABLE |
851 COH901318_CX_CTRL_DDMA_LEGACY,
852 .param.ctrl_lli_last = 0 |
853 COH901318_CX_CTRL_TC_ENABLE |
854 COH901318_CX_CTRL_MASTER_MODE_M1RW |
855 COH901318_CX_CTRL_TCP_ENABLE |
856 COH901318_CX_CTRL_TC_IRQ_ENABLE |
857 COH901318_CX_CTRL_HSP_ENABLE |
858 COH901318_CX_CTRL_HSS_DISABLE |
859 COH901318_CX_CTRL_DDMA_LEGACY,
860 },
861 {
862 .number = U300_DMA_APEX_TX,
863 .name = "APEX TX",
864 .priority_high = 0,
865 },
866 {
867 .number = U300_DMA_APEX_RX,
868 .name = "APEX RX",
869 .priority_high = 0,
870 },
871 {
872 .number = U300_DMA_PCM_I2S0_TX,
873 .name = "PCM I2S0 TX",
874 .priority_high = 1,
24dbcd8a
LW		 875 .param.config = COH901318_CX_CFG_CH_DISABLE |
876 COH901318_CX_CFG_LCR_DISABLE |
877 COH901318_CX_CFG_TC_IRQ_ENABLE |
878 COH901318_CX_CFG_BE_IRQ_ENABLE,
879 .param.ctrl_lli_chained = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
882 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
883 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
884 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
885 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
886 COH901318_CX_CTRL_MASTER_MODE_M1RW |
887 COH901318_CX_CTRL_TCP_DISABLE |
888 COH901318_CX_CTRL_TC_IRQ_DISABLE |
889 COH901318_CX_CTRL_HSP_ENABLE |
890 COH901318_CX_CTRL_HSS_DISABLE |
891 COH901318_CX_CTRL_DDMA_LEGACY |
892 COH901318_CX_CTRL_PRDD_SOURCE,
893 .param.ctrl_lli = 0 |
894 COH901318_CX_CTRL_TC_ENABLE |
895 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
896 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
897 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
898 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
899 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
900 COH901318_CX_CTRL_MASTER_MODE_M1RW |
901 COH901318_CX_CTRL_TCP_ENABLE |
902 COH901318_CX_CTRL_TC_IRQ_DISABLE |
903 COH901318_CX_CTRL_HSP_ENABLE |
904 COH901318_CX_CTRL_HSS_DISABLE |
905 COH901318_CX_CTRL_DDMA_LEGACY |
906 COH901318_CX_CTRL_PRDD_SOURCE,
907 .param.ctrl_lli_last = 0 |
908 COH901318_CX_CTRL_TC_ENABLE |
909 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
910 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
911 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
912 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
913 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
914 COH901318_CX_CTRL_MASTER_MODE_M1RW |
915 COH901318_CX_CTRL_TCP_ENABLE |
916 COH901318_CX_CTRL_TC_IRQ_DISABLE |
917 COH901318_CX_CTRL_HSP_ENABLE |
918 COH901318_CX_CTRL_HSS_DISABLE |
919 COH901318_CX_CTRL_DDMA_LEGACY |
920 COH901318_CX_CTRL_PRDD_SOURCE,
921 },
922 {
923 .number = U300_DMA_PCM_I2S0_RX,
924 .name = "PCM I2S0 RX",
925 .priority_high = 1,
24dbcd8a
LW		 926 .param.config = COH901318_CX_CFG_CH_DISABLE |
927 COH901318_CX_CFG_LCR_DISABLE |
928 COH901318_CX_CFG_TC_IRQ_ENABLE |
929 COH901318_CX_CFG_BE_IRQ_ENABLE,
930 .param.ctrl_lli_chained = 0 |
931 COH901318_CX_CTRL_TC_ENABLE |
932 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
933 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
934 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
935 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
936 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
937 COH901318_CX_CTRL_MASTER_MODE_M1RW |
938 COH901318_CX_CTRL_TCP_DISABLE |
939 COH901318_CX_CTRL_TC_IRQ_DISABLE |
940 COH901318_CX_CTRL_HSP_ENABLE |
941 COH901318_CX_CTRL_HSS_DISABLE |
942 COH901318_CX_CTRL_DDMA_LEGACY |
943 COH901318_CX_CTRL_PRDD_DEST,
944 .param.ctrl_lli = 0 |
945 COH901318_CX_CTRL_TC_ENABLE |
946 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
947 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
948 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
949 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
950 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
951 COH901318_CX_CTRL_MASTER_MODE_M1RW |
952 COH901318_CX_CTRL_TCP_ENABLE |
953 COH901318_CX_CTRL_TC_IRQ_DISABLE |
954 COH901318_CX_CTRL_HSP_ENABLE |
955 COH901318_CX_CTRL_HSS_DISABLE |
956 COH901318_CX_CTRL_DDMA_LEGACY |
957 COH901318_CX_CTRL_PRDD_DEST,
958 .param.ctrl_lli_last = 0 |
959 COH901318_CX_CTRL_TC_ENABLE |
960 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
961 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
962 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
963 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
964 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
965 COH901318_CX_CTRL_MASTER_MODE_M1RW |
966 COH901318_CX_CTRL_TCP_ENABLE |
967 COH901318_CX_CTRL_TC_IRQ_ENABLE |
968 COH901318_CX_CTRL_HSP_ENABLE |
969 COH901318_CX_CTRL_HSS_DISABLE |
970 COH901318_CX_CTRL_DDMA_LEGACY |
971 COH901318_CX_CTRL_PRDD_DEST,
972 },
973 {
974 .number = U300_DMA_PCM_I2S1_TX,
975 .name = "PCM I2S1 TX",
976 .priority_high = 1,
24dbcd8a
LW		 977 .param.config = COH901318_CX_CFG_CH_DISABLE |
978 COH901318_CX_CFG_LCR_DISABLE |
979 COH901318_CX_CFG_TC_IRQ_ENABLE |
980 COH901318_CX_CFG_BE_IRQ_ENABLE,
981 .param.ctrl_lli_chained = 0 |
982 COH901318_CX_CTRL_TC_ENABLE |
983 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
984 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
985 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
986 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_DISABLE |
990 COH901318_CX_CTRL_TC_IRQ_DISABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY |
994 COH901318_CX_CTRL_PRDD_SOURCE,
995 .param.ctrl_lli = 0 |
996 COH901318_CX_CTRL_TC_ENABLE |
997 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
998 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
999 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1000 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1001 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1002 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1003 COH901318_CX_CTRL_TCP_ENABLE |
1004 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1005 COH901318_CX_CTRL_HSP_ENABLE |
1006 COH901318_CX_CTRL_HSS_DISABLE |
1007 COH901318_CX_CTRL_DDMA_LEGACY |
1008 COH901318_CX_CTRL_PRDD_SOURCE,
1009 .param.ctrl_lli_last = 0 |
1010 COH901318_CX_CTRL_TC_ENABLE |
1011 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1012 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1013 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1014 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1015 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1016 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1017 COH901318_CX_CTRL_TCP_ENABLE |
1018 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1019 COH901318_CX_CTRL_HSP_ENABLE |
1020 COH901318_CX_CTRL_HSS_DISABLE |
1021 COH901318_CX_CTRL_DDMA_LEGACY |
1022 COH901318_CX_CTRL_PRDD_SOURCE,
1023 },
1024 {
1025 .number = U300_DMA_PCM_I2S1_RX,
1026 .name = "PCM I2S1 RX",
1027 .priority_high = 1,
24dbcd8a
LW		 1028 .param.config = COH901318_CX_CFG_CH_DISABLE |
1029 COH901318_CX_CFG_LCR_DISABLE |
1030 COH901318_CX_CFG_TC_IRQ_ENABLE |
1031 COH901318_CX_CFG_BE_IRQ_ENABLE,
1032 .param.ctrl_lli_chained = 0 |
1033 COH901318_CX_CTRL_TC_ENABLE |
1034 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1035 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1036 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1037 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1038 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1039 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1040 COH901318_CX_CTRL_TCP_DISABLE |
1041 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1042 COH901318_CX_CTRL_HSP_ENABLE |
1043 COH901318_CX_CTRL_HSS_DISABLE |
1044 COH901318_CX_CTRL_DDMA_LEGACY |
1045 COH901318_CX_CTRL_PRDD_DEST,
1046 .param.ctrl_lli = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1049 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1050 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1051 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1052 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1053 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1054 COH901318_CX_CTRL_TCP_ENABLE |
1055 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1056 COH901318_CX_CTRL_HSP_ENABLE |
1057 COH901318_CX_CTRL_HSS_DISABLE |
1058 COH901318_CX_CTRL_DDMA_LEGACY |
1059 COH901318_CX_CTRL_PRDD_DEST,
1060 .param.ctrl_lli_last = 0 |
1061 COH901318_CX_CTRL_TC_ENABLE |
1062 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1063 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1064 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1065 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1066 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1067 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1068 COH901318_CX_CTRL_TCP_ENABLE |
1069 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1070 COH901318_CX_CTRL_HSP_ENABLE |
1071 COH901318_CX_CTRL_HSS_DISABLE |
1072 COH901318_CX_CTRL_DDMA_LEGACY |
1073 COH901318_CX_CTRL_PRDD_DEST,
1074 },
1075 {
1076 .number = U300_DMA_XGAM_CDI,
1077 .name = "XGAM CDI",
1078 .priority_high = 0,
1079 },
1080 {
1081 .number = U300_DMA_XGAM_PDI,
1082 .name = "XGAM PDI",
1083 .priority_high = 0,
1084 },
1085 /*
1086 * Don't set up device address, burst count or size of src
1087 * or dst bus for this peripheral - handled by PrimeCell
1088 * DMA extension.
1089 */
1090 {
1091 .number = U300_DMA_SPI_TX,
1092 .name = "SPI TX",
1093 .priority_high = 0,
1094 .param.config = COH901318_CX_CFG_CH_DISABLE |
1095 COH901318_CX_CFG_LCR_DISABLE |
1096 COH901318_CX_CFG_TC_IRQ_ENABLE |
1097 COH901318_CX_CFG_BE_IRQ_ENABLE,
1098 .param.ctrl_lli_chained = 0 |
1099 COH901318_CX_CTRL_TC_ENABLE |
1100 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1101 COH901318_CX_CTRL_TCP_DISABLE |
1102 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1103 COH901318_CX_CTRL_HSP_ENABLE |
1104 COH901318_CX_CTRL_HSS_DISABLE |
1105 COH901318_CX_CTRL_DDMA_LEGACY,
1106 .param.ctrl_lli = 0 |
1107 COH901318_CX_CTRL_TC_ENABLE |
1108 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1109 COH901318_CX_CTRL_TCP_DISABLE |
1110 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1111 COH901318_CX_CTRL_HSP_ENABLE |
1112 COH901318_CX_CTRL_HSS_DISABLE |
1113 COH901318_CX_CTRL_DDMA_LEGACY,
1114 .param.ctrl_lli_last = 0 |
1115 COH901318_CX_CTRL_TC_ENABLE |
1116 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1117 COH901318_CX_CTRL_TCP_DISABLE |
1118 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1119 COH901318_CX_CTRL_HSP_ENABLE |
1120 COH901318_CX_CTRL_HSS_DISABLE |
1121 COH901318_CX_CTRL_DDMA_LEGACY,
1122 },
1123 {
1124 .number = U300_DMA_SPI_RX,
1125 .name = "SPI RX",
1126 .priority_high = 0,
1127 .param.config = COH901318_CX_CFG_CH_DISABLE |
1128 COH901318_CX_CFG_LCR_DISABLE |
1129 COH901318_CX_CFG_TC_IRQ_ENABLE |
1130 COH901318_CX_CFG_BE_IRQ_ENABLE,
1131 .param.ctrl_lli_chained = 0 |
1132 COH901318_CX_CTRL_TC_ENABLE |
1133 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134 COH901318_CX_CTRL_TCP_DISABLE |
1135 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136 COH901318_CX_CTRL_HSP_ENABLE |
1137 COH901318_CX_CTRL_HSS_DISABLE |
1138 COH901318_CX_CTRL_DDMA_LEGACY,
1139 .param.ctrl_lli = 0 |
1140 COH901318_CX_CTRL_TC_ENABLE |
1141 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1142 COH901318_CX_CTRL_TCP_DISABLE |
1143 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1144 COH901318_CX_CTRL_HSP_ENABLE |
1145 COH901318_CX_CTRL_HSS_DISABLE |
1146 COH901318_CX_CTRL_DDMA_LEGACY,
1147 .param.ctrl_lli_last = 0 |
1148 COH901318_CX_CTRL_TC_ENABLE |
1149 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1150 COH901318_CX_CTRL_TCP_DISABLE |
1151 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1152 COH901318_CX_CTRL_HSP_ENABLE |
1153 COH901318_CX_CTRL_HSS_DISABLE |
1154 COH901318_CX_CTRL_DDMA_LEGACY,
1155
1156 },
1157 {
1158 .number = U300_DMA_GENERAL_PURPOSE_0,
1159 .name = "GENERAL 00",
1160 .priority_high = 0,
1161
1162 .param.config = flags_memcpy_config,
1163 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1164 .param.ctrl_lli = flags_memcpy_lli,
1165 .param.ctrl_lli_last = flags_memcpy_lli_last,
1166 },
1167 {
1168 .number = U300_DMA_GENERAL_PURPOSE_1,
1169 .name = "GENERAL 01",
1170 .priority_high = 0,
1171
1172 .param.config = flags_memcpy_config,
1173 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1174 .param.ctrl_lli = flags_memcpy_lli,
1175 .param.ctrl_lli_last = flags_memcpy_lli_last,
1176 },
1177 {
1178 .number = U300_DMA_GENERAL_PURPOSE_2,
1179 .name = "GENERAL 02",
1180 .priority_high = 0,
1181
1182 .param.config = flags_memcpy_config,
1183 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1184 .param.ctrl_lli = flags_memcpy_lli,
1185 .param.ctrl_lli_last = flags_memcpy_lli_last,
1186 },
1187 {
1188 .number = U300_DMA_GENERAL_PURPOSE_3,
1189 .name = "GENERAL 03",
1190 .priority_high = 0,
1191
1192 .param.config = flags_memcpy_config,
1193 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1194 .param.ctrl_lli = flags_memcpy_lli,
1195 .param.ctrl_lli_last = flags_memcpy_lli_last,
1196 },
1197 {
1198 .number = U300_DMA_GENERAL_PURPOSE_4,
1199 .name = "GENERAL 04",
1200 .priority_high = 0,
1201
1202 .param.config = flags_memcpy_config,
1203 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1204 .param.ctrl_lli = flags_memcpy_lli,
1205 .param.ctrl_lli_last = flags_memcpy_lli_last,
1206 },
1207 {
1208 .number = U300_DMA_GENERAL_PURPOSE_5,
1209 .name = "GENERAL 05",
1210 .priority_high = 0,
1211
1212 .param.config = flags_memcpy_config,
1213 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1214 .param.ctrl_lli = flags_memcpy_lli,
1215 .param.ctrl_lli_last = flags_memcpy_lli_last,
1216 },
1217 {
1218 .number = U300_DMA_GENERAL_PURPOSE_6,
1219 .name = "GENERAL 06",
1220 .priority_high = 0,
1221
1222 .param.config = flags_memcpy_config,
1223 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1224 .param.ctrl_lli = flags_memcpy_lli,
1225 .param.ctrl_lli_last = flags_memcpy_lli_last,
1226 },
1227 {
1228 .number = U300_DMA_GENERAL_PURPOSE_7,
1229 .name = "GENERAL 07",
1230 .priority_high = 0,
1231
1232 .param.config = flags_memcpy_config,
1233 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1234 .param.ctrl_lli = flags_memcpy_lli,
1235 .param.ctrl_lli_last = flags_memcpy_lli_last,
1236 },
1237 {
1238 .number = U300_DMA_GENERAL_PURPOSE_8,
1239 .name = "GENERAL 08",
1240 .priority_high = 0,
1241
1242 .param.config = flags_memcpy_config,
1243 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1244 .param.ctrl_lli = flags_memcpy_lli,
1245 .param.ctrl_lli_last = flags_memcpy_lli_last,
1246 },
1247 {
1248 .number = U300_DMA_UART1_TX,
1249 .name = "UART1 TX",
1250 .priority_high = 0,
1251 },
1252 {
1253 .number = U300_DMA_UART1_RX,
1254 .name = "UART1 RX",
1255 .priority_high = 0,
1256 }
1257};
1258
61f135b9
LW		 1259#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1260
1261#ifdef VERBOSE_DEBUG
1262#define COH_DBG(x) ({ if (1) x; 0; })
1263#else
1264#define COH_DBG(x) ({ if (0) x; 0; })
1265#endif
1266
1267struct coh901318_desc {
1268 struct dma_async_tx_descriptor desc;
1269 struct list_head node;
1270 struct scatterlist *sg;
1271 unsigned int sg_len;
cecd87da 1272 struct coh901318_lli *lli;
db8196df 1273 enum dma_transfer_direction dir;
61f135b9 1274 unsigned long flags;
b89243dd
LW		 1275 u32 head_config;
1276 u32 head_ctrl;
61f135b9
LW		 1277};
1278
1279struct coh901318_base {
1280 struct device *dev;
1281 void __iomem *virtbase;
1282 struct coh901318_pool pool;
1283 struct powersave pm;
1284 struct dma_device dma_slave;
1285 struct dma_device dma_memcpy;
1286 struct coh901318_chan *chans;
61f135b9
LW		 1287};
1288
1289struct coh901318_chan {
1290 spinlock_t lock;
1291 int allocated;
61f135b9
LW		 1292 int id;
1293 int stopped;
1294
1295 struct work_struct free_work;
1296 struct dma_chan chan;
1297
1298 struct tasklet_struct tasklet;
1299
1300 struct list_head active;
1301 struct list_head queue;
1302 struct list_head free;
1303
1304 unsigned long nbr_active_done;
1305 unsigned long busy;
61f135b9 1306
9aab4d6f
LW		 1307 u32 addr;
1308 u32 ctrl;
128f904a 1309
61f135b9
LW		 1310 struct coh901318_base *base;
1311};
1312
1313static void coh901318_list_print(struct coh901318_chan *cohc,
1314 struct coh901318_lli *lli)
1315{
848ad121 1316 struct coh901318_lli *l = lli;
61f135b9
LW		 1317 int i = 0;
1318
848ad121 1319 while (l) {
61f135b9 1320 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
848ad121 1321 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
61f135b9 1322 i, l, l->control, l->src_addr, l->dst_addr,
848ad121 1323 l->link_addr, l->virt_link_addr);
61f135b9 1324 i++;
848ad121 1325 l = l->virt_link_addr;
61f135b9
LW		 1326 }
1327}
1328
1329#ifdef CONFIG_DEBUG_FS
1330
1331#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1332
1333static struct coh901318_base *debugfs_dma_base;
1334static struct dentry *dma_dentry;
1335
61f135b9
LW		 1336static int coh901318_debugfs_read(struct file *file, char __user *buf,
1337 size_t count, loff_t *f_pos)
1338{
1339 u64 started_channels = debugfs_dma_base->pm.started_channels;
1340 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1341 int i;
1342 int ret = 0;
1343 char *dev_buf;
1344 char *tmp;
1345 int dev_size;
1346
1347 dev_buf = kmalloc(4*1024, GFP_KERNEL);
1348 if (dev_buf == NULL)
1349 goto err_kmalloc;
1350 tmp = dev_buf;
1351
848ad121 1352 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
61f135b9 1353
73b31eae 1354 for (i = 0; i < U300_DMA_CHANNELS; i++)
61f135b9
LW		 1355 if (started_channels & (1 << i))
1356 tmp += sprintf(tmp, "channel %d\n", i);
1357
1358 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1359 dev_size = tmp - dev_buf;
1360
1361 /* No more to read if offset != 0 */
1362 if (*f_pos > dev_size)
1363 goto out;
1364
1365 if (count > dev_size - *f_pos)
1366 count = dev_size - *f_pos;
1367
1368 if (copy_to_user(buf, dev_buf + *f_pos, count))
1369 ret = -EINVAL;
1370 ret = count;
1371 *f_pos += count;
1372
1373 out:
1374 kfree(dev_buf);
1375 return ret;
1376
1377 err_kmalloc:
1378 return 0;
1379}
1380
1381static const struct file_operations coh901318_debugfs_status_operations = {
1382 .owner = THIS_MODULE,
234e3405 1383 .open = simple_open,
61f135b9 1384 .read = coh901318_debugfs_read,
6038f373 1385 .llseek = default_llseek,
61f135b9
LW		 1386};
1387
1388
1389static int __init init_coh901318_debugfs(void)
1390{
1391
1392 dma_dentry = debugfs_create_dir("dma", NULL);
1393
1394 (void) debugfs_create_file("status",
1395 S_IFREG | S_IRUGO,
1396 dma_dentry, NULL,
1397 &coh901318_debugfs_status_operations);
1398 return 0;
1399}
1400
1401static void __exit exit_coh901318_debugfs(void)
1402{
1403 debugfs_remove_recursive(dma_dentry);
1404}
1405
1406module_init(init_coh901318_debugfs);
1407module_exit(exit_coh901318_debugfs);
1408#else
1409
1410#define COH901318_DEBUGFS_ASSIGN(x, y)
1411
1412#endif /* CONFIG_DEBUG_FS */
1413
1414static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1415{
1416 return container_of(chan, struct coh901318_chan, chan);
1417}
1418
61f135b9
LW		 1419static inline const struct coh901318_params *
1420cohc_chan_param(struct coh901318_chan *cohc)
1421{
73b31eae 1422 return &chan_config[cohc->id].param;
61f135b9
LW		 1423}
1424
1425static inline const struct coh_dma_channel *
1426cohc_chan_conf(struct coh901318_chan *cohc)
1427{
73b31eae 1428 return &chan_config[cohc->id];
61f135b9
LW		 1429}
1430
1431static void enable_powersave(struct coh901318_chan *cohc)
1432{
1433 unsigned long flags;
1434 struct powersave *pm = &cohc->base->pm;
1435
1436 spin_lock_irqsave(&pm->lock, flags);
1437
1438 pm->started_channels &= ~(1ULL << cohc->id);
1439
61f135b9
LW		 1440 spin_unlock_irqrestore(&pm->lock, flags);
1441}
1442static void disable_powersave(struct coh901318_chan *cohc)
1443{
1444 unsigned long flags;
1445 struct powersave *pm = &cohc->base->pm;
1446
1447 spin_lock_irqsave(&pm->lock, flags);
1448
61f135b9
LW		 1449 pm->started_channels |= (1ULL << cohc->id);
1450
1451 spin_unlock_irqrestore(&pm->lock, flags);
1452}
1453
1454static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1455{
1456 int channel = cohc->id;
1457 void __iomem *virtbase = cohc->base->virtbase;
1458
1459 writel(control,
1460 virtbase + COH901318_CX_CTRL +
1461 COH901318_CX_CTRL_SPACING * channel);
1462 return 0;
1463}
1464
1465static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1466{
1467 int channel = cohc->id;
1468 void __iomem *virtbase = cohc->base->virtbase;
1469
1470 writel(conf,
1471 virtbase + COH901318_CX_CFG +
1472 COH901318_CX_CFG_SPACING*channel);
1473 return 0;
1474}
1475
1476
1477static int coh901318_start(struct coh901318_chan *cohc)
1478{
1479 u32 val;
1480 int channel = cohc->id;
1481 void __iomem *virtbase = cohc->base->virtbase;
1482
1483 disable_powersave(cohc);
1484
1485 val = readl(virtbase + COH901318_CX_CFG +
1486 COH901318_CX_CFG_SPACING * channel);
1487
1488 /* Enable channel */
1489 val |= COH901318_CX_CFG_CH_ENABLE;
1490 writel(val, virtbase + COH901318_CX_CFG +
1491 COH901318_CX_CFG_SPACING * channel);
1492
1493 return 0;
1494}
1495
1496static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
cecd87da 1497 struct coh901318_lli *lli)
61f135b9
LW		 1498{
1499 int channel = cohc->id;
1500 void __iomem *virtbase = cohc->base->virtbase;
1501
1502 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1503 COH901318_CX_STAT_SPACING*channel) &
1504 COH901318_CX_STAT_ACTIVE);
1505
cecd87da 1506 writel(lli->src_addr,
61f135b9
LW		 1507 virtbase + COH901318_CX_SRC_ADDR +
1508 COH901318_CX_SRC_ADDR_SPACING * channel);
1509
cecd87da 1510 writel(lli->dst_addr, virtbase +
61f135b9
LW		 1511 COH901318_CX_DST_ADDR +
1512 COH901318_CX_DST_ADDR_SPACING * channel);
1513
cecd87da 1514 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
61f135b9
LW		 1515 COH901318_CX_LNK_ADDR_SPACING * channel);
1516
cecd87da 1517 writel(lli->control, virtbase + COH901318_CX_CTRL +
61f135b9
LW		 1518 COH901318_CX_CTRL_SPACING * channel);
1519
1520 return 0;
1521}
61f135b9
LW		 1522
1523static struct coh901318_desc *
1524coh901318_desc_get(struct coh901318_chan *cohc)
1525{
1526 struct coh901318_desc *desc;
1527
1528 if (list_empty(&cohc->free)) {
1529 /* alloc new desc because we're out of used ones
1530 * TODO: alloc a pile of descs instead of just one,
1531 * avoid many small allocations.
1532 */
b87108a7 1533 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
61f135b9
LW		 1534 if (desc == NULL)
1535 goto out;
1536 INIT_LIST_HEAD(&desc->node);
b87108a7 1537 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
61f135b9
LW		 1538 } else {
1539 /* Reuse an old desc. */
1540 desc = list_first_entry(&cohc->free,
1541 struct coh901318_desc,
1542 node);
1543 list_del(&desc->node);
b87108a7
LW		 1544 /* Initialize it a bit so it's not insane */
1545 desc->sg = NULL;
1546 desc->sg_len = 0;
1547 desc->desc.callback = NULL;
1548 desc->desc.callback_param = NULL;
61f135b9
LW		 1549 }
1550
1551 out:
1552 return desc;
1553}
1554
1555static void
1556coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1557{
1558 list_add_tail(&cohd->node, &cohc->free);
1559}
1560
1561/* call with irq lock held */
1562static void
1563coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1564{
1565 list_add_tail(&desc->node, &cohc->active);
61f135b9
LW		 1566}
1567
1568static struct coh901318_desc *
1569coh901318_first_active_get(struct coh901318_chan *cohc)
1570{
1571 struct coh901318_desc *d;
1572
1573 if (list_empty(&cohc->active))
1574 return NULL;
1575
1576 d = list_first_entry(&cohc->active,
1577 struct coh901318_desc,
1578 node);
1579 return d;
1580}
1581
1582static void
1583coh901318_desc_remove(struct coh901318_desc *cohd)
1584{
1585 list_del(&cohd->node);
1586}
1587
1588static void
1589coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1590{
1591 list_add_tail(&desc->node, &cohc->queue);
1592}
1593
1594static struct coh901318_desc *
1595coh901318_first_queued(struct coh901318_chan *cohc)
1596{
1597 struct coh901318_desc *d;
1598
1599 if (list_empty(&cohc->queue))
1600 return NULL;
1601
1602 d = list_first_entry(&cohc->queue,
1603 struct coh901318_desc,
1604 node);
1605 return d;
1606}
1607
84c8447c
LW		 1608static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1609{
1610 struct coh901318_lli *lli = in_lli;
1611 u32 bytes = 0;
1612
1613 while (lli) {
1614 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1615 lli = lli->virt_link_addr;
1616 }
1617 return bytes;
1618}
1619
61f135b9 1620/*
84c8447c
LW		 1621 * Get the number of bytes left to transfer on this channel,
1622 * it is unwise to call this before stopping the channel for
1623 * absolute measures, but for a rough guess you can still call
1624 * it.
61f135b9 1625 */
07934481 1626static u32 coh901318_get_bytes_left(struct dma_chan *chan)
61f135b9 1627{
61f135b9 1628 struct coh901318_chan *cohc = to_coh901318_chan(chan);
84c8447c
LW		 1629 struct coh901318_desc *cohd;
1630 struct list_head *pos;
1631 unsigned long flags;
1632 u32 left = 0;
1633 int i = 0;
61f135b9
LW		 1634
1635 spin_lock_irqsave(&cohc->lock, flags);
1636
84c8447c
LW		 1637 /*
1638 * If there are many queued jobs, we iterate and add the
1639 * size of them all. We take a special look on the first
1640 * job though, since it is probably active.
1641 */
1642 list_for_each(pos, &cohc->active) {
1643 /*
1644 * The first job in the list will be working on the
1645 * hardware. The job can be stopped but still active,
1646 * so that the transfer counter is somewhere inside
1647 * the buffer.
1648 */
1649 cohd = list_entry(pos, struct coh901318_desc, node);
1650
1651 if (i == 0) {
1652 struct coh901318_lli *lli;
1653 dma_addr_t ladd;
1654
1655 /* Read current transfer count value */
1656 left = readl(cohc->base->virtbase +
1657 COH901318_CX_CTRL +
1658 COH901318_CX_CTRL_SPACING * cohc->id) &
1659 COH901318_CX_CTRL_TC_VALUE_MASK;
1660
1661 /* See if the transfer is linked... */
1662 ladd = readl(cohc->base->virtbase +
1663 COH901318_CX_LNK_ADDR +
1664 COH901318_CX_LNK_ADDR_SPACING *
1665 cohc->id) &
1666 ~COH901318_CX_LNK_LINK_IMMEDIATE;
1667 /* Single transaction */
1668 if (!ladd)
1669 continue;
1670
1671 /*
1672 * Linked transaction, follow the lli, find the
1673 * currently processing lli, and proceed to the next
1674 */
1675 lli = cohd->lli;
1676 while (lli && lli->link_addr != ladd)
1677 lli = lli->virt_link_addr;
1678
1679 if (lli)
1680 lli = lli->virt_link_addr;
1681
1682 /*
1683 * Follow remaining lli links around to count the total
1684 * number of bytes left
1685 */
1686 left += coh901318_get_bytes_in_lli(lli);
1687 } else {
1688 left += coh901318_get_bytes_in_lli(cohd->lli);
1689 }
1690 i++;
1691 }
1692
1693 /* Also count bytes in the queued jobs */
1694 list_for_each(pos, &cohc->queue) {
1695 cohd = list_entry(pos, struct coh901318_desc, node);
1696 left += coh901318_get_bytes_in_lli(cohd->lli);
1697 }
61f135b9
LW		 1698
1699 spin_unlock_irqrestore(&cohc->lock, flags);
1700
84c8447c 1701 return left;
61f135b9 1702}
61f135b9 1703
c3635c78
LW		 1704/*
1705 * Pauses a transfer without losing data. Enables power save.
1706 * Use this function in conjunction with coh901318_resume.
1707 */
1708static void coh901318_pause(struct dma_chan *chan)
61f135b9
LW		 1709{
1710 u32 val;
1711 unsigned long flags;
1712 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1713 int channel = cohc->id;
1714 void __iomem *virtbase = cohc->base->virtbase;
1715
1716 spin_lock_irqsave(&cohc->lock, flags);
1717
1718 /* Disable channel in HW */
1719 val = readl(virtbase + COH901318_CX_CFG +
1720 COH901318_CX_CFG_SPACING * channel);
1721
25985edc 1722 /* Stopping infinite transfer */
61f135b9
LW		 1723 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1724 (val & COH901318_CX_CFG_CH_ENABLE))
1725 cohc->stopped = 1;
1726
1727
1728 val &= ~COH901318_CX_CFG_CH_ENABLE;
1729 /* Enable twice, HW bug work around */
1730 writel(val, virtbase + COH901318_CX_CFG +
1731 COH901318_CX_CFG_SPACING * channel);
1732 writel(val, virtbase + COH901318_CX_CFG +
1733 COH901318_CX_CFG_SPACING * channel);
1734
1735 /* Spin-wait for it to actually go inactive */
1736 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1737 channel) & COH901318_CX_STAT_ACTIVE)
1738 cpu_relax();
1739
1740 /* Check if we stopped an active job */
1741 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1742 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1743 cohc->stopped = 1;
1744
1745 enable_powersave(cohc);
1746
1747 spin_unlock_irqrestore(&cohc->lock, flags);
1748}
61f135b9 1749
c3635c78 1750/* Resumes a transfer that has been stopped via 300_dma_stop(..).
61f135b9
LW		 1751 Power save is handled.
1752*/
c3635c78 1753static void coh901318_resume(struct dma_chan *chan)
61f135b9
LW		 1754{
1755 u32 val;
1756 unsigned long flags;
1757 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1758 int channel = cohc->id;
1759
1760 spin_lock_irqsave(&cohc->lock, flags);
1761
1762 disable_powersave(cohc);
1763
1764 if (cohc->stopped) {
1765 /* Enable channel in HW */
1766 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1767 COH901318_CX_CFG_SPACING * channel);
1768
1769 val |= COH901318_CX_CFG_CH_ENABLE;
1770
1771 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1772 COH901318_CX_CFG_SPACING*channel);
1773
1774 cohc->stopped = 0;
1775 }
1776
1777 spin_unlock_irqrestore(&cohc->lock, flags);
1778}
61f135b9
LW		 1779
1780bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1781{
1782 unsigned int ch_nr = (unsigned int) chan_id;
1783
1784 if (ch_nr == to_coh901318_chan(chan)->id)
1785 return true;
1786
1787 return false;
1788}
1789EXPORT_SYMBOL(coh901318_filter_id);
1790
1791/*
1792 * DMA channel allocation
1793 */
1794static int coh901318_config(struct coh901318_chan *cohc,
1795 struct coh901318_params *param)
1796{
1797 unsigned long flags;
1798 const struct coh901318_params *p;
1799 int channel = cohc->id;
1800 void __iomem *virtbase = cohc->base->virtbase;
1801
1802 spin_lock_irqsave(&cohc->lock, flags);
1803
1804 if (param)
1805 p = param;
1806 else
73b31eae 1807 p = cohc_chan_param(cohc);
61f135b9
LW		 1808
1809 /* Clear any pending BE or TC interrupt */
1810 if (channel < 32) {
1811 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1812 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1813 } else {
1814 writel(1 << (channel - 32), virtbase +
1815 COH901318_BE_INT_CLEAR2);
1816 writel(1 << (channel - 32), virtbase +
1817 COH901318_TC_INT_CLEAR2);
1818 }
1819
1820 coh901318_set_conf(cohc, p->config);
1821 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1822
1823 spin_unlock_irqrestore(&cohc->lock, flags);
1824
1825 return 0;
1826}
1827
1828/* must lock when calling this function
1829 * start queued jobs, if any
1830 * TODO: start all queued jobs in one go
1831 *
1832 * Returns descriptor if queued job is started otherwise NULL.
1833 * If the queue is empty NULL is returned.
1834 */
1835static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1836{
cecd87da 1837 struct coh901318_desc *cohd;
61f135b9 1838
cecd87da
LW		 1839 /*
1840 * start queued jobs, if any
61f135b9
LW		 1841 * TODO: transmit all queued jobs in one go
1842 */
cecd87da 1843 cohd = coh901318_first_queued(cohc);
61f135b9 1844
cecd87da 1845 if (cohd != NULL) {
61f135b9 1846 /* Remove from queue */
cecd87da 1847 coh901318_desc_remove(cohd);
61f135b9
LW		 1848 /* initiate DMA job */
1849 cohc->busy = 1;
1850
cecd87da 1851 coh901318_desc_submit(cohc, cohd);
61f135b9 1852
b89243dd
LW		 1853 /* Program the transaction head */
1854 coh901318_set_conf(cohc, cohd->head_config);
1855 coh901318_set_ctrl(cohc, cohd->head_ctrl);
cecd87da 1856 coh901318_prep_linked_list(cohc, cohd->lli);
61f135b9 1857
cecd87da 1858 /* start dma job on this channel */
61f135b9
LW		 1859 coh901318_start(cohc);
1860
1861 }
1862
cecd87da 1863 return cohd;
61f135b9
LW		 1864}
1865
848ad121
LW		 1866/*
1867 * This tasklet is called from the interrupt handler to
1868 * handle each descriptor (DMA job) that is sent to a channel.
1869 */
61f135b9
LW		 1870static void dma_tasklet(unsigned long data)
1871{
1872 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1873 struct coh901318_desc *cohd_fin;
1874 unsigned long flags;
1875 dma_async_tx_callback callback;
1876 void *callback_param;
1877
848ad121
LW		 1878 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1879 " nbr_active_done %ld\n", __func__,
1880 cohc->id, cohc->nbr_active_done);
1881
61f135b9
LW		 1882 spin_lock_irqsave(&cohc->lock, flags);
1883
848ad121 1884 /* get first active descriptor entry from list */
61f135b9
LW		 1885 cohd_fin = coh901318_first_active_get(cohc);
1886
61f135b9
LW		 1887 if (cohd_fin == NULL)
1888 goto err;
1889
0b58828c
LW		 1890 /* locate callback to client */
1891 callback = cohd_fin->desc.callback;
1892 callback_param = cohd_fin->desc.callback_param;
61f135b9 1893
0b58828c 1894 /* sign this job as completed on the channel */
f7fbce07 1895 dma_cookie_complete(&cohd_fin->desc);
61f135b9 1896
0b58828c 1897 /* release the lli allocation and remove the descriptor */
cecd87da 1898 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
61f135b9 1899
0b58828c
LW		 1900 /* return desc to free-list */
1901 coh901318_desc_remove(cohd_fin);
1902 coh901318_desc_free(cohc, cohd_fin);
61f135b9 1903
0b58828c 1904 spin_unlock_irqrestore(&cohc->lock, flags);
61f135b9 1905
0b58828c
LW		 1906 /* Call the callback when we're done */
1907 if (callback)
1908 callback(callback_param);
61f135b9 1909
0b58828c 1910 spin_lock_irqsave(&cohc->lock, flags);
61f135b9 1911
848ad121
LW		 1912 /*
1913 * If another interrupt fired while the tasklet was scheduling,
1914 * we don't get called twice, so we have this number of active
1915 * counter that keep track of the number of IRQs expected to
1916 * be handled for this channel. If there happen to be more than
1917 * one IRQ to be ack:ed, we simply schedule this tasklet again.
1918 */
0b58828c 1919 cohc->nbr_active_done--;
61f135b9 1920 if (cohc->nbr_active_done) {
848ad121
LW		 1921 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1922 "came in while we were scheduling this tasklet\n");
61f135b9
LW		 1923 if (cohc_chan_conf(cohc)->priority_high)
1924 tasklet_hi_schedule(&cohc->tasklet);
1925 else
1926 tasklet_schedule(&cohc->tasklet);
1927 }
61f135b9 1928
0b58828c 1929 spin_unlock_irqrestore(&cohc->lock, flags);
61f135b9
LW		 1930
1931 return;
1932
1933 err:
1934 spin_unlock_irqrestore(&cohc->lock, flags);
1935 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1936}
1937
1938
1939/* called from interrupt context */
1940static void dma_tc_handle(struct coh901318_chan *cohc)
1941{
cecd87da
LW		 1942 /*
1943 * If the channel is not allocated, then we shouldn't have
1944 * any TC interrupts on it.
1945 */
1946 if (!cohc->allocated) {
1947 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
1948 "unallocated channel\n");
61f135b9 1949 return;
cecd87da 1950 }
61f135b9 1951
0b58828c 1952 spin_lock(&cohc->lock);
61f135b9 1953
cecd87da
LW		 1954 /*
1955 * When we reach this point, at least one queue item
1956 * should have been moved over from cohc->queue to
1957 * cohc->active and run to completion, that is why we're
1958 * getting a terminal count interrupt is it not?
1959 * If you get this BUG() the most probable cause is that
1960 * the individual nodes in the lli chain have IRQ enabled,
1961 * so check your platform config for lli chain ctrl.
1962 */
1963 BUG_ON(list_empty(&cohc->active));
1964
61f135b9
LW		 1965 cohc->nbr_active_done++;
1966
cecd87da
LW		 1967 /*
1968 * This attempt to take a job from cohc->queue, put it
1969 * into cohc->active and start it.
1970 */
0b58828c 1971 if (coh901318_queue_start(cohc) == NULL)
61f135b9
LW		 1972 cohc->busy = 0;
1973
0b58828c
LW		 1974 spin_unlock(&cohc->lock);
1975
cecd87da
LW		 1976 /*
1977 * This tasklet will remove items from cohc->active
1978 * and thus terminates them.
1979 */
61f135b9
LW		 1980 if (cohc_chan_conf(cohc)->priority_high)
1981 tasklet_hi_schedule(&cohc->tasklet);
1982 else
1983 tasklet_schedule(&cohc->tasklet);
1984}
1985
1986
1987static irqreturn_t dma_irq_handler(int irq, void *dev_id)
1988{
1989 u32 status1;
1990 u32 status2;
1991 int i;
1992 int ch;
1993 struct coh901318_base *base = dev_id;
1994 struct coh901318_chan *cohc;
1995 void __iomem *virtbase = base->virtbase;
1996
1997 status1 = readl(virtbase + COH901318_INT_STATUS1);
1998 status2 = readl(virtbase + COH901318_INT_STATUS2);
1999
2000 if (unlikely(status1 == 0 && status2 == 0)) {
2001 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
2002 return IRQ_HANDLED;
2003 }
2004
2005 /* TODO: consider handle IRQ in tasklet here to
2006 * minimize interrupt latency */
2007
2008 /* Check the first 32 DMA channels for IRQ */
2009 while (status1) {
2010 /* Find first bit set, return as a number. */
2011 i = ffs(status1) - 1;
2012 ch = i;
2013
2014 cohc = &base->chans[ch];
2015 spin_lock(&cohc->lock);
2016
2017 /* Mask off this bit */
2018 status1 &= ~(1 << i);
2019 /* Check the individual channel bits */
2020 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2021 dev_crit(COHC_2_DEV(cohc),
2022 "DMA bus error on channel %d!\n", ch);
2023 BUG_ON(1);
2024 /* Clear BE interrupt */
2025 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2026 } else {
2027 /* Caused by TC, really? */
2028 if (unlikely(!test_bit(i, virtbase +
2029 COH901318_TC_INT_STATUS1))) {
2030 dev_warn(COHC_2_DEV(cohc),
2031 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2032 /* Clear TC interrupt */
2033 BUG_ON(1);
2034 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2035 } else {
2036 /* Enable powersave if transfer has finished */
2037 if (!(readl(virtbase + COH901318_CX_STAT +
2038 COH901318_CX_STAT_SPACING*ch) &
2039 COH901318_CX_STAT_ENABLED)) {
2040 enable_powersave(cohc);
2041 }
2042
2043 /* Must clear TC interrupt before calling
2044 * dma_tc_handle
bc0b44c3 2045 * in case tc_handle initiate a new dma job
61f135b9
LW		 2046 */
2047 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2048
2049 dma_tc_handle(cohc);
2050 }
2051 }
2052 spin_unlock(&cohc->lock);
2053 }
2054
2055 /* Check the remaining 32 DMA channels for IRQ */
2056 while (status2) {
2057 /* Find first bit set, return as a number. */
2058 i = ffs(status2) - 1;
2059 ch = i + 32;
2060 cohc = &base->chans[ch];
2061 spin_lock(&cohc->lock);
2062
2063 /* Mask off this bit */
2064 status2 &= ~(1 << i);
2065 /* Check the individual channel bits */
2066 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2067 dev_crit(COHC_2_DEV(cohc),
2068 "DMA bus error on channel %d!\n", ch);
2069 /* Clear BE interrupt */
2070 BUG_ON(1);
2071 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2072 } else {
2073 /* Caused by TC, really? */
2074 if (unlikely(!test_bit(i, virtbase +
2075 COH901318_TC_INT_STATUS2))) {
2076 dev_warn(COHC_2_DEV(cohc),
2077 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2078 /* Clear TC interrupt */
2079 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2080 BUG_ON(1);
2081 } else {
2082 /* Enable powersave if transfer has finished */
2083 if (!(readl(virtbase + COH901318_CX_STAT +
2084 COH901318_CX_STAT_SPACING*ch) &
2085 COH901318_CX_STAT_ENABLED)) {
2086 enable_powersave(cohc);
2087 }
2088 /* Must clear TC interrupt before calling
2089 * dma_tc_handle
bc0b44c3 2090 * in case tc_handle initiate a new dma job
61f135b9
LW		 2091 */
2092 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2093
2094 dma_tc_handle(cohc);
2095 }
2096 }
2097 spin_unlock(&cohc->lock);
2098 }
2099
2100 return IRQ_HANDLED;
2101}
2102
2103static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2104{
2105 struct coh901318_chan *cohc = to_coh901318_chan(chan);
84c8447c 2106 unsigned long flags;
61f135b9
LW		 2107
2108 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2109 __func__, cohc->id);
2110
2111 if (chan->client_count > 1)
2112 return -EBUSY;
2113
84c8447c
LW		 2114 spin_lock_irqsave(&cohc->lock, flags);
2115
61f135b9
LW		 2116 coh901318_config(cohc, NULL);
2117
2118 cohc->allocated = 1;
d3ee98cd 2119 dma_cookie_init(chan);
61f135b9 2120
84c8447c
LW		 2121 spin_unlock_irqrestore(&cohc->lock, flags);
2122
61f135b9
LW		 2123 return 1;
2124}
2125
2126static void
2127coh901318_free_chan_resources(struct dma_chan *chan)
2128{
2129 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2130 int channel = cohc->id;
2131 unsigned long flags;
2132
2133 spin_lock_irqsave(&cohc->lock, flags);
2134
2135 /* Disable HW */
2136 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2137 COH901318_CX_CFG_SPACING*channel);
2138 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2139 COH901318_CX_CTRL_SPACING*channel);
2140
2141 cohc->allocated = 0;
2142
2143 spin_unlock_irqrestore(&cohc->lock, flags);
2144
05827630 2145 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
61f135b9
LW		 2146}
2147
2148
2149static dma_cookie_t
2150coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2151{
2152 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2153 desc);
2154 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2155 unsigned long flags;
884485e1 2156 dma_cookie_t cookie;
61f135b9
LW		 2157
2158 spin_lock_irqsave(&cohc->lock, flags);
884485e1 2159 cookie = dma_cookie_assign(tx);
61f135b9
LW		 2160
2161 coh901318_desc_queue(cohc, cohd);
2162
2163 spin_unlock_irqrestore(&cohc->lock, flags);
2164
884485e1 2165 return cookie;
61f135b9
LW		 2166}
2167
2168static struct dma_async_tx_descriptor *
2169coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2170 size_t size, unsigned long flags)
2171{
cecd87da 2172 struct coh901318_lli *lli;
61f135b9
LW		 2173 struct coh901318_desc *cohd;
2174 unsigned long flg;
2175 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2176 int lli_len;
2177 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
b87108a7 2178 int ret;
61f135b9
LW		 2179
2180 spin_lock_irqsave(&cohc->lock, flg);
2181
2182 dev_vdbg(COHC_2_DEV(cohc),
2183 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
2184 __func__, cohc->id, src, dest, size);
2185
2186 if (flags & DMA_PREP_INTERRUPT)
2187 /* Trigger interrupt after last lli */
2188 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2189
2190 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2191 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2192 lli_len++;
2193
cecd87da 2194 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
61f135b9 2195
cecd87da 2196 if (lli == NULL)
61f135b9
LW		 2197 goto err;
2198
b87108a7 2199 ret = coh901318_lli_fill_memcpy(
cecd87da 2200 &cohc->base->pool, lli, src, size, dest,
b87108a7
LW		 2201 cohc_chan_param(cohc)->ctrl_lli_chained,
2202 ctrl_last);
2203 if (ret)
2204 goto err;
61f135b9 2205
cecd87da 2206 COH_DBG(coh901318_list_print(cohc, lli));
61f135b9 2207
b87108a7
LW		 2208 /* Pick a descriptor to handle this transfer */
2209 cohd = coh901318_desc_get(cohc);
cecd87da 2210 cohd->lli = lli;
b87108a7 2211 cohd->flags = flags;
61f135b9
LW		 2212 cohd->desc.tx_submit = coh901318_tx_submit;
2213
2214 spin_unlock_irqrestore(&cohc->lock, flg);
2215
2216 return &cohd->desc;
2217 err:
2218 spin_unlock_irqrestore(&cohc->lock, flg);
2219 return NULL;
2220}
2221
2222static struct dma_async_tx_descriptor *
2223coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
db8196df 2224 unsigned int sg_len, enum dma_transfer_direction direction,
185ecb5f 2225 unsigned long flags, void *context)
61f135b9
LW		 2226{
2227 struct coh901318_chan *cohc = to_coh901318_chan(chan);
cecd87da 2228 struct coh901318_lli *lli;
61f135b9 2229 struct coh901318_desc *cohd;
516fd430 2230 const struct coh901318_params *params;
61f135b9
LW		 2231 struct scatterlist *sg;
2232 int len = 0;
2233 int size;
2234 int i;
2235 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2236 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2237 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
516fd430 2238 u32 config;
61f135b9 2239 unsigned long flg;
0b58828c 2240 int ret;
61f135b9
LW		 2241
2242 if (!sgl)
2243 goto out;
fdaf9c4b 2244 if (sg_dma_len(sgl) == 0)
61f135b9
LW		 2245 goto out;
2246
2247 spin_lock_irqsave(&cohc->lock, flg);
2248
2249 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2250 __func__, sg_len, direction);
2251
2252 if (flags & DMA_PREP_INTERRUPT)
2253 /* Trigger interrupt after last lli */
2254 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2255
516fd430
LW		 2256 params = cohc_chan_param(cohc);
2257 config = params->config;
128f904a
LW		 2258 /*
2259 * Add runtime-specific control on top, make
2260 * sure the bits you set per peripheral channel are
2261 * cleared in the default config from the platform.
2262 */
9aab4d6f
LW		 2263 ctrl_chained |= cohc->ctrl;
2264 ctrl_last |= cohc->ctrl;
2265 ctrl |= cohc->ctrl;
516fd430 2266
db8196df 2267 if (direction == DMA_MEM_TO_DEV) {
61f135b9
LW		 2268 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2269 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2270
516fd430 2271 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
61f135b9
LW		 2272 ctrl_chained |= tx_flags;
2273 ctrl_last |= tx_flags;
2274 ctrl |= tx_flags;
db8196df 2275 } else if (direction == DMA_DEV_TO_MEM) {
61f135b9
LW		 2276 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2277 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2278
516fd430 2279 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
61f135b9
LW		 2280 ctrl_chained |= rx_flags;
2281 ctrl_last |= rx_flags;
2282 ctrl |= rx_flags;
2283 } else
2284 goto err_direction;
2285
61f135b9
LW		 2286 /* The dma only supports transmitting packages up to
2287 * MAX_DMA_PACKET_SIZE. Calculate to total number of
2288 * dma elemts required to send the entire sg list
2289 */
2290 for_each_sg(sgl, sg, sg_len, i) {
2291 unsigned int factor;
2292 size = sg_dma_len(sg);
2293
2294 if (size <= MAX_DMA_PACKET_SIZE) {
2295 len++;
2296 continue;
2297 }
2298
2299 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2300 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2301 factor++;
2302
2303 len += factor;
2304 }
2305
848ad121 2306 pr_debug("Allocate %d lli:s for this transfer\n", len);
cecd87da 2307 lli = coh901318_lli_alloc(&cohc->base->pool, len);
61f135b9 2308
cecd87da 2309 if (lli == NULL)
61f135b9
LW		 2310 goto err_dma_alloc;
2311
cecd87da
LW		 2312 /* initiate allocated lli list */
2313 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
9aab4d6f 2314 cohc->addr,
0b58828c
LW		 2315 ctrl_chained,
2316 ctrl,
2317 ctrl_last,
2318 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2319 if (ret)
2320 goto err_lli_fill;
61f135b9 2321
128f904a 2322
cecd87da 2323 COH_DBG(coh901318_list_print(cohc, lli));
61f135b9 2324
b87108a7
LW		 2325 /* Pick a descriptor to handle this transfer */
2326 cohd = coh901318_desc_get(cohc);
b89243dd
LW		 2327 cohd->head_config = config;
2328 /*
2329 * Set the default head ctrl for the channel to the one from the
2330 * lli, things may have changed due to odd buffer alignment
2331 * etc.
2332 */
2333 cohd->head_ctrl = lli->control;
b87108a7
LW		 2334 cohd->dir = direction;
2335 cohd->flags = flags;
2336 cohd->desc.tx_submit = coh901318_tx_submit;
cecd87da 2337 cohd->lli = lli;
b87108a7 2338
61f135b9
LW		 2339 spin_unlock_irqrestore(&cohc->lock, flg);
2340
2341 return &cohd->desc;
0b58828c 2342 err_lli_fill:
61f135b9
LW		 2343 err_dma_alloc:
2344 err_direction:
61f135b9
LW		 2345 spin_unlock_irqrestore(&cohc->lock, flg);
2346 out:
2347 return NULL;
2348}
2349
2350static enum dma_status
07934481
LW		 2351coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2352 struct dma_tx_state *txstate)
61f135b9
LW		 2353{
2354 struct coh901318_chan *cohc = to_coh901318_chan(chan);
96a2af41 2355 enum dma_status ret;
61f135b9 2356
96a2af41 2357 ret = dma_cookie_status(chan, cookie, txstate);
9b562639
AS		 2358 if (ret == DMA_SUCCESS)
2359 return ret;
2360
96a2af41 2361 dma_set_residue(txstate, coh901318_get_bytes_left(chan));
61f135b9 2362
07934481
LW		 2363 if (ret == DMA_IN_PROGRESS && cohc->stopped)
2364 ret = DMA_PAUSED;
61f135b9
LW		 2365
2366 return ret;
2367}
2368
2369static void
2370coh901318_issue_pending(struct dma_chan *chan)
2371{
2372 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2373 unsigned long flags;
2374
2375 spin_lock_irqsave(&cohc->lock, flags);
2376
cecd87da
LW		 2377 /*
2378 * Busy means that pending jobs are already being processed,
2379 * and then there is no point in starting the queue: the
2380 * terminal count interrupt on the channel will take the next
2381 * job on the queue and execute it anyway.
2382 */
61f135b9
LW		 2383 if (!cohc->busy)
2384 coh901318_queue_start(cohc);
2385
2386 spin_unlock_irqrestore(&cohc->lock, flags);
2387}
2388
128f904a
LW		 2389/*
2390 * Here we wrap in the runtime dma control interface
2391 */
2392struct burst_table {
2393 int burst_8bit;
2394 int burst_16bit;
2395 int burst_32bit;
2396 u32 reg;
2397};
2398
2399static const struct burst_table burst_sizes[] = {
2400 {
2401 .burst_8bit = 64,
2402 .burst_16bit = 32,
2403 .burst_32bit = 16,
2404 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2405 },
2406 {
2407 .burst_8bit = 48,
2408 .burst_16bit = 24,
2409 .burst_32bit = 12,
2410 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2411 },
2412 {
2413 .burst_8bit = 32,
2414 .burst_16bit = 16,
2415 .burst_32bit = 8,
2416 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2417 },
2418 {
2419 .burst_8bit = 16,
2420 .burst_16bit = 8,
2421 .burst_32bit = 4,
2422 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2423 },
2424 {
2425 .burst_8bit = 8,
2426 .burst_16bit = 4,
2427 .burst_32bit = 2,
2428 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2429 },
2430 {
2431 .burst_8bit = 4,
2432 .burst_16bit = 2,
2433 .burst_32bit = 1,
2434 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2435 },
2436 {
2437 .burst_8bit = 2,
2438 .burst_16bit = 1,
2439 .burst_32bit = 0,
2440 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2441 },
2442 {
2443 .burst_8bit = 1,
2444 .burst_16bit = 0,
2445 .burst_32bit = 0,
2446 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2447 },
2448};
2449
2450static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2451 struct dma_slave_config *config)
2452{
2453 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2454 dma_addr_t addr;
2455 enum dma_slave_buswidth addr_width;
2456 u32 maxburst;
9aab4d6f 2457 u32 ctrl = 0;
128f904a
LW		 2458 int i = 0;
2459
2460 /* We only support mem to per or per to mem transfers */
db8196df 2461 if (config->direction == DMA_DEV_TO_MEM) {
128f904a
LW		 2462 addr = config->src_addr;
2463 addr_width = config->src_addr_width;
2464 maxburst = config->src_maxburst;
db8196df 2465 } else if (config->direction == DMA_MEM_TO_DEV) {
128f904a
LW		 2466 addr = config->dst_addr;
2467 addr_width = config->dst_addr_width;
2468 maxburst = config->dst_maxburst;
2469 } else {
2470 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2471 return;
2472 }
2473
2474 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2475 addr_width);
2476 switch (addr_width) {
2477 case DMA_SLAVE_BUSWIDTH_1_BYTE:
9aab4d6f 2478 ctrl |=
128f904a
LW		 2479 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2480 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2481
2482 while (i < ARRAY_SIZE(burst_sizes)) {
2483 if (burst_sizes[i].burst_8bit <= maxburst)
2484 break;
2485 i++;
2486 }
2487
2488 break;
2489 case DMA_SLAVE_BUSWIDTH_2_BYTES:
9aab4d6f 2490 ctrl |=
128f904a
LW		 2491 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2492 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2493
2494 while (i < ARRAY_SIZE(burst_sizes)) {
2495 if (burst_sizes[i].burst_16bit <= maxburst)
2496 break;
2497 i++;
2498 }
2499
2500 break;
2501 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2502 /* Direction doesn't matter here, it's 32/32 bits */
9aab4d6f 2503 ctrl |=
128f904a
LW		 2504 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2505 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2506
2507 while (i < ARRAY_SIZE(burst_sizes)) {
2508 if (burst_sizes[i].burst_32bit <= maxburst)
2509 break;
2510 i++;
2511 }
2512
2513 break;
2514 default:
2515 dev_err(COHC_2_DEV(cohc),
2516 "bad runtimeconfig: alien address width\n");
2517 return;
2518 }
2519
9aab4d6f 2520 ctrl |= burst_sizes[i].reg;
128f904a
LW		 2521 dev_dbg(COHC_2_DEV(cohc),
2522 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2523 burst_sizes[i].burst_8bit, addr_width, maxburst);
2524
9aab4d6f
LW		 2525 cohc->addr = addr;
2526 cohc->ctrl = ctrl;
128f904a
LW		 2527}
2528
c3635c78 2529static int
05827630
LW		 2530coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2531 unsigned long arg)
61f135b9
LW		 2532{
2533 unsigned long flags;
2534 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2535 struct coh901318_desc *cohd;
2536 void __iomem *virtbase = cohc->base->virtbase;
2537
128f904a
LW		 2538 if (cmd == DMA_SLAVE_CONFIG) {
2539 struct dma_slave_config *config =
2540 (struct dma_slave_config *) arg;
2541
2542 coh901318_dma_set_runtimeconfig(chan, config);
2543 return 0;
2544 }
2545
c3635c78
LW		 2546 if (cmd == DMA_PAUSE) {
2547 coh901318_pause(chan);
2548 return 0;
2549 }
2550
2551 if (cmd == DMA_RESUME) {
2552 coh901318_resume(chan);
2553 return 0;
2554 }
2555
2556 if (cmd != DMA_TERMINATE_ALL)
2557 return -ENXIO;
61f135b9 2558
c3635c78
LW		 2559 /* The remainder of this function terminates the transfer */
2560 coh901318_pause(chan);
61f135b9
LW		 2561 spin_lock_irqsave(&cohc->lock, flags);
2562
2563 /* Clear any pending BE or TC interrupt */
2564 if (cohc->id < 32) {
2565 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2566 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2567 } else {
2568 writel(1 << (cohc->id - 32), virtbase +
2569 COH901318_BE_INT_CLEAR2);
2570 writel(1 << (cohc->id - 32), virtbase +
2571 COH901318_TC_INT_CLEAR2);
2572 }
2573
2574 enable_powersave(cohc);
2575
2576 while ((cohd = coh901318_first_active_get(cohc))) {
2577 /* release the lli allocation*/
cecd87da 2578 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
61f135b9 2579
61f135b9 2580 /* return desc to free-list */
848ad121 2581 coh901318_desc_remove(cohd);
61f135b9
LW		 2582 coh901318_desc_free(cohc, cohd);
2583 }
2584
2585 while ((cohd = coh901318_first_queued(cohc))) {
2586 /* release the lli allocation*/
cecd87da 2587 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
61f135b9 2588
61f135b9 2589 /* return desc to free-list */
848ad121 2590 coh901318_desc_remove(cohd);
61f135b9
LW		 2591 coh901318_desc_free(cohc, cohd);
2592 }
2593
2594
2595 cohc->nbr_active_done = 0;
2596 cohc->busy = 0;
61f135b9
LW		 2597
2598 spin_unlock_irqrestore(&cohc->lock, flags);
c3635c78
LW		 2599
2600 return 0;
61f135b9 2601}
128f904a 2602
61f135b9
LW		 2603void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2604 struct coh901318_base *base)
2605{
2606 int chans_i;
2607 int i = 0;
2608 struct coh901318_chan *cohc;
2609
2610 INIT_LIST_HEAD(&dma->channels);
2611
2612 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2613 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2614 cohc = &base->chans[i];
2615
2616 cohc->base = base;
2617 cohc->chan.device = dma;
2618 cohc->id = i;
2619
2620 /* TODO: do we really need this lock if only one
2621 * client is connected to each channel?
2622 */
2623
2624 spin_lock_init(&cohc->lock);
2625
61f135b9
LW		 2626 cohc->nbr_active_done = 0;
2627 cohc->busy = 0;
2628 INIT_LIST_HEAD(&cohc->free);
2629 INIT_LIST_HEAD(&cohc->active);
2630 INIT_LIST_HEAD(&cohc->queue);
2631
2632 tasklet_init(&cohc->tasklet, dma_tasklet,
2633 (unsigned long) cohc);
2634
2635 list_add_tail(&cohc->chan.device_node,
2636 &dma->channels);
2637 }
2638 }
2639}
2640
2641static int __init coh901318_probe(struct platform_device *pdev)
2642{
2643 int err = 0;
61f135b9
LW		 2644 struct coh901318_base *base;
2645 int irq;
2646 struct resource *io;
2647
2648 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2649 if (!io)
f7ceb362 2650 return -ENODEV;
61f135b9
LW		 2651
2652 /* Map DMA controller registers to virtual memory */
f7ceb362
LW		 2653 if (devm_request_mem_region(&pdev->dev,
2654 io->start,
2655 resource_size(io),
2656 pdev->dev.driver->name) == NULL)
2657 return -ENOMEM;
61f135b9 2658
f7ceb362
LW		 2659 base = devm_kzalloc(&pdev->dev,
2660 ALIGN(sizeof(struct coh901318_base), 4) +
73b31eae 2661 U300_DMA_CHANNELS *
f7ceb362
LW		 2662 sizeof(struct coh901318_chan),
2663 GFP_KERNEL);
61f135b9 2664 if (!base)
f7ceb362 2665 return -ENOMEM;
61f135b9
LW		 2666
2667 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2668
f7ceb362
LW		 2669 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2670 if (!base->virtbase)
2671 return -ENOMEM;
61f135b9
LW		 2672
2673 base->dev = &pdev->dev;
61f135b9
LW		 2674 spin_lock_init(&base->pm.lock);
2675 base->pm.started_channels = 0;
2676
2677 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2678
61f135b9
LW		 2679 irq = platform_get_irq(pdev, 0);
2680 if (irq < 0)
f7ceb362
LW		 2681 return irq;
2682
2683 err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
2684 "coh901318", base);
2685 if (err)
2686 return err;
61f135b9
LW		 2687
2688 err = coh901318_pool_create(&base->pool, &pdev->dev,
2689 sizeof(struct coh901318_lli),
2690 32);
2691 if (err)
f7ceb362 2692 return err;
61f135b9
LW		 2693
2694 /* init channels for device transfers */
73b31eae 2695 coh901318_base_init(&base->dma_slave, dma_slave_channels,
61f135b9
LW		 2696 base);
2697
2698 dma_cap_zero(base->dma_slave.cap_mask);
2699 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2700
2701 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2702 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2703 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
07934481 2704 base->dma_slave.device_tx_status = coh901318_tx_status;
61f135b9 2705 base->dma_slave.device_issue_pending = coh901318_issue_pending;
c3635c78 2706 base->dma_slave.device_control = coh901318_control;
61f135b9
LW		 2707 base->dma_slave.dev = &pdev->dev;
2708
2709 err = dma_async_device_register(&base->dma_slave);
2710
2711 if (err)
2712 goto err_register_slave;
2713
2714 /* init channels for memcpy */
73b31eae 2715 coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
61f135b9
LW		 2716 base);
2717
2718 dma_cap_zero(base->dma_memcpy.cap_mask);
2719 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2720
2721 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2722 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2723 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
07934481 2724 base->dma_memcpy.device_tx_status = coh901318_tx_status;
61f135b9 2725 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
c3635c78 2726 base->dma_memcpy.device_control = coh901318_control;
61f135b9 2727 base->dma_memcpy.dev = &pdev->dev;
516fd430
LW		 2728 /*
2729 * This controller can only access address at even 32bit boundaries,
2730 * i.e. 2^2
2731 */
2732 base->dma_memcpy.copy_align = 2;
61f135b9
LW		 2733 err = dma_async_device_register(&base->dma_memcpy);
2734
2735 if (err)
2736 goto err_register_memcpy;
2737
f7ceb362 2738 platform_set_drvdata(pdev, base);
848ad121 2739 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
61f135b9
LW		 2740 (u32) base->virtbase);
2741
2742 return err;
2743
2744 err_register_memcpy:
2745 dma_async_device_unregister(&base->dma_slave);
2746 err_register_slave:
2747 coh901318_pool_destroy(&base->pool);
61f135b9
LW		 2748 return err;
2749}
2750
1d1bbd30 2751static int coh901318_remove(struct platform_device *pdev)
61f135b9
LW		 2752{
2753 struct coh901318_base *base = platform_get_drvdata(pdev);
2754
2755 dma_async_device_unregister(&base->dma_memcpy);
2756 dma_async_device_unregister(&base->dma_slave);
2757 coh901318_pool_destroy(&base->pool);
61f135b9
LW		 2758 return 0;
2759}
2760
2761
2762static struct platform_driver coh901318_driver = {
1d1bbd30 2763 .remove = coh901318_remove,
61f135b9
LW		 2764 .driver = {
2765 .name = "coh901318",
2766 },
2767};
2768
2769int __init coh901318_init(void)
2770{
2771 return platform_driver_probe(&coh901318_driver, coh901318_probe);
2772}
a0eb221a 2773subsys_initcall(coh901318_init);
61f135b9
LW		 2774
2775void __exit coh901318_exit(void)
2776{
2777 platform_driver_unregister(&coh901318_driver);
2778}
2779module_exit(coh901318_exit);
2780
2781MODULE_LICENSE("GPL");
2782MODULE_AUTHOR("Per Friden");
kernel source for telekom puls (alcatel/mediatek)