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crypto: talitos - consolidate cra_type assignments
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
81eb024c
KP		 56static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
57{
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 59 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 60}
61
9c4a7965
KP		 62/*
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
64 */
65static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
68 unsigned char extent,
69 enum dma_data_direction dir)
70{
81eb024c
KP		 71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
72
9c4a7965 73 talitos_ptr->len = cpu_to_be16(len);
81eb024c 74 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 75 talitos_ptr->j_extent = extent;
76}
77
78/*
79 * unmap bus single (contiguous) h/w descriptor pointer
80 */
81static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
84{
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
87}
88
89static int reset_channel(struct device *dev, int ch)
90{
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
93
ad42d5fc 94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
9c4a7965 95
ad42d5fc 96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
9c4a7965
KP		 97 && --timeout)
98 cpu_relax();
99
100 if (timeout == 0) {
101 dev_err(dev, "failed to reset channel %d\n", ch);
102 return -EIO;
103 }
104
81eb024c 105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 108
fe5720e2
KP		 109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 112 TALITOS_CCCR_LO_IWSE);
113
9c4a7965
KP		 114 return 0;
115}
116
117static int reset_device(struct device *dev)
118{
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
c3e337f8 121 u32 mcr = TALITOS_MCR_SWR;
9c4a7965 122
c3e337f8 123 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965
KP		 124
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
126 && --timeout)
127 cpu_relax();
128
2cdba3cf 129 if (priv->irq[1]) {
c3e337f8
KP		 130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
132 }
133
9c4a7965
KP		 134 if (timeout == 0) {
135 dev_err(dev, "failed to reset device\n");
136 return -EIO;
137 }
138
139 return 0;
140}
141
142/*
143 * Reset and initialize the device
144 */
145static int init_device(struct device *dev)
146{
147 struct talitos_private *priv = dev_get_drvdata(dev);
148 int ch, err;
149
150 /*
151 * Master reset
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
155 */
156 err = reset_device(dev);
157 if (err)
158 return err;
159
160 err = reset_device(dev);
161 if (err)
162 return err;
163
164 /* reset channels */
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
167 if (err)
168 return err;
169 }
170
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
174
fe5720e2
KP		 175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
179
9c4a7965
KP		 180 return 0;
181}
182
183/**
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
5228f0f7 186 * @ch: the SEC device channel to be used
9c4a7965
KP		 187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
190 *
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
194 */
865d5061
HG		 195int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
199 void *context)
9c4a7965
KP		 200{
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
5228f0f7 203 unsigned long flags;
9c4a7965
KP		 204 int head;
205
4b992628 206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 207
4b992628 208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 209 /* h/w fifo is full */
4b992628 210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 211 return -EAGAIN;
212 }
213
4b992628
KP		 214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
ec6644d6 216
9c4a7965
KP		 217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
219 DMA_BIDIRECTIONAL);
220 request->callback = callback;
221 request->context = context;
222
223 /* increment fifo head */
4b992628 224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 225
226 smp_wmb();
227 request->desc = desc;
228
229 /* GO! */
230 wmb();
ad42d5fc
KP		 231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 234 lower_32_bits(request->dma_desc));
9c4a7965 235
4b992628 236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 237
238 return -EINPROGRESS;
239}
865d5061 240EXPORT_SYMBOL(talitos_submit);
9c4a7965
KP		 241
242/*
243 * process what was done, notify callback of error if not
244 */
245static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
246{
247 struct talitos_private *priv = dev_get_drvdata(dev);
248 struct talitos_request *request, saved_req;
249 unsigned long flags;
250 int tail, status;
251
4b992628 252 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 253
4b992628
KP		 254 tail = priv->chan[ch].tail;
255 while (priv->chan[ch].fifo[tail].desc) {
256 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 257
258 /* descriptors with their done bits set don't get the error */
259 rmb();
ca38a814 260 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 261 status = 0;
ca38a814 262 else
9c4a7965
KP		 263 if (!error)
264 break;
265 else
266 status = error;
267
268 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 269 sizeof(struct talitos_desc),
270 DMA_BIDIRECTIONAL);
9c4a7965
KP		 271
272 /* copy entries so we can call callback outside lock */
273 saved_req.desc = request->desc;
274 saved_req.callback = request->callback;
275 saved_req.context = request->context;
276
277 /* release request entry in fifo */
278 smp_wmb();
279 request->desc = NULL;
280
281 /* increment fifo tail */
4b992628 282 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 283
4b992628 284 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 285
4b992628 286 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 287
9c4a7965
KP		 288 saved_req.callback(dev, saved_req.desc, saved_req.context,
289 status);
290 /* channel may resume processing in single desc error case */
291 if (error && !reset_ch && status == error)
292 return;
4b992628
KP		 293 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
294 tail = priv->chan[ch].tail;
9c4a7965
KP		 295 }
296
4b992628 297 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 298}
299
300/*
301 * process completed requests for channels that have done status
302 */
c3e337f8
KP		 303#define DEF_TALITOS_DONE(name, ch_done_mask) \
304static void talitos_done_##name(unsigned long data) \
305{ \
306 struct device *dev = (struct device *)data; \
307 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 308 unsigned long flags; \
c3e337f8
KP		 309 \
310 if (ch_done_mask & 1) \
311 flush_channel(dev, 0, 0, 0); \
312 if (priv->num_channels == 1) \
313 goto out; \
314 if (ch_done_mask & (1 << 2)) \
315 flush_channel(dev, 1, 0, 0); \
316 if (ch_done_mask & (1 << 4)) \
317 flush_channel(dev, 2, 0, 0); \
318 if (ch_done_mask & (1 << 6)) \
319 flush_channel(dev, 3, 0, 0); \
320 \
321out: \
322 /* At this point, all completed channels have been processed */ \
323 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 324 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 325 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
326 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
511d63cb 327 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 328}
c3e337f8
KP		 329DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
330DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
331DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
9c4a7965
KP		 332
333/*
334 * locate current (offending) descriptor
335 */
3e721aeb 336static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 337{
338 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 339 int tail = priv->chan[ch].tail;
9c4a7965
KP		 340 dma_addr_t cur_desc;
341
ad42d5fc 342 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 343
4b992628 344 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 345 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 346 if (tail == priv->chan[ch].tail) {
9c4a7965 347 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 348 return 0;
9c4a7965
KP		 349 }
350 }
351
3e721aeb 352 return priv->chan[ch].fifo[tail].desc->hdr;
9c4a7965
KP		 353}
354
355/*
356 * user diagnostics; report root cause of error based on execution unit status
357 */
3e721aeb 358static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 359{
360 struct talitos_private *priv = dev_get_drvdata(dev);
361 int i;
362
3e721aeb 363 if (!desc_hdr)
ad42d5fc 364 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 365
366 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 367 case DESC_HDR_SEL0_AFEU:
368 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
369 in_be32(priv->reg + TALITOS_AFEUISR),
370 in_be32(priv->reg + TALITOS_AFEUISR_LO));
371 break;
372 case DESC_HDR_SEL0_DEU:
373 dev_err(dev, "DEUISR 0x%08x_%08x\n",
374 in_be32(priv->reg + TALITOS_DEUISR),
375 in_be32(priv->reg + TALITOS_DEUISR_LO));
376 break;
377 case DESC_HDR_SEL0_MDEUA:
378 case DESC_HDR_SEL0_MDEUB:
379 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
380 in_be32(priv->reg + TALITOS_MDEUISR),
381 in_be32(priv->reg + TALITOS_MDEUISR_LO));
382 break;
383 case DESC_HDR_SEL0_RNG:
384 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
385 in_be32(priv->reg + TALITOS_RNGUISR),
386 in_be32(priv->reg + TALITOS_RNGUISR_LO));
387 break;
388 case DESC_HDR_SEL0_PKEU:
389 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
390 in_be32(priv->reg + TALITOS_PKEUISR),
391 in_be32(priv->reg + TALITOS_PKEUISR_LO));
392 break;
393 case DESC_HDR_SEL0_AESU:
394 dev_err(dev, "AESUISR 0x%08x_%08x\n",
395 in_be32(priv->reg + TALITOS_AESUISR),
396 in_be32(priv->reg + TALITOS_AESUISR_LO));
397 break;
398 case DESC_HDR_SEL0_CRCU:
399 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
400 in_be32(priv->reg + TALITOS_CRCUISR),
401 in_be32(priv->reg + TALITOS_CRCUISR_LO));
402 break;
403 case DESC_HDR_SEL0_KEU:
404 dev_err(dev, "KEUISR 0x%08x_%08x\n",
405 in_be32(priv->reg + TALITOS_KEUISR),
406 in_be32(priv->reg + TALITOS_KEUISR_LO));
407 break;
408 }
409
3e721aeb 410 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 411 case DESC_HDR_SEL1_MDEUA:
412 case DESC_HDR_SEL1_MDEUB:
413 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
414 in_be32(priv->reg + TALITOS_MDEUISR),
415 in_be32(priv->reg + TALITOS_MDEUISR_LO));
416 break;
417 case DESC_HDR_SEL1_CRCU:
418 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
419 in_be32(priv->reg + TALITOS_CRCUISR),
420 in_be32(priv->reg + TALITOS_CRCUISR_LO));
421 break;
422 }
423
424 for (i = 0; i < 8; i++)
425 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
427 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 428}
429
430/*
431 * recover from error interrupts
432 */
5e718a09 433static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 434{
9c4a7965
KP		 435 struct talitos_private *priv = dev_get_drvdata(dev);
436 unsigned int timeout = TALITOS_TIMEOUT;
437 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 438 u32 v, v_lo;
9c4a7965
KP		 439
440 for (ch = 0; ch < priv->num_channels; ch++) {
441 /* skip channels without errors */
442 if (!(isr & (1 << (ch * 2 + 1))))
443 continue;
444
445 error = -EINVAL;
446
ad42d5fc
KP		 447 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
448 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 449
450 if (v_lo & TALITOS_CCPSR_LO_DOF) {
451 dev_err(dev, "double fetch fifo overflow error\n");
452 error = -EAGAIN;
453 reset_ch = 1;
454 }
455 if (v_lo & TALITOS_CCPSR_LO_SOF) {
456 /* h/w dropped descriptor */
457 dev_err(dev, "single fetch fifo overflow error\n");
458 error = -EAGAIN;
459 }
460 if (v_lo & TALITOS_CCPSR_LO_MDTE)
461 dev_err(dev, "master data transfer error\n");
462 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
463 dev_err(dev, "s/g data length zero error\n");
464 if (v_lo & TALITOS_CCPSR_LO_FPZ)
465 dev_err(dev, "fetch pointer zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_IDH)
467 dev_err(dev, "illegal descriptor header error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IEU)
469 dev_err(dev, "invalid execution unit error\n");
470 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 471 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
9c4a7965
KP		 472 if (v_lo & TALITOS_CCPSR_LO_GB)
473 dev_err(dev, "gather boundary error\n");
474 if (v_lo & TALITOS_CCPSR_LO_GRL)
475 dev_err(dev, "gather return/length error\n");
476 if (v_lo & TALITOS_CCPSR_LO_SB)
477 dev_err(dev, "scatter boundary error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SRL)
479 dev_err(dev, "scatter return/length error\n");
480
481 flush_channel(dev, ch, error, reset_ch);
482
483 if (reset_ch) {
484 reset_channel(dev, ch);
485 } else {
ad42d5fc 486 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
9c4a7965 487 TALITOS_CCCR_CONT);
ad42d5fc
KP		 488 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
489 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
9c4a7965
KP		 490 TALITOS_CCCR_CONT) && --timeout)
491 cpu_relax();
492 if (timeout == 0) {
493 dev_err(dev, "failed to restart channel %d\n",
494 ch);
495 reset_dev = 1;
496 }
497 }
498 }
c3e337f8 499 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
9c4a7965
KP		 500 dev_err(dev, "done overflow, internal time out, or rngu error: "
501 "ISR 0x%08x_%08x\n", isr, isr_lo);
502
503 /* purge request queues */
504 for (ch = 0; ch < priv->num_channels; ch++)
505 flush_channel(dev, ch, -EIO, 1);
506
507 /* reset and reinitialize the device */
508 init_device(dev);
509 }
510}
511
c3e337f8
KP		 512#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
513static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
514{ \
515 struct device *dev = data; \
516 struct talitos_private *priv = dev_get_drvdata(dev); \
517 u32 isr, isr_lo; \
511d63cb 518 unsigned long flags; \
c3e337f8 519 \
511d63cb 520 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 521 isr = in_be32(priv->reg + TALITOS_ISR); \
522 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
523 /* Acknowledge interrupt */ \
524 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
525 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
526 \
511d63cb
HG		 527 if (unlikely(isr & ch_err_mask || isr_lo)) { \
528 spin_unlock_irqrestore(&priv->reg_lock, flags); \
529 talitos_error(dev, isr & ch_err_mask, isr_lo); \
530 } \
531 else { \
c3e337f8
KP		 532 if (likely(isr & ch_done_mask)) { \
533 /* mask further done interrupts. */ \
534 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
535 /* done_task will unmask done interrupts at exit */ \
536 tasklet_schedule(&priv->done_task[tlet]); \
537 } \
511d63cb
HG		 538 spin_unlock_irqrestore(&priv->reg_lock, flags); \
539 } \
c3e337f8
KP		 540 \
541 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
542 IRQ_NONE; \
9c4a7965 543}
c3e337f8
KP		 544DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
545DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
546DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
9c4a7965
KP		 547
548/*
549 * hwrng
550 */
551static int talitos_rng_data_present(struct hwrng *rng, int wait)
552{
553 struct device *dev = (struct device *)rng->priv;
554 struct talitos_private *priv = dev_get_drvdata(dev);
555 u32 ofl;
556 int i;
557
558 for (i = 0; i < 20; i++) {
559 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
560 TALITOS_RNGUSR_LO_OFL;
561 if (ofl || !wait)
562 break;
563 udelay(10);
564 }
565
566 return !!ofl;
567}
568
569static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
570{
571 struct device *dev = (struct device *)rng->priv;
572 struct talitos_private *priv = dev_get_drvdata(dev);
573
574 /* rng fifo requires 64-bit accesses */
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
576 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
577
578 return sizeof(u32);
579}
580
581static int talitos_rng_init(struct hwrng *rng)
582{
583 struct device *dev = (struct device *)rng->priv;
584 struct talitos_private *priv = dev_get_drvdata(dev);
585 unsigned int timeout = TALITOS_TIMEOUT;
586
587 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
588 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
589 && --timeout)
590 cpu_relax();
591 if (timeout == 0) {
592 dev_err(dev, "failed to reset rng hw\n");
593 return -ENODEV;
594 }
595
596 /* start generating */
597 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
598
599 return 0;
600}
601
602static int talitos_register_rng(struct device *dev)
603{
604 struct talitos_private *priv = dev_get_drvdata(dev);
605
606 priv->rng.name = dev_driver_string(dev),
607 priv->rng.init = talitos_rng_init,
608 priv->rng.data_present = talitos_rng_data_present,
609 priv->rng.data_read = talitos_rng_data_read,
610 priv->rng.priv = (unsigned long)dev;
611
612 return hwrng_register(&priv->rng);
613}
614
615static void talitos_unregister_rng(struct device *dev)
616{
617 struct talitos_private *priv = dev_get_drvdata(dev);
618
619 hwrng_unregister(&priv->rng);
620}
621
622/*
623 * crypto alg
624 */
625#define TALITOS_CRA_PRIORITY 3000
357fb605 626#define TALITOS_MAX_KEY_SIZE 96
3952f17e 627#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 628
497f2e6b 629#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 630
631struct talitos_ctx {
632 struct device *dev;
5228f0f7 633 int ch;
9c4a7965
KP		 634 __be32 desc_hdr_template;
635 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 636 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 637 unsigned int keylen;
638 unsigned int enckeylen;
639 unsigned int authkeylen;
640 unsigned int authsize;
641};
642
497f2e6b
LN		 643#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
644#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
645
646struct talitos_ahash_req_ctx {
60f208d7 647 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 648 unsigned int hw_context_size;
649 u8 buf[HASH_MAX_BLOCK_SIZE];
650 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 651 unsigned int swinit;
497f2e6b
LN		 652 unsigned int first;
653 unsigned int last;
654 unsigned int to_hash_later;
5e833bc4 655 u64 nbuf;
497f2e6b
LN		 656 struct scatterlist bufsl[2];
657 struct scatterlist *psrc;
658};
659
56af8cd4
LN		 660static int aead_setauthsize(struct crypto_aead *authenc,
661 unsigned int authsize)
9c4a7965
KP		 662{
663 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
664
665 ctx->authsize = authsize;
666
667 return 0;
668}
669
56af8cd4
LN		 670static int aead_setkey(struct crypto_aead *authenc,
671 const u8 *key, unsigned int keylen)
9c4a7965
KP		 672{
673 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
674 struct rtattr *rta = (void *)key;
675 struct crypto_authenc_key_param *param;
676 unsigned int authkeylen;
677 unsigned int enckeylen;
678
679 if (!RTA_OK(rta, keylen))
680 goto badkey;
681
682 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
683 goto badkey;
684
685 if (RTA_PAYLOAD(rta) < sizeof(*param))
686 goto badkey;
687
688 param = RTA_DATA(rta);
689 enckeylen = be32_to_cpu(param->enckeylen);
690
691 key += RTA_ALIGN(rta->rta_len);
692 keylen -= RTA_ALIGN(rta->rta_len);
693
694 if (keylen < enckeylen)
695 goto badkey;
696
697 authkeylen = keylen - enckeylen;
698
699 if (keylen > TALITOS_MAX_KEY_SIZE)
700 goto badkey;
701
702 memcpy(&ctx->key, key, keylen);
703
704 ctx->keylen = keylen;
705 ctx->enckeylen = enckeylen;
706 ctx->authkeylen = authkeylen;
707
708 return 0;
709
710badkey:
711 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
712 return -EINVAL;
713}
714
715/*
56af8cd4 716 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 717 * @src_nents: number of segments in input scatterlist
718 * @dst_nents: number of segments in output scatterlist
719 * @dma_len: length of dma mapped link_tbl space
720 * @dma_link_tbl: bus physical address of link_tbl
721 * @desc: h/w descriptor
722 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
723 *
724 * if decrypting (with authcheck), or either one of src_nents or dst_nents
725 * is greater than 1, an integrity check value is concatenated to the end
726 * of link_tbl data
727 */
56af8cd4 728struct talitos_edesc {
9c4a7965
KP		 729 int src_nents;
730 int dst_nents;
4de9d0b5
LN		 731 int src_is_chained;
732 int dst_is_chained;
9c4a7965
KP		 733 int dma_len;
734 dma_addr_t dma_link_tbl;
735 struct talitos_desc desc;
736 struct talitos_ptr link_tbl[0];
737};
738
4de9d0b5
LN		 739static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
740 unsigned int nents, enum dma_data_direction dir,
741 int chained)
742{
743 if (unlikely(chained))
744 while (sg) {
745 dma_map_sg(dev, sg, 1, dir);
746 sg = scatterwalk_sg_next(sg);
747 }
748 else
749 dma_map_sg(dev, sg, nents, dir);
750 return nents;
751}
752
753static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
754 enum dma_data_direction dir)
755{
756 while (sg) {
757 dma_unmap_sg(dev, sg, 1, dir);
758 sg = scatterwalk_sg_next(sg);
759 }
760}
761
762static void talitos_sg_unmap(struct device *dev,
763 struct talitos_edesc *edesc,
764 struct scatterlist *src,
765 struct scatterlist *dst)
766{
767 unsigned int src_nents = edesc->src_nents ? : 1;
768 unsigned int dst_nents = edesc->dst_nents ? : 1;
769
770 if (src != dst) {
771 if (edesc->src_is_chained)
772 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
773 else
774 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
775
497f2e6b
LN		 776 if (dst) {
777 if (edesc->dst_is_chained)
778 talitos_unmap_sg_chain(dev, dst,
779 DMA_FROM_DEVICE);
780 else
781 dma_unmap_sg(dev, dst, dst_nents,
782 DMA_FROM_DEVICE);
783 }
4de9d0b5
LN		 784 } else
785 if (edesc->src_is_chained)
786 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
787 else
788 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
789}
790
9c4a7965 791static void ipsec_esp_unmap(struct device *dev,
56af8cd4 792 struct talitos_edesc *edesc,
9c4a7965
KP		 793 struct aead_request *areq)
794{
795 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
796 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
797 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
798 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
799
800 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
801
4de9d0b5 802 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 803
804 if (edesc->dma_len)
805 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
806 DMA_BIDIRECTIONAL);
807}
808
809/*
810 * ipsec_esp descriptor callbacks
811 */
812static void ipsec_esp_encrypt_done(struct device *dev,
813 struct talitos_desc *desc, void *context,
814 int err)
815{
816 struct aead_request *areq = context;
9c4a7965
KP		 817 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
818 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 819 struct talitos_edesc *edesc;
9c4a7965
KP		 820 struct scatterlist *sg;
821 void *icvdata;
822
19bbbc63
KP		 823 edesc = container_of(desc, struct talitos_edesc, desc);
824
9c4a7965
KP		 825 ipsec_esp_unmap(dev, edesc, areq);
826
827 /* copy the generated ICV to dst */
828 if (edesc->dma_len) {
829 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 830 edesc->dst_nents + 2];
9c4a7965
KP		 831 sg = sg_last(areq->dst, edesc->dst_nents);
832 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
833 icvdata, ctx->authsize);
834 }
835
836 kfree(edesc);
837
838 aead_request_complete(areq, err);
839}
840
fe5720e2 841static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 842 struct talitos_desc *desc,
843 void *context, int err)
9c4a7965
KP		 844{
845 struct aead_request *req = context;
9c4a7965
KP		 846 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
847 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 848 struct talitos_edesc *edesc;
9c4a7965
KP		 849 struct scatterlist *sg;
850 void *icvdata;
851
19bbbc63
KP		 852 edesc = container_of(desc, struct talitos_edesc, desc);
853
9c4a7965
KP		 854 ipsec_esp_unmap(dev, edesc, req);
855
856 if (!err) {
857 /* auth check */
858 if (edesc->dma_len)
859 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 860 edesc->dst_nents + 2];
9c4a7965
KP		 861 else
862 icvdata = &edesc->link_tbl[0];
863
864 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
865 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
866 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
867 }
868
869 kfree(edesc);
870
871 aead_request_complete(req, err);
872}
873
fe5720e2 874static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 875 struct talitos_desc *desc,
876 void *context, int err)
fe5720e2
KP		 877{
878 struct aead_request *req = context;
19bbbc63
KP		 879 struct talitos_edesc *edesc;
880
881 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 882
883 ipsec_esp_unmap(dev, edesc, req);
884
885 /* check ICV auth status */
e938e465
KP		 886 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
887 DESC_HDR_LO_ICCR1_PASS))
888 err = -EBADMSG;
fe5720e2
KP		 889
890 kfree(edesc);
891
892 aead_request_complete(req, err);
893}
894
9c4a7965
KP		 895/*
896 * convert scatterlist to SEC h/w link table format
897 * stop at cryptlen bytes
898 */
70bcaca7 899static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 900 int cryptlen, struct talitos_ptr *link_tbl_ptr)
901{
70bcaca7
LN		 902 int n_sg = sg_count;
903
904 while (n_sg--) {
81eb024c 905 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 906 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
907 link_tbl_ptr->j_extent = 0;
908 link_tbl_ptr++;
909 cryptlen -= sg_dma_len(sg);
4de9d0b5 910 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 911 }
912
70bcaca7 913 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 914 link_tbl_ptr--;
c0e741d4 915 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 916 /* Empty this entry, and move to previous one */
917 cryptlen += be16_to_cpu(link_tbl_ptr->len);
918 link_tbl_ptr->len = 0;
919 sg_count--;
920 link_tbl_ptr--;
921 }
9c4a7965
KP		 922 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
923 + cryptlen);
924
925 /* tag end of link table */
926 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 927
928 return sg_count;
9c4a7965
KP		 929}
930
931/*
932 * fill in and submit ipsec_esp descriptor
933 */
56af8cd4 934static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 935 u8 *giv, u64 seq,
936 void (*callback) (struct device *dev,
937 struct talitos_desc *desc,
938 void *context, int error))
939{
940 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
941 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
942 struct device *dev = ctx->dev;
943 struct talitos_desc *desc = &edesc->desc;
944 unsigned int cryptlen = areq->cryptlen;
945 unsigned int authsize = ctx->authsize;
e41256f1 946 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 947 int sg_count, ret;
fe5720e2 948 int sg_link_tbl_len;
9c4a7965
KP		 949
950 /* hmac key */
951 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
952 0, DMA_TO_DEVICE);
953 /* hmac data */
e41256f1
KP		 954 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
955 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 956 /* cipher iv */
9c4a7965
KP		 957 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
958 DMA_TO_DEVICE);
959
960 /* cipher key */
961 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
962 (char *)&ctx->key + ctx->authkeylen, 0,
963 DMA_TO_DEVICE);
964
965 /*
966 * cipher in
967 * map and adjust cipher len to aead request cryptlen.
968 * extent is bytes of HMAC postpended to ciphertext,
969 * typically 12 for ipsec
970 */
971 desc->ptr[4].len = cpu_to_be16(cryptlen);
972 desc->ptr[4].j_extent = authsize;
973
e938e465
KP		 974 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
975 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
976 : DMA_TO_DEVICE,
4de9d0b5 977 edesc->src_is_chained);
9c4a7965
KP		 978
979 if (sg_count == 1) {
81eb024c 980 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 981 } else {
fe5720e2
KP		 982 sg_link_tbl_len = cryptlen;
983
962a9c99 984 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 985 sg_link_tbl_len = cryptlen + authsize;
e938e465 986
fe5720e2 987 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 988 &edesc->link_tbl[0]);
989 if (sg_count > 1) {
990 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 991 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 992 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
993 edesc->dma_len,
994 DMA_BIDIRECTIONAL);
70bcaca7
LN		 995 } else {
996 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 997 to_talitos_ptr(&desc->ptr[4],
998 sg_dma_address(areq->src));
70bcaca7 999 }
9c4a7965
KP		 1000 }
1001
1002 /* cipher out */
1003 desc->ptr[5].len = cpu_to_be16(cryptlen);
1004 desc->ptr[5].j_extent = authsize;
1005
e938e465 1006 if (areq->src != areq->dst)
4de9d0b5
LN		 1007 sg_count = talitos_map_sg(dev, areq->dst,
1008 edesc->dst_nents ? : 1,
1009 DMA_FROM_DEVICE,
1010 edesc->dst_is_chained);
9c4a7965
KP		 1011
1012 if (sg_count == 1) {
81eb024c 1013 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1014 } else {
1015 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1016 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1017
81eb024c
KP		 1018 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1019 (edesc->src_nents + 1) *
1020 sizeof(struct talitos_ptr));
fe5720e2
KP		 1021 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1022 link_tbl_ptr);
1023
f3c85bc1 1024 /* Add an entry to the link table for ICV data */
9c4a7965 1025 link_tbl_ptr += sg_count - 1;
9c4a7965 1026 link_tbl_ptr->j_extent = 0;
f3c85bc1 1027 sg_count++;
9c4a7965
KP		 1028 link_tbl_ptr++;
1029 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1030 link_tbl_ptr->len = cpu_to_be16(authsize);
1031
1032 /* icv data follows link tables */
81eb024c
KP		 1033 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1034 (edesc->src_nents + edesc->dst_nents + 2) *
1035 sizeof(struct talitos_ptr));
9c4a7965
KP		 1036 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1037 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1038 edesc->dma_len, DMA_BIDIRECTIONAL);
1039 }
1040
1041 /* iv out */
1042 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1043 DMA_FROM_DEVICE);
1044
5228f0f7 1045 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1046 if (ret != -EINPROGRESS) {
1047 ipsec_esp_unmap(dev, edesc, areq);
1048 kfree(edesc);
1049 }
1050 return ret;
9c4a7965
KP		 1051}
1052
9c4a7965
KP		 1053/*
1054 * derive number of elements in scatterlist
1055 */
4de9d0b5 1056static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1057{
1058 struct scatterlist *sg = sg_list;
1059 int sg_nents = 0;
1060
4de9d0b5
LN		 1061 *chained = 0;
1062 while (nbytes > 0) {
9c4a7965
KP		 1063 sg_nents++;
1064 nbytes -= sg->length;
4de9d0b5
LN		 1065 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1066 *chained = 1;
1067 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1068 }
1069
1070 return sg_nents;
1071}
1072
497f2e6b
LN		 1073/**
1074 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1075 * @sgl: The SG list
1076 * @nents: Number of SG entries
1077 * @buf: Where to copy to
1078 * @buflen: The number of bytes to copy
1079 * @skip: The number of bytes to skip before copying.
1080 * Note: skip + buflen should equal SG total size.
1081 *
1082 * Returns the number of copied bytes.
1083 *
1084 **/
1085static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1086 void *buf, size_t buflen, unsigned int skip)
1087{
1088 unsigned int offset = 0;
1089 unsigned int boffset = 0;
1090 struct sg_mapping_iter miter;
1091 unsigned long flags;
1092 unsigned int sg_flags = SG_MITER_ATOMIC;
1093 size_t total_buffer = buflen + skip;
1094
1095 sg_flags |= SG_MITER_FROM_SG;
1096
1097 sg_miter_start(&miter, sgl, nents, sg_flags);
1098
1099 local_irq_save(flags);
1100
1101 while (sg_miter_next(&miter) && offset < total_buffer) {
1102 unsigned int len;
1103 unsigned int ignore;
1104
1105 if ((offset + miter.length) > skip) {
1106 if (offset < skip) {
1107 /* Copy part of this segment */
1108 ignore = skip - offset;
1109 len = miter.length - ignore;
7260042b
LN		 1110 if (boffset + len > buflen)
1111 len = buflen - boffset;
497f2e6b
LN		 1112 memcpy(buf + boffset, miter.addr + ignore, len);
1113 } else {
7260042b 1114 /* Copy all of this segment (up to buflen) */
497f2e6b 1115 len = miter.length;
7260042b
LN		 1116 if (boffset + len > buflen)
1117 len = buflen - boffset;
497f2e6b
LN		 1118 memcpy(buf + boffset, miter.addr, len);
1119 }
1120 boffset += len;
1121 }
1122 offset += miter.length;
1123 }
1124
1125 sg_miter_stop(&miter);
1126
1127 local_irq_restore(flags);
1128 return boffset;
1129}
1130
9c4a7965 1131/*
56af8cd4 1132 * allocate and map the extended descriptor
9c4a7965 1133 */
4de9d0b5
LN		 1134static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1135 struct scatterlist *src,
1136 struct scatterlist *dst,
497f2e6b 1137 int hash_result,
4de9d0b5
LN		 1138 unsigned int cryptlen,
1139 unsigned int authsize,
1140 int icv_stashing,
1141 u32 cryptoflags)
9c4a7965 1142{
56af8cd4 1143 struct talitos_edesc *edesc;
9c4a7965 1144 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1145 int src_chained, dst_chained = 0;
1146 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1147 GFP_ATOMIC;
9c4a7965 1148
4de9d0b5
LN		 1149 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1150 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1151 return ERR_PTR(-EINVAL);
1152 }
1153
4de9d0b5 1154 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1155 src_nents = (src_nents == 1) ? 0 : src_nents;
1156
497f2e6b
LN		 1157 if (hash_result) {
1158 dst_nents = 0;
9c4a7965 1159 } else {
497f2e6b
LN		 1160 if (dst == src) {
1161 dst_nents = src_nents;
1162 } else {
1163 dst_nents = sg_count(dst, cryptlen + authsize,
1164 &dst_chained);
1165 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1166 }
9c4a7965
KP		 1167 }
1168
1169 /*
1170 * allocate space for base edesc plus the link tables,
f3c85bc1 1171 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1172 * and the ICV data itself
1173 */
56af8cd4 1174 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1175 if (src_nents || dst_nents) {
f3c85bc1 1176 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1177 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1178 alloc_len += dma_len;
1179 } else {
1180 dma_len = 0;
4de9d0b5 1181 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1182 }
1183
586725f8 1184 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1185 if (!edesc) {
4de9d0b5 1186 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1187 return ERR_PTR(-ENOMEM);
1188 }
1189
1190 edesc->src_nents = src_nents;
1191 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1192 edesc->src_is_chained = src_chained;
1193 edesc->dst_is_chained = dst_chained;
9c4a7965 1194 edesc->dma_len = dma_len;
497f2e6b
LN		 1195 if (dma_len)
1196 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1197 edesc->dma_len,
1198 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1199
1200 return edesc;
1201}
1202
4de9d0b5
LN		 1203static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1204 int icv_stashing)
1205{
1206 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1207 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1208
497f2e6b 1209 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
4de9d0b5
LN		 1210 areq->cryptlen, ctx->authsize, icv_stashing,
1211 areq->base.flags);
1212}
1213
56af8cd4 1214static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1215{
1216 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1217 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1218 struct talitos_edesc *edesc;
9c4a7965
KP		 1219
1220 /* allocate extended descriptor */
4de9d0b5 1221 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1222 if (IS_ERR(edesc))
1223 return PTR_ERR(edesc);
1224
1225 /* set encrypt */
70bcaca7 1226 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1227
1228 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1229}
1230
56af8cd4 1231static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1232{
1233 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1234 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1235 unsigned int authsize = ctx->authsize;
fe5720e2 1236 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1237 struct talitos_edesc *edesc;
9c4a7965
KP		 1238 struct scatterlist *sg;
1239 void *icvdata;
1240
1241 req->cryptlen -= authsize;
1242
1243 /* allocate extended descriptor */
4de9d0b5 1244 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1245 if (IS_ERR(edesc))
1246 return PTR_ERR(edesc);
1247
fe5720e2 1248 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1249 ((!edesc->src_nents && !edesc->dst_nents) ||
1250 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1251
fe5720e2 1252 /* decrypt and check the ICV */
e938e465
KP		 1253 edesc->desc.hdr = ctx->desc_hdr_template |
1254 DESC_HDR_DIR_INBOUND |
fe5720e2 1255 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1256
fe5720e2
KP		 1257 /* reset integrity check result bits */
1258 edesc->desc.hdr_lo = 0;
9c4a7965 1259
e938e465
KP		 1260 return ipsec_esp(edesc, req, NULL, 0,
1261 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1262
e938e465 1263 }
fe5720e2 1264
e938e465
KP		 1265 /* Have to check the ICV with software */
1266 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1267
e938e465
KP		 1268 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1269 if (edesc->dma_len)
1270 icvdata = &edesc->link_tbl[edesc->src_nents +
1271 edesc->dst_nents + 2];
1272 else
1273 icvdata = &edesc->link_tbl[0];
fe5720e2 1274
e938e465 1275 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1276
e938e465
KP		 1277 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1278 ctx->authsize);
fe5720e2 1279
e938e465 1280 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1281}
1282
56af8cd4 1283static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1284{
1285 struct aead_request *areq = &req->areq;
1286 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1287 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1288 struct talitos_edesc *edesc;
9c4a7965
KP		 1289
1290 /* allocate extended descriptor */
4de9d0b5 1291 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1292 if (IS_ERR(edesc))
1293 return PTR_ERR(edesc);
1294
1295 /* set encrypt */
70bcaca7 1296 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1297
1298 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1299 /* avoid consecutive packets going out with same IV */
1300 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1301
1302 return ipsec_esp(edesc, areq, req->giv, req->seq,
1303 ipsec_esp_encrypt_done);
1304}
1305
4de9d0b5
LN		 1306static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1307 const u8 *key, unsigned int keylen)
1308{
1309 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
4de9d0b5
LN		 1310
1311 memcpy(&ctx->key, key, keylen);
1312 ctx->keylen = keylen;
1313
1314 return 0;
4de9d0b5
LN		 1315}
1316
1317static void common_nonsnoop_unmap(struct device *dev,
1318 struct talitos_edesc *edesc,
1319 struct ablkcipher_request *areq)
1320{
1321 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1322 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1323 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1324
1325 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1326
1327 if (edesc->dma_len)
1328 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1329 DMA_BIDIRECTIONAL);
1330}
1331
1332static void ablkcipher_done(struct device *dev,
1333 struct talitos_desc *desc, void *context,
1334 int err)
1335{
1336 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1337 struct talitos_edesc *edesc;
1338
1339 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1340
1341 common_nonsnoop_unmap(dev, edesc, areq);
1342
1343 kfree(edesc);
1344
1345 areq->base.complete(&areq->base, err);
1346}
1347
1348static int common_nonsnoop(struct talitos_edesc *edesc,
1349 struct ablkcipher_request *areq,
4de9d0b5
LN		 1350 void (*callback) (struct device *dev,
1351 struct talitos_desc *desc,
1352 void *context, int error))
1353{
1354 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1355 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1356 struct device *dev = ctx->dev;
1357 struct talitos_desc *desc = &edesc->desc;
1358 unsigned int cryptlen = areq->nbytes;
1359 unsigned int ivsize;
1360 int sg_count, ret;
1361
1362 /* first DWORD empty */
1363 desc->ptr[0].len = 0;
81eb024c 1364 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1365 desc->ptr[0].j_extent = 0;
1366
1367 /* cipher iv */
1368 ivsize = crypto_ablkcipher_ivsize(cipher);
febec542 1369 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0,
4de9d0b5
LN		 1370 DMA_TO_DEVICE);
1371
1372 /* cipher key */
1373 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1374 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1375
1376 /*
1377 * cipher in
1378 */
1379 desc->ptr[3].len = cpu_to_be16(cryptlen);
1380 desc->ptr[3].j_extent = 0;
1381
1382 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1383 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1384 : DMA_TO_DEVICE,
1385 edesc->src_is_chained);
1386
1387 if (sg_count == 1) {
81eb024c 1388 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1389 } else {
1390 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1391 &edesc->link_tbl[0]);
1392 if (sg_count > 1) {
81eb024c 1393 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1394 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1395 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1396 edesc->dma_len,
1397 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1398 } else {
1399 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1400 to_talitos_ptr(&desc->ptr[3],
1401 sg_dma_address(areq->src));
4de9d0b5
LN		 1402 }
1403 }
1404
1405 /* cipher out */
1406 desc->ptr[4].len = cpu_to_be16(cryptlen);
1407 desc->ptr[4].j_extent = 0;
1408
1409 if (areq->src != areq->dst)
1410 sg_count = talitos_map_sg(dev, areq->dst,
1411 edesc->dst_nents ? : 1,
1412 DMA_FROM_DEVICE,
1413 edesc->dst_is_chained);
1414
1415 if (sg_count == 1) {
81eb024c 1416 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1417 } else {
1418 struct talitos_ptr *link_tbl_ptr =
1419 &edesc->link_tbl[edesc->src_nents + 1];
1420
81eb024c
KP		 1421 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1422 (edesc->src_nents + 1) *
1423 sizeof(struct talitos_ptr));
4de9d0b5 1424 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1425 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1426 link_tbl_ptr);
1427 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1428 edesc->dma_len, DMA_BIDIRECTIONAL);
1429 }
1430
1431 /* iv out */
1432 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1433 DMA_FROM_DEVICE);
1434
1435 /* last DWORD empty */
1436 desc->ptr[6].len = 0;
81eb024c 1437 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1438 desc->ptr[6].j_extent = 0;
1439
5228f0f7 1440 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1441 if (ret != -EINPROGRESS) {
1442 common_nonsnoop_unmap(dev, edesc, areq);
1443 kfree(edesc);
1444 }
1445 return ret;
1446}
1447
e938e465
KP		 1448static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1449 areq)
4de9d0b5
LN		 1450{
1451 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1452 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1453
497f2e6b
LN		 1454 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1455 areq->nbytes, 0, 0, areq->base.flags);
4de9d0b5
LN		 1456}
1457
1458static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1459{
1460 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1461 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1462 struct talitos_edesc *edesc;
1463
1464 /* allocate extended descriptor */
1465 edesc = ablkcipher_edesc_alloc(areq);
1466 if (IS_ERR(edesc))
1467 return PTR_ERR(edesc);
1468
1469 /* set encrypt */
1470 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1471
febec542 1472 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1473}
1474
1475static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1476{
1477 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1478 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1479 struct talitos_edesc *edesc;
1480
1481 /* allocate extended descriptor */
1482 edesc = ablkcipher_edesc_alloc(areq);
1483 if (IS_ERR(edesc))
1484 return PTR_ERR(edesc);
1485
1486 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1487
febec542 1488 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1489}
1490
497f2e6b
LN		 1491static void common_nonsnoop_hash_unmap(struct device *dev,
1492 struct talitos_edesc *edesc,
1493 struct ahash_request *areq)
1494{
1495 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1496
1497 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1498
1499 /* When using hashctx-in, must unmap it. */
1500 if (edesc->desc.ptr[1].len)
1501 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1502 DMA_TO_DEVICE);
1503
1504 if (edesc->desc.ptr[2].len)
1505 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1506 DMA_TO_DEVICE);
1507
1508 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1509
1510 if (edesc->dma_len)
1511 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1512 DMA_BIDIRECTIONAL);
1513
1514}
1515
1516static void ahash_done(struct device *dev,
1517 struct talitos_desc *desc, void *context,
1518 int err)
1519{
1520 struct ahash_request *areq = context;
1521 struct talitos_edesc *edesc =
1522 container_of(desc, struct talitos_edesc, desc);
1523 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1524
1525 if (!req_ctx->last && req_ctx->to_hash_later) {
1526 /* Position any partial block for next update/final/finup */
1527 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1528 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1529 }
1530 common_nonsnoop_hash_unmap(dev, edesc, areq);
1531
1532 kfree(edesc);
1533
1534 areq->base.complete(&areq->base, err);
1535}
1536
1537static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1538 struct ahash_request *areq, unsigned int length,
1539 void (*callback) (struct device *dev,
1540 struct talitos_desc *desc,
1541 void *context, int error))
1542{
1543 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1544 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1545 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1546 struct device *dev = ctx->dev;
1547 struct talitos_desc *desc = &edesc->desc;
1548 int sg_count, ret;
1549
1550 /* first DWORD empty */
1551 desc->ptr[0] = zero_entry;
1552
60f208d7
KP		 1553 /* hash context in */
1554 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1555 map_single_talitos_ptr(dev, &desc->ptr[1],
1556 req_ctx->hw_context_size,
1557 (char *)req_ctx->hw_context, 0,
1558 DMA_TO_DEVICE);
60f208d7 1559 req_ctx->swinit = 0;
497f2e6b
LN		 1560 } else {
1561 desc->ptr[1] = zero_entry;
1562 /* Indicate next op is not the first. */
1563 req_ctx->first = 0;
1564 }
1565
1566 /* HMAC key */
1567 if (ctx->keylen)
1568 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1569 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1570 else
1571 desc->ptr[2] = zero_entry;
1572
1573 /*
1574 * data in
1575 */
1576 desc->ptr[3].len = cpu_to_be16(length);
1577 desc->ptr[3].j_extent = 0;
1578
1579 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1580 edesc->src_nents ? : 1,
1581 DMA_TO_DEVICE,
1582 edesc->src_is_chained);
1583
1584 if (sg_count == 1) {
1585 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1586 } else {
1587 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1588 &edesc->link_tbl[0]);
1589 if (sg_count > 1) {
1590 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1591 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1592 dma_sync_single_for_device(ctx->dev,
1593 edesc->dma_link_tbl,
1594 edesc->dma_len,
1595 DMA_BIDIRECTIONAL);
1596 } else {
1597 /* Only one segment now, so no link tbl needed */
1598 to_talitos_ptr(&desc->ptr[3],
1599 sg_dma_address(req_ctx->psrc));
1600 }
1601 }
1602
1603 /* fifth DWORD empty */
1604 desc->ptr[4] = zero_entry;
1605
1606 /* hash/HMAC out -or- hash context out */
1607 if (req_ctx->last)
1608 map_single_talitos_ptr(dev, &desc->ptr[5],
1609 crypto_ahash_digestsize(tfm),
1610 areq->result, 0, DMA_FROM_DEVICE);
1611 else
1612 map_single_talitos_ptr(dev, &desc->ptr[5],
1613 req_ctx->hw_context_size,
1614 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1615
1616 /* last DWORD empty */
1617 desc->ptr[6] = zero_entry;
1618
5228f0f7 1619 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1620 if (ret != -EINPROGRESS) {
1621 common_nonsnoop_hash_unmap(dev, edesc, areq);
1622 kfree(edesc);
1623 }
1624 return ret;
1625}
1626
1627static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1628 unsigned int nbytes)
1629{
1630 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1631 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1632 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1633
1634 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1635 nbytes, 0, 0, areq->base.flags);
1636}
1637
1638static int ahash_init(struct ahash_request *areq)
1639{
1640 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1641 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1642
1643 /* Initialize the context */
5e833bc4 1644 req_ctx->nbuf = 0;
60f208d7
KP		 1645 req_ctx->first = 1; /* first indicates h/w must init its context */
1646 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1647 req_ctx->hw_context_size =
1648 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1649 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1650 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1651
1652 return 0;
1653}
1654
60f208d7
KP		 1655/*
1656 * on h/w without explicit sha224 support, we initialize h/w context
1657 * manually with sha224 constants, and tell it to run sha256.
1658 */
1659static int ahash_init_sha224_swinit(struct ahash_request *areq)
1660{
1661 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1662
1663 ahash_init(areq);
1664 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1665
a752447a
KP		 1666 req_ctx->hw_context[0] = SHA224_H0;
1667 req_ctx->hw_context[1] = SHA224_H1;
1668 req_ctx->hw_context[2] = SHA224_H2;
1669 req_ctx->hw_context[3] = SHA224_H3;
1670 req_ctx->hw_context[4] = SHA224_H4;
1671 req_ctx->hw_context[5] = SHA224_H5;
1672 req_ctx->hw_context[6] = SHA224_H6;
1673 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1674
1675 /* init 64-bit count */
1676 req_ctx->hw_context[8] = 0;
1677 req_ctx->hw_context[9] = 0;
1678
1679 return 0;
1680}
1681
497f2e6b
LN		 1682static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1683{
1684 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1685 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1686 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1687 struct talitos_edesc *edesc;
1688 unsigned int blocksize =
1689 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1690 unsigned int nbytes_to_hash;
1691 unsigned int to_hash_later;
5e833bc4 1692 unsigned int nsg;
497f2e6b
LN		 1693 int chained;
1694
5e833bc4
LN		 1695 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1696 /* Buffer up to one whole block */
497f2e6b
LN		 1697 sg_copy_to_buffer(areq->src,
1698 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1699 req_ctx->buf + req_ctx->nbuf, nbytes);
1700 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1701 return 0;
1702 }
1703
5e833bc4
LN		 1704 /* At least (blocksize + 1) bytes are available to hash */
1705 nbytes_to_hash = nbytes + req_ctx->nbuf;
1706 to_hash_later = nbytes_to_hash & (blocksize - 1);
1707
1708 if (req_ctx->last)
1709 to_hash_later = 0;
1710 else if (to_hash_later)
1711 /* There is a partial block. Hash the full block(s) now */
1712 nbytes_to_hash -= to_hash_later;
1713 else {
1714 /* Keep one block buffered */
1715 nbytes_to_hash -= blocksize;
1716 to_hash_later = blocksize;
1717 }
1718
1719 /* Chain in any previously buffered data */
1720 if (req_ctx->nbuf) {
1721 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1722 sg_init_table(req_ctx->bufsl, nsg);
1723 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1724 if (nsg > 1)
1725 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1726 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1727 } else
497f2e6b 1728 req_ctx->psrc = areq->src;
5e833bc4
LN		 1729
1730 if (to_hash_later) {
1731 int nents = sg_count(areq->src, nbytes, &chained);
1732 sg_copy_end_to_buffer(areq->src, nents,
1733 req_ctx->bufnext,
1734 to_hash_later,
1735 nbytes - to_hash_later);
497f2e6b 1736 }
5e833bc4 1737 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1738
5e833bc4 1739 /* Allocate extended descriptor */
497f2e6b
LN		 1740 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1741 if (IS_ERR(edesc))
1742 return PTR_ERR(edesc);
1743
1744 edesc->desc.hdr = ctx->desc_hdr_template;
1745
1746 /* On last one, request SEC to pad; otherwise continue */
1747 if (req_ctx->last)
1748 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1749 else
1750 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1751
60f208d7
KP		 1752 /* request SEC to INIT hash. */
1753 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1754 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1755
1756 /* When the tfm context has a keylen, it's an HMAC.
1757 * A first or last (ie. not middle) descriptor must request HMAC.
1758 */
1759 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1760 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1761
1762 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1763 ahash_done);
1764}
1765
1766static int ahash_update(struct ahash_request *areq)
1767{
1768 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1769
1770 req_ctx->last = 0;
1771
1772 return ahash_process_req(areq, areq->nbytes);
1773}
1774
1775static int ahash_final(struct ahash_request *areq)
1776{
1777 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1778
1779 req_ctx->last = 1;
1780
1781 return ahash_process_req(areq, 0);
1782}
1783
1784static int ahash_finup(struct ahash_request *areq)
1785{
1786 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1787
1788 req_ctx->last = 1;
1789
1790 return ahash_process_req(areq, areq->nbytes);
1791}
1792
1793static int ahash_digest(struct ahash_request *areq)
1794{
1795 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1796 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1797
60f208d7 1798 ahash->init(areq);
497f2e6b
LN		 1799 req_ctx->last = 1;
1800
1801 return ahash_process_req(areq, areq->nbytes);
1802}
1803
79b3a418
LN		 1804struct keyhash_result {
1805 struct completion completion;
1806 int err;
1807};
1808
1809static void keyhash_complete(struct crypto_async_request *req, int err)
1810{
1811 struct keyhash_result *res = req->data;
1812
1813 if (err == -EINPROGRESS)
1814 return;
1815
1816 res->err = err;
1817 complete(&res->completion);
1818}
1819
1820static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1821 u8 *hash)
1822{
1823 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1824
1825 struct scatterlist sg[1];
1826 struct ahash_request *req;
1827 struct keyhash_result hresult;
1828 int ret;
1829
1830 init_completion(&hresult.completion);
1831
1832 req = ahash_request_alloc(tfm, GFP_KERNEL);
1833 if (!req)
1834 return -ENOMEM;
1835
1836 /* Keep tfm keylen == 0 during hash of the long key */
1837 ctx->keylen = 0;
1838 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1839 keyhash_complete, &hresult);
1840
1841 sg_init_one(&sg[0], key, keylen);
1842
1843 ahash_request_set_crypt(req, sg, hash, keylen);
1844 ret = crypto_ahash_digest(req);
1845 switch (ret) {
1846 case 0:
1847 break;
1848 case -EINPROGRESS:
1849 case -EBUSY:
1850 ret = wait_for_completion_interruptible(
1851 &hresult.completion);
1852 if (!ret)
1853 ret = hresult.err;
1854 break;
1855 default:
1856 break;
1857 }
1858 ahash_request_free(req);
1859
1860 return ret;
1861}
1862
1863static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1864 unsigned int keylen)
1865{
1866 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1867 unsigned int blocksize =
1868 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1869 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1870 unsigned int keysize = keylen;
1871 u8 hash[SHA512_DIGEST_SIZE];
1872 int ret;
1873
1874 if (keylen <= blocksize)
1875 memcpy(ctx->key, key, keysize);
1876 else {
1877 /* Must get the hash of the long key */
1878 ret = keyhash(tfm, key, keylen, hash);
1879
1880 if (ret) {
1881 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1882 return -EINVAL;
1883 }
1884
1885 keysize = digestsize;
1886 memcpy(ctx->key, hash, digestsize);
1887 }
1888
1889 ctx->keylen = keysize;
1890
1891 return 0;
1892}
1893
1894
9c4a7965 1895struct talitos_alg_template {
d5e4aaef
LN		 1896 u32 type;
1897 union {
1898 struct crypto_alg crypto;
acbf7c62 1899 struct ahash_alg hash;
d5e4aaef 1900 } alg;
9c4a7965
KP		 1901 __be32 desc_hdr_template;
1902};
1903
1904static struct talitos_alg_template driver_algs[] = {
56af8cd4 1905 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1906 { .type = CRYPTO_ALG_TYPE_AEAD,
1907 .alg.crypto = {
56af8cd4
LN		 1908 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1909 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1910 .cra_blocksize = AES_BLOCK_SIZE,
1911 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 1912 .cra_aead = {
1913 .setkey = aead_setkey,
1914 .setauthsize = aead_setauthsize,
1915 .encrypt = aead_encrypt,
1916 .decrypt = aead_decrypt,
1917 .givencrypt = aead_givencrypt,
1918 .geniv = "<built-in>",
1919 .ivsize = AES_BLOCK_SIZE,
1920 .maxauthsize = SHA1_DIGEST_SIZE,
1921 }
1922 },
9c4a7965
KP		 1923 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1924 DESC_HDR_SEL0_AESU |
1925 DESC_HDR_MODE0_AESU_CBC |
1926 DESC_HDR_SEL1_MDEUA |
1927 DESC_HDR_MODE1_MDEU_INIT |
1928 DESC_HDR_MODE1_MDEU_PAD |
1929 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1930 },
d5e4aaef
LN		 1931 { .type = CRYPTO_ALG_TYPE_AEAD,
1932 .alg.crypto = {
56af8cd4
LN		 1933 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1934 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1935 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1936 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 1937 .cra_aead = {
1938 .setkey = aead_setkey,
1939 .setauthsize = aead_setauthsize,
1940 .encrypt = aead_encrypt,
1941 .decrypt = aead_decrypt,
1942 .givencrypt = aead_givencrypt,
1943 .geniv = "<built-in>",
1944 .ivsize = DES3_EDE_BLOCK_SIZE,
1945 .maxauthsize = SHA1_DIGEST_SIZE,
1946 }
1947 },
70bcaca7
LN		 1948 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1949 DESC_HDR_SEL0_DEU |
1950 DESC_HDR_MODE0_DEU_CBC |
1951 DESC_HDR_MODE0_DEU_3DES |
1952 DESC_HDR_SEL1_MDEUA |
1953 DESC_HDR_MODE1_MDEU_INIT |
1954 DESC_HDR_MODE1_MDEU_PAD |
1955 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1956 },
357fb605
HG		 1957 { .type = CRYPTO_ALG_TYPE_AEAD,
1958 .alg.crypto = {
1959 .cra_name = "authenc(hmac(sha224),cbc(aes))",
1960 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1961 .cra_blocksize = AES_BLOCK_SIZE,
1962 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 1963 .cra_aead = {
1964 .setkey = aead_setkey,
1965 .setauthsize = aead_setauthsize,
1966 .encrypt = aead_encrypt,
1967 .decrypt = aead_decrypt,
1968 .givencrypt = aead_givencrypt,
1969 .geniv = "<built-in>",
1970 .ivsize = AES_BLOCK_SIZE,
1971 .maxauthsize = SHA224_DIGEST_SIZE,
1972 }
1973 },
1974 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1975 DESC_HDR_SEL0_AESU |
1976 DESC_HDR_MODE0_AESU_CBC |
1977 DESC_HDR_SEL1_MDEUA |
1978 DESC_HDR_MODE1_MDEU_INIT |
1979 DESC_HDR_MODE1_MDEU_PAD |
1980 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1981 },
1982 { .type = CRYPTO_ALG_TYPE_AEAD,
1983 .alg.crypto = {
1984 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1985 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1986 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1987 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 1988 .cra_aead = {
1989 .setkey = aead_setkey,
1990 .setauthsize = aead_setauthsize,
1991 .encrypt = aead_encrypt,
1992 .decrypt = aead_decrypt,
1993 .givencrypt = aead_givencrypt,
1994 .geniv = "<built-in>",
1995 .ivsize = DES3_EDE_BLOCK_SIZE,
1996 .maxauthsize = SHA224_DIGEST_SIZE,
1997 }
1998 },
1999 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2000 DESC_HDR_SEL0_DEU |
2001 DESC_HDR_MODE0_DEU_CBC |
2002 DESC_HDR_MODE0_DEU_3DES |
2003 DESC_HDR_SEL1_MDEUA |
2004 DESC_HDR_MODE1_MDEU_INIT |
2005 DESC_HDR_MODE1_MDEU_PAD |
2006 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2007 },
d5e4aaef
LN		 2008 { .type = CRYPTO_ALG_TYPE_AEAD,
2009 .alg.crypto = {
56af8cd4
LN		 2010 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2011 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2012 .cra_blocksize = AES_BLOCK_SIZE,
2013 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 2014 .cra_aead = {
2015 .setkey = aead_setkey,
2016 .setauthsize = aead_setauthsize,
2017 .encrypt = aead_encrypt,
2018 .decrypt = aead_decrypt,
2019 .givencrypt = aead_givencrypt,
2020 .geniv = "<built-in>",
2021 .ivsize = AES_BLOCK_SIZE,
2022 .maxauthsize = SHA256_DIGEST_SIZE,
2023 }
2024 },
3952f17e
LN		 2025 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2026 DESC_HDR_SEL0_AESU |
2027 DESC_HDR_MODE0_AESU_CBC |
2028 DESC_HDR_SEL1_MDEUA |
2029 DESC_HDR_MODE1_MDEU_INIT |
2030 DESC_HDR_MODE1_MDEU_PAD |
2031 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2032 },
d5e4aaef
LN		 2033 { .type = CRYPTO_ALG_TYPE_AEAD,
2034 .alg.crypto = {
56af8cd4
LN		 2035 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2036 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2037 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2038 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 2039 .cra_aead = {
2040 .setkey = aead_setkey,
2041 .setauthsize = aead_setauthsize,
2042 .encrypt = aead_encrypt,
2043 .decrypt = aead_decrypt,
2044 .givencrypt = aead_givencrypt,
2045 .geniv = "<built-in>",
2046 .ivsize = DES3_EDE_BLOCK_SIZE,
2047 .maxauthsize = SHA256_DIGEST_SIZE,
2048 }
2049 },
3952f17e
LN		 2050 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2051 DESC_HDR_SEL0_DEU |
2052 DESC_HDR_MODE0_DEU_CBC |
2053 DESC_HDR_MODE0_DEU_3DES |
2054 DESC_HDR_SEL1_MDEUA |
2055 DESC_HDR_MODE1_MDEU_INIT |
2056 DESC_HDR_MODE1_MDEU_PAD |
2057 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2058 },
d5e4aaef 2059 { .type = CRYPTO_ALG_TYPE_AEAD,
357fb605
HG		 2060 .alg.crypto = {
2061 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2062 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2063 .cra_blocksize = AES_BLOCK_SIZE,
2064 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 2065 .cra_aead = {
2066 .setkey = aead_setkey,
2067 .setauthsize = aead_setauthsize,
2068 .encrypt = aead_encrypt,
2069 .decrypt = aead_decrypt,
2070 .givencrypt = aead_givencrypt,
2071 .geniv = "<built-in>",
2072 .ivsize = AES_BLOCK_SIZE,
2073 .maxauthsize = SHA384_DIGEST_SIZE,
2074 }
2075 },
2076 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2077 DESC_HDR_SEL0_AESU |
2078 DESC_HDR_MODE0_AESU_CBC |
2079 DESC_HDR_SEL1_MDEUB |
2080 DESC_HDR_MODE1_MDEU_INIT |
2081 DESC_HDR_MODE1_MDEU_PAD |
2082 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2083 },
2084 { .type = CRYPTO_ALG_TYPE_AEAD,
2085 .alg.crypto = {
2086 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2087 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2088 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2089 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 2090 .cra_aead = {
2091 .setkey = aead_setkey,
2092 .setauthsize = aead_setauthsize,
2093 .encrypt = aead_encrypt,
2094 .decrypt = aead_decrypt,
2095 .givencrypt = aead_givencrypt,
2096 .geniv = "<built-in>",
2097 .ivsize = DES3_EDE_BLOCK_SIZE,
2098 .maxauthsize = SHA384_DIGEST_SIZE,
2099 }
2100 },
2101 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2102 DESC_HDR_SEL0_DEU |
2103 DESC_HDR_MODE0_DEU_CBC |
2104 DESC_HDR_MODE0_DEU_3DES |
2105 DESC_HDR_SEL1_MDEUB |
2106 DESC_HDR_MODE1_MDEU_INIT |
2107 DESC_HDR_MODE1_MDEU_PAD |
2108 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2109 },
2110 { .type = CRYPTO_ALG_TYPE_AEAD,
2111 .alg.crypto = {
2112 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2113 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2114 .cra_blocksize = AES_BLOCK_SIZE,
2115 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 2116 .cra_aead = {
2117 .setkey = aead_setkey,
2118 .setauthsize = aead_setauthsize,
2119 .encrypt = aead_encrypt,
2120 .decrypt = aead_decrypt,
2121 .givencrypt = aead_givencrypt,
2122 .geniv = "<built-in>",
2123 .ivsize = AES_BLOCK_SIZE,
2124 .maxauthsize = SHA512_DIGEST_SIZE,
2125 }
2126 },
2127 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2128 DESC_HDR_SEL0_AESU |
2129 DESC_HDR_MODE0_AESU_CBC |
2130 DESC_HDR_SEL1_MDEUB |
2131 DESC_HDR_MODE1_MDEU_INIT |
2132 DESC_HDR_MODE1_MDEU_PAD |
2133 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2134 },
2135 { .type = CRYPTO_ALG_TYPE_AEAD,
2136 .alg.crypto = {
2137 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2138 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2139 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2140 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
357fb605
HG		 2141 .cra_aead = {
2142 .setkey = aead_setkey,
2143 .setauthsize = aead_setauthsize,
2144 .encrypt = aead_encrypt,
2145 .decrypt = aead_decrypt,
2146 .givencrypt = aead_givencrypt,
2147 .geniv = "<built-in>",
2148 .ivsize = DES3_EDE_BLOCK_SIZE,
2149 .maxauthsize = SHA512_DIGEST_SIZE,
2150 }
2151 },
2152 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2153 DESC_HDR_SEL0_DEU |
2154 DESC_HDR_MODE0_DEU_CBC |
2155 DESC_HDR_MODE0_DEU_3DES |
2156 DESC_HDR_SEL1_MDEUB |
2157 DESC_HDR_MODE1_MDEU_INIT |
2158 DESC_HDR_MODE1_MDEU_PAD |
2159 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2160 },
2161 { .type = CRYPTO_ALG_TYPE_AEAD,
d5e4aaef 2162 .alg.crypto = {
56af8cd4
LN		 2163 .cra_name = "authenc(hmac(md5),cbc(aes))",
2164 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2165 .cra_blocksize = AES_BLOCK_SIZE,
2166 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 2167 .cra_aead = {
2168 .setkey = aead_setkey,
2169 .setauthsize = aead_setauthsize,
2170 .encrypt = aead_encrypt,
2171 .decrypt = aead_decrypt,
2172 .givencrypt = aead_givencrypt,
2173 .geniv = "<built-in>",
2174 .ivsize = AES_BLOCK_SIZE,
2175 .maxauthsize = MD5_DIGEST_SIZE,
2176 }
2177 },
3952f17e
LN		 2178 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2179 DESC_HDR_SEL0_AESU |
2180 DESC_HDR_MODE0_AESU_CBC |
2181 DESC_HDR_SEL1_MDEUA |
2182 DESC_HDR_MODE1_MDEU_INIT |
2183 DESC_HDR_MODE1_MDEU_PAD |
2184 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2185 },
d5e4aaef
LN		 2186 { .type = CRYPTO_ALG_TYPE_AEAD,
2187 .alg.crypto = {
56af8cd4
LN		 2188 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2189 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2190 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2191 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
56af8cd4
LN		 2192 .cra_aead = {
2193 .setkey = aead_setkey,
2194 .setauthsize = aead_setauthsize,
2195 .encrypt = aead_encrypt,
2196 .decrypt = aead_decrypt,
2197 .givencrypt = aead_givencrypt,
2198 .geniv = "<built-in>",
2199 .ivsize = DES3_EDE_BLOCK_SIZE,
2200 .maxauthsize = MD5_DIGEST_SIZE,
2201 }
2202 },
3952f17e
LN		 2203 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2204 DESC_HDR_SEL0_DEU |
2205 DESC_HDR_MODE0_DEU_CBC |
2206 DESC_HDR_MODE0_DEU_3DES |
2207 DESC_HDR_SEL1_MDEUA |
2208 DESC_HDR_MODE1_MDEU_INIT |
2209 DESC_HDR_MODE1_MDEU_PAD |
2210 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2211 },
2212 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2213 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2214 .alg.crypto = {
4de9d0b5
LN		 2215 .cra_name = "cbc(aes)",
2216 .cra_driver_name = "cbc-aes-talitos",
2217 .cra_blocksize = AES_BLOCK_SIZE,
2218 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2219 CRYPTO_ALG_ASYNC,
4de9d0b5
LN		 2220 .cra_ablkcipher = {
2221 .setkey = ablkcipher_setkey,
2222 .encrypt = ablkcipher_encrypt,
2223 .decrypt = ablkcipher_decrypt,
2224 .geniv = "eseqiv",
2225 .min_keysize = AES_MIN_KEY_SIZE,
2226 .max_keysize = AES_MAX_KEY_SIZE,
2227 .ivsize = AES_BLOCK_SIZE,
2228 }
2229 },
2230 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2231 DESC_HDR_SEL0_AESU |
2232 DESC_HDR_MODE0_AESU_CBC,
2233 },
d5e4aaef
LN		 2234 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2235 .alg.crypto = {
4de9d0b5
LN		 2236 .cra_name = "cbc(des3_ede)",
2237 .cra_driver_name = "cbc-3des-talitos",
2238 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2239 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2240 CRYPTO_ALG_ASYNC,
4de9d0b5
LN		 2241 .cra_ablkcipher = {
2242 .setkey = ablkcipher_setkey,
2243 .encrypt = ablkcipher_encrypt,
2244 .decrypt = ablkcipher_decrypt,
2245 .geniv = "eseqiv",
2246 .min_keysize = DES3_EDE_KEY_SIZE,
2247 .max_keysize = DES3_EDE_KEY_SIZE,
2248 .ivsize = DES3_EDE_BLOCK_SIZE,
2249 }
2250 },
2251 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2252 DESC_HDR_SEL0_DEU |
2253 DESC_HDR_MODE0_DEU_CBC |
2254 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2255 },
2256 /* AHASH algorithms. */
2257 { .type = CRYPTO_ALG_TYPE_AHASH,
2258 .alg.hash = {
2259 .init = ahash_init,
2260 .update = ahash_update,
2261 .final = ahash_final,
2262 .finup = ahash_finup,
2263 .digest = ahash_digest,
2264 .halg.digestsize = MD5_DIGEST_SIZE,
2265 .halg.base = {
2266 .cra_name = "md5",
2267 .cra_driver_name = "md5-talitos",
2268 .cra_blocksize = MD5_BLOCK_SIZE,
2269 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2270 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2271 }
2272 },
2273 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2274 DESC_HDR_SEL0_MDEUA |
2275 DESC_HDR_MODE0_MDEU_MD5,
2276 },
2277 { .type = CRYPTO_ALG_TYPE_AHASH,
2278 .alg.hash = {
2279 .init = ahash_init,
2280 .update = ahash_update,
2281 .final = ahash_final,
2282 .finup = ahash_finup,
2283 .digest = ahash_digest,
2284 .halg.digestsize = SHA1_DIGEST_SIZE,
2285 .halg.base = {
2286 .cra_name = "sha1",
2287 .cra_driver_name = "sha1-talitos",
2288 .cra_blocksize = SHA1_BLOCK_SIZE,
2289 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2290 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2291 }
2292 },
2293 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2294 DESC_HDR_SEL0_MDEUA |
2295 DESC_HDR_MODE0_MDEU_SHA1,
2296 },
60f208d7
KP		 2297 { .type = CRYPTO_ALG_TYPE_AHASH,
2298 .alg.hash = {
2299 .init = ahash_init,
2300 .update = ahash_update,
2301 .final = ahash_final,
2302 .finup = ahash_finup,
2303 .digest = ahash_digest,
2304 .halg.digestsize = SHA224_DIGEST_SIZE,
2305 .halg.base = {
2306 .cra_name = "sha224",
2307 .cra_driver_name = "sha224-talitos",
2308 .cra_blocksize = SHA224_BLOCK_SIZE,
2309 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2310 CRYPTO_ALG_ASYNC,
60f208d7
KP		 2311 }
2312 },
2313 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2314 DESC_HDR_SEL0_MDEUA |
2315 DESC_HDR_MODE0_MDEU_SHA224,
2316 },
497f2e6b
LN		 2317 { .type = CRYPTO_ALG_TYPE_AHASH,
2318 .alg.hash = {
2319 .init = ahash_init,
2320 .update = ahash_update,
2321 .final = ahash_final,
2322 .finup = ahash_finup,
2323 .digest = ahash_digest,
2324 .halg.digestsize = SHA256_DIGEST_SIZE,
2325 .halg.base = {
2326 .cra_name = "sha256",
2327 .cra_driver_name = "sha256-talitos",
2328 .cra_blocksize = SHA256_BLOCK_SIZE,
2329 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2330 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2331 }
2332 },
2333 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2334 DESC_HDR_SEL0_MDEUA |
2335 DESC_HDR_MODE0_MDEU_SHA256,
2336 },
2337 { .type = CRYPTO_ALG_TYPE_AHASH,
2338 .alg.hash = {
2339 .init = ahash_init,
2340 .update = ahash_update,
2341 .final = ahash_final,
2342 .finup = ahash_finup,
2343 .digest = ahash_digest,
2344 .halg.digestsize = SHA384_DIGEST_SIZE,
2345 .halg.base = {
2346 .cra_name = "sha384",
2347 .cra_driver_name = "sha384-talitos",
2348 .cra_blocksize = SHA384_BLOCK_SIZE,
2349 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2350 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2351 }
2352 },
2353 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2354 DESC_HDR_SEL0_MDEUB |
2355 DESC_HDR_MODE0_MDEUB_SHA384,
2356 },
2357 { .type = CRYPTO_ALG_TYPE_AHASH,
2358 .alg.hash = {
2359 .init = ahash_init,
2360 .update = ahash_update,
2361 .final = ahash_final,
2362 .finup = ahash_finup,
2363 .digest = ahash_digest,
2364 .halg.digestsize = SHA512_DIGEST_SIZE,
2365 .halg.base = {
2366 .cra_name = "sha512",
2367 .cra_driver_name = "sha512-talitos",
2368 .cra_blocksize = SHA512_BLOCK_SIZE,
2369 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2370 CRYPTO_ALG_ASYNC,
497f2e6b
LN		 2371 }
2372 },
2373 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2374 DESC_HDR_SEL0_MDEUB |
2375 DESC_HDR_MODE0_MDEUB_SHA512,
2376 },
79b3a418
LN		 2377 { .type = CRYPTO_ALG_TYPE_AHASH,
2378 .alg.hash = {
2379 .init = ahash_init,
2380 .update = ahash_update,
2381 .final = ahash_final,
2382 .finup = ahash_finup,
2383 .digest = ahash_digest,
2384 .setkey = ahash_setkey,
2385 .halg.digestsize = MD5_DIGEST_SIZE,
2386 .halg.base = {
2387 .cra_name = "hmac(md5)",
2388 .cra_driver_name = "hmac-md5-talitos",
2389 .cra_blocksize = MD5_BLOCK_SIZE,
2390 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2391 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2392 }
2393 },
2394 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2395 DESC_HDR_SEL0_MDEUA |
2396 DESC_HDR_MODE0_MDEU_MD5,
2397 },
2398 { .type = CRYPTO_ALG_TYPE_AHASH,
2399 .alg.hash = {
2400 .init = ahash_init,
2401 .update = ahash_update,
2402 .final = ahash_final,
2403 .finup = ahash_finup,
2404 .digest = ahash_digest,
2405 .setkey = ahash_setkey,
2406 .halg.digestsize = SHA1_DIGEST_SIZE,
2407 .halg.base = {
2408 .cra_name = "hmac(sha1)",
2409 .cra_driver_name = "hmac-sha1-talitos",
2410 .cra_blocksize = SHA1_BLOCK_SIZE,
2411 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2412 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2413 }
2414 },
2415 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2416 DESC_HDR_SEL0_MDEUA |
2417 DESC_HDR_MODE0_MDEU_SHA1,
2418 },
2419 { .type = CRYPTO_ALG_TYPE_AHASH,
2420 .alg.hash = {
2421 .init = ahash_init,
2422 .update = ahash_update,
2423 .final = ahash_final,
2424 .finup = ahash_finup,
2425 .digest = ahash_digest,
2426 .setkey = ahash_setkey,
2427 .halg.digestsize = SHA224_DIGEST_SIZE,
2428 .halg.base = {
2429 .cra_name = "hmac(sha224)",
2430 .cra_driver_name = "hmac-sha224-talitos",
2431 .cra_blocksize = SHA224_BLOCK_SIZE,
2432 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2433 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2434 }
2435 },
2436 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2437 DESC_HDR_SEL0_MDEUA |
2438 DESC_HDR_MODE0_MDEU_SHA224,
2439 },
2440 { .type = CRYPTO_ALG_TYPE_AHASH,
2441 .alg.hash = {
2442 .init = ahash_init,
2443 .update = ahash_update,
2444 .final = ahash_final,
2445 .finup = ahash_finup,
2446 .digest = ahash_digest,
2447 .setkey = ahash_setkey,
2448 .halg.digestsize = SHA256_DIGEST_SIZE,
2449 .halg.base = {
2450 .cra_name = "hmac(sha256)",
2451 .cra_driver_name = "hmac-sha256-talitos",
2452 .cra_blocksize = SHA256_BLOCK_SIZE,
2453 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2454 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2455 }
2456 },
2457 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2458 DESC_HDR_SEL0_MDEUA |
2459 DESC_HDR_MODE0_MDEU_SHA256,
2460 },
2461 { .type = CRYPTO_ALG_TYPE_AHASH,
2462 .alg.hash = {
2463 .init = ahash_init,
2464 .update = ahash_update,
2465 .final = ahash_final,
2466 .finup = ahash_finup,
2467 .digest = ahash_digest,
2468 .setkey = ahash_setkey,
2469 .halg.digestsize = SHA384_DIGEST_SIZE,
2470 .halg.base = {
2471 .cra_name = "hmac(sha384)",
2472 .cra_driver_name = "hmac-sha384-talitos",
2473 .cra_blocksize = SHA384_BLOCK_SIZE,
2474 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2475 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2476 }
2477 },
2478 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2479 DESC_HDR_SEL0_MDEUB |
2480 DESC_HDR_MODE0_MDEUB_SHA384,
2481 },
2482 { .type = CRYPTO_ALG_TYPE_AHASH,
2483 .alg.hash = {
2484 .init = ahash_init,
2485 .update = ahash_update,
2486 .final = ahash_final,
2487 .finup = ahash_finup,
2488 .digest = ahash_digest,
2489 .setkey = ahash_setkey,
2490 .halg.digestsize = SHA512_DIGEST_SIZE,
2491 .halg.base = {
2492 .cra_name = "hmac(sha512)",
2493 .cra_driver_name = "hmac-sha512-talitos",
2494 .cra_blocksize = SHA512_BLOCK_SIZE,
2495 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2496 CRYPTO_ALG_ASYNC,
79b3a418
LN		 2497 }
2498 },
2499 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2500 DESC_HDR_SEL0_MDEUB |
2501 DESC_HDR_MODE0_MDEUB_SHA512,
2502 }
9c4a7965
KP		 2503};
2504
2505struct talitos_crypto_alg {
2506 struct list_head entry;
2507 struct device *dev;
acbf7c62 2508 struct talitos_alg_template algt;
9c4a7965
KP		 2509};
2510
2511static int talitos_cra_init(struct crypto_tfm *tfm)
2512{
2513 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2514 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2515 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2516 struct talitos_private *priv;
9c4a7965 2517
497f2e6b
LN		 2518 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2519 talitos_alg = container_of(__crypto_ahash_alg(alg),
2520 struct talitos_crypto_alg,
2521 algt.alg.hash);
2522 else
2523 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2524 algt.alg.crypto);
19bbbc63 2525
9c4a7965
KP		 2526 /* update context with ptr to dev */
2527 ctx->dev = talitos_alg->dev;
19bbbc63 2528
5228f0f7
KP		 2529 /* assign SEC channel to tfm in round-robin fashion */
2530 priv = dev_get_drvdata(ctx->dev);
2531 ctx->ch = atomic_inc_return(&priv->last_chan) &
2532 (priv->num_channels - 1);
2533
9c4a7965 2534 /* copy descriptor header template value */
acbf7c62 2535 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2536
602dba5a
KP		 2537 /* select done notification */
2538 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2539
497f2e6b
LN		 2540 return 0;
2541}
2542
2543static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2544{
2545 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2546
2547 talitos_cra_init(tfm);
9c4a7965
KP		 2548
2549 /* random first IV */
70bcaca7 2550 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2551
2552 return 0;
2553}
2554
497f2e6b
LN		 2555static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2556{
2557 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2558
2559 talitos_cra_init(tfm);
2560
2561 ctx->keylen = 0;
2562 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2563 sizeof(struct talitos_ahash_req_ctx));
2564
2565 return 0;
2566}
2567
9c4a7965
KP		 2568/*
2569 * given the alg's descriptor header template, determine whether descriptor
2570 * type and primary/secondary execution units required match the hw
2571 * capabilities description provided in the device tree node.
2572 */
2573static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2574{
2575 struct talitos_private *priv = dev_get_drvdata(dev);
2576 int ret;
2577
2578 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2579 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2580
2581 if (SECONDARY_EU(desc_hdr_template))
2582 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2583 & priv->exec_units);
2584
2585 return ret;
2586}
2587
2dc11581 2588static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2589{
2590 struct device *dev = &ofdev->dev;
2591 struct talitos_private *priv = dev_get_drvdata(dev);
2592 struct talitos_crypto_alg *t_alg, *n;
2593 int i;
2594
2595 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2596 switch (t_alg->algt.type) {
2597 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2598 case CRYPTO_ALG_TYPE_AEAD:
2599 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2600 break;
2601 case CRYPTO_ALG_TYPE_AHASH:
2602 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2603 break;
2604 }
9c4a7965
KP		 2605 list_del(&t_alg->entry);
2606 kfree(t_alg);
2607 }
2608
2609 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2610 talitos_unregister_rng(dev);
2611
4b992628 2612 for (i = 0; i < priv->num_channels; i++)
0b798247 2613 kfree(priv->chan[i].fifo);
9c4a7965 2614
4b992628 2615 kfree(priv->chan);
9c4a7965 2616
c3e337f8 2617 for (i = 0; i < 2; i++)
2cdba3cf 2618 if (priv->irq[i]) {
c3e337f8
KP		 2619 free_irq(priv->irq[i], dev);
2620 irq_dispose_mapping(priv->irq[i]);
2621 }
9c4a7965 2622
c3e337f8 2623 tasklet_kill(&priv->done_task[0]);
2cdba3cf 2624 if (priv->irq[1])
c3e337f8 2625 tasklet_kill(&priv->done_task[1]);
9c4a7965
KP		 2626
2627 iounmap(priv->reg);
2628
2629 dev_set_drvdata(dev, NULL);
2630
2631 kfree(priv);
2632
2633 return 0;
2634}
2635
2636static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2637 struct talitos_alg_template
2638 *template)
2639{
60f208d7 2640 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2641 struct talitos_crypto_alg *t_alg;
2642 struct crypto_alg *alg;
2643
2644 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2645 if (!t_alg)
2646 return ERR_PTR(-ENOMEM);
2647
acbf7c62
LN		 2648 t_alg->algt = *template;
2649
2650 switch (t_alg->algt.type) {
2651 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2652 alg = &t_alg->algt.alg.crypto;
2653 alg->cra_init = talitos_cra_init;
d4cd3283 2654 alg->cra_type = &crypto_ablkcipher_type;
497f2e6b 2655 break;
acbf7c62
LN		 2656 case CRYPTO_ALG_TYPE_AEAD:
2657 alg = &t_alg->algt.alg.crypto;
497f2e6b 2658 alg->cra_init = talitos_cra_init_aead;
d4cd3283 2659 alg->cra_type = &crypto_aead_type;
acbf7c62
LN		 2660 break;
2661 case CRYPTO_ALG_TYPE_AHASH:
2662 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2663 alg->cra_init = talitos_cra_init_ahash;
d4cd3283 2664 alg->cra_type = &crypto_ahash_type;
79b3a418 2665 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8
KP		 2666 !strncmp(alg->cra_name, "hmac", 4)) {
2667 kfree(t_alg);
79b3a418 2668 return ERR_PTR(-ENOTSUPP);
0b2730d8 2669 }
60f208d7 2670 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 2671 (!strcmp(alg->cra_name, "sha224") ||
2672 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 2673 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2674 t_alg->algt.desc_hdr_template =
2675 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2676 DESC_HDR_SEL0_MDEUA |
2677 DESC_HDR_MODE0_MDEU_SHA256;
2678 }
497f2e6b 2679 break;
1d11911a
KP		 2680 default:
2681 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2682 return ERR_PTR(-EINVAL);
acbf7c62 2683 }
9c4a7965 2684
9c4a7965 2685 alg->cra_module = THIS_MODULE;
9c4a7965 2686 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2687 alg->cra_alignmask = 0;
9c4a7965 2688 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 2689 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 2690
9c4a7965
KP		 2691 t_alg->dev = dev;
2692
2693 return t_alg;
2694}
2695
c3e337f8
KP		 2696static int talitos_probe_irq(struct platform_device *ofdev)
2697{
2698 struct device *dev = &ofdev->dev;
2699 struct device_node *np = ofdev->dev.of_node;
2700 struct talitos_private *priv = dev_get_drvdata(dev);
2701 int err;
2702
2703 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 2704 if (!priv->irq[0]) {
c3e337f8
KP		 2705 dev_err(dev, "failed to map irq\n");
2706 return -EINVAL;
2707 }
2708
2709 priv->irq[1] = irq_of_parse_and_map(np, 1);
2710
2711 /* get the primary irq line */
2cdba3cf 2712 if (!priv->irq[1]) {
c3e337f8
KP		 2713 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2714 dev_driver_string(dev), dev);
2715 goto primary_out;
2716 }
2717
2718 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2719 dev_driver_string(dev), dev);
2720 if (err)
2721 goto primary_out;
2722
2723 /* get the secondary irq line */
2724 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2725 dev_driver_string(dev), dev);
2726 if (err) {
2727 dev_err(dev, "failed to request secondary irq\n");
2728 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 2729 priv->irq[1] = 0;
c3e337f8
KP		 2730 }
2731
2732 return err;
2733
2734primary_out:
2735 if (err) {
2736 dev_err(dev, "failed to request primary irq\n");
2737 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 2738 priv->irq[0] = 0;
c3e337f8
KP		 2739 }
2740
2741 return err;
2742}
2743
1c48a5c9 2744static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2745{
2746 struct device *dev = &ofdev->dev;
61c7a080 2747 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2748 struct talitos_private *priv;
2749 const unsigned int *prop;
2750 int i, err;
2751
2752 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2753 if (!priv)
2754 return -ENOMEM;
2755
2756 dev_set_drvdata(dev, priv);
2757
2758 priv->ofdev = ofdev;
2759
511d63cb
HG		 2760 spin_lock_init(&priv->reg_lock);
2761
c3e337f8
KP		 2762 err = talitos_probe_irq(ofdev);
2763 if (err)
9c4a7965 2764 goto err_out;
9c4a7965 2765
2cdba3cf 2766 if (!priv->irq[1]) {
c3e337f8
KP		 2767 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2768 (unsigned long)dev);
2769 } else {
2770 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2771 (unsigned long)dev);
2772 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2773 (unsigned long)dev);
9c4a7965
KP		 2774 }
2775
c3e337f8
KP		 2776 INIT_LIST_HEAD(&priv->alg_list);
2777
9c4a7965
KP		 2778 priv->reg = of_iomap(np, 0);
2779 if (!priv->reg) {
2780 dev_err(dev, "failed to of_iomap\n");
2781 err = -ENOMEM;
2782 goto err_out;
2783 }
2784
2785 /* get SEC version capabilities from device tree */
2786 prop = of_get_property(np, "fsl,num-channels", NULL);
2787 if (prop)
2788 priv->num_channels = *prop;
2789
2790 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2791 if (prop)
2792 priv->chfifo_len = *prop;
2793
2794 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2795 if (prop)
2796 priv->exec_units = *prop;
2797
2798 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2799 if (prop)
2800 priv->desc_types = *prop;
2801
2802 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2803 !priv->exec_units || !priv->desc_types) {
2804 dev_err(dev, "invalid property data in device tree node\n");
2805 err = -EINVAL;
2806 goto err_out;
2807 }
2808
f3c85bc1
LN		 2809 if (of_device_is_compatible(np, "fsl,sec3.0"))
2810 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2811
fe5720e2 2812 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 2813 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 2814 TALITOS_FTR_SHA224_HWINIT |
2815 TALITOS_FTR_HMAC_OK;
fe5720e2 2816
4b992628
KP		 2817 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2818 priv->num_channels, GFP_KERNEL);
2819 if (!priv->chan) {
2820 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2821 err = -ENOMEM;
2822 goto err_out;
2823 }
2824
c3e337f8
KP		 2825 for (i = 0; i < priv->num_channels; i++) {
2826 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2cdba3cf 2827 if (!priv->irq[1] || !(i & 1))
c3e337f8
KP		 2828 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2829 }
ad42d5fc 2830
9c4a7965 2831 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2832 spin_lock_init(&priv->chan[i].head_lock);
2833 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2834 }
2835
2836 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2837
2838 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2839 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2840 priv->fifo_len, GFP_KERNEL);
2841 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2842 dev_err(dev, "failed to allocate request fifo %d\n", i);
2843 err = -ENOMEM;
2844 goto err_out;
2845 }
2846 }
2847
ec6644d6 2848 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2849 atomic_set(&priv->chan[i].submit_count,
2850 -(priv->chfifo_len - 1));
9c4a7965 2851
81eb024c
KP		 2852 dma_set_mask(dev, DMA_BIT_MASK(36));
2853
9c4a7965
KP		 2854 /* reset and initialize the h/w */
2855 err = init_device(dev);
2856 if (err) {
2857 dev_err(dev, "failed to initialize device\n");
2858 goto err_out;
2859 }
2860
2861 /* register the RNG, if available */
2862 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2863 err = talitos_register_rng(dev);
2864 if (err) {
2865 dev_err(dev, "failed to register hwrng: %d\n", err);
2866 goto err_out;
2867 } else
2868 dev_info(dev, "hwrng\n");
2869 }
2870
2871 /* register crypto algorithms the device supports */
9c4a7965
KP		 2872 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2873 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2874 struct talitos_crypto_alg *t_alg;
acbf7c62 2875 char *name = NULL;
9c4a7965
KP		 2876
2877 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2878 if (IS_ERR(t_alg)) {
2879 err = PTR_ERR(t_alg);
0b2730d8 2880 if (err == -ENOTSUPP)
79b3a418 2881 continue;
9c4a7965
KP		 2882 goto err_out;
2883 }
2884
acbf7c62
LN		 2885 switch (t_alg->algt.type) {
2886 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2887 case CRYPTO_ALG_TYPE_AEAD:
2888 err = crypto_register_alg(
2889 &t_alg->algt.alg.crypto);
2890 name = t_alg->algt.alg.crypto.cra_driver_name;
2891 break;
2892 case CRYPTO_ALG_TYPE_AHASH:
2893 err = crypto_register_ahash(
2894 &t_alg->algt.alg.hash);
2895 name =
2896 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2897 break;
2898 }
9c4a7965
KP		 2899 if (err) {
2900 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2901 name);
9c4a7965 2902 kfree(t_alg);
5b859b6e 2903 } else
9c4a7965 2904 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 2905 }
2906 }
5b859b6e
KP		 2907 if (!list_empty(&priv->alg_list))
2908 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2909 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 2910
2911 return 0;
2912
2913err_out:
2914 talitos_remove(ofdev);
9c4a7965
KP		 2915
2916 return err;
2917}
2918
6c3f975a 2919static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2920 {
2921 .compatible = "fsl,sec2.0",
2922 },
2923 {},
2924};
2925MODULE_DEVICE_TABLE(of, talitos_match);
2926
1c48a5c9 2927static struct platform_driver talitos_driver = {
4018294b
GL		 2928 .driver = {
2929 .name = "talitos",
2930 .owner = THIS_MODULE,
2931 .of_match_table = talitos_match,
2932 },
9c4a7965 2933 .probe = talitos_probe,
596f1034 2934 .remove = talitos_remove,
9c4a7965
KP		 2935};
2936
741e8c2d 2937module_platform_driver(talitos_driver);
9c4a7965
KP		 2938
2939MODULE_LICENSE("GPL");
2940MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2941MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
kernel source for telekom puls (alcatel/mediatek)