Merge tag 'v3.10.72' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / cpufreq / exynos-cpufreq.c
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1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - CPU frequency scaling support for EXYNOS series
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
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12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/regulator/consumer.h>
18#include <linux/cpufreq.h>
19#include <linux/suspend.h>
a125a17f 20
6c523c61 21#include <plat/cpu.h>
a125a17f 22
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23#include "exynos-cpufreq.h"
24
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25static struct exynos_dvfs_info *exynos_info;
26
27static struct regulator *arm_regulator;
28static struct cpufreq_freqs freqs;
29
30static unsigned int locking_frequency;
31static bool frequency_locked;
32static DEFINE_MUTEX(cpufreq_lock);
33
5542721a 34static int exynos_verify_speed(struct cpufreq_policy *policy)
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35{
36 return cpufreq_frequency_table_verify(policy,
37 exynos_info->freq_table);
38}
39
5542721a 40static unsigned int exynos_getspeed(unsigned int cpu)
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41{
42 return clk_get_rate(exynos_info->cpu_clk) / 1000;
43}
44
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45static int exynos_cpufreq_get_index(unsigned int freq)
46{
47 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
48 int index;
49
50 for (index = 0;
51 freq_table[index].frequency != CPUFREQ_TABLE_END; index++)
52 if (freq_table[index].frequency == freq)
53 break;
54
55 if (freq_table[index].frequency == CPUFREQ_TABLE_END)
56 return -EINVAL;
57
58 return index;
59}
60
61static int exynos_cpufreq_scale(unsigned int target_freq)
a125a17f 62{
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63 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
64 unsigned int *volt_table = exynos_info->volt_table;
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65 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
66 unsigned int arm_volt, safe_arm_volt = 0;
a125a17f 67 unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
d271d077 68 int index, old_index;
0e0e425f 69 int ret = 0;
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70
71 freqs.old = policy->cur;
c098ea74 72 freqs.new = target_freq;
a125a17f 73
c098ea74 74 if (freqs.new == freqs.old)
a125a17f 75 goto out;
a125a17f 76
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77 /*
78 * The policy max have been changed so that we cannot get proper
79 * old_index with cpufreq_frequency_table_target(). Thus, ignore
80 * policy and get the index from the raw freqeuncy table.
81 */
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82 old_index = exynos_cpufreq_get_index(freqs.old);
83 if (old_index < 0) {
84 ret = old_index;
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85 goto out;
86 }
87
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88 index = exynos_cpufreq_get_index(target_freq);
89 if (index < 0) {
90 ret = index;
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91 goto out;
92 }
93
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94 /*
95 * ARM clock source will be changed APLL to MPLL temporary
96 * To support this level, need to control regulator for
97 * required voltage level
98 */
99 if (exynos_info->need_apll_change != NULL) {
100 if (exynos_info->need_apll_change(old_index, index) &&
101 (freq_table[index].frequency < mpll_freq_khz) &&
102 (freq_table[old_index].frequency < mpll_freq_khz))
103 safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
104 }
105 arm_volt = volt_table[index];
106
b43a7ffb 107 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
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108
109 /* When the new frequency is higher than current frequency */
110 if ((freqs.new > freqs.old) && !safe_arm_volt) {
111 /* Firstly, voltage up to increase frequency */
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112 ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
113 if (ret) {
114 pr_err("%s: failed to set cpu voltage to %d\n",
115 __func__, arm_volt);
116 goto out;
117 }
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118 }
119
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120 if (safe_arm_volt) {
121 ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
a125a17f 122 safe_arm_volt);
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123 if (ret) {
124 pr_err("%s: failed to set cpu voltage to %d\n",
125 __func__, safe_arm_volt);
126 goto out;
127 }
128 }
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129
130 exynos_info->set_freq(old_index, index);
a125a17f 131
b43a7ffb 132 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
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133
134 /* When the new frequency is lower than current frequency */
135 if ((freqs.new < freqs.old) ||
136 ((freqs.new > freqs.old) && safe_arm_volt)) {
137 /* down the voltage after frequency change */
138 regulator_set_voltage(arm_regulator, arm_volt,
139 arm_volt);
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140 if (ret) {
141 pr_err("%s: failed to set cpu voltage to %d\n",
142 __func__, arm_volt);
143 goto out;
144 }
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145 }
146
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147out:
148
149 cpufreq_cpu_put(policy);
150
151 return ret;
152}
153
154static int exynos_target(struct cpufreq_policy *policy,
155 unsigned int target_freq,
156 unsigned int relation)
157{
158 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
159 unsigned int index;
c098ea74 160 unsigned int new_freq;
229b21e2 161 int ret = 0;
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162
163 mutex_lock(&cpufreq_lock);
164
165 if (frequency_locked)
166 goto out;
167
168 if (cpufreq_frequency_table_target(policy, freq_table,
169 target_freq, relation, &index)) {
170 ret = -EINVAL;
171 goto out;
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172 }
173
c098ea74 174 new_freq = freq_table[index].frequency;
0e0e425f 175
c098ea74 176 ret = exynos_cpufreq_scale(new_freq);
0e0e425f 177
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178out:
179 mutex_unlock(&cpufreq_lock);
180
181 return ret;
182}
183
184#ifdef CONFIG_PM
185static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
186{
187 return 0;
188}
189
190static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
191{
192 return 0;
193}
194#endif
195
196/**
197 * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
198 * context
199 * @notifier
200 * @pm_event
201 * @v
202 *
203 * While frequency_locked == true, target() ignores every frequency but
204 * locking_frequency. The locking_frequency value is the initial frequency,
205 * which is set by the bootloader. In order to eliminate possible
206 * inconsistency in clock values, we save and restore frequencies during
207 * suspend and resume and block CPUFREQ activities. Note that the standard
208 * suspend/resume cannot be used as they are too deep (syscore_ops) for
209 * regulator actions.
210 */
211static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
212 unsigned long pm_event, void *v)
213{
0e0e425f 214 int ret;
a125a17f 215
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216 switch (pm_event) {
217 case PM_SUSPEND_PREPARE:
0e0e425f 218 mutex_lock(&cpufreq_lock);
a125a17f 219 frequency_locked = true;
0e0e425f 220 mutex_unlock(&cpufreq_lock);
a125a17f 221
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222 ret = exynos_cpufreq_scale(locking_frequency);
223 if (ret < 0)
224 return NOTIFY_BAD;
a125a17f 225
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226 break;
227
228 case PM_POST_SUSPEND:
0e0e425f 229 mutex_lock(&cpufreq_lock);
a125a17f 230 frequency_locked = false;
0e0e425f 231 mutex_unlock(&cpufreq_lock);
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232 break;
233 }
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234
235 return NOTIFY_OK;
236}
237
238static struct notifier_block exynos_cpufreq_nb = {
239 .notifier_call = exynos_cpufreq_pm_notifier,
240};
241
242static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
243{
244 policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
245
246 cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
247
248 /* set the transition latency value */
249 policy->cpuinfo.transition_latency = 100000;
250
6ca939b3 251 cpumask_setall(policy->cpus);
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252
253 return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
254}
255
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256static int exynos_cpufreq_cpu_exit(struct cpufreq_policy *policy)
257{
258 cpufreq_frequency_table_put_attr(policy->cpu);
259 return 0;
260}
261
262static struct freq_attr *exynos_cpufreq_attr[] = {
263 &cpufreq_freq_attr_scaling_available_freqs,
264 NULL,
265};
266
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267static struct cpufreq_driver exynos_driver = {
268 .flags = CPUFREQ_STICKY,
269 .verify = exynos_verify_speed,
270 .target = exynos_target,
271 .get = exynos_getspeed,
272 .init = exynos_cpufreq_cpu_init,
1298271b 273 .exit = exynos_cpufreq_cpu_exit,
a125a17f 274 .name = "exynos_cpufreq",
1298271b 275 .attr = exynos_cpufreq_attr,
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276#ifdef CONFIG_PM
277 .suspend = exynos_cpufreq_suspend,
278 .resume = exynos_cpufreq_resume,
279#endif
280};
281
282static int __init exynos_cpufreq_init(void)
283{
284 int ret = -EINVAL;
285
286 exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
287 if (!exynos_info)
288 return -ENOMEM;
289
290 if (soc_is_exynos4210())
291 ret = exynos4210_cpufreq_init(exynos_info);
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292 else if (soc_is_exynos4212() || soc_is_exynos4412())
293 ret = exynos4x12_cpufreq_init(exynos_info);
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294 else if (soc_is_exynos5250())
295 ret = exynos5250_cpufreq_init(exynos_info);
a125a17f 296 else
c1585207 297 return 0;
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298
299 if (ret)
300 goto err_vdd_arm;
301
302 if (exynos_info->set_freq == NULL) {
303 pr_err("%s: No set_freq function (ERR)\n", __func__);
304 goto err_vdd_arm;
305 }
306
307 arm_regulator = regulator_get(NULL, "vdd_arm");
308 if (IS_ERR(arm_regulator)) {
309 pr_err("%s: failed to get resource vdd_arm\n", __func__);
310 goto err_vdd_arm;
311 }
312
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313 locking_frequency = exynos_getspeed(0);
314
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315 register_pm_notifier(&exynos_cpufreq_nb);
316
317 if (cpufreq_register_driver(&exynos_driver)) {
318 pr_err("%s: failed to register cpufreq driver\n", __func__);
319 goto err_cpufreq;
320 }
321
322 return 0;
323err_cpufreq:
324 unregister_pm_notifier(&exynos_cpufreq_nb);
325
184cddd1 326 regulator_put(arm_regulator);
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327err_vdd_arm:
328 kfree(exynos_info);
329 pr_debug("%s: failed initialization\n", __func__);
330 return -EINVAL;
331}
332late_initcall(exynos_cpufreq_init);