[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / clocksource / sun4i_timer.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		(1 << val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		(1 << 0)
#define TIMER_CTL_AUTORELOAD		(1 << 1)
#define TIMER_CTL_ONESHOT		(1 << 7)
#define TIMER_INTVAL_REG(val)	(0x10 * val + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * val + 0x18)

#define TIMER_SCAL		16

static void __iomem *timer_base;

static void sun4i_clkevt_mode(enum clock_event_mode mode,
			      struct clock_event_device *clk)
{
	u32 u = readl(timer_base + TIMER_CTL_REG(0));

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		u &= ~(TIMER_CTL_ONESHOT);
		writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
		break;
	}
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	u32 u = readl(timer_base + TIMER_CTL_REG(0));
	writel(evt, timer_base + TIMER_CNTVAL_REG(0));
	writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
	       timer_base + TIMER_CTL_REG(0));

	return 0;
}

static struct clock_event_device sun4i_clockevent = {
	.name = "sun4i_tick",
	.rating = 300,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sun4i_clkevt_mode,
	.set_next_event = sun4i_clkevt_next_event,
};


static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun4i_timer_irq = {
	.name = "sun4i_timer0",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun4i_timer_interrupt,
	.dev_id = &sun4i_clockevent,
};

static void __init sun4i_timer_init(struct device_node *node)
{
	unsigned long rate = 0;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base)
		panic("Can't map registers");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))
		panic("Can't get timer clock");

	rate = clk_get_rate(clk);

	writel(rate / (TIMER_SCAL * HZ),
	       timer_base + TIMER_INTVAL_REG(0));

	/* set clock source to HOSC, 16 pre-division */
	val = readl(timer_base + TIMER_CTL_REG(0));
	val &= ~(0x07 << 4);
	val &= ~(0x03 << 2);
	val |= (4 << 4) | (1 << 2);
	writel(val, timer_base + TIMER_CTL_REG(0));

	/* set mode to auto reload */
	val = readl(timer_base + TIMER_CTL_REG(0));
	writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));

	ret = setup_irq(irq, &sun4i_timer_irq);
	if (ret)
		pr_warn("failed to setup irq %d\n", irq);

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	sun4i_clockevent.cpumask = cpumask_of(0);

	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
					0x1, 0xff);
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_irq.h>
b2ac5d75	25
04981731 MR	26	#define TIMER_IRQ_EN_REG 0x00
04981731 MR	27	#define TIMER_IRQ_EN(val) (1 << val)
b2ac5d75	28	#define TIMER_IRQ_ST_REG 0x04
04981731 MR	29	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
	30	#define TIMER_CTL_ENABLE (1 << 0)
	31	#define TIMER_CTL_AUTORELOAD (1 << 1)
	32	#define TIMER_CTL_ONESHOT (1 << 7)
	33	#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
	34	#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
b2ac5d75 MR	35
	36	#define TIMER_SCAL 16
	37
	38	static void __iomem *timer_base;
	39
119fd635	40	static void sun4i_clkevt_mode(enum clock_event_mode mode,
b2ac5d75 MR	41	struct clock_event_device *clk)
b2ac5d75 MR	42	{
04981731	43	u32 u = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	44
	45	switch (mode) {
	46	case CLOCK_EVT_MODE_PERIODIC:
04981731 MR	47	u &= ~(TIMER_CTL_ONESHOT);
04981731 MR	48	writel(u \| TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	49	break;
	50
	51	case CLOCK_EVT_MODE_ONESHOT:
04981731	52	writel(u \| TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	53	break;
	54	case CLOCK_EVT_MODE_UNUSED:
	55	case CLOCK_EVT_MODE_SHUTDOWN:
	56	default:
04981731	57	writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	58	break;
	59	}
	60	}
	61
119fd635	62	static int sun4i_clkevt_next_event(unsigned long evt,
b2ac5d75 MR	63	struct clock_event_device *unused)
b2ac5d75 MR	64	{
04981731 MR	65	u32 u = readl(timer_base + TIMER_CTL_REG(0));
	66	writel(evt, timer_base + TIMER_CNTVAL_REG(0));
	67	writel(u \| TIMER_CTL_ENABLE \| TIMER_CTL_AUTORELOAD,
	68	timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	69
	70	return 0;
	71	}
	72
119fd635 MR	73	static struct clock_event_device sun4i_clockevent = {
119fd635 MR	74	.name = "sun4i_tick",
b2ac5d75 MR	75	.rating = 300,
b2ac5d75 MR	76	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
119fd635 MR	77	.set_mode = sun4i_clkevt_mode,
119fd635 MR	78	.set_next_event = sun4i_clkevt_next_event,
b2ac5d75 MR	79	};
	80
	81
119fd635	82	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	83	{
	84	struct clock_event_device evt = (struct clock_event_device )dev_id;
	85
	86	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	87	evt->event_handler(evt);
	88
	89	return IRQ_HANDLED;
	90	}
	91
119fd635 MR	92	static struct irqaction sun4i_timer_irq = {
119fd635 MR	93	.name = "sun4i_timer0",
b2ac5d75	94	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
119fd635 MR	95	.handler = sun4i_timer_interrupt,
119fd635 MR	96	.dev_id = &sun4i_clockevent,
b2ac5d75 MR	97	};
b2ac5d75 MR	98
119fd635	99	static void __init sun4i_timer_init(struct device_node *node)
b2ac5d75	100	{
b2ac5d75 MR	101	unsigned long rate = 0;
	102	struct clk *clk;
	103	int ret, irq;
	104	u32 val;
	105
b2ac5d75 MR	106	timer_base = of_iomap(node, 0);
	107	if (!timer_base)
	108	panic("Can't map registers");
	109
	110	irq = irq_of_parse_and_map(node, 0);
	111	if (irq <= 0)
	112	panic("Can't parse IRQ");
	113
b2ac5d75 MR	114	clk = of_clk_get(node, 0);
	115	if (IS_ERR(clk))
	116	panic("Can't get timer clock");
	117
	118	rate = clk_get_rate(clk);
	119
	120	writel(rate / (TIMER_SCAL * HZ),
04981731	121	timer_base + TIMER_INTVAL_REG(0));
b2ac5d75 MR	122
b2ac5d75 MR	123	/* set clock source to HOSC, 16 pre-division */
04981731	124	val = readl(timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	125	val &= ~(0x07 << 4);
	126	val &= ~(0x03 << 2);
	127	val \|= (4 << 4) \| (1 << 2);
04981731	128	writel(val, timer_base + TIMER_CTL_REG(0));
b2ac5d75 MR	129
b2ac5d75 MR	130	/* set mode to auto reload */
04981731 MR	131	val = readl(timer_base + TIMER_CTL_REG(0));
04981731 MR	132	writel(val \| TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
b2ac5d75	133
119fd635	134	ret = setup_irq(irq, &sun4i_timer_irq);
b2ac5d75 MR	135	if (ret)
	136	pr_warn("failed to setup irq %d\n", irq);
	137
	138	/* Enable timer0 interrupt */
04981731 MR	139	val = readl(timer_base + TIMER_IRQ_EN_REG);
04981731 MR	140	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
b2ac5d75	141
119fd635	142	sun4i_clockevent.cpumask = cpumask_of(0);
b2ac5d75	143
119fd635	144	clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
77cc982f	145	0x1, 0xff);
b2ac5d75	146	}
119fd635 MR	147	CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
119fd635 MR	148	sun4i_timer_init);